Method of manufacturing a semiconductor structure

Abstract

The embodiment of the present disclosure relates to the technical field of semiconductor, and provides a manufacturing method of a semiconductor structure, comprising: providing a substrate; forming a semiconductor layer initial mask layer on the substrate; performing P-type doping on the semiconductor layer to convert the semiconductor layer into the initial mask layer; performing a first patterning treatment on the initial mask layer to form a mask layer with an opening; performing a second patterning treatment on the substrate by taking the mask layer as a mask and using an etching process, and the etching rate of the etching process on the substrate is greater than the etching rate on the mask layer. The embodiment of the present disclosure is at least beneficial to improving the patterning treatment precision of the initial mask layer and the substrate.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a method for manufacturing a semiconductor structure. Background Technology

[0002] In semiconductor manufacturing, as the geometric pattern size of semiconductor devices decreases, higher demands are placed on the precision of patterning. Factors affecting patterning precision during semiconductor structure fabrication include the alignment accuracy between the mask layer and the photomask, and the etching selectivity between the mask layer and the substrate to be etched. A higher etching selectivity between the mask layer and the substrate is more conducive to transferring the pattern to the substrate through the mask layer during the etching process. Furthermore, the optical properties of the mask layer itself affect the alignment accuracy between the mask layer and the photomask. Summary of the Invention

[0003] This disclosure provides a method for manufacturing a semiconductor structure, which at least helps to improve the patterning accuracy of the initial mask layer and the substrate.

[0004] According to some embodiments of this disclosure, one aspect of this disclosure provides a method for manufacturing a semiconductor structure, comprising: providing a substrate; forming a semiconductor layer on the substrate; performing P-type doping on the semiconductor layer to convert the semiconductor layer into an initial mask layer; performing a first patterning process on the initial mask layer to form a mask layer with openings; using the mask layer as a mask, performing a second patterning process on the substrate using an etching process, wherein the etching rate of the substrate is greater than the etching rate of the mask layer.

[0005] In some embodiments, the material of the initial mask layer comprises a borosilicate compound, and the atomic percentage of boron atoms to silicon atoms in the borosilicate compound ranges from 1:1 to 3:2.

[0006] In some embodiments, the extinction coefficient of the initial mask layer is less than 0.45.

[0007] In some embodiments, the extinction coefficient of the initial mask layer ranges from 0.34 to 0.44.

[0008] In some embodiments, the thickness of the initial mask layer is in the range of 400 nm to 460 nm along the direction from the substrate to the initial mask layer.

[0009] In some embodiments, after performing the second patterning process on the substrate using an etching process, a portion of the mask layer is retained, and the ratio of the thickness of the retained mask layer to the thickness of the initial mask layer in the direction from the substrate to the initial mask layer ranges from 0.13 to 0.16.

[0010] In some embodiments, the thickness of the retained mask layer in the direction from the substrate to the initial mask layer ranges from 65 nm to 75 nm.

[0011] In some embodiments, the step of forming the semiconductor layer includes: forming an initial semiconductor layer on the substrate; and performing N-type doping or P-type doping on the initial semiconductor layer to convert the initial semiconductor layer into the semiconductor layer.

[0012] In some embodiments, the initial mask layer has photolithographic markings; the step of performing a first patterning process on the initial mask layer using a first etching process further includes: providing a photomask having the opening, the photomask also having the photolithographic markings; wherein the photolithographic markings on the photomask coincide with the photolithographic markings on the initial mask layer.

[0013] In some embodiments, after the initial mask layer is formed on the substrate and before the first patterning process is performed on the initial mask layer, the method further includes: sequentially stacking a first mask layer and a second mask layer on the side of the initial mask layer away from the substrate, the second mask layer including adjacent first and second regions; illuminating the second region with the photomask to change the film properties of the illuminated second region; etching the first region and the second region using the same etching process, wherein the etching rate of the first region is less than the etching rate of the second region, so that when the first region is removed, a portion of the second region is retained to form the second mask layer having the opening.

[0014] In some embodiments, the first patterning process of the initial mask layer includes: etching the first mask layer with the second mask layer having the opening as a mask to form the first mask layer having the opening; and etching the initial mask layer with the first mask layer having the opening as a mask.

[0015] In some embodiments, the step of providing the substrate includes: providing a substrate; forming a stacked structure on the substrate, the stacked structure being used to form a capacitor contact hole; and the step of performing the second patterning process on the substrate includes: using the mask layer as a mask, etching the stacked structure using the etching process to form the capacitor contact hole.

[0016] In some embodiments, the step of forming the stacked structure includes: sequentially stacking a bottom support layer, a first dielectric layer, an intermediate support layer, a second dielectric layer, and a top support layer on the substrate.

[0017] The technical solutions provided in this disclosure have at least the following advantages:

[0018] On the one hand, p-type doping of the semiconductor layer improves the optical performance of the initial mask layer. This improves the alignment accuracy between the initial mask layer and the photomask during subsequent photolithography alignment. Furthermore, the improved alignment accuracy during the first patterning process enhances the precision of the first patterning process, allowing for more accurate transfer of the pattern from the photomask to the initial mask layer, thus forming a mask layer that meets the requirements.

[0019] On the other hand, the mask layer is also a p-type doped semiconductor layer, which helps to reduce the etching rate of the mask layer during subsequent substrate etching. Therefore, in the step of using the mask layer as a mask and employing an etching process to perform the second patterning process on the substrate, while ensuring that the etching rate of the substrate is greater than the etching rate of the mask layer, it is beneficial to increase the difference between the etching rates of the substrate and the mask layer. This facilitates the accurate transfer of the pattern to the substrate through the mask layer, thereby improving the accuracy of the second patterning process. Attached Figure Description

[0020] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings represent similar elements. Unless otherwise stated, the figures in the drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this disclosure or the conventional technology, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 A flowchart illustrating a method for manufacturing a semiconductor structure according to an embodiment of this disclosure;

[0022] Figures 2 to 8 A schematic diagram of the structure corresponding to each step in the manufacturing method of the semiconductor structure provided in the embodiments of this disclosure;

[0023] Figure 9 A graph showing the relationship between the boron content in the initial mask layer and the extinction coefficient of the initial mask layer in the semiconductor structure manufacturing method provided in this embodiment of the disclosure. Detailed Implementation

[0024] As can be seen from the background technology, the accuracy of semiconductor structure patterning needs to be improved.

[0025] This disclosure provides a method for manufacturing a semiconductor structure. On one hand, p-type doping of the semiconductor layer improves the optical performance of the initial mask layer. This improves the alignment accuracy between the initial mask layer and the photomask during subsequent photolithography alignment. Furthermore, the improved alignment accuracy during the first patterning process enhances the accuracy of the first patterning process, allowing for more accurate transfer of the pattern from the photomask to the initial mask layer, thus forming a mask layer that meets the requirements. On the other hand, since the mask layer is also a p-type doped semiconductor layer, it reduces the etching rate of the mask layer during subsequent substrate etching. Therefore, in the step of using the mask layer as a mask and performing a second patterning process on the substrate, while ensuring that the etching rate of the substrate is greater than the etching rate of the mask layer, it increases the difference between the etching rates of the substrate and the mask layer. This facilitates accurate transfer of the pattern to the substrate through the mask layer, improving the accuracy of the second patterning process. This improves the patterning accuracy of both the initial mask layer and the substrate, thereby increasing the accuracy of transferring the pattern from the photomask to the substrate and forming a semiconductor structure with higher dimensional accuracy.

[0026] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this disclosure to facilitate a better understanding of the embodiments. However, the technical solutions claimed in the embodiments of this disclosure can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0027] This disclosure provides a method for manufacturing a semiconductor structure. The method for manufacturing a semiconductor structure provided in this disclosure will be described in detail below with reference to the accompanying drawings. Figure 1 A flowchart illustrating a method for manufacturing a semiconductor structure according to an embodiment of this disclosure; Figures 2 to 8 A schematic diagram of the structure corresponding to each step in the manufacturing method of the semiconductor structure provided in the embodiments of this disclosure; Figure 9 This diagram illustrates the relationship between the boron content in the initial mask layer and the extinction coefficient of the initial mask layer in the semiconductor structure manufacturing method provided in this embodiment. It should be noted that, for ease of description and clear illustration of the steps of the semiconductor structure manufacturing method, the following diagram is used in this embodiment. Figures 2 to 8 These are partial structural diagrams of semiconductor structures.

[0028] refer to Figures 1 to 9 The manufacturing method of a semiconductor structure may include the following steps:

[0029] S101: Reference Figure 2Provides a base of 100.

[0030] In some embodiments, reference Figure 2 The step of providing substrate 100 may include: providing substrate 110; forming a stacked structure 120 on substrate 110, the stacked structure 120 being used to form capacitor contact holes 121 (see reference). Figure 8 The step of performing a second patterning process on the substrate 100 may include: using the mask layer 112 as a mask, etching the stacked structure 120 using an etching process to form capacitor contact holes 121.

[0031] In some embodiments, after forming the capacitor contact hole 121, the method for manufacturing the semiconductor structure further includes forming a capacitor structure based on the capacitor contact hole 121. It should be noted that the specific manufacturing method of the capacitor structure is not limited in the embodiments of this disclosure. In one example, the substrate 110 includes a transistor structure, and the capacitor contact hole 121 exposes the source or drain of the transistor structure, so that the capacitor structure is electrically connected to the source or drain of the transistor.

[0032] It is understandable that the capacitor structure subsequently formed using the capacitor contact hole 121 generally needs to have a relatively long aspect ratio to ensure that the capacitor structure has a high capacitance. Therefore, forming a stacked structure 120 on the substrate 110 has two advantages. First, it helps to increase the depth of the subsequently formed capacitor structure in the direction from the substrate 113 to the stacked structure 120, thereby increasing the aspect ratio of the capacitor structure. Second, some of the film layers in the stacked structure 120 can later serve as a support layer when forming the capacitor structure using the capacitor contact hole 121, preventing the collapse of the capacitor structure with a large aspect ratio, thereby improving the stability of the semiconductor structure.

[0033] In some embodiments, the substrate 110 may be a silicon substrate, a germanium substrate, a silicon germanide substrate, a silicon carbide substrate, or a silicon substrate on an insulator, etc.

[0034] In some embodiments, continue to refer to Figure 1 The step of forming the stacked structure 120 may include: sequentially stacking a bottom support layer 130, a first dielectric layer 140, an intermediate support layer 150, a second dielectric layer 160 and a top support layer 170 on a substrate 110.

[0035] In one example, the materials of the bottom support layer 130, the middle support layer 150, and the top support layer 170 can be equal. For example, the materials of the bottom support layer 130, the middle support layer 150, and the top support layer 170 can all be silicon nitride; the materials of the first dielectric layer 140 and the second dielectric layer 160 can be equal. For example, the materials of the first dielectric layer 140 and the second dielectric layer 160 can both be silicon oxide.

[0036] It should be noted that, Figure 2 as well as Figures 6 to 8 The bottom support layer 130, the middle support layer 150, and the top support layer 170 are all displayed with the same filling method. This does not mean that the bottom support layer 130, the middle support layer 150, and the top support layer 170 are made of the same material. In actual applications, the materials of the bottom support layer 130, the middle support layer 150, and the top support layer 170 can be different.

[0037] S102: Reference Figures 3 to 4 A semiconductor layer 101 is formed on the substrate 100.

[0038] In some embodiments, the step of forming the semiconductor layer 101 may include: referencing Figure 3 An initial semiconductor layer 111 is formed on the substrate 100; Reference Figure 4 The initial semiconductor layer 111 is doped with N-type or P-type doping to convert the initial semiconductor layer 111 into semiconductor layer 101.

[0039] In some embodiments, the material of the initial semiconductor layer 111 may be silicon.

[0040] In one example, the initial semiconductor layer 111 is N-type doped, that is, an N-type dopant element is implanted into the initial semiconductor layer 11, wherein the N-type dopant element can be at least one of arsenic, phosphorus or antimony.

[0041] In another example, the initial semiconductor layer 111 is p-type doped, that is, p-type doping elements are implanted into the initial semiconductor layer 11, wherein the p-type doping element can be at least one of boron, indium or gallium.

[0042] S103: Reference Figure 5 The semiconductor layer 101 is p-type doped to convert it into an initial mask layer 102. P-type doping of the semiconductor layer 101 involves implanting p-type dopant elements into the semiconductor layer 101.

[0043] In one example, p-type doping of semiconductor layer 101 can be achieved by implanting boron into semiconductor layer 101.

[0044] It should be noted that, for the sake of simplicity, Figures 3 to 5 Only the substrate 100 is shown in the diagram. The structures contained in the substrate 100 are as follows: Figure 2 As shown.

[0045] In some embodiments, the material of the initial mask layer 102 may include a borosilicate compound, and the atomic percentage of boron atoms to silicon atoms in the borosilicate compound may range from 1:1 to 3:2.

[0046] Understandably, reference Figure 9 The extinction coefficient of borosilicate compounds decreases with increasing boron atom content. Therefore, increasing the boron atom content in the initial mask layer 102 is beneficial for reducing the extinction coefficient of the initial mask layer 102, thus making the initial mask layer 102 more transparent. Furthermore, the boron atom content in the initial mask layer 102 determines the boron atom content in the subsequent mask layer 112. The boron atom content in the mask layer 112 affects the etching rate of the mask layer 112 during the etching process of the substrate 100. Therefore, it is necessary to comprehensively consider the influence of the boron atom content in the mask layer 112 on the extinction coefficient of the mask layer 112 and the etching rate of the mask layer 112 during the etching process. Controlling the atomic percentage of boron atoms to silicon atoms in the borosilicate compound within the range of 1:1 to 3:2 is beneficial for reducing both the extinction coefficient of the initial mask layer 102 and the etching rate of the mask layer 112 during the etching process of the substrate 100.

[0047] In some embodiments, continue to refer to Figure 9 The extinction coefficient of the initial mask layer 102 can be less than 0.45. It is understood that when the extinction coefficient of the initial mask layer 102 is less than 0.45, the initial mask layer 102 has good light transmittance. In some embodiments, both the initial mask layer 102 and the substrate 100 have photolithographic markings. Improving the light transmittance of the initial mask layer 102 facilitates the alignment of the photolithographic markings on the initial mask layer 102 with those on the substrate 100 during the illumination step, thereby achieving higher alignment accuracy between the initial mask layer 102 and the substrate 100. It is understood that an extinction coefficient of less than 0.45 for the initial mask layer 102 is beneficial for improving the alignment accuracy between the initial mask layer 102 and the substrate 100. Furthermore, during the subsequent second patterning process on the substrate 100, it is beneficial for forming the capacitor contact hole 121 (see reference) at a predetermined position. Figure 8 This is beneficial for improving the accuracy of subsequent second-stage graphical processing.

[0048] In some embodiments, the extinction coefficient of the initial mask layer 102 can be in the range of 0.34 to 0.44. As can be seen from the above analysis, when the extinction coefficient of the initial mask layer 102 is in the range of 0.34 to 0.44, the extinction coefficient of the initial mask layer 102 is relatively low. Furthermore, the boron atom content in the borosilicate compound within this range is advantageous in reducing the etching rate of the mask layer 112 during the etching process of the substrate 100. This ensures that the initial mask layer 102 has a low extinction coefficient while increasing the ratio of the etching rate of the substrate to the etching rate of the mask layer 112 during the same etching process, thereby further improving the accuracy of the first patterning process and the second patterning process.

[0049] In one example, the initial mask layer 102 is made of a borosilicate compound, and the atomic percentage of boron atoms to silicon atoms in the borosilicate compound ranges from 3:2, with an extinction coefficient of 0.34.

[0050] In some embodiments, the initial mask layer 102 has photolithographic markings; in the step of performing a first patterning process on the initial mask layer 102 using a first etching process, the method for manufacturing a semiconductor structure may further include: providing a photomask with an opening, the photomask also having photolithographic markings; wherein the photolithographic markings on the photomask coincide with the photolithographic markings on the initial mask layer 102.

[0051] It is understandable that when the extinction coefficient of the initial mask layer 102 is less than 0.45, the initial mask layer 102 has good light transmittance, which is beneficial for the operator to observe the photolithographic marks on the initial mask layer 102 and the photolithographic marks on the photomask. This is beneficial for aligning the photolithographic marks on the initial mask layer 102 and the photolithographic marks on the photomask, that is, making the orthographic projection of the photolithographic marks on the initial mask layer 102 onto the substrate 100 the same as the orthographic projection of the photolithographic marks on the photomask onto the substrate 100. In this way, it is beneficial for aligning the opening 122 with the part of the initial mask layer 102 that needs to be etched, thereby improving the accuracy of the first patterning process on the initial mask layer 102.

[0052] In some embodiments, the thickness of the initial mask layer 102 can be in the direction X along the substrate 100 pointing to the initial mask layer 102, and the thickness range of the initial mask layer 102 can be 400 nm to 460 nm.

[0053] As described above, the initial mask layer 102 is composed of a P-type doped semiconductor layer, and the mask layer 112 formed by the first patterning process of the initial mask layer 102 is also composed of a P-type doped semiconductor layer. This helps to reduce the etching rate of the mask layer 112 during the subsequent etching process of the substrate 100. It is understood that, in order to increase the capacitance of the subsequently formed capacitor structure, the substrate 100 has a relatively large thickness in the direction X along the substrate 100 pointing to the initial mask layer 102. The etching time for the second patterning process of the substrate 100 is relatively long. The mask layer 112, as the mask, will also be etched and consumed during the second patterning process. Therefore, reducing the etching rate of the mask layer 112 helps to reduce the thickness of the mask layer 112 etched during the second patterning process.

[0054] Understandably, reference Figures 6 to 8By reducing the thickness of the mask layer 112 etched in the second patterning step, a thinner initial mask layer 102 can be fabricated in the X direction when forming the initial mask layer 102. This allows for a thinner initial mask layer 112 in the X direction, which in turn reduces the aspect ratio of the openings 122 in the mask layer 112. This makes it easier for the etching material to etch the substrate 100 through the openings 122 during the etching process. In the second patterning step, this reduces the aspect ratio of the formed trenches, thus improving the accuracy of the second patterning process on the substrate 100. It should be noted that the final shape of the trenches formed in the second patterning step is jointly constituted by the openings 122 in the mask layer 112 and the capacitor contact holes 121 in the substrate 100.

[0055] In one example, when performing the second patterning process on a substrate 100 of the same size, capacitor contact holes 121 of the same size are not formed, and the thickness of the initial mask layer formed without P-type doping of the semiconductor layer is 500 nm. In this embodiment of the present disclosure, the thickness of the initial mask layer 102 formed by P-type doping of the semiconductor layer can be 450 nm. It is evident that forming the initial mask layer 102 by P-type doping of the semiconductor layer reduces the etching rate of the mask layer 112 during subsequent etching processes on the substrate 100, which helps to reduce the thickness of the initial mask layer 102 that needs to be formed, thereby reducing the difficulty of the second patterning process and improving its accuracy.

[0056] S104: Reference Figure 2 , Figure 6 and Figure 7 The initial mask layer 102 is first patterned to form a mask layer 112 with openings 122.

[0057] It is understood that the first patterning process for the initial mask layer 102 further includes: providing a photomask with openings, and illuminating the initial mask layer 102 with the photomask to form a mask layer 112 with openings 122. P-type doping of the semiconductor layer helps reduce the extinction coefficient of the initial mask layer 102, thereby improving the alignment accuracy between the initial mask layer 102 and the photomask, thus improving the accuracy of the first patterning process. This means that the pattern in the photomask can be more accurately transferred to the initial mask layer 102 to form a mask layer 112 that meets the requirements. It should be noted that the pattern in the photomask refers to the pattern formed by the openings in the photomask.

[0058] In some embodiments, after forming the initial mask layer 102 on the substrate 100 and before performing a first patterning process on the initial mask layer 102, the method for manufacturing the semiconductor structure may further include the following steps:

[0059] refer to Figure 2 A first mask layer 103 and a second mask layer 104 are sequentially stacked on the side of the initial mask layer 102 away from the substrate 100. The second mask layer 104 includes adjacent first regions 114 and second regions 124. The second region 124 is used for subsequent etching to form an opening 122.

[0060] In one example, the material of the first mask layer 103 can be silicon oxide, and the material of the second mask layer 104 can be amorphous carbon.

[0061] It should be noted that both the first mask layer 103 and the second mask layer 104 have photolithographic markings, and both the first mask layer 103 and the second mask layer 104 have good light transmittance. Therefore, based on improving the light transmittance of the initial mask layer 102 in this embodiment, it is beneficial for the operator to align the photolithographic markings on the first mask layer 103, the second mask layer 104, and the initial mask layer 102, thereby improving the accuracy of the first patterning process.

[0062] Reference Figure 2 and Figure 6 The second region 124 is illuminated using a photomask, which alters the film properties of the illuminated second region 124. The first region 114 and the second region 124 are etched using the same etching process, with the etching rate of the first region 114 being lower than that of the second region 124, so that when the first region 114 is removed, a portion of the second region 124 is retained to form a second mask layer 104 with an opening 122.

[0063] It should be noted that in the etching step of the second mask layer 104, both the first region 114 and the second region 124 are etched. However, since the second region 124 is photo-treated, the etching rate of the first region 114 is less than that of the second region 124. Therefore, the second mask layer 104 with the opening 122 can be formed.

[0064] In some embodiments, the first patterning step of the initial mask layer 102 may include: combining a reference Figures 6 to 8 The first mask layer 103 is etched using the second mask layer 104 with opening 122 as a mask to form the first mask layer 103 with opening 122; the initial mask layer 102 is etched using the first mask layer 103 with opening 122 as a mask.

[0065] It should be noted that in some embodiments, during the step of etching the first mask layer 103 using the second mask layer 104 with opening 122 as a mask, the second mask layer 104 is also etched, and when the first mask layer 103 with opening 122 is formed, the second mask layer 104 is completely etched away. In other embodiments, during the step of etching the first mask layer 103 using the second mask layer 104 with opening 122 as a mask, the second mask layer 104 is completely etched away, and the portion of the first mask layer 103 not exposed by opening 122 in the second mask layer 104 is etched away. In this case, the thickness of the first mask layer 103 with opening 122 in the X direction is lower than the thickness of the first mask layer 103 before the first patterning process.

[0066] Furthermore, in some embodiments, during the step of etching the initial mask layer 102 using the first mask layer 103 with opening 122 as a mask, the first mask layer 103 is also etched, and when the mask layer 112 with opening 122 is formed, the entire first mask layer 103 is etched away. In other embodiments, during the step of etching the initial mask layer 102 using the first mask layer 103 with opening 122 as a mask, the entire first mask layer 103 has been etched away, and the portion of the initial mask layer 102 not exposed by opening 122 is etched away. In this case, the thickness of the mask layer 112 with opening 122 in the X direction is lower than the thickness of the initial mask layer 102 before the first patterning process.

[0067] S105: Reference Figure 7 and Figure 8 Using the mask layer 112 as a mask, the substrate 100 is subjected to a second patterning process by an etching process. The etching rate of the substrate 100 is greater than the etching rate of the mask layer 112.

[0068] It is understandable that in the step of performing the second patterning process on the substrate 100 using the etching process, the etching process also etches the mask layer 112. At this time, the mask layer 112 is a P-type doped semiconductor layer, which helps to reduce the etching rate of the mask layer 112 during the etching of the substrate 100. In the step of performing the second patterning process on the substrate 100 using the mask layer 112 as a mask and the etching process, under the premise of ensuring that the etching rate of the substrate 100 is greater than the etching rate of the mask layer 112, it is beneficial to increase the difference between the etching rate of the substrate 100 and the etching rate of the mask layer 112. This helps to accurately transfer the pattern formed by the openings 122 in the mask layer 112 to the substrate 100 through the mask layer 112, thereby improving the accuracy of the second patterning process.

[0069] Furthermore, the manufacturing method provided in this embodiment is beneficial to increasing the difference between the etching rate of the substrate 100 and the etching rate of the mask layer 112, which helps to avoid over-etching of the mask layer 112 on the sidewall of the opening 122 in the formed mask layer 112, and avoids large changes in the size of the opening 122, thereby avoiding changes in the size of the capacitor contact hole 121 formed based on the opening 122, so as to ensure the accuracy of the second patterning process of the substrate 100.

[0070] In some embodiments, after performing a second patterning process on the substrate 100 using an etching process, a portion of the mask layer 112 is retained along the direction X from the substrate 100 toward the initial mask layer 102. The ratio of the thickness of the retained mask layer 112 to the thickness of the initial mask layer 102 can range from 0.13 to 0.16. It is understood that in practical applications, after etching the substrate 100 to form the capacitor contact hole 121, the remaining mask layer 112 can be removed.

[0071] It is understandable that in the step of performing the second patterning process on the substrate 100 using the etching process, a mask layer 112 of a certain thickness needs to be retained to protect the substrate 100 that does not need to be etched, so as to improve the accuracy of the formed capacitor contact hole 121.

[0072] Furthermore, in the step of transforming the initial mask layer 102 into a mask layer 112 with openings 122, a portion of the initial mask layer thickness is consumed. In the step of etching the substrate 100, the remaining mask layer 112 composed of the initial mask layer 102 is also consumed. In this case, the thickness of the initial mask layer 102 in the direction X along the substrate 100 pointing to the initial mask layer 102 ranges from 400 nm to 460 nm. This is beneficial because after the initial mask layer 102 undergoes the first patterning process and the mask layer 112 undergoes the second patterning process, the ratio of the thickness of the retained mask layer 112 to the thickness of the initial mask layer 102 ranges from 0.13 to 0.16. On the one hand, when the thickness of the initial mask layer 102 is less than 400 nm, during the second patterning process on the substrate 100, the mask layer 112 may be completely etched away before the capacitor contact hole 121 is formed, causing the substrate 100, which does not require the second patterning process, to be etched, affecting the size of the final capacitor contact hole 121. On the other hand, when the thickness of the initial mask layer 102 is less than 460 nm, the trench formed during the second patterning process on the substrate 100 has a large depth-to-width ratio, increasing the difficulty of the second patterning process on the substrate 100 and reducing the accuracy of the second patterning process. Therefore, in this embodiment, the thickness range of the initial mask layer 102 is controlled between 400 nm and 460 nm, and the ratio of the thickness of the retained mask layer 112 to the thickness of the initial mask layer 102 is further controlled between 0.13 and 0.16. This helps to reduce the difficulty of the second patterning process while ensuring that a portion of the mask layer 112 is retained when the capacitor contact hole 121 is formed.

[0073] In some embodiments, the thickness of the retained mask layer 112 along the direction X from the substrate 100 to the initial mask layer 102 can range from 65 nm to 75 nm. In one example, the thickness of the retained mask layer 112 along the direction X from the substrate 100 to the initial mask layer 102 is 71 nm.

[0074] In summary, the manufacturing method provided in this disclosure, by performing P-type doping on the semiconductor layer 101, has several advantages. First, it improves the optical performance of the initial mask layer 102. When aligning the initial mask layer 102 with a photomask, it enhances the alignment accuracy between the initial mask layer 102 and the photomask. During the first patterning process of the initial mask layer 102, the improved alignment accuracy between the initial mask layer 102 and the photomask further enhances the accuracy of the first patterning process, allowing for more accurate transfer of the pattern from the photomask to the initial mask layer 102 to form a compliant mask layer 112. Second, it reduces the etching rate of the mask layer 112 during the etching process on the substrate 100. Therefore, in the second patterning process, it increases the difference between the etching rate of the substrate 100 and the etching rate of the mask layer 112, thereby facilitating accurate transfer of the pattern to the substrate 100 through the mask layer 112 and improving the accuracy of the second patterning process. This improves the patterning accuracy of both the initial mask layer 102 and the substrate 100, thereby increasing the accuracy of transferring the pattern in the photomask to the substrate 100 and forming a semiconductor structure with higher dimensional accuracy.

[0075] Those skilled in the art will understand that the above embodiments are specific examples of implementing this disclosure, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of the embodiments of this disclosure. Any person skilled in the art can make their own modifications and alterations without departing from the spirit and scope of the embodiments of this disclosure; therefore, the scope of protection of the embodiments of this disclosure should be determined by the scope defined in the claims.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that, include: Provide a base; A semiconductor layer is formed on the substrate; The semiconductor layer is p-type doped to convert it into an initial mask layer; The initial mask layer is subjected to a first patterning process to form a mask layer with openings; Using the mask layer as a mask, the substrate is subjected to a second patterning process by an etching process, wherein the etching rate of the substrate is greater than the etching rate of the mask layer; the material of the initial mask layer includes a borosilicate compound, and the atomic percentage of boron atoms to silicon atoms in the borosilicate compound ranges from 1:1 to 3:2; The steps of providing the substrate include: Provide substrate; A stacked structure is formed on the substrate, the stacked structure being used to form capacitor contact holes; The step of performing the second patterning process on the substrate includes: Using the mask layer as a mask, the etching process is used to etch the stacked structure to form the capacitor contact hole.

2. The manufacturing method as described in claim 1, characterized in that, The extinction coefficient of the initial mask layer is less than 0.

45.

3. The manufacturing method as described in claim 2, characterized in that, The extinction coefficient of the initial mask layer ranges from 0.34 to 0.

44.

4. The manufacturing method as described in claim 1, characterized in that, Along the direction from the substrate to the initial mask layer, the thickness of the initial mask layer ranges from 400 nm to 460 nm.

5. The manufacturing method as described in claim 1, characterized in that, After performing the second patterning process on the substrate using the etching process, a portion of the mask layer is retained. The ratio of the thickness of the retained mask layer to the thickness of the initial mask layer in the direction from the substrate to the initial mask layer ranges from 0.13 to 0.

16.

6. The manufacturing method as described in claim 5, characterized in that, Along the direction from the substrate to the initial mask layer, the thickness of the retained mask layer ranges from 65 nm to 75 nm.

7. The manufacturing method as described in claim 1, characterized in that, The steps for forming the semiconductor layer include: An initial semiconductor layer is formed on the substrate; The initial semiconductor layer is subjected to N-type doping or P-type doping to transform the initial semiconductor layer into the semiconductor layer.

8. The manufacturing method as described in claim 1, characterized in that, The initial mask layer has photolithographic markings; the step of performing a first patterning process on the initial mask layer using a first etching process further includes: A photomask with the said opening is provided, and the photomask also has the said photolithographic markings; The photolithographic markings on the photomask coincide with the photolithographic markings on the initial mask layer.

9. The manufacturing method as described in claim 8, characterized in that, After the initial mask layer is formed on the substrate, and before the first patterning process is performed on the initial mask layer, the method further includes: A first mask layer and a second mask layer are sequentially stacked on the side of the initial mask layer away from the substrate, and the second mask layer includes an adjacent first region and a second region; The second region is illuminated using the photomask, which alters the film properties of the illuminated second region. The first region and the second region are etched using the same etching process, wherein the etching rate of the first region is less than the etching rate of the second region, so that when the first region is removed, a portion of the second region is retained to form the second mask layer having the opening.

10. The manufacturing method as described in claim 9, characterized in that, The first patterning process for the initial mask layer includes: The first mask layer is etched using the second mask layer having the opening as a mask to form the first mask layer having the opening; The initial mask layer is etched using the first mask layer having the opening as a mask.

11. The manufacturing method as described in claim 1, characterized in that, The steps for forming the stacked structure include: sequentially stacking a bottom support layer, a first dielectric layer, an intermediate support layer, a second dielectric layer, and a top support layer on the substrate.

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