Schottky diode and method of manufacturing the same

Abstract

The application discloses a Schottky diode and a preparation method thereof, and relates to the technical field of semiconductor chip manufacturing. The Schottky diode preparation method comprises the following steps: providing a Schottky diode chip, wherein the Schottky diode chip has a barrier layer; and forming a separation layer according to the position of the barrier layer, so that the position of a first through hole of the separation layer is opposite to the barrier layer. In this way, when a first metal layer is formed in the first through hole of the separation layer, the first metal layer is opposite to the barrier layer, so that the first metal layer serves as an anode of the Schottky diode. The diameter of the first through hole linearly decreases in a direction away from the Schottky diode chip. In this way, the bonding force between the separation layer and the first metal layer can be reduced, the separation of the separation layer is facilitated, and the preparation rate of the Schottky diode is improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor chip manufacturing technology, and in particular to a Schottky diode and its fabrication method. Background Technology

[0002] Unlike PN junction diodes, which are composed of P-type semiconductors (also known as hole-type semiconductors) and N-type semiconductors (also known as electron-type semiconductors), Schottky barrier diodes (SBDs) are diodes fabricated using the principle of forming a metal-semiconductor junction through the contact between a metal and a semiconductor. In fabricating a Schottky diode, a front electrode (anode) is formed on the front side of the chip, and a back electrode (cathode) is formed on the back side.

[0003] In related technologies, when forming the front electrode of a Schottky diode, the area of ​​the front electrode is typically defined by a lifter adhesive, which is then removed after the front electrode is formed. However, in these technologies, the lifter adhesive has low removal efficiency, affecting the fabrication rate of the Schottky diode. Summary of the Invention

[0004] This application provides a Schottky diode and its fabrication method, which can solve the problem of low release efficiency of release adhesive in related technologies. The technical solution is as follows:

[0005] In one aspect, a method for fabricating a Schottky diode is provided, comprising:

[0006] A Schottky diode chip is provided, the Schottky diode chip comprising a substrate layer, an epitaxial layer and a barrier layer, wherein the epitaxial layer and the substrate layer are stacked along a predetermined direction; along a direction perpendicular to the predetermined direction, the epitaxial layer has a first region and a second region surrounding the first region, and the barrier layer is located on the side of the epitaxial layer away from the substrate layer and embedded in the first region of the epitaxial layer;

[0007] A release layer is formed on one side of the Schottky diode chip having the barrier layer. The release layer has a first via, and the orthographic projection of the first via onto the plane of the barrier layer is located within the barrier layer. The diameter of the first via decreases linearly along a predetermined direction.

[0008] A first metal is evaporated on the side of the release layer away from the Schottky diode chip to form a first metal layer within the first via.

[0009] Peel off the peeling layer;

[0010] A second metal layer is formed on the side of the Schottky diode chip that does not have the first metal layer.

[0011] In this application, when fabricating a Schottky diode, a Schottky diode chip with a barrier layer is first provided. Then, a release layer is formed according to the position of the barrier layer, with the first via of the release layer aligned with the barrier layer. Thus, when a first metal layer is formed within the first via of the release layer, the first metal layer is aligned with the barrier layer, thereby serving as the anode of the Schottky diode. The diameter of the first via decreases linearly along the direction away from the Schottky diode chip, i.e., along a predetermined direction. In this case, the width of the first metal layer also decreases linearly along the predetermined direction. This reduces the bonding force between the release layer and the first metal layer, facilitating the removal of the release layer and thus increasing the fabrication rate of the Schottky diode.

[0012] Optionally, before forming a release layer on the side of the Schottky diode chip having the barrier layer, the method further includes:

[0013] A contact metal layer and a medium metal layer covering the contact metal layer are formed on one side of the Schottky diode chip having the barrier layer. The coverage area of ​​the orthogonal projection of the contact metal layer and the medium metal layer on the plane where the barrier layer is located is larger than that of the barrier layer. The medium metal layer is used to connect the contact metal layer and the first metal layer.

[0014] Vacuum bonding is performed on the contact metal layer and the medium metal layer to increase the bonding force between them.

[0015] Optionally, the Schottky diode chip further includes a guard ring located on the side of the epitaxial layer away from the substrate layer and covering a second region of the epitaxial layer; along the preset direction, the height of the barrier layer is lower than the height of the guard ring; along the direction perpendicular to the preset direction, the guard ring includes a third region and a fourth region surrounding the third region;

[0016] A contact metal layer and a dielectric metal layer covering the contact metal layer are formed on one side of the Schottky diode chip having the barrier layer, including:

[0017] A third metal is evaporated on the side of the barrier layer and the guard ring away from the Schottky diode chip to form a third metal layer. The third metal layer covers the surface of the barrier layer away from the substrate layer, the surface of the guard ring away from the epitaxial layer, and the inner surface of the guard ring.

[0018] A fourth metal is evaporated on the side of the third metal layer away from the Schottky diode chip to form a fourth metal layer, which covers the third metal layer;

[0019] A photoresist covering the fourth metal layer is formed, and the photoresist is photolithographically etched to form a patterned structure. Along the preset direction, the projection of the patterned structure overlaps with the projection of the fourth region.

[0020] The fourth metal layer is etched using the patterned structure to obtain the medium metal layer;

[0021] The third metal layer is etched using the patterned structure to obtain the contact metal layer.

[0022] Optionally, the first metal layer includes a plurality of sub-metal layers;

[0023] The material of the sub-metal layer closest to the medium metal layer among the plurality of sub-metal layers is the same as the material of the contact metal layer.

[0024] Optionally, after vacuum bonding the contact metal layer and the medium metal layer, the process further includes:

[0025] A passivation layer is formed on one side of the Schottky diode chip having the barrier layer. The passivation layer has a second via for exposing a portion of the surface of the medium metal layer. The orthogonal projection of the second via onto the plane of the barrier layer is located within the barrier layer.

[0026] Optionally, forming a release layer on the side of the Schottky diode chip having the barrier layer includes:

[0027] A release adhesive is formed on the side of the Schottky diode chip where the barrier layer is located.

[0028] The release adhesive is exposed, baked, and developed to form the release layer having the first through-hole.

[0029] Optionally, when exposing the release adhesive, the exposure energy is 180 megajoules to 190 megajoules;

[0030] When baking the release adhesive, the baking temperature is between 90 degrees Celsius and 110 degrees Celsius.

[0031] Optionally, the first metal includes titanium, nickel, and gold, and the first metal layer includes a first sub-metal layer, a second sub-metal layer, and a third sub-metal layer.

[0032] The step of evaporating a first metal on the side of the release layer away from the Schottky diode chip to form a first metal layer within the first via includes:

[0033] Titanium metal is evaporated on the side of the release layer away from the Schottky diode chip to form a first sub-metal layer;

[0034] Metallic nickel is evaporated on the side of the release layer away from the Schottky diode chip to form a second sub-metal layer;

[0035] Metallic gold is evaporated on the side of the release layer away from the Schottky diode chip to form a third sub-metal layer.

[0036] In a second aspect, a Schottky diode is provided, which is prepared by the preparation method described in any one of the first aspects, wherein the Schottky diode comprises: a Schottky diode chip, a first metal layer, and a second metal layer;

[0037] The Schottky diode chip includes a substrate layer, an epitaxial layer, and a barrier layer. The epitaxial layer and the substrate layer are stacked along a preset direction. Along a direction perpendicular to the preset direction, the epitaxial layer has a first region and a second region surrounding the first region. The barrier layer is located on the side of the epitaxial layer away from the substrate layer and is embedded in the first region of the epitaxial layer.

[0038] The first metal layer is located on the side of the barrier layer away from the Schottky diode chip, and the orthographic projection of the first metal layer onto the plane of the barrier layer is located within the barrier layer. The width of the first metal layer decreases linearly along a preset direction.

[0039] The second metal layer is located on the side of the Schottky diode chip that does not have the first metal layer.

[0040] Optionally, the Schottky diode chip further includes a guard ring located on the side of the epitaxial layer away from the substrate layer and covering a second region of the epitaxial layer; the guard ring includes a third region and a fourth region surrounding the third region along a direction perpendicular to the preset direction;

[0041] The Schottky diode further includes: a contact metal layer, a dielectric metal layer, and a passivation layer;

[0042] The contact metal layer covers the surface of the barrier layer away from the substrate layer, the third region, and the inner surface of the protective ring;

[0043] The medium metal layer covers the contact metal layer;

[0044] The first metal layer is located on the surface of the medium metal layer away from the Schottky diode chip.

[0045] The technical effects achieved by the second aspect are similar to those achieved by the corresponding technical means in the first aspect, and will not be repeated here. Attached Figure Description

[0046] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0047] Figures 1 to 5 This is a flowchart illustrating the fabrication process of a Schottky diode according to Embodiment 1 of this application;

[0048] Figure 6 This is a schematic cross-sectional view of a peeling layer provided in Embodiment 1 of this application;

[0049] Figure 7 This is a schematic diagram of the structure of a Schottky diode chip provided in Embodiment 2 of this application;

[0050] Figures 8 to 18 This is a flowchart illustrating the fabrication process of a Schottky diode chip according to Embodiment 2 of this application;

[0051] Figure 19 This is a cross-sectional structural diagram of a contact metal layer and a medium metal layer provided in Embodiment 2 of this application;

[0052] Figures 20 to 25 This is a flowchart illustrating the fabrication process of a contact metal layer and a dielectric metal layer, as provided in Embodiment 2 of this application.

[0053] Figure 26 This is a schematic diagram of the passivation layer provided in Embodiment 2 of this application;

[0054] Figures 27 to 28 This is a flowchart illustrating the preparation of a release layer according to Embodiment 2 of this application;

[0055] Figure 29 This is a schematic diagram of the structure of a Schottky diode provided in Embodiment 2 of this application;

[0056] Figures 30 to 32 This is a flowchart illustrating the preparation of a first metal layer according to Embodiment 2 of this application;

[0057] Figure 33 This is a schematic diagram of a peeling layer provided in Embodiment 2 of this application;

[0058] Figure 34This is a schematic diagram of the structure of the first Schottky diode provided in Embodiment 4 of this application;

[0059] Figure 35 This is a schematic diagram of the structure of the second type of Schottky diode provided in Embodiment 4 of this application.

[0060] The meanings of the various symbols in the attached icons are as follows:

[0061] 10. Schottky diode chip; 101. Photoresist; 102. First region; 104. Second region; 110. Substrate layer; 120. Epitaxial layer; 1202. Epitaxial prefabrication layer; 1204. Boron ring; 130. Barrier layer; 1302. Contact area pattern; 1304. Barrier metal; 140. Guard ring; 1402. Silicon dioxide film; 1404. Window pattern; 142. Third region; 144. Fourth region; 20. Schottky diode; 21. 0. Release layer; 212. First through-hole; 214. Release adhesive; 220. First metal; 222. First metal layer; 2222. First sub-metal layer; 2224. Second sub-metal layer; 2226. Third sub-metal layer; 230. Second metal layer; 240. Contact metal layer; 242. Third metal layer; 245. Patterned structure; 250. Medium metal layer; 252. Fourth metal layer; 260. Passivation layer; 262. Second through-hole; 272. Adhesive tape. Detailed Implementation

[0062] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0063] It should be understood that "multiple" as mentioned in this application refers to two or more. In the description of this application, unless otherwise stated, " / " indicates "or," for example, A / B can mean A or B; "and / or" in this document is merely a description of the relationship between related objects, indicating that three relationships can exist, for example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Furthermore, to facilitate a clear description of the technical solutions of this application, the terms "first," "second," etc., are used to distinguish identical or similar items with essentially the same function and effect. Those skilled in the art will understand that the terms "first," "second," etc., do not limit the quantity or execution order, and that "first," "second," etc., do not necessarily imply differences.

[0064] The fabrication method of the Schottky diode provided in the embodiments of this application will be explained in detail below with reference to the accompanying drawings.

[0065] Example 1:

[0066] Figures 1 to 5This is a flowchart illustrating the fabrication process of a Schottky diode 20 provided in Embodiment 1 of this application. Figures 1 to 5 As shown, the preparation method includes the following steps S110 to S150.

[0067] S110 provides Schottky diode chip 10.

[0068] The Schottky diode 20 includes a Schottky diode chip 10, a front electrode located on the front side of the Schottky diode chip 10, and a back electrode located on the back side of the Schottky diode chip 10. Therefore, in fabricating the Schottky diode 20, the Schottky diode chip 10 must first be provided. For example... Figure 1 As shown, the Schottky diode chip 10 includes a substrate layer 110, an epitaxial layer 120, and a barrier layer 130. The substrate layer 110 can be a heavily doped silicon substrate. The epitaxial layer 120 can be a lightly doped silicon epitaxial layer. That is, the doping concentration of the epitaxial layer 120 is less than the doping concentration of the substrate layer 110. The epitaxial layer 120 and the substrate layer 110 are stacked along a predetermined direction, which is the direction upwards along the paper in the figure. For ease of description, in this embodiment, a first direction X, a second direction (not shown in the figure, but the Y direction in a Cartesian coordinate system), and a third direction Z are defined. The first direction X, the second direction, and the third direction Z are all perpendicular to each other. The third direction Z is the predetermined direction. The plane formed by the first direction X and the second direction is perpendicular to the third direction Z.

[0069] Along a direction perpendicular to the third direction Z, i.e., along the plane formed by the first direction X and the second direction, the epitaxial layer 120 has a first region 102 and a second region 104. The second region 104 surrounds the first region 102. A barrier layer 130 is located on the side of the epitaxial layer 120 away from the substrate layer 110 and is embedded in the first region 102 of the epitaxial layer 120. The barrier layer 130 may be formed by combining a metal with the epitaxial layer 120.

[0070] S120, a stripping layer 210 is formed on one side of the Schottky diode chip 10 where the barrier layer 130 is located.

[0071] In the illustrated direction, a release layer 210 is formed above the Schottky diode chip 10. For example... Figure 2As shown, the release layer 210 has a first through-hole 212 for forming a first metal layer 222. That is, the release layer 210 defines the area for forming the first metal layer 222. The orthographic projection of the first through-hole 212 onto the plane of the barrier layer 130 lies within the barrier layer 130. The plane of the barrier layer 130 is the plane formed by the first direction X and the second direction. The orthographic projection of the first through-hole 212 onto the plane of the barrier layer 130 refers to the projection of the first through-hole 212 along the third direction Z (the opposite direction) onto the plane formed by the first direction X and the second direction. This projection lies within the barrier layer 130, meaning that the position of the first through-hole 212 is directly opposite the barrier layer 130, thereby ensuring that the first metal layer 222 formed within the first through-hole 212 in subsequent processes is directly above the barrier layer 130, and the coverage area of ​​the first metal layer 222 does not exceed the coverage area of ​​the barrier layer 130.

[0072] In this embodiment, the diameter of the first through hole 212 decreases linearly along the third direction Z. That is, in a cross-section along the third direction Z, the shape of the first through hole 212 is a trapezoid that is wider at the bottom and narrower at the top, and the two sides of this trapezoid can be curved inwards. In some specific embodiments, such as... Figure 2 As shown, the first through hole 212 is an isosceles trapezoid that is wider at the bottom and narrower at the top. In this case, the shape of the first through hole 212 can be either a frustum or a pyramid.

[0073] S130, the first metal 220 is evaporated on the side of the release layer 210 away from the Schottky diode chip 10 to form a first metal layer 222 in the first via 212.

[0074] After the release layer 210 is formed, the first metal 220 is evaporated on the side of the release layer 210 away from the Schottky diode chip 10. In this case, as... Figure 3 As shown, a portion of the first metal 220 is deposited within the first via 212, while the remaining first metal 220 is deposited on the surface of the release layer 210 away from the Schottky diode chip 10. The first metal 220 deposited within the first via 212 forms a first metal layer 222, which allows for carrier transport between itself and the barrier layer 130. In other words, the first metal layer 222 is the front electrode formed on the front side of the Schottky diode chip 10. The first metal 220 deposited on the surface of the release layer 210 has no function and needs to be removed. In this step, the first metal 220 is not limited to a single metal and can include multiple metals. The first metal layer 222 is also not limited to a single metal film layer and can include multiple sub-metal layers.

[0075] S140, peel off the peeling layer 210.

[0076] After the first metal layer 222 is formed, the release layer 210 can be peeled off. During this process, a high-viscosity adhesive tape can be adhered to the first metal 220 deposited on the surface of the release layer 210, thereby utilizing the adhesive properties of the tape to peel off the release layer 210. After the release layer 210 is peeled off, the non-functional first metal 220 deposited on the surface of the release layer 210 in step S130 will also be removed. At this point, the front electrode of the Schottky diode 20 is fabricated, and the resulting structure is as follows. Figure 4 As shown.

[0077] S150, a second metal layer 230 is formed on the side of the Schottky diode chip 10 that does not have the first metal layer 222.

[0078] The Schottky diode chip 10 has a first metal layer 222 on one side, which is the front side, and a second metal layer 230 on the other side, which is not covered by the first metal layer 222. A second metal layer 230 is formed on the back side of the Schottky diode chip 10, allowing for carrier transport between the second metal layer 230 and the chip. In other words, the second metal layer 230 serves as the back electrode on the back side of the Schottky diode chip 10. After fabricating the second metal layer 230, a Schottky diode 20 is obtained, and its structure can be as follows: Figure 5 As shown.

[0079] In this embodiment, when fabricating the Schottky diode 20, a Schottky diode chip 10 is first provided, which has a barrier layer 130. Then, a release layer 210 is formed according to the position of the barrier layer 130, with the first via 212 of the release layer 210 facing the barrier layer 130. Thus, when a first metal layer 222 is formed within the first via 212 of the release layer 210, the first metal layer 222 faces the barrier layer 130, thereby making the first metal layer 222 the anode of the Schottky diode 20. The diameter of the first via 212 decreases linearly along the direction away from the Schottky diode chip 10, i.e., along a predetermined direction (third direction Z). In this case, the width of the first metal layer 222 decreases linearly along the predetermined direction. This reduces the bonding force between the release layer 210 and the first metal layer 222, facilitating the removal of the release layer 210 and thus increasing the fabrication rate of the Schottky diode 20.

[0080] Understandably, in Figures 2 to 5 In the embodiments shown, only the case where the shape of the first through hole 212 is an isosceles trapezoid that is wider at the bottom and narrower at the top is shown. Figure 6 This is a cross-sectional structural diagram of a release layer 210 provided in Embodiment 1 of this application, as shown below. Figure 6As shown, in some other specific embodiments, the first through hole 212 is shaped as an isosceles trapezoid that is wider at the bottom and narrower at the top, and the two sides of the trapezoid are curved lines that bend inwards.

[0081] In the following embodiments, the method for fabricating the Schottky diode 20 of this application will continue to be described using the example of "the shape of the first through hole 212 being an isosceles trapezoid that is wider at the bottom and narrower at the top".

[0082] Example 2:

[0083] Figure 7 This is a schematic diagram of the structure of a Schottky diode chip 10 provided in Embodiment 2 of this application. Figure 7 As shown, the Schottky diode chip 10 also includes a guard ring 140. The guard ring 140 is annular and is located on the side of the epitaxial layer 120 away from the substrate layer 110, covering the second region 104 of the epitaxial layer 120. Generally, as... Figure 7 As shown, along the third direction Z, the height of the barrier layer 130 is lower than the height of the guard ring 140.

[0084] Figures 8 to 18 This is a flowchart illustrating the fabrication process of a Schottky diode chip 10 according to Embodiment 2 of this application. The following is in conjunction with... Figures 8 to 18 ,right Figure 7 The fabrication process of the Schottky diode chip 10 shown is explained in detail, specifically including the following steps S1101 to S1111.

[0085] S1101, an epitaxial prefabricated layer 1202 of a certain thickness is deposited on the substrate layer 110.

[0086] like Figure 8 As shown, step S1101 is epitaxy, that is, depositing a lightly doped silicon layer of a certain thickness on the heavily doped silicon substrate layer 110. To distinguish it from the epitaxial layer 120 mentioned above, the deposited lightly doped silicon layer is referred to as the epitaxial prefabrication layer 1202.

[0087] S1102, the epitaxial preform 1202 is oxidized to form a silicon dioxide film 1402 on the surface of the epitaxial preform 1202 away from the substrate layer 110.

[0088] like Figure 9 As shown, step S1102 is oxidation to form a silicon dioxide film 1402. The silicon dioxide film 1402 has the functions of masking and passivation protection.

[0089] S1103, photoresist 101 is formed on the surface of silicon dioxide film 1402 away from substrate layer 110, and photolithography is performed on photoresist 101 to form window pattern 1404.

[0090] Step S1103 is a single photolithography step. For example... Figure 10 As shown, photoresist 101 can first be formed on the surface of silicon dioxide film 1402 away from substrate layer 110. Then, photolithography (including exposure, development, and curing) is performed on photoresist 101 to form a window pattern 1404, such as... Figure 11 As shown. In Figure 11 In the structure shown, the portion without photoresist 101 after photolithography is the window pattern 1404. The extent of the window pattern 1404 in the horizontal plane (i.e., the plane formed by the first direction X and the second direction) can be slightly larger than the extent of the first region of the epitaxial prefabricated layer 1202 (i.e., the first region 102 of the epitaxial layer 120) in the horizontal plane, thus ensuring that the extent of the first region 102 in the horizontal plane is within the extent of the window pattern 1404 in the horizontal plane. In some specific embodiments, the extent of the first region 102 in the horizontal plane and the extent of the window pattern 1404 in the horizontal plane are concentric circles.

[0091] S1104, the silicon dioxide film 1402 is etched from the window pattern 1404 to form a protective ring 140.

[0092] Step S1104 involves silica etching. After etching, a protective ring 140 is formed, resulting in the structure shown below. Figure 12 As shown. Generally, after step S1104, the thickness of the silicon dioxide corresponding to the location of window pattern 1404 is less than 100 angstroms (1 angstrom is 0.1 nanometers).

[0093] S1105, boron is implanted into the epitaxial preform 1202.

[0094] like Figure 13 As shown, step S1105 is boron implantation, which involves implanting boron into the epitaxial prefabricated layer 1202 to form a boron ring 1204. Generally, along the horizontal plane, part of the boron ring 1204 is located in the first region 102, and another part is located in the second region 104. The portion of the boron ring 1204 located in the first region 102 needs to contact the barrier layer 130 in subsequent processes.

[0095] S1106 is used to anneal the structure formed after boron implantation.

[0096] The structure obtained in step S1105 is subjected to high-temperature annealing. Here, high temperature refers to above 1000℃ (degrees Celsius). This allows the impurities doped in the epitaxial prefabricated layer 1202 to diffuse and activate.

[0097] S1107, photoresist 101 is formed on the surface of silicon dioxide film 1402 away from substrate layer 110, and photolithography is performed on photoresist 101 to form contact area pattern 1302.

[0098] Step S1107 is a secondary photolithography process. For example... Figure 14 As shown, photoresist 101 can first be formed on the surface of silicon dioxide film 1402 away from substrate layer 110. Then, photolithography (including exposure, development, and curing) is performed on photoresist 101 to form contact area pattern 1302, such as... Figure 15 As shown. In Figure 15 In the structure shown, the portion without photoresist 101 after photolithography is the contact area pattern 1302. The range of the contact area pattern 1302 in the horizontal plane is the range of the first region 102 of the epitaxial preform layer 1202 (i.e., the first region 102 of the epitaxial layer 120) in the horizontal plane.

[0099] S1108, etching silicon dioxide from contact area pattern 1302.

[0100] like Figure 16 As shown, step S1108 is silicon dioxide etching. After etching, the silicon dioxide at the location of the contact area pattern 1302 can be removed, thereby exposing the surface of the first region 102 of the epitaxial preform 1202 (i.e., the first region 102 of the epitaxial layer 120) away from the substrate layer 110.

[0101] S1109, barrier metal 1304 is deposited in the first region 102 of the epitaxial preform 1202.

[0102] like Figure 17 As shown, step S1109 is barrier deposition, which involves depositing a barrier metal 1304 on the surface of the first region 102 of the epitaxial prefabricated layer 1202 away from the substrate layer 110 using vacuum evaporation or sputtering. The barrier metal 1304 can be one or more of nickel, platinum, and chromium. For example, the barrier metal 1304 can include 5% platinum and 95% nickel, or 10% platinum and 90% nickel, or 15% platinum and 85% nickel, or 30% platinum and 70% nickel, or 60% platinum and 40% nickel.

[0103] S1110, the structure formed after the precipitation of barrier metal 1304 is subjected to low temperature treatment so that the barrier metal 1304 and the epitaxial prefabricated layer 1202 are combined to form barrier layer 130.

[0104] Step S1110 is a barrier alloy, whereby the barrier metal 1304 and the epitaxial preform 1202 are combined to form the barrier layer 130. The low temperature here can be, for example, 450°C to 550°C.

[0105] S1111, etch the structure formed after the formation of barrier layer 130 to remove the barrier metal 1304 that has not formed an alloy.

[0106] Step S1111 is barrier etching, the purpose of which is to remove the barrier metal 1304 that is not bonded to the epitaxial prefabricated layer 1202. Generally, the structure formed in step S1110 can be etched using an etchant corresponding to the barrier metal 1304. Afterwards, the structure as shown in the image is obtained. Figure 18 The Schottky diode chip 10 shown is an example. After the barrier layer 130 is formed, the epitaxial prefabrication layer 1202 becomes the aforementioned epitaxial layer 120.

[0107] In some embodiments, step S110 may further include cleaning the Schottky diode chip 10. That is, the Schottky diode chip 10 may be cleaned with standard No. 3 solution or hydrofluoric acid (HF) to ensure the cleanliness of the surface of the Schottky diode chip 10.

[0108] In some embodiments, based on Figure 7 The structure of the Schottky diode chip 10 shown, and the method for fabricating the Schottky diode 20 provided in this application embodiment, further includes the following steps S160 and S170 before step S120.

[0109] S160, a contact metal layer 240 and a dielectric metal layer 250 covering the contact metal layer 240 are formed on one side of the Schottky diode chip 10 having a barrier layer 130.

[0110] After providing the Schottky diode chip 10 and before forming the release layer 210, a contact metal layer 240 and a dielectric metal layer 250 covering the contact metal layer 240 can be formed on the side of the Schottky diode chip 10 with the barrier layer 130 (i.e., the side for forming the release layer 210). The thickness of the contact metal layer 240 can be from 1000 angstroms to 3000 angstroms, and the thickness of the dielectric metal layer 250 can be from 20000 angstroms to 45000 angstroms. Figure 19 This is a cross-sectional structural diagram of a contact metal layer 240 and a medium metal layer 250 provided in Embodiment 2 of this application. Figure 19As shown, the coverage areas of the contact metal layer 240 and the medium metal layer 250 on the plane where the barrier layer 130 is located are both larger than the barrier layer 130. That is, the contact metal layer 240 and the medium metal layer 250 not only cover the barrier layer 130 but also a portion of the guard ring 140. The purpose of the contact metal layer 240 and the medium metal layer 250 only covering a portion of the guard ring 140 is to prevent the contact metal layers 240 and the medium metal layer 250 of two adjacent Schottky diodes 20 from connecting together. In this embodiment, along the plane direction formed by the first direction X and the second direction, the guard ring 140 can be divided into a third region 142 and a fourth region 144 surrounding the third region 142. The contact metal layer 240 and the medium metal layer 250 not only cover the barrier layer 130 but also cover the third region 142 of the guard ring 140. Thus, the contact metal layers 240 and the medium metal layer 250 of two adjacent Schottky diodes 20 can be prevented from connecting together.

[0111] The contact metal layer 240 is used to contact the Schottky diode chip 10. Here, the contact metal layer 240 can be made of a metal material with strong adhesion to the guard ring 140. The medium metal layer 250 is used to connect the contact metal layer 240 and the first metal layer 222; therefore, the medium metal layer 250 can be made of a metal material with strong adhesion to the contact metal layer 240. For example, in some specific embodiments, the contact metal layer 240 is a titanium layer, and the medium metal layer 250 is an aluminum layer. In this embodiment, in step S120, when forming the release layer 210, the release layer 210 can be formed on the side of the medium metal layer 250 away from the Schottky diode chip 10.

[0112] Figures 20 to 25 This is a flowchart illustrating the fabrication process of a contact metal layer 240 and a medium metal layer 250 according to Embodiment 2 of this application. The following is in conjunction with... Figures 20 to 25 ,right Figure 19 The preparation process of the structure shown is explained in detail, specifically including the following steps S161 to S165.

[0113] S161, a third metal is evaporated on the side of the barrier layer 130 and the guard ring 140 away from the Schottky diode chip 10 to form a third metal layer 242.

[0114] like Figure 20As shown, a third metal is evaporated on the side of the barrier layer 130 and the guard ring 140 away from the Schottky diode chip 10 to form a third metal layer 242. The third metal layer 242 completely covers the barrier layer 130 and the guard ring 140. That is, the third metal layer 242 covers the surface of the barrier layer 130 away from the substrate layer 110, the surface of the guard ring 140 away from the epitaxial layer 120, and the inner surface of the guard ring 140. The third metal layer 242 is used to form the contact metal layer 240.

[0115] S162, a fourth metal is evaporated on the side of the third metal layer 242 away from the Schottky diode chip 10 to form a fourth metal layer 252, which covers the third metal layer 242.

[0116] like Figure 21 As shown, a fourth metal is evaporated on the side of the third metal layer 242 away from the Schottky diode chip 10 to form a fourth metal layer 252, which covers the third metal layer 242. The fourth metal layer 252 is used to form the dielectric metal layer 250.

[0117] S163, a photoresist 101 covering the fourth metal layer 252 is formed, and the photoresist 101 is photolithographically formed to form a patterned structure 245.

[0118] Step S163 is a three-stage photolithography process. For example... Figure 22 As shown, a photoresist 101 covering the fourth metal layer 252 can be formed first. Then, photolithography (including exposure, development, and curing) is performed on the photoresist 101 to form a patterned structure 245. Along the third direction Z, the projection of the patterned structure 245 overlaps with the projection of the fourth region 144, as shown... Figure 23 As shown. In Figure 23 In the structure shown, the portion without photoresist 101 after photolithography is a patterned structure 245.

[0119] S164, the fourth metal layer 252 is etched through the patterned structure 245 to obtain the medium metal layer 250.

[0120] S165, the third metal layer 242 is etched through the patterned structure 245 to obtain the contact metal layer 240.

[0121] By sequentially etching the fourth metal layer 252 and the third metal layer 242 through the patterned structure 245, the portions of the fourth metal layer 252 and the third metal layer 242 covering the fourth region 144 of the protective ring 140 can be etched away. Therefore, after etching the fourth metal layer 252, the medium metal layer 250 is obtained; after etching the third metal layer 242, the contact metal layer 240 is obtained, such as... Figure 24 As shown.

[0122] After obtaining the dielectric metal layer 250 and the contact metal layer 240, the cured photoresist 101 is removed to obtain the following: Figure 25 The structure shown is such that the portion of the third region 142 of the protective ring 140 covered by the contact metal layer 240 and the dielectric metal layer 250 can act as a voltage divider, thereby improving the voltage withstand performance of the Schottky diode 20.

[0123] S170, vacuum bonding is performed on the contact metal layer 240 and the medium metal layer 250 to increase the bonding force between the contact metal layer 240 and the medium metal layer 250.

[0124] As previously described, the medium metal layer 250 is used to connect the contact metal layer 240 and the first metal layer 222. Therefore, the contact metal layer 240 and the medium metal layer 250 can be vacuum bonded to increase the bonding force between them. Generally, the structure obtained after step S160 can be placed in a vacuum environment and a temperature of 400°C can be applied for 30 minutes to vacuum bond the contact metal layer 240 and the medium metal layer 250.

[0125] In some embodiments, after step S170 and before step S120, the following step S180 may also be included.

[0126] S180, a passivation layer 260 is formed on one side of the Schottky diode chip 10 where the barrier layer 130 is located. The passivation layer 260 has a second via 262 for exposing a portion of the surface of the dielectric metal layer 250. The orthogonal projection of the second via 262 onto the plane of the barrier layer 130 lies within the barrier layer 130. The material of the passivation layer 260 may be polyimide.

[0127] Figure 26 This is a schematic diagram of the passivation layer 260 provided in Embodiment 2 of this application. Figure 26 As shown, before forming the release layer 210, a passivation layer 260 for covering the contact metal layer 240 and the medium metal layer 250 can be formed first. The passivation layer 260 has a second via 262 for exposing a portion of the surface of the medium metal layer 250. The orthogonal projection of the second via 262 onto the plane of the barrier layer 130 lies within the barrier layer 130. That is, along the third direction Z (opposite direction), the projection of the second via 262 onto the plane of the barrier layer 130 lies within the barrier layer 130.

[0128] Figures 27 to 28 This is a flowchart illustrating the preparation process of a release layer 210 according to Embodiment 2 of this application. Figures 27 to 28 As shown, in some embodiments, step S120 specifically includes the following steps S122 and S124.

[0129] S122, a release adhesive 214 is formed on one side of the Schottky diode chip 10 where the barrier layer 130 is located.

[0130] like Figure 27 As shown, after forming the contact metal layer 240, the medium metal layer 250, and the passivation layer 260 on the front side of the Schottky diode chip 10, a release adhesive 214 (a material used to form the release layer 210) needs to be formed first to form the release layer 210. The release adhesive 214 covers the passivation layer 260 and fills the second via 262 of the passivation layer 260. In some specific embodiments, the release adhesive 214 is a negative photoresist 101.

[0131] S124, the release adhesive 214 is exposed, baked and developed to form a release layer 210 with a first through hole 212.

[0132] After the release adhesive 214 is formed, it can be exposed, baked, and developed to give the remaining release adhesive 214 a predetermined shape, thus obtaining the desired result. Figure 28 The release layer 210 is shown. During the process, the shape of the first through-hole 212 can be controlled by adjusting the exposure energy and baking temperature. In this embodiment, to make the first through-hole 212 a trapezoid with a wider bottom and a narrower top, the exposure energy when exposing the release adhesive 214 can be between 180 megajoules and 190 megajoules. For example, the exposure energy can be 180 megajoules, 185 megajoules, or 190 megajoules. When baking the release adhesive 214, the baking temperature can be between 90°C and 110°C. For example, the baking temperature can be 90°C, 100°C, or 110°C.

[0133] Figure 29 This is a schematic diagram of the structure of a Schottky diode 20 provided in Embodiment 2 of this application. Figure 29 As shown, in some embodiments, the first metal layer 222 includes a plurality of sub-metal layers, wherein the material of the sub-metal layer closest to the medium metal layer 250 is the same as the material of the contact metal layer 240.

[0134] As described above, the medium metal layer 250 is used to connect the contact metal layer 240 and the first metal layer 222, and the medium metal layer 250 is made of a metal material with a strong bonding force to the contact metal layer 240. Therefore, when the material of the sub-metal layer near the medium metal layer 250 in the first metal layer 222 is the same as the material of the contact metal layer 240, the bonding force between the first metal layer 222 and the medium metal layer 250 can be relatively large. Figure 29In the illustrated embodiment, the first metal layer 222 includes a first sub-metal layer 2222, a second sub-metal layer 2224, and a third sub-metal layer 2226 stacked along a third direction Z. That is, the first sub-metal layer 2222 is the sub-metal layer of the first metal layer 222 that is closest to the medium metal layer 250. In this case, the first metal 220 may include titanium, nickel, and gold, wherein titanium is used to form the first sub-metal layer 2222, nickel is used to form the second sub-metal layer 2224, and gold is used to form the third sub-metal layer 2226.

[0135] Figures 30 to 32 This is a flowchart illustrating the fabrication process of a first metal layer 222 according to Embodiment 2 of this application. Figures 30 to 32 As shown, step S130 may specifically include the following steps S132 to S136.

[0136] S132, evaporate metallic titanium on the side of the stripping layer 210 away from the Schottky diode chip 10 to form a first sub-metal layer 2222.

[0137] like Figure 30 As shown, titanium metal is evaporated on the side of the release layer 210 away from the Schottky diode chip 10, and deposited within the first via 212 to form a first sub-metal layer 2222. The thickness of the first sub-metal layer can be from 1000 angstroms to 3000 angstroms.

[0138] S134, evaporate metallic nickel on the side of the stripping layer 210 away from the Schottky diode chip 10 to form a second sub-metal layer 2224.

[0139] like Figure 31 As shown, nickel metal is evaporated on the side of the release layer 210 away from the Schottky diode chip 10, and the nickel metal deposited in the first via 212 forms a second sub-metal layer 2224. The thickness of the second sub-metal layer 2224 can be from 3000 angstroms to 8000 angstroms.

[0140] S136, evaporate metallic gold on the side of the stripping layer 210 away from the Schottky diode chip 10 to form a third sub-metal layer 2226.

[0141] like Figure 32 As shown, gold is evaporated on the side of the release layer 210 away from the Schottky diode chip 10, and the gold deposited in the first via 212 forms a third sub-metal layer 2226. The thickness of the third sub-metal layer 2226 can be from 300 angstroms to 1000 angstroms.

[0142] Figure 33 This is a schematic diagram of a peeling layer 210 provided in Embodiment 2 of this application. Figure 33As shown, step S140 can specifically involve: attaching a high-viscosity adhesive tape 272 to the first metal 220 deposited on the surface of the release layer 210; simultaneously peeling off the adhesive tape 272, using its adhesive properties to remove the release layer 210. Afterwards, if any remaining release layer 210 remains, it can be dissolved using a desiccant. After completely removing the release layer 210, step S150 is then performed to obtain the desired product. Figure 29 The Schottky diode 20 shown is an example.

[0143] Before performing step S150, the substrate 110 can be polished and thinned so that the thickness of the polished and thinned substrate 110 is between 240 micrometers and 290 micrometers.

[0144] In this embodiment, the gold is not etched during the formation of the first metal layer 222, thus reducing the risk of contamination from gold ions. Furthermore, the first metal layer 222 is composed of a titanium layer, a nickel layer, and a gold layer, without the introduction of silver. This avoids the problem of film detachment caused by weak adhesion between silver and other film layers, thereby improving the product reliability of the Schottky diode 20.

[0145] The fabrication method of Schottky diode 20 will be described in detail below with reference to the accompanying drawings, using a specific embodiment.

[0146] Example 3:

[0147] The fabrication method of Schottky diode 20 includes the following steps:

[0148] S1, an epitaxial prefabricated layer 1202 of a certain thickness is deposited on the substrate layer 110, such as Figure 8 As shown.

[0149] S2, the epitaxial preform 1202 is oxidized to form a silicon dioxide film 1402 on the surface of the epitaxial preform 1202 away from the substrate layer 110, such as Figure 9 As shown.

[0150] S3, a photoresist 101 is formed on the surface of the silicon dioxide film 1402 away from the substrate layer 110, and photolithography is performed on the photoresist 101 to form a window pattern 1404, such as... Figure 10 and Figure 11 As shown.

[0151] S4, etching is performed on the silicon dioxide film 1402 from the window pattern 1404 to form a protective ring 140, such as Figure 12 As shown.

[0152] S5, Boron implantation is performed on the epitaxial prefabricated layer 1202, such as Figure 13 As shown.

[0153] S6, Annealing.

[0154] S7, a photoresist 101 is formed on the surface of the silicon dioxide film 1402 away from the substrate layer 110, and photolithography is performed on the photoresist 101 to form a contact area pattern 1302, such as... Figure 14 and Figure 15 As shown.

[0155] S8, etching of silicon dioxide from contact area pattern 1302, such as Figure 16 As shown.

[0156] S9, in the first region 102 of the epitaxial prefabricated layer 1202, a barrier metal 1304 is deposited, such as Figure 17 As shown.

[0157] S10, the structure formed after the precipitation of barrier metal 1304 is subjected to low temperature treatment so that the barrier metal 1304 and the epitaxial prefabricated layer 1202 are combined to form barrier layer 130.

[0158] S11, the structure formed after the formation of barrier layer 130 is etched to remove the barrier metal 1304 that has not formed an alloy, to obtain as shown. Figure 18 The structure shown.

[0159] S12. Use standard No. 3 solution or hydrofluoric acid to clean the Schottky diode chip 10 to ensure the cleanliness of the surface of the Schottky diode chip 10.

[0160] S13, a third metal is evaporated on the side of the barrier layer 130 and the guard ring 140 away from the Schottky diode chip 10, forming a third metal layer 242, as shown below. Figure 20 As shown. A fourth metal is evaporated on the side of the third metal layer 242 away from the Schottky diode chip 10, forming a fourth metal layer 252. The fourth metal layer 252 covers the third metal layer 242, as shown. Figure 21 As shown.

[0161] S14, a photoresist 101 covering the fourth metal layer 252 is formed, and photolithography is performed on the photoresist 101 to form a patterned structure 245, such as... Figure 22 and Figure 23 As shown.

[0162] S15, the fourth metal layer 252 and the third metal layer 242 are etched through the patterned structure 245 to obtain the medium metal layer 250 and the contact metal layer 240, such as Figure 24 As shown. Remove photoresist 101, as... Figure 25 As shown.

[0163] S16, vacuum bonding is performed on the contact metal layer 240 and the medium metal layer 250 to increase the bonding force between the contact metal layer 240 and the medium metal layer 250.

[0164] S17, a passivation layer 260 is formed on one side of the Schottky diode chip 10 where the barrier layer 130 is located. The passivation layer 260 has a second via 262, which is used to expose a portion of the surface of the dielectric metal layer 250. The orthographic projection of the second via 262 onto the plane of the barrier layer 130 is located within the barrier layer 130. Figure 26 As shown.

[0165] S18, a release adhesive 214 is formed on one side of the Schottky diode chip 10 where the barrier layer 130 is located, such as... Figure 27 As shown. The release adhesive 214 is exposed, baked, and developed to form a release layer 210 with a first through-hole 212, as shown. Figure 28 As shown.

[0166] S19, titanium metal is evaporated on the side of the release layer 210 away from the Schottky diode chip 10 to form a first sub-metal layer 2222, as shown. Figure 30 As shown, metallic nickel is evaporated on the side of the release layer 210 away from the Schottky diode chip 10 to form a second sub-metal layer 2224, as shown. Figure 31 As shown, metallic gold is evaporated on the side of the release layer 210 away from the Schottky diode chip 10 to form a third sub-metal layer 2226, as shown. Figure 32 As shown.

[0167] S20, peel off the peeling layer 210 and peel off the non-functional first metal 220 deposited on the surface of the peeling layer 210, such as Figure 33 As shown.

[0168] S21, thinning of substrate 110.

[0169] S22, a second metal layer 230 is formed on the side of the Schottky diode chip 10 that does not have the first metal layer 222 as a back electrode, resulting in... Figure 29 The Schottky diode 20 shown is an example.

[0170] Example 4:

[0171] This application also provides a Schottky diode 20, which is prepared by the preparation method in any of the above embodiments.

[0172] Specifically Figure 34 This is a schematic diagram of the structure of a Schottky diode 20 provided in Embodiment 4 of this application. Figure 34As shown, the Schottky diode 20 includes a Schottky diode chip 10, a first metal layer 222, and a second metal layer 230. The Schottky diode chip 10 includes a substrate layer 110, an epitaxial layer 120, and a barrier layer 130, with the epitaxial layer 120 and the substrate layer 110 stacked along a predetermined direction. Along a direction perpendicular to the predetermined direction, the epitaxial layer 120 has a first region 102 and a second region 104 surrounding the first region 102. The barrier layer 130 is located on the side of the epitaxial layer 120 away from the substrate layer 110 and is embedded in the first region 102 of the epitaxial layer 120. The first metal layer 222 is located on the side of the barrier layer 130 away from the Schottky diode chip 10, and the orthographic projection of the first metal layer 222 onto the plane of the barrier layer 130 lies within the barrier layer 130. The width of the first metal layer 222 decreases linearly along the predetermined direction. The second metal layer 230 is located on the side of the Schottky diode chip 10 without the first metal layer 222.

[0173] Figure 35 This is a schematic diagram of another Schottky diode 20 provided in Embodiment 4 of this application. Figure 35 As shown, in some embodiments, the Schottky diode chip 10 further includes a guard ring 140 located on the side of the epitaxial layer 120 away from the substrate layer 110 and covering a second region 104 of the epitaxial layer 120. Along a direction perpendicular to the third direction Z, the guard ring 140 includes a third region 142 and a fourth region 144 surrounding the third region 142.

[0174] The Schottky diode 20 further includes a contact metal layer 240, a dielectric metal layer 250, and a passivation layer 260. The contact metal layer 240 covers the surface of the barrier layer 130 away from the substrate layer 110, the third region 142, and the inner surface of the guard ring 140. The dielectric metal layer 250 covers the contact metal layer 240. A first metal layer 222 is located on the surface of the dielectric metal layer 250 away from the Schottky diode chip 10.

[0175] In some embodiments, such as Figure 35 As shown, the first metal layer 222 includes a first sub-metal layer 2222, a second sub-metal layer 2224, and a third sub-metal layer 2226 stacked along a third-direction Z-layer. The first sub-metal layer 2222 and the contact metal layer 240 are titanium layers, with the contact metal layer 240 having a thickness of 1000 angstroms to 3000 angstroms, and the first sub-metal layer 2222 having a thickness of 1000 angstroms to 3000 angstroms. The medium metal layer 250 is an aluminum layer with a thickness of 20000 angstroms to 45000 angstroms. The second sub-metal layer 2224 is a nickel layer with a thickness of 3000 angstroms to 8000 angstroms. The third sub-metal layer 2226 is a gold layer with a thickness of 300 angstroms to 1000 angstroms.

[0176] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A method for fabricating a Schottky diode, characterized in that, include: A Schottky diode chip is provided, the Schottky diode chip comprising a substrate layer, an epitaxial layer and a barrier layer, wherein the epitaxial layer and the substrate layer are stacked along a predetermined direction; Along a direction perpendicular to the preset direction, the epitaxial layer has a first region and a second region surrounding the first region, and the barrier layer is located on the side of the epitaxial layer away from the substrate layer and embedded in the first region of the epitaxial layer; A release layer is formed on one side of the Schottky diode chip having the barrier layer, the release layer having a first via, the orthogonal projection of the first via onto the plane of the barrier layer being located within the barrier layer; Along a predetermined direction, the diameter of the first through hole decreases linearly; A first metal is evaporated on the side of the release layer away from the Schottky diode chip to form a first metal layer within the first via. Peel off the peeling layer; A second metal layer is formed on the side of the Schottky diode chip that does not have the first metal layer; The Schottky diode chip further includes a guard ring, which is located on the side of the epitaxial layer away from the substrate layer and covers a second region of the epitaxial layer; along the preset direction, the height of the barrier layer is lower than the height of the guard ring; Before forming a stripping layer on the side of the Schottky diode chip having the barrier layer, the method further includes: A contact metal layer and a medium metal layer covering the contact metal layer are formed on one side of the Schottky diode chip having the barrier layer. The coverage area of ​​the contact metal layer and the medium metal layer in the orthographic projection of the plane where the barrier layer is located is larger than that of the barrier layer. The medium metal layer is used to connect the contact metal layer and the first metal layer. In a direction perpendicular to the preset direction, the protective ring includes a third region and a fourth region surrounding the third region. The contact metal layer covers the barrier layer, the third region of the protective ring, and the inner surface of the protective ring, and the contact metal layer does not cover the fourth region of the protective ring. Vacuum bonding of the contact metal layer and the medium metal layer is performed in a vacuum environment of 400 degrees Celsius for 30 minutes to increase the bonding force between the contact metal layer and the medium metal layer. The step of forming a stripping layer on one side of the Schottky diode chip having the barrier layer includes: A release adhesive is formed on the side of the Schottky diode chip where the barrier layer is located. The release adhesive is exposed, baked, and developed to form the release layer having the first through-hole, wherein the exposure energy of the release adhesive is 180 megajoules to 190 megajoules, and the baking temperature of the release adhesive is 90 degrees Celsius to 110 degrees Celsius.

2. The method for fabricating a Schottky diode as described in claim 1, characterized in that, A contact metal layer and a dielectric metal layer covering the contact metal layer are formed on one side of the Schottky diode chip having the barrier layer, including: A third metal is evaporated on the side of the barrier layer and the guard ring away from the Schottky diode chip to form a third metal layer. The third metal layer covers the surface of the barrier layer away from the substrate layer, the surface of the guard ring away from the epitaxial layer, and the inner surface of the guard ring. A fourth metal is evaporated on the side of the third metal layer away from the Schottky diode chip to form a fourth metal layer, which covers the third metal layer; A photoresist covering the fourth metal layer is formed, and the photoresist is photolithographically etched to form a patterned structure. Along the preset direction, the projection of the patterned structure overlaps with the projection of the fourth region. The fourth metal layer is etched using the patterned structure to obtain the medium metal layer; The third metal layer is etched using the patterned structure to obtain the contact metal layer.

3. The method for fabricating a Schottky diode as described in claim 1, characterized in that, The first metal layer includes multiple sub-metal layers; The material of the sub-metal layer closest to the medium metal layer among the plurality of sub-metal layers is the same as the material of the contact metal layer.

4. The method for fabricating a Schottky diode as described in claim 1, characterized in that, After vacuum bonding the contact metal layer and the medium metal layer, the process further includes: A passivation layer is formed on one side of the Schottky diode chip having the barrier layer. The passivation layer has a second via for exposing a portion of the surface of the medium metal layer. The orthogonal projection of the second via onto the plane of the barrier layer is located within the barrier layer.

5. The method for fabricating a Schottky diode as described in any one of claims 1 to 4, characterized in that, The first metal includes titanium, nickel and gold, and the first metal layer includes a first sub-metal layer, a second sub-metal layer and a third sub-metal layer; The step of evaporating a first metal on the side of the release layer away from the Schottky diode chip to form a first metal layer within the first via includes: Titanium metal is evaporated on the side of the release layer away from the Schottky diode chip to form a first sub-metal layer; Metallic nickel is evaporated on the side of the release layer away from the Schottky diode chip to form a second sub-metal layer; Metallic gold is evaporated on the side of the release layer away from the Schottky diode chip to form a third sub-metal layer.

6. A Schottky diode, prepared by the method according to any one of claims 1 to 5, characterized in that, The Schottky diode includes: a Schottky diode chip, a first metal layer, and a second metal layer; The Schottky diode chip includes a substrate layer, an epitaxial layer, and a barrier layer. The epitaxial layer and the substrate layer are stacked along a preset direction. Along a direction perpendicular to the preset direction, the epitaxial layer has a first region and a second region surrounding the first region. The barrier layer is located on the side of the epitaxial layer away from the substrate layer and is embedded in the first region of the epitaxial layer. The first metal layer is located on the side of the barrier layer away from the Schottky diode chip, and the orthographic projection of the first metal layer onto the plane of the barrier layer is located within the barrier layer. The width of the first metal layer decreases linearly along a preset direction. The second metal layer is located on the side of the Schottky diode chip that does not have the first metal layer; The Schottky diode chip further includes a guard ring, which is located on the side of the epitaxial layer away from the substrate layer and covers a second region of the epitaxial layer; along the preset direction, the height of the barrier layer is lower than the height of the guard ring; along the direction perpendicular to the preset direction, the guard ring includes a third region and a fourth region surrounding the third region; The Schottky diode further includes a contact metal layer and a dielectric metal layer, wherein the coverage area of ​​the orthogonal projection of the contact metal layer and the dielectric metal layer on the plane where the barrier layer is located is greater than that of the barrier layer, and the dielectric metal layer is used to connect the contact metal layer and the first metal layer; wherein the contact metal layer covers the barrier layer, the third region of the guard ring and the inner surface of the guard ring, and the contact metal layer does not cover the fourth region of the guard ring; the dielectric metal layer covers the contact metal layer.

7. The Schottky diode as described in claim 6, characterized in that, The Schottky diode further includes: a passivation layer; the passivation layer is located on the side of the Schottky diode chip having the barrier layer, the passivation layer has a second via, the second via is used to expose a portion of the surface of the medium metal layer, the orthogonal projection of the second via onto the plane of the barrier layer is located within the barrier layer; the first metal layer is located within the second via.

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