Method for manufacturing MOS device

Abstract

This application discloses a method for fabricating a MOS device, comprising: providing a substrate including a cell region and a termination region, forming a first trench in the substrate of the cell region and forming a second trench in the substrate of the termination region; forming a first dielectric layer on the surface of the substrate, the first trench, and the second trench; forming a first shielding gate in the first trench and a second shielding gate in the second trench; forming a second dielectric layer that fills the first trench but does not fill the second trench, the second dielectric layer being a conformal dielectric layer; removing the first dielectric layer and the second dielectric layer from regions other than a target region, the target region including the sidewalls of the second trench and the region above the first shielding gate in the first trench; forming a third dielectric layer on the sidewalls of the first trench; filling the first trench and the second trench with polysilicon layers, the polysilicon layer in the first trench constituting the gate of the MOS device, and the polysilicon layer in the second trench constituting the gate of the termination structure.

Description

Technical Field

[0001] This application relates to the field of semiconductor integrated circuit manufacturing technology, specifically to a method for fabricating a MOS device. Background Technology

[0002] Metal-oxide-semiconductor field-effect transistors (MOSFETs, referred to as "MOS" in this application) are electronic devices used in analog and digital circuits.

[0003] Among them, trench MOS devices, due to their lower on-resistance and gate-drain charge density, exhibit lower conduction and switching losses, as well as faster switching speeds. They are commonly used as power devices (also known as "electronic power devices") in consumer electronics, new energy vehicles, servers, and control equipment. Typically, on wafers integrating trench MOS devices, the surface electric field of the devices can be reduced by setting termination structures.

[0004] refer to Figure 1 This illustrates a cross-sectional schematic diagram of a trench-type MOS device provided in the related art. For example, such as... Figure 1 As shown, the substrate 110 includes a cell region 101 and a termination region 102. The cell region 101 is used to integrate MOS devices, and the termination region 102 is used to integrate termination structures. A doped region 111 is formed on the substrate 110. A first shielding gate structure is formed in the doped region 111 of the cell region 101 and the substrate 110. The first shielding gate structure includes, from the inside out, a first gate dielectric layer 121 and a polysilicon gate of the MOS device. The polysilicon gate includes a first shielding gate 131 and a first gate 132 located above the first shielding gate 131. The first shielding gate 131 and the first gate The electrodes 132 are isolated by a first gate dielectric layer 121. Heavily doped regions 1121 and 1122 are formed in the doped regions 111 on both sides of the first shielding gate structure. A second shielding gate structure is formed in the doped region 111 of the terminal region 102 and the substrate 110. The second shielding gate structure includes a second gate dielectric layer 122 and a polysilicon gate of the terminal structure from the inside out. The polysilicon gate includes a second shielding gate 133 and a second gate 134 located above the second shielding gate 133. The second shielding gate 133 and the second gate 134 are isolated by the second gate dielectric layer 122. Since the sidewall regions of the first gate dielectric layer 121 and the second gate dielectric layer 122 are formed simultaneously, the sidewall region of the second gate dielectric layer 122 is relatively thin and easily... Figure 1 The area indicated by the dashed ellipse in the middle is where the breakdown occurs.

[0005] In view of this, the related technology provides a method for fabricating a trench-type MOS device, in which after the polysilicon layer is etched back, the dielectric layer is continued to be filled and the cell region and the terminal region are simultaneously etched back, and then the barrier layer is selectively oxidized, thereby forming a thicker gate dielectric layer on the sidewall of the terminal structure.

[0006] refer to Figures 2 to 5 It shows a schematic diagram of a method for fabricating a trench-type MOS device provided in the related art: as shown Figure 2 As shown, a first trench 1011 and a second trench 1012 are formed in the substrate 110. The first trench 1011 is used to form a first shielding gate structure, and the second trench 1012 is used to form a second shielding gate structure. A first dielectric layer 1201 is formed on the surface of the substrate 110 and the trenches (first trench 1011 and second trench 1012). After sequentially depositing a polysilicon layer and etching, the remaining polysilicon layer in the first trench 1011 forms the first shielding gate 131, and the remaining polysilicon layer in the second trench 1012 forms the second shielding gate 133. Figure 3 As shown, a second dielectric layer 1202 is filled into trenches 1011 and 1022, and the dielectric layer outside the trenches is removed; as Figure 4 As shown, a barrier layer 140 is formed on the substrate 110, and photoresist is coated on the barrier layer 140 by photolithography. Figure 4 (Not shown in the image), exposing the area above the first trench 1011 and the second trench 1012, wherein the first trench 1011 is a repeating unit of multiple trenches of the same size connected in parallel ( Figures 2 to 5 (Using one unit as an example), the upper part needs to be exposed simultaneously. Therefore, the width W1 of the area exposed above the first trench 1011 is greater than the width W2 of the area exposed above the second trench 1012. Etching is performed to remove the dielectric layer above the first shielding gate 131 in the first trench 1011 and to remove the dielectric layer in the middle region above the second shielding gate 133 in the second trench 1012. The remaining dielectric layer in the second trench 1012 forms the second gate dielectric layer 122 of the terminal structure; as shown... Figure 5 As shown, a third dielectric layer is subsequently formed on the sidewall above the first shielding gate 131. The third dielectric layer and the remaining first dielectric layer 1201 form the first gate dielectric layer 121 of the MOS device. A first gate 132 is formed above the first shielding gate 131, and a second gate 134 is formed above the second shielding gate 133. A doped region 111 is formed in the substrate 110, and heavily doped regions 1121 and 1122 are formed in the doped regions 111 on both sides of the first shielding gate structure.

[0007] As can be seen from the above, although the relevant technologies have increased the thickness of the sidewall gate dielectric layer of the terminal structure, it is necessary to open windows of different sizes above the first trench and the second trench during its fabrication process. As the size of the second trench 1012 continues to decrease, the exposed area above the second trench is greatly affected by the overlay error of the photolithography process, resulting in a low yield. Summary of the Invention

[0008] This application provides a method for fabricating a MOS device, which can solve the problem of low yield caused by the large influence of overlay error in the fabrication method of trench MOS device provided in the related art. The method includes:

[0009] A substrate is provided, which, when viewed from a top view, includes a cell region and a termination region. The cell region is used to integrate MOS devices, and the termination region is used to integrate termination structures. A first trench is formed in the substrate of the cell region, and a second trench is formed in the substrate of the termination region. The width of the second trench is greater than the width of the first trench. A first dielectric layer is formed on the surfaces of the substrate, the first trench, and the second trench. A first shielding gate is formed in the first trench, and a second shielding gate is formed in the second trench. The top of the first shielding gate is lower than the opening of the first trench, and the top of the second shielding gate is lower than the opening of the second trench.

[0010] A second dielectric layer is formed, which fills the first trench but does not fill the second trench. The second dielectric layer is a conformal dielectric layer.

[0011] Remove the first and second dielectric layers from areas other than the target area, wherein the target area includes the sidewall of the second trench, the area above the second shielding grid in the second trench, and the area above the first shielding grid in the first trench.

[0012] A third dielectric layer is formed on the sidewall of the first trench;

[0013] Polysilicon layers are filled in the first trench and the second trench. The polysilicon layer in the first trench forms a first gate, which is the gate of the MOS device. The polysilicon layer in the second trench forms a second gate, which is the gate of the termination structure.

[0014] In some embodiments, removing the first and second dielectric layers from regions other than the target region includes:

[0015] Photoresist is applied to a predetermined area above the second trench using a photolithography process;

[0016] Etching is performed to remove the first and second dielectric layers in areas other than the target area;

[0017] Remove light resistance.

[0018] In some embodiments, the width of the predetermined region is greater than the width of the second trench.

[0019] In some embodiments, removing the first and second dielectric layers from regions other than the target region includes:

[0020] The second trench is filled with photoresist using a photolithography process;

[0021] Etching is performed to remove the second dielectric layer excluding the first trench and the second trench;

[0022] Photoresist is applied to a predetermined area above the second trench using a photolithography process;

[0023] Etching is performed to remove the first and second dielectric layers in areas other than the target area;

[0024] Remove light resistance.

[0025] In some embodiments, after filling the first trench and the second trench with a polysilicon layer, the method further includes:

[0026] A doped region is formed in the substrate;

[0027] Heavily doped regions are formed in the doped regions on both sides of the first shielding gate and the first gate.

[0028] In some embodiments, the first dielectric layer, the second dielectric layer, and the third dielectric layer include an oxide layer.

[0029] In some embodiments, the types of impurities incorporated into the doped region and the heavily doped region are different.

[0030] The technical solution of this application has at least the following advantages:

[0031] In the fabrication of trench-type MOS devices, after forming the shielding gate of the MOS device and the shielding gate of the termination structure, a dielectric layer is formed to fill the trench of the MOS device, and the trench sidewalls of the termination structure are thickened. By removing the dielectric layer in the trench of the MOS device but not the dielectric layer in the termination structure, a thinner sidewall dielectric layer is formed in the trench of the MOS device. Then, the gate of the MOS device and the termination structure are formed through subsequent steps. Since it is not necessary to use photomasks of different window sizes for etching, it is less affected by overlay errors and has a higher yield. Attached Figure Description

[0032] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0033] Figure 1 This is a cross-sectional schematic diagram of a trench-type MOS device provided in related technologies;

[0034] Figures 2 to 5 This is a schematic diagram of the formation of a trench-type MOS device provided in related technologies;

[0035] Figure 6 This is a flowchart of a method for fabricating a MOS device according to an exemplary embodiment of this application;

[0036] Figures 7 to 15 This is a schematic diagram of the formation of the MOS device provided in the embodiments of this application. Detailed Implementation

[0037] The technical solutions of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0038] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0039] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0040] Furthermore, the technical features involved in the different embodiments of this application described below can be combined with each other as long as they do not conflict with each other.

[0041] refer to Figure 6 It illustrates a flowchart of a method for fabricating a MOS device according to an exemplary embodiment of this application, such as... Figure 6 As shown, the method includes:

[0042] Step S1: A substrate is provided, the substrate including a cell region and a terminal region, a first trench is formed in the substrate of the cell region, a second trench is formed in the substrate of the terminal region, a first dielectric layer is formed on the surface of the substrate, the first trench and the second trench, a first shielding gate is formed in the first trench and a second shielding gate is formed in the second trench.

[0043] refer to Figure 7 It shows a schematic cross-sectional view after the formation of the first and second shielding gates. For example, as shown... Figure 7 As shown, viewed from a top view, the substrate 310 includes a cell region 301 and a terminal region 302. The cell region 301 is used to integrate MOS devices, and the terminal region 302 is used to integrate terminal structures. A first trench 3011 is formed in the substrate 310 of the cell region 301, and a second trench 3012 is formed in the substrate 310 of the terminal region 302. The width of the second trench 3012 is greater than the width of the first trench 3011. A first dielectric layer 3201 is formed on the surfaces of the substrate 310, the first trench 3011, and the second trench 3012. A first shielding gate 331 is formed in the first trench 3011, and a second shielding gate 333 is formed in the second trench 3012. The top of the first shielding gate 331 is lower than the opening of the first trench 3011, and the top of the second shielding gate 333 is lower than the opening of the second trench 3012.

[0044] The substrate 310 may be an epitaxial layer formed on a silicon substrate (not shown in the figure), and the first dielectric layer 3201 may be an oxide layer (e.g., a silicon dioxide (SiO2) layer). After etching to form the first trench 3011 and the second trench 3012 in the substrate 310, the first dielectric layer 3201 is formed on the surface of the substrate 310, the first trench 3011 and the second trench 3012 by a thermal oxidation process. After depositing a polysilicon layer, the polysilicon layer outside the first trench 3011 and the second trench 3012 and the polysilicon layer of a predetermined depth in the first trench 3011 and the second trench 3012 are removed by etching. The remaining polysilicon layer in the first trench 3011 forms the first shielding gate 331, and the remaining polysilicon layer in the second trench 3012 forms the second shielding gate 333.

[0045] Step S2: A second dielectric layer is formed. The second dielectric layer fills the first trench but does not fill the second trench. The second dielectric layer is a conformal dielectric layer.

[0046] refer to Figure 8 This illustrates a schematic cross-sectional view of the formation of the second dielectric layer. For example, as shown... Figure 8 As shown, the second dielectric layer 3202 and the first dielectric layer 3201 are made of the same material, both being oxide layers. The second dielectric layer 3202 is formed by depositing silicon dioxide or partially oxidizing sidewall silicon material using chemical vapor deposition (CVD) to achieve both density and conformal properties. The second dielectric layer 3202 fills the first trench 3011 but not the second trench 3012. The second dielectric layer 3202 formed on the sidewall of the second trench 3012 can subsequently serve as the sidewall gate dielectric layer for its gate electrode. Its thickness reduces the probability of breakdown.

[0047] Step S3: Remove the first dielectric layer and the second dielectric layer from areas other than the target area. The target area includes the sidewall of the second trench, the area above the second shielding grid in the second trench, and the area above the first shielding grid in the first trench.

[0048] Step S4: A third dielectric layer is formed on the sidewall of the first trench.

[0049] Step S5: Fill the first trench and the second trench with polysilicon layers. The polysilicon layer in the first trench forms the gate of the MOS device, and the polysilicon layer in the second trench forms the gate of the termination structure.

[0050] In this embodiment, steps S3 to S5 can be implemented in two ways, which are respectively achieved through... Figures 9 to 11 ,as well as Figures 12 to 15 For example:

[0051] Implementation method (1): Step S3 includes, but is not limited to: covering a predetermined area above the second trench with photoresist by photolithography; etching to remove the first dielectric layer and the second dielectric layer in areas other than the target area; and removing the photoresist.

[0052] refer to Figure 9 It shows a schematic cross-sectional view after removing the first and second dielectric layers, excluding the target region. For example, as shown... Figure 9As shown, photoresist 340 can be covered in a predetermined area above the second trench 3012 by photolithography. The width of the predetermined area is greater than the width of the second trench 3012. After etching, the first dielectric layer 3201 and the second dielectric layer 3202 in areas other than the target area are removed. The target area includes two parts: one part is the area where the sidewall of the second trench 3012 is located, and the other part is the area above the first shielding gate 331 in the first trench 3011.

[0053] refer to Figure 10 It shows a schematic cross-sectional view after removing the first and second dielectric layers, excluding the target region. For example, as shown... Figure 10 As shown, it can be removed by dry etching. During the etching process, due to the protection of photoresist 340 and the width of the area covered by photoresist 340 being greater than the width of the second trench 3012, the second dielectric layer 3202 in the second trench 3012 and its periphery is retained after etching, and its cross-section presents an inverted "V" shape.

[0054] After step S5, the method further includes: forming a doped region in the substrate; forming a heavily doped region in the doped regions on both sides of the first shielding gate and the first gate.

[0055] refer to Figure 11 This illustrates a cross-sectional view after the formation of the MOS device and termination structure. For example, as shown... Figure 11 As shown, step S4 includes, but is not limited to: forming a third dielectric layer 3203 by CVD process, removing the third dielectric layer 3203 in other areas except the first trench 3011 by etching, the remaining first dielectric layer 3201, second dielectric layer 3202 and third dielectric layer 3203 in the first trench 3011 constitute the gate dielectric layer of the MOS device, and the thickness of the third dielectric layer 3203 above the first shielding gate 331 in the first trench 3011 is less than the thickness of the second dielectric layer 3202 above the second shielding gate 333 in the second trench 3012.

[0056] Step S5 includes, but is not limited to: forming a polysilicon layer, removing the polysilicon layer outside the first trench 3011 and the second trench 3012 by etching, forming the first gate 332 with the remaining polysilicon layer in the first trench 3011, and forming the second gate 334 with the remaining polysilicon layer in the second trench 3012.

[0057] After step S5, the method further includes: forming a doped region (which can serve as a well region of a MOS device) 311 in the substrate 310 by ion implantation; and forming heavily doped regions 3121 and 3122 in the doped regions 311 on both sides of the first gate 332 by photolithography, wherein the heavily doped region 3121 can serve as the source of the MOS device and the heavily doped region 3122 can serve as the drain of the MOS device.

[0058] Implementation method (2): Step S3 includes, but is not limited to: filling the second trench with photoresist by photolithography; etching to remove the second dielectric layer except for the first trench and the second trench; covering the predetermined area above the second trench with photoresist by photolithography; etching to remove the first dielectric layer and the second dielectric layer in areas other than the target area; and removing the photoresist.

[0059] refer to Figure 12 It shows a cross-sectional schematic diagram of the second trench filled with photoresist using a photolithography process; Reference Figure 13 It shows a cross-sectional schematic diagram of the first and second dielectric layers after removing regions other than the target region; Reference Figure 14 It shows a schematic cross-sectional view after removing the photoresist.

[0060] For example, such as Figures 12 to 14 As shown, after the photoresist 340 is filled into the second trench 3102, etching is performed to remove the second dielectric layer 3202 other than the first trench 3011 and the second trench 3012. The photoresist 340 can be covered in a predetermined area above the second trench 3012 by photolithography. The width of the predetermined area is the same as the width of the second trench 3012. The first dielectric layer 3201 and the second dielectric layer 3202 in other areas except the target area can be removed by dry etching. During the etching process, the second dielectric layer 3202 in the second trench 3012 is retained due to the protection of the photoresist 340, and the photoresist 340 is removed.

[0061] refer to Figure 15 The diagram shows a cross-sectional view after the formation of the MOS device and the termination structure. The implementation after step S3 in implementation (2) can be referred to the implementation after step S3 in implementation (1), and will not be repeated here. The difference between the MOS device formed by implementation (2) and the MOS device formed by implementation (1) is whether the second dielectric layer 3202 has a residue on the periphery of the opening of the second trench 3012.

[0062] In summary, in the embodiments of this application, during the fabrication of the trench-type MOS device, after forming the shielding gate of the MOS device and the shielding gate of the termination structure, a dielectric layer is formed to fill the trench of the MOS device, and the trench sidewalls of the termination structure are thickened. By removing the dielectric layer in the trench of the MOS device but not removing the dielectric layer in the termination structure, a thinner sidewall dielectric layer is formed in the trench of the MOS device. Then, the gate of the MOS device and the termination structure are formed through subsequent steps. Since it is not necessary to use photomasks of different window sizes for etching, it is less affected by overlay errors and has a higher yield.

[0063] Figure 6 Other implementation methods may also be used in this embodiment. After step S2, the method further includes:

[0064] Step S3.1: Using the polysilicon layer as an etch barrier layer, remove the first dielectric layer and the second dielectric layer in areas other than the target area. The remaining polysilicon layer in the second trench forms the second gate. The target area includes the sidewalls of the second trench and the area above the first shielding gate in the first trench.

[0065] Step S4.1: A third dielectric layer is formed on the sidewall of the first trench.

[0066] Step S5.1: Fill the first trench with a polysilicon layer, and the polysilicon layer in the first trench constitutes the first gate.

[0067] In this embodiment of the application, steps S3.1 to S5.1 can be implemented in two ways, as follows:

[0068] Implementation method (3) Step S3.1 includes, but is not limited to: forming a polysilicon layer in a predetermined area above the second trench using a photolithography process, the polysilicon layer filling the second trench; performing etching to remove the first dielectric layer and the second dielectric layer in areas other than the target area, the cross-section of the remaining polysilicon layer after etching being T-shaped (the formed T-shaped polysilicon layer can be referred to...). Figure 9 (Cross-sectional view of photoresist 340); after removing the top of the T-type polysilicon layer, the remaining polysilicon layer forms the second gate.

[0069] The implementation method of step S4.1 can be referred to the above embodiments, and will not be repeated here.

[0070] Step S5.1 includes, but is not limited to: forming a polysilicon layer in areas other than the second trench, removing the polysilicon layer outside the first trench by etching, and forming the first gate with the remaining polysilicon layer of the first trench (a cross-sectional view of the MOS device and termination structure formed in this embodiment can be referred to). Figure 11 ).

[0071] Implementation method (4): Step S3.1 includes, but is not limited to: filling the second trench with a polysilicon layer by photolithography (the filled polysilicon layer can be referred to...). Figure 12 The photoresist 340 in the middle is etched to remove the second dielectric layer except for the first trench and the second trench; a polysilicon layer is formed in a predetermined area above the second trench by photolithography, the polysilicon layer and the polysilicon layer in the second trench form a T-shape (thereby protecting the second dielectric layer of the second trench sidewall); the first dielectric layer and the second dielectric layer in other areas except the target area are etched to remove the top of the T-shaped polysilicon layer, and the remaining polysilicon layer forms the second gate.

[0072] The implementation method of step S4.1 can be referred to the above embodiments, and will not be repeated here.

[0073] Step S5.1 includes, but is not limited to: forming a polysilicon layer in areas other than the second trench, removing the polysilicon layer outside the first trench by etching, and forming the first gate with the remaining polysilicon layer of the first trench (a cross-sectional view of the MOS device and termination structure formed in this embodiment can be referred to). Figure 15 ).

[0074] Similarly, after step S5.1, the method further includes: forming a doped region in the substrate (which can serve as a well region for a MOS device) by ion implantation; and forming a heavily doped region in the doped regions on both sides of the first gate by photolithography.

[0075] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this application.

Claims

1. A method for fabricating a MOS device, characterized in that, include: A substrate is provided, which, when viewed from a top view, includes a cell region and a termination region. The cell region is used to integrate MOS devices, and the termination region is used to integrate termination structures. A first trench is formed in the substrate of the cell region, and a second trench is formed in the substrate of the termination region. The width of the second trench is greater than the width of the first trench. A first dielectric layer is formed on the surfaces of the substrate, the first trench, and the second trench. A first shielding gate is formed in the first trench, and a second shielding gate is formed in the second trench. The top of the first shielding gate is lower than the opening of the first trench, and the top of the second shielding gate is lower than the opening of the second trench. A second dielectric layer is formed, which fills the first trench but does not fill the second trench. The second dielectric layer is a conformal dielectric layer. Remove the first and second dielectric layers from areas other than the target area, wherein the target area includes the sidewall of the second trench, the area above the second shielding grid in the second trench, and the area above the first shielding grid in the first trench. A third dielectric layer is formed on the sidewall of the first trench; Polysilicon layers are filled in the first trench and the second trench. The polysilicon layer in the first trench forms a first gate, which is the gate of the MOS device. The polysilicon layer in the second trench forms a second gate, which is the gate of the termination structure.

2. The method according to claim 1, characterized in that, The removal of the first and second dielectric layers from areas other than the target area includes: Photoresist is applied to a predetermined area above the second trench using a photolithography process; Etching is performed to remove the first and second dielectric layers in areas other than the target area; Remove light resistance.

3. The method according to claim 2, characterized in that, The width of the predetermined area is greater than the width of the second trench.

4. The method according to claim 1, characterized in that, The removal of the first and second dielectric layers from areas other than the target area includes: The second trench is filled with photoresist using a photolithography process; Etching is performed to remove the second dielectric layer excluding the first trench and the second trench; Photoresist is applied to a predetermined area above the second trench using a photolithography process; Etching is performed to remove the first and second dielectric layers in areas other than the target area; Remove light resistance.

5. The method according to any one of claims 1 to 4, characterized in that, After filling the first trench and the second trench with a polysilicon layer, the method further includes: A doped region is formed in the substrate; Heavily doped regions are formed in the doped regions on both sides of the first shielding gate and the first gate.

6. The method according to claim 5, characterized in that, The first dielectric layer, the second dielectric layer, and the third dielectric layer each include an oxide layer.

7. The method according to claim 6, characterized in that, The types of impurities incorporated into the doped region and the heavily doped region are different.

Images