Semiconductor structure and its preparation method
Patent Information
- Application Number
- CN202210785352.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-07-05
- Publication Date
- 2026-09-01
- Estimated Expiration
- 2042-07-05
AI Technical Summary
随着半导体技术的发展，半导体结构的尺寸越来越小，易产生寄生电容，导致半导体结构的性能较差
[0037]本公开实施例所提供的半导体结构及其制备方法中，通过形成封堵件，并利用封堵件封堵缝隙，避免去除初始保护层时扩大缝隙，防止后续的导电材料填充到缝隙中，进而防止填充到缝隙中的导电材料与字线之间形成寄生电容，提高了半导体结构的性能。
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Figure CN115172267B_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and its fabrication method. Background Technology
[0002] Dynamic random access memory (DRAM) is a type of semiconductor memory that allows for high-speed, random data writing and retrieval, and is widely used in data storage devices. DRAM consists of multiple repeatedly arranged memory cells, each including a transistor and a capacitor. The capacitor is connected to the source or drain of the transistor via a capacitive contact structure. With the development of semiconductor technology, the size of semiconductor structures has become increasingly smaller, making them prone to parasitic capacitance, which leads to poorer performance. Summary of the Invention
[0003] In view of the above problems, this disclosure provides a semiconductor structure and its fabrication method to prevent parasitic capacitance from being generated in the semiconductor structure and improve the performance of the semiconductor structure.
[0004] A first aspect of this disclosure provides a method for fabricating a semiconductor structure, comprising:
[0005] A substrate is provided having word line trenches extending in a first direction and bit line trenches extending in a second direction, the word line trenches and the bit line trenches dividing the substrate into a plurality of spaced active pillars, wherein a dielectric layer is provided between adjacent active pillars along the first direction; wherein the first direction and the second direction intersect.
[0006] An initial protective layer is formed on the sidewall of the letter groove, and the area enclosed by the initial protective layer exposes the substrate;
[0007] A word line isolation structure is formed within the area enclosed by the initial protective layer, and the word line isolation structure has gaps;
[0008] A sealing element is formed, which at least seals the top of the gap;
[0009] A first filling region is formed, which is exposed on the outer peripheral surface of the active pillar and the word line isolation structure;
[0010] A word line extending along the first direction is formed within the first filling area, and the word line connects all the active columns located in the same first direction.
[0011] In some embodiments, the sealing element includes a plurality of sealing strips, each of the sealing strips projecting onto the substrate to cover all of the active posts located in the same second direction, or at least cover the word line isolation structure.
[0012] In some embodiments, the step of forming a sealing member that at least seals the top of the gap includes:
[0013] A sealing layer is formed on the substrate, and the sealing layer also covers the initial protective layer and the word line isolation structure;
[0014] Removing a portion of the sealing layer leaves the remaining sealing layer in the form of a plurality of first sealing strips spaced apart along a first direction. Each first sealing strip extends along a second direction, and the projection of each first sealing strip onto the substrate covers all of the active posts located in the same second direction. The plurality of first sealing strips constitute a sealing element.
[0015] In some embodiments, the step of forming a sealing member that at least seals the top of the gap includes:
[0016] The word line isolation structure with a portion of its thickness is removed, and the remaining word line isolation structure, together with the initial protective layer, forms a second filling area, in which the gap is not exposed.
[0017] A second sealing strip is formed within each of the second filling areas, and multiple second sealing strips constitute the sealing element.
[0018] In some embodiments, the step of forming a sealing member that at least seals the top of the gap includes:
[0019] A first etching process is used to remove a portion of the initial protective layer to form an etched hole extending along the first direction;
[0020] A third sealing strip is formed inside the etched hole. The top surface of the third sealing strip is flush with the top surface of the word line isolation structure. The third sealing strip and the top of the word line isolation structure constitute the sealing element.
[0021] In some embodiments, the etching selectivity ratio of the first etching process for the initial protective layer and the word line isolation structure is greater than 2, and the first etching time of the first etching process is in the range of 2s-5s.
[0022] In some embodiments, the step of forming a sealing member that at least seals the top of the gap includes:
[0023] By removing part of the word line isolation structure, the top surface of the remaining word line isolation structure is not exposed to the gap, such that the area between the top surface of the remaining word line isolation structure and the top of the gap constitutes the sealing element.
[0024] In some embodiments, the step of removing a portion of the word line isolation structure includes:
[0025] A second etching process is used to remove part of the word line isolation structure. The etching rate of the second etching process on the word line isolation structure is greater than the etching rate of the initial protective layer.
[0026] In some embodiments, the second etching process has an etching selectivity ratio greater than 2 for the word line isolation structure and the initial protective layer.
[0027] In some embodiments, along the second direction, the size of the initial protective layer is larger than the size of the word line isolation structure; the step of removing a portion of the word line isolation structure includes:
[0028] A third etching process is used to remove part of the word line isolation structure and part of the initial protective layer. The etching rate of the third etching process on the word line isolation structure is less than the etching rate of the initial protective layer, so that the top surface of the retained initial protective layer is lower than the top surface of the retained word line isolation structure.
[0029] In some embodiments, the etching time using the third etching process is greater than or equal to 10 seconds.
[0030] In some embodiments, the step of forming the first filled area includes:
[0031] Using a fourth etching process with high etching selectivity for the word line isolation structure, a portion of the initial protective layer and a portion of the dielectric layer are removed to form a first filling region that exposes a portion of the outer peripheral surface of the active pillar and the word line isolation structure. The retained dielectric layer constitutes the bit line isolation structure, and the retained initial protective layer constitutes the protective layer.
[0032] In some embodiments, after the step of forming the first filling region and before the step of forming word lines extending along the first direction within the first filling region, the preparation method further includes:
[0033] A gate oxide layer is formed, which encapsulates the active pillar exposed on the outer peripheral surface within the first filling region.
[0034] In some embodiments, after the step of forming a word line extending in the first direction within the first filling area, the method further includes:
[0035] An insulating layer is formed covering the gate oxide layer and the word lines, the top surface of which is flush with the substrate.
[0036] A second aspect of this disclosure provides a semiconductor structure, which is obtained by the semiconductor structure and its preparation method described in the first aspect above.
[0037] In the semiconductor structure and its fabrication method provided in this disclosure, by forming a sealing element and sealing the gap, the gap is prevented from expanding when the initial protective layer is removed, and the subsequent conductive material is prevented from filling the gap. This prevents the formation of parasitic capacitance between the conductive material filling the gap and the word line, thereby improving the performance of the semiconductor structure.
[0038] In addition to the technical problems solved by the embodiments of this disclosure, the technical features constituting the technical solutions, and the beneficial effects brought about by the technical features of these technical solutions described above, other technical problems that can be solved by the semiconductor structure and its preparation method provided by the embodiments of this disclosure, other technical features included in the technical solutions, and the beneficial effects brought about by these technical features will be further described in detail in the specific implementation. Attached Figure Description
[0039] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0040] Figure 1 A process flow diagram of the method for fabricating a semiconductor structure provided in this disclosure embodiment;
[0041] Figure 2 A schematic diagram of forming a word line isolation structure in a method for fabricating a semiconductor structure provided in this embodiment of the disclosure;
[0042] Figure 3 For along Figure 2 A sectional view along the A2-A2 direction;
[0043] Figure 4 This is a schematic diagram of the formation of a sealing layer in a method for fabricating a semiconductor structure according to an embodiment of the present disclosure;
[0044] Figure 5 A schematic diagram of the formation of a sealing element in the method for fabricating a semiconductor structure provided in this disclosure. Figure 1 ;
[0045] Figure 6 For along Figure 5A sectional view along the A3-A3 direction;
[0046] Figure 7 A schematic diagram of the formation of the first filling region in the method for fabricating the semiconductor structure provided in this embodiment of the disclosure. Figure 1 ;
[0047] Figure 8 This is a schematic diagram of the formation of a bit line isolation structure in the method for fabricating a semiconductor structure provided in the embodiments of this disclosure;
[0048] Figure 9 A schematic diagram of word line formation in the method for fabricating a semiconductor structure provided in this embodiment of the disclosure. Figure 1 ;
[0049] Figure 10 Schematic diagram of the formation of an insulating layer in the method for fabricating a semiconductor structure provided in this disclosure. Figure 1 ;
[0050] Figure 11 This is a schematic diagram of the formation of the second filling region in the method for fabricating a semiconductor structure provided in this embodiment of the present disclosure;
[0051] Figure 12 A schematic diagram of the formation of a sealing element in the method for fabricating a semiconductor structure provided in this disclosure. Figure 2 ;
[0052] Figure 13 A schematic diagram of the formation of the first filling region in the method for fabricating the semiconductor structure provided in this embodiment of the disclosure. Figure 2 ;
[0053] Figure 14 A schematic diagram of word line formation in the method for fabricating a semiconductor structure provided in this embodiment of the disclosure. Figure 2 ;
[0054] Figure 15 A schematic diagram illustrating the formation of etched holes in a method for fabricating a semiconductor structure according to an embodiment of this disclosure;
[0055] Figure 16 A schematic diagram of the formation of a sealing element in the method for fabricating a semiconductor structure provided in this disclosure. Figure 3 ;
[0056] Figure 17 for Figure 16 Top view;
[0057] Figure 18 A schematic diagram of the formation of the first filling region in the method for fabricating the semiconductor structure provided in this embodiment of the disclosure. Figure 3 ;
[0058] Figure 19 for Figure 18Top view;
[0059] Figure 20 A schematic diagram of word line formation in the method for fabricating a semiconductor structure provided in this embodiment of the disclosure. Figure 3 ;
[0060] Figure 21 A schematic diagram of the formation of a sealing element in the method for fabricating a semiconductor structure provided in this disclosure. Figure 4 ;
[0061] Figure 22 A schematic diagram of the formation of the first filling region in the method for fabricating the semiconductor structure provided in this embodiment of the disclosure. Figure 4 ;
[0062] Figure 23 A schematic diagram of word line formation in the method for fabricating a semiconductor structure provided in this embodiment of the disclosure. Figure 4 ;
[0063] Figure 24 A schematic diagram of the formation of a sealing element in the method for fabricating a semiconductor structure provided in this disclosure. Figure 5 ;
[0064] Figure 25 A schematic diagram of the formation of the first filling region in the method for fabricating the semiconductor structure provided in this embodiment of the disclosure. Figure 5 ;
[0065] Figure 26 A schematic diagram of word line formation in the method for fabricating a semiconductor structure provided in this embodiment of the disclosure. Figure 5 . Detailed Implementation
[0066] As described in the background section, transistors in semiconductor structures of related technologies are prone to coupling capacitance. The inventors have discovered that this problem arises because, during word line formation, word line trenches are typically formed first within the substrate, followed by the formation of stacked dielectric layers and word line isolation structures within the trenches, with the word line isolation structures filling the area enclosed by the dielectric layers. However, gaps easily form within the word line isolation structures during their formation. When the dielectric layer is subsequently removed to create a filling area for the word lines between the active pillars and the word line isolation structures, these gaps widen. Consequently, when conductive material is deposited into the filling area, it fills these gaps, causing parasitic capacitance to form between the conductive material and the word lines, thus degrading the performance of the semiconductor structure.
[0067] To address the aforementioned technical problems, this disclosure provides a semiconductor structure and its fabrication method. By forming a sealing element and sealing the gaps using the sealing element, the gaps are prevented from expanding when the initial protective layer is removed, and subsequent conductive materials are prevented from filling the gaps. This prevents the formation of parasitic capacitance between the conductive materials filling the gaps and the word lines, thereby improving the performance of the semiconductor structure.
[0068] To make the above-mentioned objects, features, and advantages of the embodiments of this disclosure more apparent and understandable, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are merely some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.
[0069] This embodiment does not limit the semiconductor structure. The following description will take dynamic random access memory (DRAM) as an example, but this embodiment is not limited to this. Other semiconductor structures are also possible in this embodiment.
[0070] Please refer to the attached document. Figure 1 The present disclosure provides a method for fabricating a semiconductor structure, comprising the following steps:
[0071] Step S100: Provide a substrate having word line trenches extending along a first direction and bit line trenches extending along a second direction, the word line trenches and bit line trenches dividing the substrate into a plurality of spaced-apart active pillars, with a dielectric layer between adjacent active pillars along the first direction; wherein the first direction and the second direction intersect. Its structure can be referenced in the appendix. Figure 2 and attached Figure 3 .
[0072] For example, the substrate 10 is used to support a semiconductor device therein or thereon. The substrate 10 can be a silicon (Si) substrate, a germanium (Ge) substrate, a silicon-germanium (GeSi) substrate, a silicon carbide (SiC) substrate, a silicon-on-insulator (SOI) substrate, or a germanium-on-insulator (GOI) substrate, etc.
[0073] Forming bit line trenches and word line trenches within the substrate 10 can be performed according to the following process steps. For example, a plurality of bit line trenches are formed within the substrate 10, the plurality of bit line trenches being spaced apart along a first direction, and each bit line trench extending along a second direction. For example, the bit line trenches are spaced apart along the first direction X, and each bit line trench extends along the second direction Y.
[0074] Multiple bit line grooves are spaced apart along the first direction X, so that the multiple bit line grooves divide the substrate 10 into multiple strips spaced apart along the first direction X.
[0075] After the bitline trenches are formed, an initial dielectric layer is formed within the bitline trenches using a deposition process. The initial dielectric layer fills the bitline trenches and extends beyond them, covering the top surface of the substrate 10. In other words, the initial dielectric layer also covers the top surface of the strip-shaped body.
[0076] The deposition process can include any one of the following: chemical vapor deposition (CVD), physical vapor deposition (PCD), or atomic layer deposition (ALD).
[0077] The initial dielectric layer is used to achieve insulation between adjacent strips. The material of the initial dielectric layer includes, but is not limited to, silicon oxide.
[0078] After the initial dielectric layer is formed, multiple word line trenches are formed in the initial dielectric layer and the substrate 10. The multiple word line trenches are spaced apart along the second direction, and each word line trench extends along the first direction. The retained initial dielectric layer constitutes the dielectric layer 32. The depth of the word line trenches is less than the depth of the bit line trenches.
[0079] The depth direction of the word line grooves is perpendicular to the base 10. Multiple word line grooves divide the strip into multiple active pillars 40 spaced apart.
[0080] The retained initial dielectric layer forms dielectric layer 32, which is used to achieve insulation between adjacent active posts 40 along the first direction.
[0081] The depth of the word line groove is less than the depth of the bit line groove, so that the bottoms of all active pillars 40 located in the same second direction are connected together, so as to facilitate the subsequent formation of bit lines in the area where the bottoms of the active pillars 40 located in the same second direction are connected together (see Appendix). Figure 3 ).
[0082] In this embodiment, by connecting the bottoms of all the active pillars 40 located in the same second direction together, the bit line can be simultaneously connected to the active pillars 40 located in the same second direction, thereby making the voltage of multiple active pillars 40 located in the same second direction the same, ensuring the critical voltage stability of the semiconductor structure, and thus reducing the floating body effect of the semiconductor structure.
[0083] Step S200: An initial protective layer is formed on the sidewall of the letter groove, and the area enclosed by the initial protective layer exposes the substrate.
[0084] For example, please refer to the appendix. Figure 2 and attached Figure 3 An insulating material is deposited on the inner wall of the word line trench using an atomic layer deposition process. Afterwards, the insulating material on the bottom wall of the word line trench is removed, leaving the insulating material on the sidewalls of the word line trench to form an initial protective layer 51. The initial protective layer 51 may be made of silicon oxide, but is not limited to this.
[0085] The initial protective layer 51 is used to protect the sidewalls of the active pillar 40 in the second direction, preventing damage to the active pillar 40 during subsequent bit line formation and improving the performance of the semiconductor structure.
[0086] The area enclosed by the initial protective layer 51 exposes the substrate 10 to facilitate subsequent processing of the substrate 10, such as pore enlargement or plasma treatment.
[0087] For example, please refer to the appendix. Figure 3 ,
[0088] The substrate exposed in the word line trench is siliconized to form a bit line 60 extending in a second direction, the bit line 60 being connected to the bottom of the active post 40.
[0089] In this embodiment, there are multiple bit lines 60, which are spaced apart along the first direction and each bit line 60 extends along the second direction. Each bit line 60 is used to connect all active pillars 40 located in the same second direction, thereby making the voltage of multiple active pillars 40 located in the same second direction the same, ensuring the critical voltage stability of the semiconductor structure, and thus reducing the floating body effect of the semiconductor structure.
[0090] It should be noted that before forming the initial protective layer, the active pillar 40 can be ion-doped to form a first doped region and a second doped region within the active pillar 40. For example, along a direction perpendicular to the substrate 10, the active pillar 40 includes a channel region and a first doped region and a second doped region located on either side of the channel region. The first doped region and the second doped region have the same type of dopant ions, for example, P-type ions or N-type ions. The type of dopant ions in the channel region is different from the type of dopant ions in the first doped region.
[0091] In one example, when the dopant ions in the first doped region are N-type ions, the corresponding dopant ions in the channel region are P-type ions. In another example, when the dopant ions in the first doped region are P-type ions, the corresponding dopant ions in the channel region are N-type ions.
[0092] At this time, bit line 60 can be connected to either the first doped region or the second doped region. For example, when the first doped region is located below the channel region, bit line 60 is connected to the first doped region. As another example, when the second doped region is located below the channel region, bit line 60 is connected to the second doped region.
[0093] Step S300: A word line isolation structure is formed within the area enclosed by the initial protective layer, and the word line isolation structure has gaps.
[0094] Please continue to refer to the appendix. Figure 2 and attached Figure 3 For example, an insulating material is deposited within the area enclosed by the initial protective layer using a deposition process. This insulating material also covers the top surfaces of the dielectric layer 32 and the active pillar 40. Subsequently, chemical mechanical polishing (CMP) can be used to remove the insulating material from the top surfaces of the dielectric layer and the active pillar, making the top surface of the insulating material flush with the top surface of the dielectric layer 32. The remaining insulating material constitutes the word line isolation structure 70. The material of the word line isolation structure 70 includes, but is not limited to, silicon nitride.
[0095] The dielectric layer 32 and word line isolation structure 70 on the top surface of the active column 40 can be removed by chemical mechanical polishing process, so that the top surface of the word line isolation structure 70 is flush with the substrate 10, so as to flatten the top surface of the substrate 10 and facilitate the subsequent preparation of the sealing layer 81.
[0096] It should be noted that, due to the influence of the deposition process and the depth-to-width ratio of the character line grooves, the resulting character line isolation structure 70 has gaps 71.
[0097] Step S400: Form a sealing element, which at least seals the top of the gap.
[0098] It should be noted that the sealing component may be composed of a portion of the word line isolation structure 70, or it may be composed of other re-deposited components.
[0099] Please refer to the attached document. Figure 3 To be continued Figure 20 In one example, the plugging element 80 includes a plurality of plugging strips, each of which projects onto the base 10 to cover all the active posts 40 located in the same second direction, or at least cover the word line isolation structure 70.
[0100] Please refer to the attached document. Figure 21 To be continued Figure 26In another example, part of the word line isolation structure 70 is removed, and the top surface of the remaining word line isolation structure 70 does not expose the gap 71, so that the area between the top surface of the remaining word line isolation structure 70 and the top of the gap 71 constitutes a sealing element 80.
[0101] Step S500: Form a first fill area, which is exposed on the outer periphery of the active pillar and word line isolation structure.
[0102] Step S600: A word line extending along a first direction is formed in the first filling area, and the word line connects all active columns located in the same first direction.
[0103] This embodiment forms a sealing element and seals the gap, avoiding the expansion of the gap when the initial protective layer is removed, preventing subsequent conductive material from filling the gap, and thus preventing the formation of parasitic capacitance between the conductive material filling the gap and the word line, thereby improving the performance of the semiconductor structure.
[0104] In one possible implementation, please refer to the appendix. Figure 4 A sealing layer 81 is formed on the substrate 10, and the sealing layer 81 also covers the initial protective layer 51 and the word line isolation structure 70. The sealing layer 81 can be prepared using a deposition process.
[0105] Please refer to the attached document. Figure 5 and attached Figure 6 A graphical sealing layer 81 is formed, and a portion of the sealing layer 81 is removed, leaving a plurality of first sealing strips 82 spaced apart along a first direction. Each first sealing strip 82 extends along a second direction, and the projection of each first sealing strip 82 onto the substrate 10 covers all active posts 40 located in the same second direction. The plurality of first sealing strips 82 constitute a sealing element 80. This sealing element 80 is capable of sealing the top of the gap 71.
[0106] The steps to form the first fill area include: Please refer to the appendix. Figure 7 and attached Figure 8 A portion of the initial protective layer 51 and a portion of the dielectric layer 32 are removed to form a first filling region 90 that exposes a portion of the outer peripheral surface of the active pillar 40 and the initial bit line isolation structure 71, wherein the retained dielectric layer 32 constitutes the bit line isolation structure 30. The retained initial protective layer constitutes the protective layer 50.
[0107] Please refer to the attached document. Figure 9 A gate oxide layer 100 is formed using a deposition process. The gate oxide layer 100 encapsulates the outer peripheral surface of the active post 40 exposed within the first filling region 90. In other words, the gate oxide layer 100 encapsulates the channel region of the active post 40.
[0108] Please refer to the appendix afterward. Figure 9This forms word lines 110 that enclose the gate oxide layer 100. Word lines 110 extend along a first direction and are used to connect all active pillars 40 in the same first direction.
[0109] In this embodiment, by forming a sealing element that can seal part of the gap, the gap can be avoided from being exposed. Furthermore, the conductive material used to form the word line 110 is deposited into the first filling region 90 from the side of the active pillar 40, rather than entering the first filling region 90 from the top surface of the active pillar 40. Therefore, the conductive material used to form the word line 110 is difficult to fill into the gap 71, thereby not increasing the parasitic capacitance of the semiconductor structure and improving the performance of the semiconductor structure.
[0110] In one possible implementation, the step of forming a sealing element that at least seals the top of the gap includes:
[0111] Please refer to the attached document. Figure 11 A portion of the thickness of the character line isolation structure 70 is removed, and the remaining character line isolation structure 70 and the initial protective layer form a second filling area 120, in which no gap 71 is exposed.
[0112] In other words, the word line isolation structure 70 located above the base 10 and part of the word line isolation structure 70 located in the word line groove are removed, and the remaining word line isolation structure 70 and the initial protective layer form a second filling area 120.
[0113] It should be noted that the dielectric layer 32 also covers the top surface of the active pillar 40. When removing part of the word line isolation structure 70, the dielectric layer 32 located on the top surface of the active pillar 40 will also be removed. At this time, it is necessary to adjust the ratio of the etching solution or etching gas, as well as the etching time, so that the etching rate of the etching gas or etching solution on the dielectric layer 32 and the initial protective layer 51 is small. At this time, more word line isolation structure 70 will be etched so that the top surface of the word line isolation structure 70 is lower than the initial protective layer 51 and forms a second filling area 120 with the initial protective layer 51.
[0114] Next, please refer to the appendix. Figure 12 A second sealing strip 83 is formed in the second filling area 120 using a deposition process. Multiple second sealing strips 83 are spaced apart along a second direction, and each second sealing strip 83 extends along a first direction.
[0115] The second sealing strip 83 projects onto the word line isolation structure 70 on the substrate 10; that is, the second sealing strip 83 projects onto the word line isolation structure 70 on the substrate 10. Multiple second sealing strips 83 constitute the sealing element 80. The material of the second sealing strip 83 includes silicon nitride, but is not limited to this.
[0116] Please refer to the attached document. Figure 13 The step of forming the first fill region 90 includes: removing a portion of the initial protective layer 51 and a portion of the dielectric layer 32 to form a first fill region 90 that exposes a portion of the outer peripheral surface of the active pillar 40 and the word line isolation structure 70, wherein the retained dielectric layer 32 constitutes the bit line isolation structure 30 and the retained initial protective layer 51 constitutes the protective layer 50.
[0117] Please refer to the attached document. Figure 14 The step of forming word lines extending in a first direction within the first filling region 90 includes: forming a gate oxide layer 100 using a deposition process, the gate oxide layer 100 covering the outer peripheral surface of the active post 40 exposed within the first filling region 90. That is, the gate oxide layer 100 covers the channel region of the active post 40.
[0118] Subsequently, word lines 110 are formed that enclose the gate oxide layer 100. Word lines 110 extend along a first direction and are used to connect all active pillars 40 in the same first direction.
[0119] In this embodiment, since a second sealing strip 83 is provided on the top surface of the retained word line isolation structure 70, the second sealing strip 83 can prevent the gap 71 from being exposed to the air. Thus, when the initial protective layer 51 is removed later, the gap 71 can be prevented from expanding, thereby preventing the conductive material that will form the word line from filling the gap 71, avoiding the generation of parasitic capacitance, and improving the performance of the semiconductor structure.
[0120] In one possible implementation, the step of forming a sealing element that at least seals the top of the gap includes:
[0121] Please refer to the attached document. Figure 15 A first etching process is used to remove a portion of the initial protective layer 51 to form an etched hole 130 extending along a first direction. In other words, the retained initial protective layer 51, word line isolation structure 70, active pillar 40, and dielectric layer form the etched hole 130.
[0122] The etching selectivity ratio of the first etching process for the initial protective layer 51 and the word line isolation structure 70 is greater than 2. That is to say, the first etching process has a smaller etching amount for the word line isolation structure 70 and a larger etching amount for the initial protective layer 51, so that the retained initial protective layer and the word line isolation structure form an etching hole 130.
[0123] In this embodiment, the initial protective layer 51 of 30nm-40nm is etched within an etching time of 2s-5s using the first etching process, so that the top surface of the retained initial protective layer is lower than the top surface of the active pillar 40, and the top surface of the word line isolation structure 70 is flush with the top surface of the active pillar 40.
[0124] It should be noted that the process of removing the initial protective layer 51 of a certain thickness can be completed through a one-step etching process or a two-step etching process. For example, the first etching process can be used to remove the initial protective layer of a first thickness within a first sub-etching time; then, the first etching process can be used again within a second sub-etching time to remove the initial protective layer of a second thickness. The sum of the first and second sub-etching times is between 2s and 5s. The sum of the first and second thicknesses is between 30nm and 40nm.
[0125] When a portion of the initial protective layer 51 is removed through a two-step etching process, the thickness of the initial protective layer 51 removed can be precisely controlled, thereby improving the accuracy of the etching process.
[0126] Please refer to the attached document. Figure 16 and attached Figure 17 A third sealing strip 84 is formed within the etched hole 130 using a deposition process. The top of the word line isolation structure 70 and the third sealing strip 84 located on both sides of the word line isolation structure 70 constitute a sealing element 80. The material of the third sealing strip 84 is the same as that of the word line isolation structure 70, including silicon nitride, but not limited to it.
[0127] After the sealing component 80 is formed, the first filling area needs to be formed. This step includes: Please refer to the attached document. Figure 18 and attached Figure 19 Using a fourth etching process with high selectivity for etching the word line isolation structure, a portion of the initial protective layer 51 and a portion of the dielectric layer 32 are removed to form a first filling region 90 exposing a portion of the outer peripheral surface of the active pillar 40 and the word line isolation structure 70. The retained dielectric layer 32 constitutes the bit line isolation structure 30, and the retained initial protective layer 51 constitutes the protective layer 50. After the first filling region is formed, please refer to the appendix. Figure 20 A gate oxide layer 100 is formed using a deposition process. The gate oxide layer 100 encapsulates the outer peripheral surface of the active post 40 exposed within the first filling region 90. In other words, the gate oxide layer 100 encapsulates the channel region of the active post 40.
[0128] Subsequently, word lines 110 are formed that enclose the gate oxide layer 100. Word lines 110 extend along a first direction and are used to connect all active pillars 40 in the same first direction.
[0129] In this embodiment, since the opening for depositing word lines 110 is located on one side of the word line isolation structure 70, the conductive material for forming word lines 110 is deposited from the side of the active pillar into the first filling region 90, rather than from the top surface of the active pillar into the first filling region 90. Therefore, the conductive material for forming word lines 110 is difficult to fill into the gap 71, thereby not increasing the parasitic capacitance of the semiconductor structure and improving the performance of the semiconductor structure.
[0130] In one possible implementation, please refer to the appendix. Figure 21 A second etching process is used to remove a portion of the word line isolation structure 70. The etching rate of the second etching process on the word line isolation structure 70 is greater than the etching rate of the initial protective layer 51. That is, the etching selectivity ratio of the first etching process for the word line isolation structure 70 and the initial protective layer 51 is greater than 2, so that only a portion of the word line isolation structure 70 is removed in the second etching process, and the top surface of the retained word line isolation structure 70 does not expose the gap 71, so that the area between the top surface of the retained word line isolation structure 70 and the top of the gap 71 constitutes a sealing element 80. (See attached...) Figure 21 Taking the orientation shown as an example, the area between the dotted line and the top of the character line isolation structure 70 is the sealing element 80.
[0131] Next, please refer to the appendix. Figure 22 A wet etching process is used to remove part of the initial protective layer 51 and part of the dielectric layer 32. The etching rate of the wet etching process on the initial protective layer 51 and the dielectric layer 32 is greater than that on the word line isolation structure 70, so that only the initial protective layer 51 and the dielectric layer 32 are etched to form a first filling area 90 that exposes part of the outer peripheral surface of the active pillar 40 and the word line isolation structure 70. The dielectric layer 32 that is retained constitutes the bit line isolation structure 30, and the initial protective layer that is retained constitutes the protective layer 50.
[0132] After the first filling area is formed, please refer to the attached document. Figure 23 A gate oxide layer 100 is formed using a deposition process. The gate oxide layer 100 encapsulates the outer peripheral surface of the active post 40 exposed within the first filling region 90. In other words, the gate oxide layer 100 encapsulates the channel region of the active post 40.
[0133] Subsequently, word lines 110 are formed that enclose the gate oxide layer 100. Word lines 110 extend along a first direction and are used to connect all active pillars 40 in the same first direction.
[0134] In one possible implementation, along the second direction, the initial protective layer 51 is larger in size than the word line isolation structure 70, that is, the thickness of the initial protective layer 51 is greater than the thickness of the word line isolation structure 70.
[0135] Please refer to the attached document. Figure 24A third etching process is used to remove a portion of the word line isolation structure 70 and a portion of the initial protective layer 51. The etching rate of the third etching process on the word line isolation structure 70 is lower than the etching rate of the initial protective layer 51, so that the top surface of the retained initial protective layer 51 is lower than the top surface of the retained word line isolation structure 70. For example, a third etching process with a high etching selectivity for the initial protective layer 51 on the word line isolation structure 70 is used to remove a portion of the word line isolation structure 70 and a portion of the initial protective layer 51. In this way, the thickness of the removed word line isolation structure is small, and no gaps are exposed, so that the area between the top surface of the retained word line isolation structure 70 and the top of the gap 71 constitutes a sealing element 80.
[0136] In this embodiment, the etching time of the third etching process is greater than or equal to 10 seconds. This allows for precise control of the thickness of the removed initial protective layer to be between 30nm and 40nm, thereby improving the yield of the semiconductor structure. Please refer to the appendix. Figure 25 The fourth etching process, which has a high etching selectivity for the word line isolation structure using the initial protective layer, removes part of the initial protective layer 51 and part of the dielectric layer 32. The etching rate of the initial protective layer 51 and the dielectric layer 32 by the wet etching process is greater than that of the word line isolation structure 70, so that only the initial protective layer 51 and the dielectric layer 32 are etched to form a first filling area 90 that exposes part of the outer peripheral surface of the active pillar 40 and the word line isolation structure 70. The dielectric layer 32 that is retained constitutes the bit line isolation structure 30, and the initial protective layer 51 that is retained constitutes the protective layer 50.
[0137] In this embodiment, a 70nm-80nm initial protective layer 51 is etched using a fourth etching process within an etching time of 2s-5s to form a first filling region 90 that exposes a portion of the outer peripheral surface of the active pillar 40 and the word line isolation structure 70. It should be noted that the removal of the 70nm-80nm initial protective layer can be accomplished through a one-step etching process or a two-step etching process.
[0138] The two-step etching process can be referred to as the two-step etching process in the first etching process, and will not be described in detail here.
[0139] Please refer to the attached document. Figure 26 After the first filling region is formed, a gate oxide layer 100 is formed using a deposition process. The gate oxide layer 100 covers the outer peripheral surface of the active post 40 exposed within the first filling region 90. In other words, the gate oxide layer 100 covers the channel region of the active post 40.
[0140] Subsequently, word lines 110 are formed that enclose the gate oxide layer 100. Word lines 110 extend along a first direction and are used to connect all active pillars 40 in the same first direction.
[0141] In some embodiments, please refer to the appendix. Figure 10 Appendix Figure 14 Appendix Figure 20 Appendix Figure 23 and attached Figure 26 After the step of forming word lines extending in a first direction within the first filling region, the method for fabricating the semiconductor structure further includes:
[0142] An insulating layer 140 is formed covering the gate oxide layer 100 and the word line 110, with the top surface of the insulating layer 140 flush with the substrate 10. The insulating layer 140 is used to achieve an insulating arrangement between other semiconductor devices subsequently formed on the substrate and the word line 110. The insulating layer 140 is made of silicon nitride, but is not limited to this material.
[0143] This disclosure also provides a semiconductor structure, which is prepared by the semiconductor structure preparation method described in the above embodiments. Therefore, the semiconductor structure possesses the beneficial effects described in the above embodiments, and will not be elaborated further in this embodiment.
[0144] The various embodiments or implementation methods described in this specification are presented in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referred to each other.
[0145] In the description of this specification, references to terms such as “one embodiment,” “some embodiments,” “illustrative embodiment,” “example,” “specific example,” or “some examples” refer to specific features, structures, materials, or characteristics described in connection with an embodiment or example that are included in at least one embodiment or example of this disclosure.
[0146] In this specification, the illustrative expressions of the terms used do not necessarily refer to the same implementation or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more implementations or examples.
[0147] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this disclosure, and are not intended to limit them. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this disclosure.
Claims
1. A method for fabricating a semiconductor structure, characterized in that, Includes the following steps: A substrate is provided having word line trenches extending in a first direction and bit line trenches extending in a second direction, the word line trenches and the bit line trenches dividing the substrate into a plurality of spaced active pillars, wherein a dielectric layer is provided between adjacent active pillars along the first direction; wherein the first direction and the second direction intersect. An initial protective layer is formed on the sidewall of the letter groove, and the area enclosed by the initial protective layer exposes the substrate; A word line isolation structure is formed within the area enclosed by the initial protective layer, and the word line isolation structure has gaps; A sealing element is formed, which at least seals the top of the gap; A first filling region is formed, the first filling region being exposed on the outer peripheral surface of the active post and the word line isolation structure, and a portion of the initial protective layer and a portion of the dielectric layer are removed to form a first filling region exposing a portion of the outer peripheral surface of the active post and the word line isolation structure; A word line extending along the first direction is formed within the first filling area, and the word line connects all the active columns located in the same first direction.
2. The method for preparing a semiconductor structure according to claim 1, characterized in that, The sealing element includes a plurality of sealing strips, each of which is projected onto the substrate to cover all of the active posts located in the same second direction, or at least to cover the word line isolation structure.
3. The method for preparing a semiconductor structure according to claim 2, characterized in that, The step of forming a sealing element that at least seals the top of the gap includes: A sealing layer is formed on the substrate, and the sealing layer also covers the initial protective layer and the word line isolation structure; Removing a portion of the sealing layer leaves the remaining sealing layer in the form of a plurality of first sealing strips spaced apart along a first direction. Each first sealing strip extends along a second direction, and the projection of each first sealing strip onto the substrate covers all of the active posts located in the same second direction. The plurality of first sealing strips constitute a sealing element.
4. The method for preparing a semiconductor structure according to claim 2, characterized in that, The step of forming a sealing element that at least seals the top of the gap includes: The word line isolation structure with a portion of its thickness is removed, and the remaining word line isolation structure, together with the initial protective layer, forms a second filling area, in which the gap is not exposed. A second sealing strip is formed within each of the second filling areas, and multiple second sealing strips constitute the sealing element.
5. The method for preparing a semiconductor structure according to claim 2, characterized in that, The step of forming a sealing element that at least seals the top of the gap includes: A first etching process is used to remove a portion of the initial protective layer to form an etched hole extending along the first direction; A third sealing strip is formed inside the etched hole. The top surface of the third sealing strip is flush with the top surface of the word line isolation structure. The third sealing strip and the top of the word line isolation structure constitute the sealing element.
6. The method for preparing a semiconductor structure according to claim 5, characterized in that, The etching selectivity ratio of the first etching process for the initial protective layer and the word line isolation structure is greater than 2, and the first etching time of the first etching process is in the range of 2s-5s.
7. The method for preparing a semiconductor structure according to claim 1, characterized in that, The step of forming a sealing element that at least seals the top of the gap includes: By removing part of the word line isolation structure, the top surface of the remaining word line isolation structure is not exposed to the gap, such that the area between the top surface of the remaining word line isolation structure and the top of the gap constitutes the sealing element.
8. The method for preparing a semiconductor structure according to claim 7, characterized in that, The step of removing part of the word line isolation structure includes: A second etching process is used to remove part of the word line isolation structure. The etching rate of the second etching process on the word line isolation structure is greater than the etching rate of the initial protective layer.
9. The method for preparing a semiconductor structure according to claim 8, characterized in that, The second etching process has an etching selectivity greater than 2 for the word line isolation structure and the initial protective layer.
10. The method for preparing a semiconductor structure according to claim 6, characterized in that, Along the second direction, the size of the initial protective layer is larger than the size of the word line isolation structure; The step of removing part of the word line isolation structure includes: A third etching process is used to remove part of the word line isolation structure and part of the initial protective layer. The etching rate of the third etching process on the word line isolation structure is less than the etching rate of the initial protective layer, so that the top surface of the retained initial protective layer is lower than the top surface of the retained word line isolation structure.
11. The method for preparing a semiconductor structure according to claim 10, characterized in that, The etching time using the third etching process is greater than or equal to 10 seconds.
12. The method for preparing a semiconductor structure according to any one of claims 1-8, characterized in that, The step of forming the first filled area includes: Using a fourth etching process with high etching selectivity for the word line isolation structure, a portion of the initial protective layer and a portion of the dielectric layer are removed to form a first filling region that exposes a portion of the outer peripheral surface of the active pillar and the word line isolation structure. The retained dielectric layer constitutes the bit line isolation structure, and the retained initial protective layer constitutes the protective layer.
13. The method for preparing a semiconductor structure according to claim 12, characterized in that, After the step of forming the first filling area and before the step of forming a word line extending along the first direction within the first filling area, the preparation method further includes: A gate oxide layer is formed, which encapsulates the active pillar exposed on the outer peripheral surface within the first filling region.
14. The method for preparing a semiconductor structure according to claim 13, characterized in that, After the step of forming a word line extending along the first direction within the first filling area, the method further includes: An insulating layer is formed covering the gate oxide layer and the word lines, the top surface of which is flush with the substrate.
15. A semiconductor structure, characterized in that, The semiconductor structure is prepared by the method for preparing the semiconductor structure according to any one of claims 1-14.
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