Semiconductor devices and their fabrication methods

Abstract

This disclosure provides a semiconductor device and a method for fabricating the same. The method includes: providing a substrate, the substrate including a contact region for forming a contact hole; forming a dielectric layer covering the substrate, the dielectric layer including a first region and a second region surrounding the first region, the orthographic projection of the first region onto the substrate surface covering the contact region and a portion of the orthographic projection located on both sides of the contact region along a first direction; thinning the second region of the dielectric layer so that the surface of the second region is lower than the surface of the first region; after thinning the second region, forming a contact hole in the first region that penetrates the dielectric layer and extends into the contact region; forming a conductive material layer covering the dielectric layer and filling the contact hole; removing a portion of the conductive material layer on the dielectric layer to form a conductor extending along a second direction, removing a portion of the conductive material layer within the contact hole to form a contact portion, and thinning the remaining dielectric layer in the first region; wherein the surfaces of the thinned first region and the second region are substantially flush.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor manufacturing, and in particular to a semiconductor device and a method for its fabrication. Background Technology

[0002] With the continuous development of semiconductor technology, the critical dimensions of semiconductor devices are constantly shrinking, and the pattern transformation of high aspect ratio structures places higher demands on etching capabilities. Especially when performing deep etching on multilayer thin films, the different etching selectivity of each layer can easily lead to the bottom morphology of the etched structure not meeting the expected effect, resulting in local over-etching or under-etching. This can affect subsequent processes, or even create defects in the product, reducing its performance. Summary of the Invention

[0003] According to a first aspect of this disclosure, a method for fabricating a semiconductor device is provided, comprising:

[0004] A substrate is provided; wherein the substrate includes a contact region for forming a contact hole;

[0005] A dielectric layer is formed covering the substrate; wherein the dielectric layer includes a first region and a second region surrounding the first region, the orthographic projection of the first region onto the substrate surface covers the contact region, and a portion of the orthographic projection is located on both sides of the contact region along a first direction; the first direction is parallel to the plane of the substrate.

[0006] Thin the second region of the dielectric layer so that the surface of the second region is lower than the surface of the first region;

[0007] After thinning the second region, the contact hole is formed in the first region, penetrating the dielectric layer and extending into the contact area;

[0008] A conductive material layer is formed that covers the dielectric layer and fills the contact holes;

[0009] A portion of the conductive material layer located on the dielectric layer is removed to form a wire extending along the second direction, a portion of the conductive material layer located within the contact hole is removed to form a contact portion, and the remaining dielectric layer in the first region is thinned; wherein, the surfaces of the thinned first region and the second region are substantially flush; the second direction is parallel to the plane of the substrate and perpendicular to the first direction.

[0010] In some embodiments, within the second region, the dielectric layer before thinning has a first dimension along a third direction, and the dielectric layer after thinning has a second dimension along the third direction;

[0011] Wherein, the second dimension is greater than or equal to one-half of the first dimension and less than or equal to three-quarters of the first dimension, and the third dimension is perpendicular to the plane where the substrate is located.

[0012] In some embodiments, along the second direction, the edge of the orthographic projection of the first region onto the substrate surface is flush with the edge of the contact region.

[0013] In some embodiments, a plurality of active regions are formed in the substrate and arranged in parallel along the first direction, and the contact region is located in the active regions;

[0014] The orthographic projection of the first region onto the substrate surface contacts or partially overlaps with the adjacent active region along the first direction.

[0015] In some embodiments, the first region, when projected onto the substrate surface, overlaps with the adjacent active region in a region having a third dimension along the first direction, and the active region has a fourth dimension along the first direction, wherein the third dimension is less than one-fifth of the fourth dimension.

[0016] In some embodiments, the second region of thinning the dielectric layer includes:

[0017] A first mask layer is formed to cover the dielectric layer; wherein the first mask layer and the dielectric layer have different etching rates under the same etching conditions;

[0018] The first mask layer and the dielectric layer located in the second region are etched to form a groove in the dielectric layer; wherein the fifth dimension of the groove along the third direction is smaller than the first dimension of the dielectric layer along the third direction, and the third direction is perpendicular to the plane of the substrate.

[0019] In some embodiments, the etching selectivity ratio of the first mask layer and the dielectric layer under the same etching conditions is greater than 2.

[0020] In some embodiments, forming a contact hole in the first region that penetrates the dielectric layer and extends into the contact region includes:

[0021] A second mask layer and a third mask layer are sequentially formed on the dielectric layer;

[0022] The third mask layer is patterned to form a mask pattern in the third mask layer over the first region;

[0023] A backfill layer is formed, which covers the mask pattern;

[0024] Remove the mask pattern to form a first trench in the backfill layer;

[0025] The second mask layer is etched through the first trench to form a second trench in the second mask layer;

[0026] The second trench is used to sequentially etch the dielectric layer and the contact area to form a contact hole.

[0027] In some embodiments, the second mask layer includes an oxide layer, a first spin-coated hard mask layer, and a first silicon oxynitride layer stacked sequentially; the oxide layer is located between the first conductive material layer and the first spin-coated hard mask layer; and / or,

[0028] The third mask layer includes a second spin-coated hard mask layer and a second silicon oxynitride layer stacked sequentially, with the second spin-coated hard mask layer located between the second mask layer and the second silicon oxynitride layer.

[0029] In some embodiments, the conductive material layer includes a first sub-conductive material layer, a second sub-conductive material layer, a barrier material layer, and a third sub-conductive material layer;

[0030] The formation of the conductive material layer covering the dielectric layer and filling the contact hole includes:

[0031] Before forming the second mask layer, a first sub-conductive material layer is formed to cover the dielectric layer; wherein the surfaces of the first sub-conductive material layer located in the first region and the second region are substantially flush.

[0032] When the dielectric layer and the contact area are sequentially etched through the second trench to form a contact hole, the first sub-conductive material layer is also etched through the second trench to form the contact hole.

[0033] After forming the contact hole, a second sub-conductive material is filled into the contact hole to form a second sub-conductive material layer; wherein the top of the second sub-conductive material layer is flush with the top of the first sub-conductive material layer.

[0034] A barrier material layer is formed covering the first sub-conductive material layer and the second sub-conductive material layer;

[0035] A third sub-conductive material layer is formed to cover the barrier material layer.

[0036] In some embodiments, the first sub-conductive material layer is made of polycrystalline silicon, the second sub-conductive material layer is made of polycrystalline silicon, the barrier material layer is made of metal nitride, and the third sub-conductive material layer is made of metal.

[0037] In some embodiments, a plurality of active regions arranged side-by-side along the first direction are formed in the substrate, and the contact portion is located within the active regions; the fabrication method further includes:

[0038] Remove the dielectric layer not covered by the conductor;

[0039] After the dielectric layer is removed, a capacitor contact plug is formed that contacts the active region; wherein the capacitor contact plug and the contact portion are arranged side by side and isolated from each other;

[0040] A capacitor is formed on the capacitor contact plug.

[0041] According to a second aspect of this disclosure, a semiconductor device is provided, which is prepared using the semiconductor device preparation method as described in the first aspect of this disclosure.

[0042] In some embodiments, the contact portion is made of polycrystalline silicon, and the wire includes a polycrystalline silicon layer, a metal nitride layer and a metal layer stacked sequentially, with the polycrystalline silicon layer located between the substrate and the metal nitride layer.

[0043] In the semiconductor device fabrication method provided in this disclosure, a dielectric layer covering the substrate is first formed. Then, a second region of the dielectric layer is thinned while keeping the thickness of the first region constant, thereby making the thickness of the second region less than the thickness of the first region. Next, a contact hole is formed in the first region, penetrating the dielectric layer and extending to the contact area. Since the orthographic projection of the first region onto the substrate surface covers the contact area, and part of this orthographic projection is located on both sides of the contact area along a first direction, the dielectric layer in the first region located in the contact area is removed when forming the contact hole, while the dielectric layer on both sides of the contact area is not removed. From a top view, the dielectric layer on both sides of the contact hole is thicker, while the dielectric layer in other areas (i.e., the second region) is thinner. Then, a conductive material layer covering the dielectric layer and filling the contact hole is formed, and the conductive material layer is etched to form wires and contacts. The conductive material layer at the bottom of the dielectric layer is thinner, while the conductive material layer at the bottom of the contact hole is thicker. During the etching of the conductive material layer, the conductive material layer at the bottom, located on top of the dielectric layer, is etched to the bottom first. At this point, the conductive material layer at the bottom, located inside the contact hole, has not yet been etched to the bottom. Therefore, some of the etching gas is concentrated in the contact hole to continue etching the conductive material layer inside the contact hole. Because the etching gas exhibits a selective etching ratio for the dielectric and conductive material layers and has a lower etching rate for the dielectric layer, when the conductive material layer inside the contact hole is etched, the dielectric layer near the contact hole (i.e., in the first region) is also etched. However, since the dielectric layer near the contact hole is thicker, when etching stops, the remaining dielectric layer thickness in the first and second regions can be approximately equal, making the surfaces of the first and second regions essentially flush and achieving a better bottom morphology. After removing the dielectric layer, a relatively flat substrate surface is obtained.

[0044] In summary, the embodiments of this disclosure pre-form dielectric layers with different thicknesses in different regions below the conductor material layer based on the different etching depths in each region during the etching process of the conductor material layer. This allows different thicknesses of the dielectric layer to be removed in each region during the etching process, ultimately resulting in a basically uniform thickness in each region of the dielectric layer after etching. This achieves a better bottom morphology and reduces the impact on subsequent processes or the performance of the final product. Attached Figure Description

[0045] Figures 1a to 1i This is a schematic diagram of the structure of a semiconductor device during the fabrication process, provided by an embodiment of this disclosure;

[0046] Figure 2 This is a schematic flowchart illustrating a method for fabricating a semiconductor device according to an embodiment of the present disclosure.

[0047] Figures 3a to 3h This is a schematic diagram of the structure of another semiconductor device provided in the present disclosure during the fabrication process;

[0048] Figure 4 A top view schematic diagram of the dielectric layer of a semiconductor device provided in an embodiment of this disclosure;

[0049] Figure 5 A schematic diagram of the structure of another semiconductor device after thinning the second region, provided in an embodiment of this disclosure;

[0050] Figures 6a to 6j This is a schematic diagram of the structure of a semiconductor device during the formation of a contact hole, provided by an embodiment of the present disclosure;

[0051] Figure 7 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of the present disclosure;

[0052] Figure 8 for Figure 7 A magnified view of a portion of the image;

[0053] Figure 9 for Figure 7 The diagram shows a top view of the semiconductor device. Detailed Implementation

[0054] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0055] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0056] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0057] It should be understood that spatial relation terms such as “below,” “under,” “below,” “below,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “below” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0058] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0059] Figures 1a to 1i This is a schematic diagram illustrating the fabrication process of a semiconductor device according to an embodiment of the present disclosure. Figure 1a This is a top view of the substrate. Figures 1b to 1h This is a cross-sectional view of the semiconductor device along line AA. Figure 1a As shown, the semiconductor device includes a substrate 10, which includes a plurality of active regions (AA) 11 and a shallow trench isolation structure (STI) 12. The plurality of active regions 11 are arranged in an array and isolated by the shallow trench isolation structure 12.

[0060] See Figure 1b An isolation layer 20 and a dielectric layer 30 are formed sequentially on a substrate 10. For example, the material of the isolation layer 20 includes, but is not limited to, silicon oxide, and the material of the dielectric layer 30 includes, but is not limited to, silicon nitride.

[0061] See Figure 1c A bit line contact hole 13 is formed, penetrating the dielectric layer 30 and the isolation layer 20 and extending into the active region 11. This bit line contact hole 13 is used to form a bit line contact plug in a subsequent process.

[0062] Next, a bit line material layer 40 is formed that covers the dielectric layer 30 and fills the bit line contact holes 13. For example, the bit line material layer 40 includes a polysilicon layer 41, a metal nitride layer 42, and a metal layer 43 stacked sequentially from bottom to top, wherein the polysilicon layer 41 fills the bit line contact holes 13 and covers the surface of the dielectric layer 30.

[0063] In some embodiments, a protective material layer 50 may also be formed over the bit line material layer to electrically isolate the bit line and the structures thereon. For example, the material of the protective material layer 50 may include, but is not limited to, silicon nitride.

[0064] Figures 1d to 1i The process of forming a bitline structure is illustrated, in which, Figure 1f for Figure 1e A magnified view of a portion of the image. Figure 1h for Figure 1g A magnified view of a portion of the image. Figure 1i This is a top view schematic diagram of a semiconductor device after the bit line structure has been formed. See also: Figure 1d A photoresist layer 60 is formed by covering the protective material layer 50, and the photoresist layer 60 is exposed and developed to form line patterns that correspond one-to-one with the bit lines in the photoresist layer 60. The lines extend along the Y direction, and multiple lines are arranged side by side along the X direction.

[0065] See Figure 1e , Figure 1f and Figure 1i The bit line material layer 40 is etched using a patterned photoresist layer 60. For example, a protective material layer 50, a metal layer 43, a metal nitride layer 42, and a polysilicon layer 41 are sequentially etched from top to bottom using the patterned photoresist layer 60 to form a protective layer 51 and a bit line structure 40'. This bit line structure 40' includes bit lines 41' located on the dielectric layer 30 and bit line contact plugs 42' located within contact holes 13. The bit lines 41' extend along the Y direction, and multiple bit lines 41' are arranged side-by-side along the X direction. The bit lines 41' include a polysilicon layer, a metal nitride layer, and a metal layer stacked sequentially from bottom to top. The bit line contact plugs 42' include a polysilicon layer.

[0066] like Figure 1fAs shown, in the bitline structure 40', the polysilicon layer at the bottom, located on the dielectric layer 30, is thinner, while the polysilicon layer at the bottom, located inside the contact hole 13, is thicker. During the etching process of the polysilicon layer, the polysilicon layer at the bottom, located on the dielectric layer 30, is etched to the bottom first. At this time, the polysilicon layer at the bottom, located inside the contact hole 13, has not yet been etched to the bottom. Therefore, some of the etching gas is concentrated in the contact hole 13 to continue etching the polysilicon layer. Since there is an etching selectivity ratio between the etching gas and the dielectric layer 30 and the polysilicon layer, when the polysilicon layer inside the contact hole 13 is etched, the dielectric layer near the contact hole 13 is also etched. Furthermore, the farther away from the contact hole 13, the lower the concentration of the etching gas, and the less the dielectric layer 30 is etched, resulting in a wedge-shaped structure of the dielectric layer 30 near the contact hole 13.

[0067] exist Figure 1g and Figure 1h During the removal of the dielectric layer 30 not covered by bit line 41', the dielectric layer 30 at the bevel of the wedge structure is removed first because it is thinner. As other areas of the dielectric layer 30 are removed, the bevel of the wedge structure is over-etched, causing the underlying isolation layer 20 and substrate 10 to be etched, forming defects 14. These defects 14 can affect subsequent processes and may even cause abnormal electrical performance of the final product.

[0068] In other implementations, if the dielectric layer 30 at the inclined surface of the wedge structure is just removed, the dielectric layer 30 in other areas will be insufficiently etched, resulting in dielectric layer 30 residue, which will affect subsequent processes and even the performance of the product.

[0069] Therefore, this disclosure provides a method for fabricating a semiconductor device. Figure 2 This is a schematic flowchart illustrating a method for fabricating a semiconductor device according to an embodiment of this disclosure. Figure 2 As shown, the method for fabricating this semiconductor device includes:

[0070] S100: A substrate is provided; wherein the substrate includes a contact region for forming a contact hole;

[0071] S200: Forming a dielectric layer covering the substrate; wherein the dielectric layer includes a first region and a second region surrounding the first region, the orthographic projection of the first region on the substrate surface covers the contact region, and the orthographic projection of a portion of the first region is located on both sides of the contact region along a first direction; the first direction is parallel to the plane of the substrate.

[0072] S300: Thinning the second region of the dielectric layer so that the surface of the second region is lower than the surface of the first region;

[0073] S400: After thinning the second region, a contact hole is formed in the first region that penetrates the dielectric layer and extends into the contact area;

[0074] S500: A conductive material layer that forms a covering dielectric layer and fills the contact holes;

[0075] S600: A portion of the conductive material layer located on the dielectric layer is removed to form a wire extending along the second direction; a portion of the conductive material layer located in the contact hole is removed to form a contact portion; and the remaining dielectric layer in the first region is thinned; wherein the surfaces of the thinned first region and the second region are substantially flush; the second direction is parallel to the plane of the substrate and perpendicular to the first direction.

[0076] Figures 3a to 3h This is a schematic diagram illustrating the fabrication process of another semiconductor device provided in this disclosure. The following will be combined with… Figures 3a to 3h The method for fabricating a semiconductor device provided in the embodiments of this disclosure is described.

[0077] See Figure 3a Step S100 is performed, in which a substrate 100 is provided, the substrate 100 including a contact region 101 for forming a contact hole.

[0078] In some embodiments, the substrate 100 includes an active region array and a shallow trench isolation structure 120. The active region array includes a plurality of active regions 110 arranged side-by-side along a first direction, and the shallow trench isolation structure 120 isolates the plurality of active regions 110. Each active region 110 includes a contact region 101 for forming a contact hole, which is used to form a contact portion in a subsequent process. Here, the first direction is the X direction.

[0079] For example, the semiconductor device may further include word lines extending along a first direction (X direction) and passing through a plurality of active regions 110 arranged side-by-side along the first direction. Each active region 110 may be traversed by two word lines to form two transistors arranged side-by-side. Each active region 110 also includes a source and a drain, which are horizontally disposed on opposite sides of the word line. Two transistors located in the same active region 110 share a common source, and a contact region 101 is located on the source, serving as a contact for electrically connecting the source and a wire. Here, the wire is a bit line.

[0080] See also Figure 3a Step S200 is executed to form a dielectric layer 300 covering the substrate 100. The dielectric layer 300 includes a first region 310 and a second region 320 including the first region 310. The orthographic projection of the first region 310 on the surface of the substrate 100 covers the contact region 101, and the orthographic projection of a portion of the first region is located on both sides of the contact region 101 along the first direction.

[0081] For example, the number of first regions 310 is the same as the number of contact regions 101, the dielectric layer 300 includes a plurality of first regions 310, and the second region 320 is other regions of the dielectric layer 300 besides the plurality of first regions 310.

[0082] Here, the orthographic projection of the first region 310 onto the surface of the substrate 100 covering the contact region 101 means that the orthographic projection of the first region 310 onto the surface of the substrate 100 covers the orthographic projection of the contact region 101 onto the surface of the substrate 100.

[0083] like Figure 3a As shown, the orthographic projection of the first region 310 on the surface of the substrate 100 covers the orthographic projection of the contact region 101 on the surface of the substrate. The size of the orthographic projection of the first region 310 on the surface of the substrate 100 along the first direction is larger than the size of the orthographic projection of the contact region 101 on the surface of the substrate along the first direction, and the orthographic projection portion of the first region 310 is located on both sides of the orthographic projection of the contact region 101.

[0084] Next, step S300 is performed to thin the second region 320 of the dielectric layer 300 so that the surface of the second region 320 is lower than the surface of the first region 310. Figures 3b to 3d This paper presents a method for thinning the second region 320.

[0085] See Figure 3b A first mask layer 810 covering the dielectric layer 300 is formed, and a first photoresist layer 910 covering the first mask layer 810 is formed. Next, the first photoresist layer 910 is exposed and developed to remove the first photoresist layer 910 on the second region 320, while retaining the first photoresist layer 910 on the first region 310, thus forming a patterned first photoresist layer 910.

[0086] See Figure 3c and Figure 3d The first mask layer 810 and the dielectric layer 300 on the second region 320 are simultaneously etched through a patterned first photoresist layer. The etching stops in the dielectric layer 300 to form a groove 330 in the dielectric layer 300. The fifth dimension L5 of the groove 330 along the third direction is smaller than the first dimension L1 of the dielectric layer 300 along the third direction. In other words, the depth of the groove 330 is less than the thickness of the dielectric layer 300, so that the surface of the second region 320 of the dielectric layer 300 is lower than the surface of the first region 310. Here, the third direction is the Z direction.

[0087] In this embodiment, the first mask layer 810 and the dielectric layer 300 have different etching rates under the same etching conditions, that is, the first mask layer 810 and the dielectric layer 300 have an etching selectivity under the same etching conditions. Here, setting the first mask layer enables the pattern of the first photoresist layer to be transferred to the dielectric layer more accurately, and by setting the etching rate of the dielectric layer to be less than the etching rate of the first mask layer, it is easier to control the etching endpoint, resulting in a smoother bottom of the groove.

[0088] In some embodiments, the etching selectivity ratio of the first mask layer 810 and the dielectric layer 300 under the same etching conditions satisfies, for example, greater than 2 or 3. In other words, the first mask layer 810 is easier to etch than the dielectric layer 300. Thus, after the first mask layer 810 is etched, the dielectric layer 300 is etched at a slower rate, making it easier to control the etching depth of the dielectric layer 300 (i.e., the depth of the groove 330), resulting in a more uniform thickness throughout the thinned second region 320.

[0089] For example, the dielectric layer 300 is made of silicon nitride, and the first mask layer 810 is made of, but is not limited to, silicon oxynitride, oxide or amorphous carbon, and the oxide includes, but is not limited to, silicon oxide.

[0090] After thinning the second region 320, the first photoresist layer 910 and the first mask layer 810 are removed. Here, the first photoresist layer 910 is removed to remove the photoresist material on the surface of the dielectric layer 300, avoiding photoresist material residue that could cause abnormalities in subsequent processes. The first mask layer 810 is also removed to expose the dielectric layer 300.

[0091] It should be understood that in some embodiments, a local planarization process or similar technique can also be used to thin the thickness of the second region. Compared to a local planarization process, the etching method for forming grooves provided in this disclosure can more precisely control the thickness of the thinning by controlling the etching time, and can more precisely control the thinned area by using a patterned first photoresist layer 910.

[0092] See Figure 3e In step S400, after thinning the second region 320, a contact hole 130 is formed in the first region 310, penetrating the dielectric layer 300 and extending into the contact region 101. Figure 3eAs shown, since the orthographic projection of the first region 310 onto the surface of the substrate 100 covers the contact region 101, and since the orthographic projection area of ​​the first region 301 is relatively large, a portion of the orthographic projection of the first region 301 is located on both sides of the contact region 101. Therefore, after the contact hole 130 is formed, the dielectric layer 300 in the first region 310 corresponding to the position of the contact hole 130 is removed, while the dielectric layers 300 located above and on both sides of the contact hole 130 are retained. From the top view, the dielectric layers 300 on both sides of the contact hole 130 are thicker, while the dielectric layers 300 in other regions (i.e., the second region 320) are thinner.

[0093] See also Figure 3e Step S500 is executed to form a conductive material layer 400 that covers the dielectric layer 300 and fills the contact hole 130.

[0094] In some embodiments, the fabrication method further includes forming a protective material layer 500 covering the conductive material layer 400 for electrically isolating the wires and structures thereon. For example, the protective material layer 500 may be made of, but is not limited to, silicon nitride.

[0095] In step S600, a portion of the conductive material layer 400 located on the dielectric layer 300 is removed to form a wire 401 extending in the second direction, and a portion of the conductive material layer 400 located in the contact hole 130 is removed to form a contact portion 402. Figures 3e to 3g The process of forming the wire structure is shown, in which, Figure 3g for Figure 3f A magnified view of a portion of the image.

[0096] See Figure 3e A second photoresist layer 920 is formed covering the protective material layer 500. The second photoresist layer 920 is exposed and developed to form line patterns corresponding to the conductors in the second photoresist layer 920.

[0097] See Figure 3f A protective material layer 500 and a conductive material layer 400 are sequentially etched from top to bottom through a patterned second photoresist layer to form a protective layer 510 and a conductive structure 400'. The conductive structure 400' includes a conductive wire 401 located on the dielectric layer 30 and a contact portion 402 located within the contact hole 130. The conductive wire 401 extends along a second direction, and multiple conductive wires 401 are arranged side-by-side along a first direction. Here, the second direction is the Y direction.

[0098] like Figure 3gAs shown, during the etching of the conductive material layer 400, the conductive material layer 400 inside the contact hole 130 and the conductive material layer 400 on the dielectric layer 300 are etched simultaneously. When the etching reaches the inside of the contact hole 130, the dielectric layer 300 is exposed. Then, the etching gas etches the conductive material layer 400 inside the contact hole 130, thus etching the dielectric layer 300 on both sides of the contact hole 130 (i.e., the first region 310). Since the etching rate of the dielectric layer 300 is relatively low, when etching the contact hole 130, most of the etching gas will concentrate inside the contact hole 130, and only a small portion of the etching gas will concentrate on both sides of the contact hole 130, i.e., the first region 310. Therefore, after the etching is completed, the dielectric layer on both sides of the contact hole 130 is consumed, thus the excess dielectric layer is consumed, thereby forming a relatively flat dielectric layer plane, i.e., the first region 310 and the second region 320 are basically flush or flush.

[0099] See Figure 3h When removing the dielectric layer 300 not covered by the wire structure 400′, since the thickness of each region of the dielectric layer 300 is uniform, each region of the dielectric layer 300 can be removed at the same time, and there will be no problem of local over-etching or local under-etching, so that the surface of the substrate 100 is relatively flat.

[0100] In the semiconductor device fabrication method provided in this disclosure, a dielectric layer covering the substrate is first formed. Then, a second region of the dielectric layer is thinned while keeping the thickness of the first region constant, thereby making the thickness of the second region less than the thickness of the first region. Next, a contact hole is formed in the first region, penetrating the dielectric layer and extending to the contact area. Since the orthographic projection of the first region onto the substrate surface covers the contact area, and part of this orthographic projection is located on both sides of the contact area along a first direction, the dielectric layer in the first region located in the contact area is removed when forming the contact hole, while the dielectric layer on both sides of the contact area is not removed. From a top view, the dielectric layer on both sides of the contact hole is thicker, while the dielectric layer in other areas (i.e., the second region) is thinner. Then, a conductive material layer covering the dielectric layer and filling the contact hole is formed, and the conductive material layer is etched to form wires and contacts. The conductive material layer at the bottom of the dielectric layer is thinner, while the conductive material layer at the bottom of the contact hole is thicker. During the etching of the conductive material layer, the conductive material layer at the bottom, located on top of the dielectric layer, is etched to the bottom first. At this point, the conductive material layer at the bottom, located inside the contact hole, has not yet been etched to the bottom. Therefore, some of the etching gas is concentrated in the contact hole to continue etching the conductive material layer inside the contact hole. Because the etching gas exhibits a selective etching ratio for the dielectric and conductive material layers and has a lower etching rate for the dielectric layer, when the conductive material layer inside the contact hole is etched, the dielectric layer near the contact hole (i.e., in the first region) is also etched. However, since the dielectric layer near the contact hole is thicker, when etching stops, the remaining dielectric layer thickness in the first and second regions can be approximately equal, making the surfaces of the first and second regions essentially flush and achieving a better bottom morphology. After removing the dielectric layer, a relatively flat substrate surface is obtained.

[0101] In summary, the embodiments of this disclosure pre-form dielectric layers with different thicknesses in different regions below the conductor material layer based on the different etching rates of the bottom regions during the etching process of the conductor material layer. This allows different thicknesses of the dielectric layer to be removed from each region during the etching process, ultimately resulting in a basically uniform thickness of the dielectric layer after etching, thus obtaining a better bottom morphology and reducing the impact on subsequent processes or the performance of the final product.

[0102] In some embodiments, such as Figure 3dAs shown, the dielectric layer 300 before thinning has a first dimension L1 along the third direction, and the dielectric layer 300 after thinning in the second region 320 has a second dimension L2 along the third direction. The second dimension L2 is determined based on the etching parameters of the wedge structure and the conductive material layer. The second dimension L2 cannot be too large; otherwise, after the contact portion is formed, the surface of the second region 320 will be higher than the surface of the first region 310, which will lead to over-etching of the first region 310 or under-etching of the second region 320 when removing the dielectric layer. The second dimension cannot be too small either; otherwise, after the contact portion is formed, the surface of the second region 320 will be lower than the surface of the first region 310, which will lead to over-etching of the second region 320 or under-etching of the first region 310 when removing the dielectric layer.

[0103] In this embodiment, the second dimension L2 and the first dimension L1 satisfy: 1 / 2L1≤L2≤3 / 4L1. This allows the thinned first region 310 and the second region 320 to be removed simultaneously, resulting in a flat substrate surface.

[0104] Figure 4 This is a top view schematic diagram of the dielectric layer of a semiconductor device provided in an embodiment of this disclosure. Figure 4 In this embodiment, the active region 110 is invisible and the conductor 401 has not yet been formed. The active region 110 and the conductor 401 are only provided to more clearly illustrate the first and second regions. In this embodiment, the orthographic projection of the first region 310 onto the surface of the substrate 100 covers the orthographic projection of the contact region 101 onto the surface of the substrate 100, and along the second direction (Y direction), the edge of the orthographic projection of the first region 310 onto the surface of the substrate 100 is flush with the edge of the contact region 101. Thus, the thickness of the dielectric layer 300 on the contact region 101 is uniform, and after the contact hole 130 is formed, the depth of the contact hole 130 is the same everywhere, thereby making the height of the contact portion equal everywhere after the contact portion is formed. Furthermore, since the edge of the orthographic projection of the first region 310 onto the surface of the substrate 100 is flush with the edge of the contact region 101, after the conductor 401 is formed, the conductor 401 is located on the second region 320 of the dielectric layer 300, which can ensure that the thickness of the conductor 401 is basically the same everywhere, thereby improving the transmission performance of the conductor structure.

[0105] In some embodiments, the orthographic projection of the first region 310 onto the surface of the substrate 100 contacts or partially overlaps with the adjacent active region 110 along the first direction.

[0106] like Figure 1f As shown, in some embodiments, the inclined surface of the wedge structure extends above the adjacent active region 110, and the first region 310 is set based on the inclined surface of the wedge structure. Therefore, the orthographic projection of the first region 310 on the surface of the substrate 100 contacts or partially overlaps with the active region 110, which can ensure that the thickness of the dielectric layer 300 is uniform throughout after the wire structure is formed.

[0107] Here, the contact between the orthographic projection of the first region 310 on the surface of the substrate 100 and the adjacent active region 110 along the first direction means that the edge of the orthographic projection of the first region 310 on the surface of the substrate 100 is aligned with the edge of the active region 110, such as... Figure 3a As shown.

[0108] Figure 5 This is a schematic diagram of the structure of another semiconductor device provided in this disclosure after thinning the second region, as shown in the example. Figure 5 As shown, in some embodiments, the overlapping area of ​​the orthographic projection of the first region 310 on the surface of the substrate 100 and the adjacent active region 110 has a third dimension L3 along the first direction, and the active region 110 has a fourth dimension L4 along the first direction. The third dimension L3 and the fourth dimension L4 satisfy: L3 < 1 / 5L4.

[0109] Figures 6a to 6j This is a schematic diagram of the semiconductor device in the process of forming a contact hole according to an embodiment of this disclosure. The following is a description of the structure of the semiconductor device in the process of forming a contact hole. Figures 6a to 6j A method for forming a contact hole is described in detail in the embodiments of this disclosure.

[0110] See Figure 6a and Figure 6b A first sub-conductive material layer 410, a second mask layer 820, a third mask layer 830, and a fourth mask layer 840 are sequentially stacked on the dielectric layer 300, wherein the surface of the first sub-conductive material layer 410 located on the first region 310 and the second region 320 is substantially flush. The second mask layer 820 includes an oxide layer 821, a first spin-coated hard mask layer (SOH) 822, and a first silicon oxynitride layer 823 sequentially stacked from bottom to top. The third mask layer 830 includes a second spin-coated hard mask layer 831 and a second silicon oxynitride layer 832 sequentially stacked from bottom to top. The fourth mask layer 840 includes another oxide layer 841, a third spin-coated hard mask layer 842, and a third silicon oxynitride layer 843 sequentially stacked from bottom to top.

[0111] See Figure 6c A third photoresist layer 930 is formed covering the fourth mask layer 840. The third photoresist layer 930 is exposed and developed to form a photoresist pattern corresponding to the contact hole in the third photoresist layer 930.

[0112] See Figure 6c and Figure 6dThe fourth mask layer 840 is etched through a patterned third photoresist layer 930. Specifically, the third silicon oxynitride layer 843, the third spin-coated hard mask layer 842, and another oxide layer 841 are etched sequentially from top to bottom through the patterned third photoresist layer 930, thereby transferring the photoresist pattern into the fourth mask layer 840. The third silicon oxynitride layer 843 and the third spin-coated hard mask layer 842 are then removed to reduce the thickness of the patterned fourth mask layer 840.

[0113] See Figure 6e The third mask layer 830 is etched through a patterned fourth mask layer to transfer the pattern to the third mask layer 830, forming a mask pattern. Specifically, the second silicon oxynitride layer 832 and the second spin-coated hard mask layer 831 are sequentially etched through the patterned fourth mask layer 840.

[0114] join Figure 6f A backfill layer 700 is formed, which covers a patterned third mask layer 830. For example, the material of the backfill layer 700 includes, but is not limited to, oxides, such as silicon oxide.

[0115] See Figure 6g A planarization process is used to treat the backfill layer 700 so that the top of the backfill layer 700 is substantially flush with the top of the third mask layer. Next, the third mask layer is removed, forming a first trench 710 in the backfill layer 700. The first trench 710 is located above the contact area.

[0116] For example, the third mask layer can be removed using either a dry etching process or a wet etching process.

[0117] See Figure 6g and Figure 6h The second mask layer 820 is etched through the first trench 710 to form the second trench 824 in the second mask layer 820. Specifically, the first silicon oxynitride layer 823, the first spin-coated hard mask layer 822 and the oxide layer 821 are etched sequentially from top to bottom through the first trench 710 to form the second trench 824, and then the first silicon oxynitride layer 823 is removed.

[0118] See Figure 6i The first sub-conductive material layer 410, the dielectric layer 300, the isolation layer 200, and the contact area 101 are sequentially etched through the second trench to form a contact hole 130.

[0119] The contact hole formation method provided in this embodiment first forms a mask pattern corresponding to the contact area in the third mask layer. Then, by forming a backfill layer and removing the mask pattern, a first trench is formed on the contact area. The second mask layer is then etched step by step through the first trench, followed by etching the first sub-conductive material layer, the dielectric layer, and the contact area to form the contact hole. This contact hole formation method results in higher dimensional and positional accuracy of the formed contact hole.

[0120] In some embodiments, the conductive material layer 400 includes a first sub-conductive material layer 410, a second sub-conductive material layer 420, a barrier material layer 430, and a third sub-conductive material layer 440.

[0121] See Figure 6j After forming a contact hole that penetrates the first sub-conductive material layer 410, the dielectric layer 300, and the insulating layer 200 and extends to the contact area, a second sub-conductive material is filled into the contact hole. Then, the second sub-conductive material is etched back to form a second sub-conductive material layer 420, wherein the top of the second sub-conductive material layer 420 is flush with the top of the first sub-conductive material layer 410. Finally, the oxide layer 821 is removed, exposing the first sub-conductive material layer 410 and the second sub-conductive material layer 420.

[0122] See Figure 3e A barrier material layer 430 is formed covering the first sub-conductive material layer 410 and the second sub-conductive material layer 420, and a third sub-conductive material layer 440 is formed covering the barrier material layer 430.

[0123] See Figure 3f and Figure 3g After removing part of the conductive material layer, a wire 401 is formed. The portion of wire 401 located on the dielectric layer 300 includes a first sub-conductive layer 411, a barrier layer 431, and a third sub-conductive layer 441 arranged sequentially from bottom to top. The portion of wire 401 located on the contact portion 402 includes a second sub-conductive layer 421, a barrier layer 431, and a third sub-conductive layer 441 arranged sequentially from bottom to top. The contact portion 402 includes a portion of the second sub-conductive layer 421.

[0124] In some embodiments, the material of the first sub-conductive material layer 410 is the same as the material of the second sub-conductive material layer 420. For example, both the material of the first sub-conductive material layer 410 and the material of the second sub-conductive material layer 420 may be polycrystalline silicon. In another embodiment, the materials of the first sub-conductive material layer 410 and the second sub-conductive material layer 420 may be different; for example, the materials of the first sub-conductive material layer 410 and the second sub-conductive material layer 420 may be doped polycrystalline silicon with different concentrations or types of ions, respectively.

[0125] For example, the barrier material layer may be made of metal nitrides, such as titanium nitride or tungsten nitride. The third conductive material layer may be made of metals, such as tungsten, cobalt, or copper.

[0126] It should be understood that, in other embodiments, a second sub-conductive material layer may be redeposited after the first sub-conductive material layer is completely removed, covering the dielectric layer and filling the contact holes.

[0127] In some embodiments, the preparation method further includes:

[0128] Remove the dielectric layer not covered by the conductor;

[0129] After removing the dielectric layer, a capacitor contact plug is formed that contacts the drain of the active region; wherein the capacitor contact plug and the contact portion are arranged side by side and isolated from each other;

[0130] A capacitor is formed on the capacitor contact plug.

[0131] It should be understood that the embodiments of this disclosure illustrate the process of forming bit line structures, but the application scope of the semiconductor device fabrication method provided by the embodiments of this disclosure is not limited thereto. The semiconductor device fabrication method provided by the embodiments of this disclosure is applicable to any etching process, especially the etching of high aspect ratio structures, which can make the high aspect ratio structure have a better bottom morphology.

[0132] This disclosure also provides a semiconductor device. Figure 7 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of the present disclosure. Figure 8 for Figure 7 A partially enlarged schematic diagram, Figure 9 for Figure 7 The diagram shows a top view of the semiconductor device, in which... Figure 9 The capacitor contact plug is not shown. For example... Figures 7 to 9 As shown, the semiconductor device includes:

[0133] The substrate 100 includes a shallow trench isolation structure 120 and a plurality of active regions 110 arranged in parallel along a first direction, wherein the shallow trench isolation structure 120 isolates the plurality of active regions 110.

[0134] The wire structure 400' includes a wire 401 and a contact portion 402 connected to the wire 401. The wire 401 is located on the substrate 100 and extends along the second direction. The contact portion 402 extends into the active region 110.

[0135] Dielectric layer 300 is located between conductor 401 and substrate 100;

[0136] The capacitor structure includes a capacitor contact plug 610 and a capacitor. The capacitor is located on the capacitor contact plug 610. The capacitor contact plug 610 is in contact with the active region 110 and isolated from the contact portion 402. The contact surface between the capacitor contact plug 610 and the active region 110 is flat.

[0137] Here, both the first and second directions are parallel to the plane where the substrate is located, and the first direction is perpendicular to the second direction.

[0138] The semiconductor device provided in this embodiment is fabricated using the above-described semiconductor device fabrication method. Therefore, the surface of the substrate 100 is flat. After the capacitor contact plug 610 is formed, the contact surface between the capacitor contact plug 610 and the active region 110 is also flat and defect-free. This improves the performance of the semiconductor device.

[0139] In some embodiments, the contact portion 402 includes a first sub-conductive layer 411 made of polysilicon. The wire 401 includes a first sub-conductive layer 411 (or a second sub-conductive layer 421), a barrier layer 431, and a third sub-conductive layer 441 stacked sequentially. The second sub-conductive layer 421 is made of polysilicon, the barrier layer 431 is made of metal silicide, and the third sub-conductive layer 441 is made of metal. That is, the wire 401 includes a polysilicon layer, a metal nitride layer, and a metal layer stacked sequentially from bottom to top, with the polysilicon layer located between the substrate 100 and the metal nitride layer.

[0140] In some embodiments, the semiconductor device further includes a protective layer 510 located on the wire structure 400' for isolating the wire structure 400' from structures thereon.

[0141] In some embodiments, an isolation structure 450 is further provided between the conductor structure 400' and the capacitor structure 600. For example, the isolation structure 450 includes a nitride layer-oxide layer-nitride layer arranged sequentially along a first direction to form a NON structure.

[0142] In some embodiments, such as Figure 9 As shown, the conductive structure is a bit line structure. The semiconductor device may also include word lines 140, which extend along a first direction (X direction) and pass through a plurality of active regions 110 arranged side by side along the first direction. Each active region 110 may be passed through by two word lines 140 to form two transistors arranged side by side. The active region 110 also includes a source 111 and a drain 112, which are horizontally disposed on both sides of the word line 140. The two transistors located in the same active region 110 share a common source 111. A wire 601 is electrically connected to the source 111 through a contact portion, and a capacitor is electrically connected to the drain 112 through a capacitor contact plug.

[0143] It should be understood that the semiconductor device provided in the embodiments of this disclosure can be a DRAM chip, and of course, it can also be other chips or other semiconductor devices, which will not be listed here. The beneficial effects of this semiconductor device can be referred to the beneficial effects of the semiconductor device preparation method described above, and will not be repeated here.

[0144] It should be understood that the phrase "an embodiment" or "one embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this disclosure. Therefore, "in one embodiment" or "one embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this disclosure, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure. The sequence numbers of the above-described embodiments are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0145] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0146] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A method of manufacturing a semiconductor device, characterized by, The method includes: A substrate is provided; wherein the substrate includes a contact region for forming a contact hole; A dielectric layer is formed covering the substrate; wherein the dielectric layer includes a first region and a second region surrounding the first region, the orthographic projection of the first region onto the substrate surface covers the contact region, and a portion of the orthographic projection is located on both sides of the contact region along a first direction; the first direction is parallel to the plane of the substrate. Thin the second region of the dielectric layer so that the surface of the second region is lower than the surface of the first region; After thinning the second region, the contact hole is formed in the first region, penetrating the dielectric layer and extending into the contact area; A conductive material layer is formed that covers the dielectric layer and fills the contact holes; A portion of the conductive material layer located on the dielectric layer is removed to form a wire extending along the second direction, a portion of the conductive material layer located within the contact hole is removed to form a contact portion, and the remaining dielectric layer in the first region is thinned; wherein, the surfaces of the thinned first region and the second region are substantially flush; the second direction is parallel to the plane of the substrate and perpendicular to the first direction.

2. The method of producing a semiconductor device according to claim 1, wherein Within the second region, the dielectric layer before thinning has a first dimension along the third direction, and the dielectric layer after thinning has a second dimension along the third direction; Wherein, the second dimension is greater than or equal to one-half of the first dimension and less than or equal to three-quarters of the first dimension, and the third dimension is perpendicular to the plane where the substrate is located.

3. The method of producing a semiconductor device according to claim 1, wherein Along the second direction, the edge of the orthographic projection of the first region onto the substrate surface is flush with the edge of the contact region.

4. The method of producing a semiconductor device according to claim 1, wherein The substrate has a plurality of active regions arranged in parallel along the first direction, and the contact region is located in the active regions; The orthographic projection of the first region onto the substrate surface contacts or partially overlaps with the adjacent active region along the first direction.

5. The method of producing a semiconductor device according to claim 4, wherein The first region, when projected onto the substrate surface, overlaps with the adjacent active region in a region having a third dimension along the first direction. The active region also has a fourth dimension along the first direction, and the third dimension is less than one-fifth of the fourth dimension.

6. The method of producing a semiconductor device according to claim 1, wherein The second region for thinning the dielectric layer includes: A first mask layer is formed to cover the dielectric layer; wherein the first mask layer and the dielectric layer have different etching rates under the same etching conditions; The first mask layer and the dielectric layer located in the second region are etched to form a groove in the dielectric layer; wherein the fifth dimension of the groove along a third direction is smaller than the first dimension of the dielectric layer along the third direction, the third direction being perpendicular to the plane of the substrate.

7. The method of producing a semiconductor device according to claim 6, wherein The etching selectivity ratio of the first mask layer and the dielectric layer under the same etching conditions is greater than 2.

8. The method of producing a semiconductor device according to Claim 1, wherein The step of forming a contact hole in the first region that penetrates the dielectric layer and extends into the contact region includes: A second mask layer and a third mask layer are sequentially formed on the dielectric layer; The third mask layer is patterned to form a mask pattern in the third mask layer over the first region; A backfill layer is formed, which covers the mask pattern; Remove the mask pattern to form a first trench in the backfill layer; The second mask layer is etched through the first trench to form a second trench in the second mask layer; The second trench is used to sequentially etch the dielectric layer and the contact area to form a contact hole.

9. The method of producing a semiconductor device according to Claim 8, wherein The second mask layer comprises an oxide layer, a first spin-coated hard mask layer, and a first silicon oxynitride layer stacked sequentially; the oxide layer is located between the dielectric layer and the first spin-coated hard mask layer; and / or, The third mask layer includes a second spin-coated hard mask layer and a second silicon oxynitride layer stacked sequentially, with the second spin-coated hard mask layer located between the second mask layer and the second silicon oxynitride layer.

10. The method of producing a semiconductor device according to Claim 8, wherein The conductive material layer includes a first sub-conductive material layer, a second sub-conductive material layer, a barrier material layer, and a third sub-conductive material layer; The formation of the conductive material layer covering the dielectric layer and filling the contact hole includes: Before forming the second mask layer, a first sub-conductive material layer is formed to cover the dielectric layer; wherein the surfaces of the first sub-conductive material layer located in the first region and the second region are substantially flush. When the dielectric layer and the contact area are sequentially etched through the second trench to form a contact hole, the first sub-conductive material layer is also etched through the second trench to form the contact hole. After forming the contact hole, a second sub-conductive material is filled into the contact hole to form a second sub-conductive material layer; wherein the top of the second sub-conductive material layer is flush with the top of the first sub-conductive material layer. A barrier material layer is formed covering the first sub-conductive material layer and the second sub-conductive material layer; A third sub-conductive material layer is formed to cover the barrier material layer.

11. The method of producing a semiconductor device according to claim 10, wherein The first sub-conductive material layer is made of polycrystalline silicon, the second sub-conductive material layer is made of polycrystalline silicon, the barrier material layer is made of metal nitride, and the third sub-conductive material layer is made of metal.

12. The method of producing a semiconductor device according to Claim 1, wherein The substrate has multiple active regions arranged side-by-side along the first direction, and the contact portion is located within the active regions; the fabrication method further includes: Remove the dielectric layer not covered by the conductor; After the dielectric layer is removed, a capacitor contact plug is formed that contacts the active region; wherein the capacitor contact plug and the contact portion are arranged side by side and isolated from each other; A capacitor is formed on the capacitor contact plug.

13. A semiconductor device, characterized by comprising: The semiconductor device is prepared by the semiconductor device preparation method as described in any one of claims 1 to 12.

14. The semiconductor device of claim 13, wherein, The contact portion is made of polycrystalline silicon, and the wire comprises a polycrystalline silicon layer, a metal nitride layer and a metal layer stacked sequentially, with the polycrystalline silicon layer located between the substrate and the metal nitride layer.

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