Wafer and chip testing method for semiconductor

Abstract

The present application provides a semiconductor wafer and chip testing method, a redistribution layer is formed on the surface of the wafer or chip, the redistribution layer redistributes the pads, so that the same wafer and chip testing system can be used to test the performance of the wafer or chip before and after turning over. The present application redistributes the pads by setting the redistribution layer, so that the same testing system can be used to test the performance of the wafer or chip before and after turning over.

Description

Technical Field

[0001] This invention relates to the field of semiconductor testing technology, and more particularly to a method for testing semiconductor wafers and chips. Background Technology

[0002] In the research and development of semiconductor wafers or chips, it is crucial to verify and analyze the circuits formed at each process step in order to identify weaknesses in chip design and manufacturing processes in a timely and accurate manner.

[0003] The manufacturing process of wafers or chips requiring flip-flops generally includes front-side and back-side processes. After the back-side process is completed, a testing system is used for performance evaluation. To promptly evaluate the performance of the front-side process, a separate testing system corresponding to the front-side process is fabricated. The two testing systems cannot be shared, increasing R&D, production, and monitoring costs. For example, the fabrication process of a back-illuminated image sensor includes front-side and back-side processes. The front-side process includes forming a photodiode array and metal interconnect layer on the front side of the silicon substrate, while the back-side process includes back-side thinning, vias connecting to the front side, and forming pads.

[0004] Figure 1 The diagram shows the structure of an existing back-illuminated image sensor after the front-side fabrication process is completed. A pixel array 101 is disposed within a semiconductor substrate 10. A metal interconnect layer connected to the pixel array 101 is also disposed on the semiconductor substrate 10. The metal interconnect layer forms internal circuits 111, 112, and 113. Front-side pads 121, 122, and 123 are connected to the internal circuits 111, 112, and 113, respectively.

[0005] Figure 2 The diagram shows the structure of an existing back-illuminated image sensor after the back-side fabrication process. After the front-side fabrication is completed, the wafer is flipped to continue the back-side fabrication. The semiconductor substrate 10 is thinned, and vias 13 connected to the metal interconnect layer and back-side pads 141, 142, and 143 leading out from the metal interconnect layer are formed. Then, a filter layer 15 and microlenses 16 are formed on the pixel array 101. Back-side pad 141 connects to internal circuit 113, back-side pad 142 connects to internal circuit 112, and back-side pad 143 connects to internal circuit 111. Therefore, the front-side and back-side pads corresponding to the same internal circuits are flipped left and right in position.

[0006] After the back-illuminated image sensor is fabricated, electrical and image performance tests are required using probe cards to confirm product performance and yield. The probes on the probe card correspond to the distribution of the back-side pads. However, during the R&D or production phase of back-illuminated image sensors, after the front-side process is completed, electrical and partial image performance tests are necessary to promptly identify any major issues in the front-side circuit design and manufacturing process. This allows for rapid implementation of preventative measures and improvement plans, preventing problematic wafers and chips from reaching the back-side processing stages. Furthermore, it avoids the inability to distinguish between front-side and back-side issues after fabrication, which increases the difficulty of problem identification and extends the project cycle.

[0007] Because back-illuminated image sensors are flipped from front to back during fabrication, their internal circuitry is also flipped horizontally. Therefore, testing systems suitable for back-side testing cannot be used for front-side testing. The existing solution is:

[0008] 1) We would need to develop a separate testing system specifically for the front pads, but this would increase R&D costs and consume human resources.

[0009] 2) Skip the front-side testing and only perform back-side testing after the image sensor is completed. However, this makes it impossible to promptly confirm whether there are problems with the front-side design or manufacturing process, increasing project risk. It may also make it impossible to distinguish whether the problem is on the front or the back, increasing the difficulty of identifying project issues. Summary of the Invention

[0010] The purpose of this invention is to provide a semiconductor wafer and chip testing method, which uses the same testing system to test the electrical performance of the wafer or chip before and after flipping, thereby saving R&D costs and shortening the R&D cycle.

[0011] Based on the above considerations, the present invention provides a method for testing semiconductor wafers and chips, comprising:

[0012] The wafer or chip surface has a metal interconnect layer and pads. A redistribution layer is formed on the wafer or chip surface, which redistributes the pads so that the performance of the wafer or chip before and after flipping can be tested using the same test system.

[0013] Optionally, the method for fabricating the redistribution layer includes:

[0014] Design a pad and pad interconnect layout that sets each pad as an independent interconnect area and metal area connected to the metal interconnect layer. The layout design also reconnects the independent interconnect areas and metal areas and rearranges the positions of the metal areas to match the requirements of the wafer and chip test system.

[0015] The layout pattern is transferred to the surface of a wafer or chip through photolithography and etching processes, so that the wafer or chip can be tested using a wafer and chip testing system.

[0016] Optionally, the method for fabricating the redistribution layer includes:

[0017] Design the pad and pad interconnect layout, which introduces new interconnects and new pads, and performs routing design for the new interconnects and pads to match the requirements of the wafer and chip test system.

[0018] Deposit a metal layer on the surface of a wafer or chip;

[0019] The layout pattern is transferred to the surface of a wafer or chip through photolithography and etching processes, so that the wafer or chip can be tested using a wafer and chip testing system.

[0020] Optionally, the metal is any one of aluminum, copper, or an aluminum-copper alloy.

[0021] Optionally, it can be applied to performance testing of wafers or chips that require flip-flop processes.

[0022] Optionally, it can be applied to the front-side performance testing of back-illuminated image sensor wafers or chips:

[0023] After the front-side process of the back-illuminated image sensor is completed, pads connected to the metal interconnect layer are formed on the front side of the image sensor wafer or chip.

[0024] A redistribution layer is fabricated on the front side of the wafer or chip. The pads are redistributed through the redistribution layer so that the wafer and chip test system corresponding to the back-side process can be used for performance testing of the wafer or chip after the front-side process.

[0025] The wafer and chip testing method of the present invention has the following beneficial effects:

[0026] By setting up a redistribution layer, the pads are redistributed to test the performance of the wafer or chip before and after flipping using the same test system. Attached Figure Description

[0027] Other features, objects, and advantages of the invention will become more apparent from the following detailed description of non-limiting embodiments, taken in conjunction with the accompanying drawings.

[0028] Figure 1 This is a schematic diagram of the structure of an existing back-illuminated image sensor after the front-side process has been completed.

[0029] Figure 2 This is a schematic diagram of the structure of an existing back-illuminated image sensor after the back-side process has been completed.

[0030] Figure 3The diagram shows the pad distribution on the back of a back-illuminated image sensor.

[0031] Figure 4 The diagram shows the probe distribution of the probe card corresponding to the pads on the back of the back-illuminated image sensor.

[0032] Figure 5 The diagram shows the pad distribution on the front of a back-illuminated image sensor.

[0033] Figure 6 The diagram shown is a schematic diagram of a redistribution layer formed on the front side, as provided by the present invention.

[0034] Throughout the figures, the same or similar reference numerals denote the same or similar devices (modules) or steps. Detailed Implementation

[0035] Numerous specific details are set forth in the following description to provide a full understanding of the invention. However, the invention can be practiced in many other ways different from those described herein, and those skilled in the art can make similar extensions without departing from the spirit of the invention. Therefore, the invention is not limited to the specific embodiments disclosed below.

[0036] Secondly, the present invention is described in detail using schematic diagrams. When describing the embodiments of the present invention in detail, the schematic diagrams are merely examples for ease of explanation and should not limit the scope of protection of the present invention.

[0037] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the method of the present invention will be described in detail below with reference to the accompanying drawings.

[0038] This invention provides a testing method for semiconductor wafers and chips, which forms a redistribution layer on the surface of the wafer or chip. The redistribution layer redistributes the pads on the surface of the wafer or chip, so that the electrical performance of the wafer or chip before and after flipping can be tested using the same wafer and chip testing system.

[0039] This invention can be specifically applied to the research and development or production stages of back-illuminated image sensors. The fabrication process of a back-illuminated image sensor includes front-side and back-side processes. The front-side process includes forming a photodiode array and a metal interconnect layer on the front side of a semiconductor substrate, while the back-side process includes back-side thinning, connection to the front side, and formation of pads. After the back-side process is completed, the back-illuminated image sensor is formed. Typically, after the back-side process is completed, the image sensor undergoes wafer or chip testing.

[0040] During the R&D or production phases, electrical or partial image performance testing is required after the front-side process is completed. This prevents problematic wafers and chips from reaching the back-side processing, allowing for timely confirmation of any major issues with the front-side circuit design and process flow. However, because back-illuminated image sensors are flipped from the front to the back during fabrication, the positions of the back-side and front-side pads for the same internal circuitry are different.

[0041] Figure 3 The diagram shows the pad distribution on the back of the back-illuminated image sensor. Figure 4 The diagram shows the probe layout of the probe card corresponding to the back pads of the back-illuminated image sensor. Figure 5 The pad distribution diagram on the front side of the back-illuminated image sensor is shown.

[0042] Please refer to Figure 3 and Figure 4 Taking two rows of parallel pads as an example, probes P1P2, P3, P4, P5, P6, Q1, Q2, Q3, Q4, Q5, and Q6 on the probe card 40 of the back-illuminated image sensor contact pads A1, A2, A3, A4, A5, A6, B1, B2, B3, B4, B5, and B6 on the back side 20, respectively, to apply test signals to the corresponding pads and internal circuits for performance testing. The internal circuits connected to each pad may be the same or different, and the position of the pad and the connected circuit must correspond to the probes on the probe card.

[0043] Each pad includes a metal area and a wiring area. The metal area is used for contact with the probes on the probe card, and the wiring area connects to the internal circuitry. The probes on the probe card contact the metal area, and then apply test signals to the internal circuitry through the wiring area for testing. Please refer to [reference needed]. Figure 3 Taking the back side 20 of the image sensor as an example, the pad A1 includes a metal area A11 and a wiring area A12. The metal area A11 is used to contact the probe P1, and the wiring area A12 is connected to the internal circuit.

[0044] Please refer to Figure 5 As shown in the figure, the front side 30 of the image sensor has the same internal circuit connected to the front and back pads, which are flipped left and right and are in different positions. The internal circuits connected to pads a1 and A6 in the front side 30 of the image sensor are the same, the internal circuits connected to pads a2 and A5 are the same, the internal circuits connected to pads a3 and A4 are the same, the internal circuits connected to pads a4 and A3 are the same, the internal circuits connected to pads a5 and A2 are the same, and the internal circuits connected to pads a6 and A1 are the same.

[0045] Using probe card 40 cannot complete the testing of the front pads. For the front side, the internal circuitry for probe P1 contacting a1 is different from that for probe P1 contacting A1, which would apply an incorrect test signal and cause the test to fail.

[0046] This invention designs a redistribution layer that rearranges the pads on the front side 30. The rearranged pads can be tested using a probe card 40, saving development time and costs.

[0047] Specifically, methods for redistributing pads in a redistribution layer include:

[0048] First, design the layout of pads and pad interconnects. This layout sets each pad as an independent interconnect area and metal area connected to the metal interconnect layer. The layout design also reconnects the independent interconnect areas and metal areas and rearranges the positions of the metal areas to match the requirements of the wafer and chip test system.

[0049] Then, the layout pattern is transferred to the wafer surface through photolithography and etching processes, so that the wafer or chip can be tested using a wafer and chip testing system.

[0050] This method forms the front 30'. The metal area of ​​each pad on the front 30' is separated from the interconnect area and then reconnected, as shown below. Figure 6 As shown. The metal area of ​​pad a1 is connected to the wiring area of ​​pad a6, the metal area of ​​pad a2 is connected to the wiring area of ​​pad a5, the metal area of ​​pad a3 is connected to the wiring area of ​​pad a4, the metal area of ​​pad a4 is connected to the wiring area of ​​pad a3, the metal area of ​​pad a5 is connected to the wiring area of ​​pad a2, and the metal area of ​​pad a6 is connected to the wiring area of ​​pad a1. Similarly, the metal area of ​​pad b1 is connected to the wiring area of ​​pad b6, the metal area of ​​pad b2 is connected to the wiring area of ​​pad b5, the metal area of ​​pad b3 is connected to the wiring area of ​​pad b4, the metal area of ​​pad b4 is connected to the wiring area of ​​pad b3, the metal area of ​​pad b5 is connected to the wiring area of ​​pad b2, and the metal area of ​​pad b6 is connected to the wiring area of ​​pad b1.

[0051] Therefore, when testing is performed through probe card 40, P1 contacts the metal area of ​​a1, and what is actually being tested is the internal circuit connected to a6, that is, the internal circuit connected to A1, so that the correct test signal can be input and the test can be completed.

[0052] This rerouting method is preferably applicable when no new metal layer is required, i.e., rewiring can be performed using existing pad layers. This method utilizes existing pad layers by rewiring the metal and interconnect areas of the separated pads, where the metal areas can be repositioned as needed to match probe positions, making it suitable for wafer or chip testing systems.

[0053] In another embodiment, the method of redistributing pads via a new redistribution layer includes:

[0054] Design the pad and pad interconnect layout, which introduces new interconnects and new pads, and performs routing design for the new interconnects and pads to match the requirements of the wafer and chip test system.

[0055] Deposit a metal layer on the surface of a wafer or chip;

[0056] The layout pattern is transferred to the surface of a wafer or chip through photolithography and etching processes, so that the wafer or chip can be tested using a wafer and chip testing system.

[0057] This method creates new pads and interconnects, and is preferably suitable for designs that require new pad layers, i.e., designs where existing pad layers cannot be reconnected. The metal and interconnect areas of the new pad layer can be positioned as needed to match the pin locations, making it suitable for wafer or chip testing systems.

[0058] The deposited metal can be aluminum, copper, aluminum-copper alloys, or other metals.

[0059] In this embodiment, by designing redistribution layer routing, the internal circuits corresponding to the front pads and back pads at the same location are identical. The redistributed front pads can be directly compatible with test systems suitable for back wafer or chip testing.

[0060] It should be noted that the technical solution provided by the present invention is not limited to wafer or chip testing of back-illuminated image sensors, but can also be used for electrical or other performance testing of wafers or chips that require flipping processes during manufacturing.

[0061] In summary, this invention provides a semiconductor wafer and chip testing method, wherein a redistribution layer is formed on the surface of the wafer or chip, and the redistribution layer redistributes the pads to enable the use of a wafer and chip testing system to test the electrical performance of the wafer or chip before and after flipping. This invention, by setting a redistribution layer to redistribute the pads, allows for the testing of the performance of the wafer or chip before and after flipping using the same testing system.

[0062] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from the spirit or essential characteristics of the invention. Therefore, the embodiments should be considered exemplary and not restrictive in any way. Furthermore, it is clear that the word "comprising" does not exclude other elements and steps, and the word "a" does not exclude a plurality. Multiple elements recited in the apparatus claims may also be implemented by a single element. The terms "first," "second," etc., are used to denote names and do not indicate any particular order.

Claims

1. A method for testing semiconductor wafers and chips, characterized in that, include: The wafer or chip surface has a metal interconnect layer and pads. A redistribution layer is formed on the wafer or chip surface, which redistributes the pads so that the performance of the wafer or chip before and after flipping can be tested using the same test system. Among them, the front-side performance testing of wafers or chips used in back-illuminated image sensors: After completing the front-side process of the back-illuminated image sensor, pads are formed on the front side of the image sensor wafer or chip to connect with the metal interconnect layer. A redistribution layer is fabricated on the front side of the wafer or chip. The pads are redistributed through the redistribution layer so that the wafer or chip test system corresponding to the back-side process can be used for performance testing of the wafer or chip after the front-side process.

2. The wafer and chip testing method according to claim 1, characterized in that, Methods for redistributing pads in a redistribution layer include: The layout of the pads and pad interconnects is designed such that each pad is set as an independent interconnect area and metal area connected to the metal interconnect layer, and the independent interconnect areas and metal areas are reconnected to match the requirements of the wafer and chip test system. The layout pattern is transferred to the surface of the wafer or chip through photolithography and etching processes, and the pads are redistributed so that the wafer or chip can be tested using a wafer and chip testing system.

3. The wafer and chip testing method according to claim 1, characterized in that, Methods for redistributing pads in a redistribution layer include: Design the layout of pads and pad connections, and introduce new pads and connections in the layout design to match the requirements of wafer and chip testing systems; Deposit a metal layer on the surface of a wafer or chip; The layout pattern is transferred to the surface of a wafer or chip through photolithography and etching processes, so that the wafer or chip can be tested using a wafer and chip testing system.

4. The wafer and chip testing method according to claim 3, characterized in that, The metal is any one of aluminum, copper, or an aluminum-copper alloy.

5. The wafer and chip testing method according to any one of claims 1 to 4, characterized in that, It is used for performance testing of wafers or chips that require flip-flop processes.

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