Semiconductor structure and method of manufacturing a semiconductor structure

Abstract

The present disclosure provides a semiconductor structure and a preparation method of the semiconductor structure, the semiconductor structure comprising a substrate, a substrate contact and a memory cell, the memory cell comprising: an active layer, the active layer being disposed on the substrate, the active layer having opposite top and bottom surfaces; a gate word line component, the gate word line component being disposed on the top and / or bottom surface of the active layer; a bit line component, the bit line component being electrically connected to a source / drain region in the active layer; a capacitor, the capacitor being electrically connected to the source / drain region in the active layer; and the substrate contact being in contact with the substrate, and a side surface of the active layer being connected to the substrate contact. By disposing the gate word line component on the top and / or bottom surface of the active layer and connecting the side surface of the active layer to the substrate contact, the active layer can be stacked in three-dimensional direction while overcoming the floating gate effect of the transistor, thereby improving the element density of the semiconductor memory device.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for preparing the semiconductor structure. Background Technology

[0002] With the rapid development of semiconductor memory technology, the component density of Dynamic Random Access Memory (DRAM) needs to be continuously increased to meet more complex requirements. Currently, DRAM typically adopts a structure of one transistor and one capacitor (1T1C) and is designed and laid out on a two-dimensional plane. Increasing the integration density of DRAM is often achieved by miniaturizing the individual components. However, this miniaturization is limited by the size limits of each component, and further reduction in component size can also lead to transistor leakage problems. Summary of the Invention

[0003] Based on this, and in order to improve the device density of semiconductor memory devices while minimizing transistor leakage current, it is necessary to provide a semiconductor structure and a method for fabricating the semiconductor structure.

[0004] To address the aforementioned technical problems, a first aspect of this disclosure provides a semiconductor structure comprising a substrate, substrate contacts, and a memory cell, wherein the memory cell comprises:

[0005] An active layer is disposed on the substrate, and the active layer has opposing top and bottom surfaces;

[0006] A gate word line component, wherein the gate word line component is disposed on the top surface and / or bottom surface of the active layer;

[0007] Bit line components, the bit line components being electrically connected to the source / drain regions in the active layer;

[0008] A capacitor, which is electrically connected to the source / drain region in the active layer;

[0009] The substrate contact is connected to the substrate, and the side of the active layer is connected to the substrate contact.

[0010] In one embodiment, there are a plurality of said memory cells along a first direction, wherein the bit line components in the plurality of said memory cells are connected to form a bit line extending along the first direction.

[0011] In one embodiment, the first direction is perpendicular to the substrate surface.

[0012] In one embodiment, the storage unit is disposed on both opposite sides of the substrate contact.

[0013] In one embodiment, the storage cells on both sides of the substrate contact are symmetrically arranged along the substrate contact.

[0014] In one embodiment, a plurality of the memory cells are provided along a second direction, which intersects the first direction, wherein the gate word line components in the plurality of memory cells are connected to form word lines extending along the second direction.

[0015] In one embodiment, the bit line component and the capacitor are disposed on the side of the active layer away from the substrate contact.

[0016] In one embodiment, a bit line contact is provided between the bit line component and the active layer; and / or, a polysilicon contact is provided between the capacitor and the active layer.

[0017] In one embodiment, the gate word line component includes a gate and a word line connection portion, the gate is stacked on the top surface and / or bottom surface of the active layer, and the word line connection portion is disposed on the side of the gate away from the active layer.

[0018] In one embodiment, the active layer includes a first doped region and a second doped region, the first doped region having a first doping type, the second doped region having a second doping type opposite to the first doping type, the first doped region being disposed on the side of the second doped region away from the substrate contact, and the first doped region constituting the source / drain region.

[0019] In one embodiment, the material of the substrate contact includes a doped semiconductor material, the second doped region is in contact with the substrate contact, and the doping type of the doped semiconductor material is the second doping type.

[0020] In one embodiment, the storage unit includes two or more of the capacitors controlled by the same bit line component.

[0021] Furthermore, another aspect of this disclosure provides a method for fabricating a semiconductor structure, comprising the following steps:

[0022] An active layer precursor is formed on a substrate, the active layer precursor having opposing top and bottom surfaces;

[0023] Gate word line components are formed on the top and / or bottom surfaces of the active layer precursor;

[0024] Forming a substrate contact that connects the substrate and the active layer precursor;

[0025] Forming bitline components and capacitors electrically connected to the active layer precursor; and

[0026] The active layer precursor is doped to form an active layer, the source / drain regions of which are electrically connected to the bit line component and the capacitor.

[0027] In one embodiment, the step of doping the active layer precursor to form an active layer includes:

[0028] A first ion diffusion is performed at the location where the active layer precursor is electrically connected to the bit line component and the capacitor to form a first doped region having a first doping type, the first doped region constituting the source / drain region of the active layer; and a second ion diffusion is performed at the location where the active layer precursor is connected to the substrate contact to form a second doped region having a second doping type, the second doping type being the opposite of the first doping type.

[0029] In one embodiment, the step of forming an active layer precursor located on a substrate includes:

[0030] A substrate is provided, the substrate comprising a base and a multilayer precursor material layer and a multilayer filler material layer located on the base, the precursor material layer and the filler material layer being alternately stacked;

[0031] The filler material layer is removed, and the precursor material layer in the substrate is etched to form a multilayer active layer precursor located on the substrate.

[0032] In one embodiment, the step of arranging multiple active layer precursors along a first direction to form bit line components electrically connected to the active layer precursors includes:

[0033] A bit line is formed extending along the first direction, the bit line comprising a plurality of bit line components electrically connected to each of the active layer precursors.

[0034] In one embodiment, each layer has a plurality of active layer precursors, and the plurality of active layer precursors located in the same layer are arranged along a second direction. The step of forming gate word line components on the top and / or bottom surfaces of the active layer precursors includes: forming word lines extending along the second direction, the word lines including a plurality of gate word line components located on the top and / or bottom surfaces of each active layer precursor.

[0035] In the semiconductor structure of at least one of the above embodiments, it includes a substrate contact and a memory cell. The memory cell includes a substrate, an active layer, a gate word line component, a bit line component, and a capacitor. The active layer is disposed on the substrate and has opposing top and bottom surfaces. The gate word line component is disposed on the top and / or bottom surfaces of the active layer. The bit line component is electrically connected to the source / drain regions in the active layer. The capacitor is electrically connected to the source / drain regions in the active layer. The substrate contact is contacted and connected to the substrate. The side surface of the active layer is connected to the substrate contact. By disposing the gate word line component on the top and / or bottom surfaces of the active layer and connecting the side surface of the active layer to the substrate contact, the active layers can be stacked in three dimensions while overcoming the floating gate effect of transistors, thereby increasing the device density of the semiconductor memory device.

[0036] The above description is merely an overview of the technical solution of the present invention. In order to better understand the technical means of the present invention and to implement it in accordance with the contents of the specification, the preferred embodiments of the present invention are described in detail below with reference to the accompanying drawings. Attached Figure Description

[0037] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other embodiments can be obtained based on these drawings without creative effort.

[0038] Figure 1 This is a schematic diagram of a semiconductor structure according to an embodiment of the present disclosure;

[0039] Figure 2 In order to be in Figure 1 A schematic diagram of a semiconductor structure with further added memory cells based on the existing structure;

[0040] Figure 3 In order to be in Figure 1 A schematic diagram of a semiconductor structure with further added memory cells based on the existing structure;

[0041] Figure 4 In order to be in Figure 1 A schematic diagram of a semiconductor structure with further added memory cells based on the existing structure;

[0042] Figure 5 for Figure 1 A schematic diagram of a partial cross-section structure taken along the AA' direction;

[0043] Figure 6 for Figure 1 A schematic diagram of a partial cross-section structure taken along the BB' direction;

[0044] Figure 7 This is a schematic diagram of the semiconductor structure according to yet another embodiment of the present disclosure;

[0045] Figure 8 This is a schematic diagram of the steps in a method for fabricating a semiconductor structure according to an embodiment of the present disclosure;

[0046] Figure 9 A schematic diagram of the substrate used to fabricate the semiconductor structure;

[0047] Figure 10 For the reason Figure 9 A schematic diagram of the structure after etching.

[0048] Figure 11 For the reason Figure 10 A schematic diagram of the structure after the word lines are formed;

[0049] Figure 12 For the reason Figure 11 A schematic diagram of the structure after the base contact element is formed;

[0050] Figure 13 For the reason Figure 12 A schematic diagram of the structure forming bit lines and capacitors;

[0051] The reference numerals and their meanings in the accompanying drawings are as follows:

[0052] 100, Substrate; 110, Substrate Contact; 210, Active Layer; 2101, First Doped Region; 2102, Second Doped Region; 220, Bit Line Component; 221, Bit Line; 230, Capacitor; 240, Gate Word Line Component; 241, Word Line; 2401, Gate; 2402, Word Line Connection; 250, Bit Line Contact; 260, Capacitor Contact; 270, Gate Dielectric Layer; 300, Precursor Material Layer; 310, Active Layer Precursor; 400, Filler Material Layer; 500, Support Material Layer. Detailed Implementation

[0053] To facilitate understanding of this disclosure, a more complete description will now be given with reference to the accompanying drawings, in which preferred embodiments of the present disclosure are shown. However, this disclosure may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0054] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of this disclosure. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0055] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. The manner of electrical connection is used to indicate that current can be conducted between multiple electrically connected elements, specifically in the manner in which one element directly contacts another element, or one element is connected to another element through another conductive element. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or parts, these elements, components, areas, layers, and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or part from another element, component, area, layer, or part. Therefore, without departing from the teachings of this disclosure, the first element, component, region, layer or part discussed below may be represented as a second element, component, region, layer or part.

[0056] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “under” the other element or feature will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0057] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0058] One embodiment of this disclosure provides a semiconductor structure, including a substrate, substrate contacts, and a memory cell, wherein the memory cell includes:

[0059] An active layer is disposed on a substrate and has a top surface and a bottom surface.

[0060] Gate word line component, the gate word line component is disposed on the top surface and / or bottom surface of the active layer;

[0061] Bit line components are electrically connected to the source / drain regions in the active layer;

[0062] A capacitor is electrically connected to the source / drain region in the active layer.

[0063] The substrate contact is connected to the substrate, and the side of the active layer is connected to the substrate contact.

[0064] It can be understood that the active layer is the main structure of the transistor, containing the transistor's channel, and the gate word line component is used to control the channel's on / off state. The active layer has source / drain regions; in this text, source / drain region can refer to the source region and / or the drain region without special distinction. Furthermore, the bit line component and capacitor are electrically connected to the source / drain regions, meaning the bit line component is electrically connected to one of the source and drain regions, and the capacitor is electrically connected to the other. For example, the bit line component is electrically connected to the drain region, while the capacitor is electrically connected to the source region, with the bit line component and capacitor spaced apart. The top and bottom surfaces of the active layer are only used to distinguish them from the sides. The top and bottom surfaces of the active layer are positioned opposite each other, and the sides are adjacent to the top and bottom surfaces, but this does not necessarily mean that the top and bottom surfaces of the active layer are in a vertically aligned position. For example, the top and bottom surfaces of the active layer can be positioned left and right respectively, in which case the corresponding sides are positioned front and back or top and bottom.

[0065] To facilitate understanding of the specific implementation of the semiconductor structure in the above embodiments, please refer to... Figure 1 As shown, it provides a schematic diagram of a semiconductor structure in one embodiment. Figure 1The illustrated semiconductor structure includes a substrate 100, a substrate contact 110, and a memory cell. The memory cell includes an active layer 210, a bit line component 220, a capacitor 230, and a gate word line component 240. The active layer 210 has opposing top and bottom surfaces, and the gate word line component 240 is disposed on the top surface of the active layer 210. The bit line component 220 is electrically connected to the source / drain regions in the active layer 210, and the capacitor 230 is electrically connected to the source / drain regions in the active layer 210. The substrate contact 110 is contacted and connected to the substrate 100, and the sidewalls of the active layer 210 are connected to the substrate contact 110.

[0066] Reference Figure 1 As shown, to facilitate the description of the specific location of each component in this semiconductor structure, Figure 1 The z-direction in the coordinate axes shown is the first direction, which is perpendicular to the base surface. Figure 1 The x-direction in the coordinate axes shown is the second direction, with Figure 1 The y-direction in the shown coordinate axes is the third direction. In other examples, the first direction, the second direction, and the third direction may intersect each other obliquely or perpendicularly. Figure 1 In a preferred embodiment, the first direction, the second direction, and the third direction are perpendicular to each other.

[0067] Reference Figure 1 As shown, an active layer 210 is disposed on a substrate 100, and the active layer 210 can be located on a plane defined by a second direction and a third direction. The first direction passes through the top and bottom surfaces of the active layer 210. The top surface of the active layer 210 is the surface away from the substrate 100, and the bottom surface of the active layer 210 is the surface close to the substrate 100. In the first direction, the top surface of the active layer 210 is located above the bottom surface. In the first direction, the gate word line component 240 is located above the active layer 210.

[0068] In traditional technology, word lines are usually placed on the side of the active layer rather than on the top and / or bottom surface. Figure 1 The semiconductor device shown transfers the gate word line component 240 to the top and / or bottom surface of the active layer 210, thereby leaving the side surface of the active layer 210 empty. The empty side surface of the active layer 210 is then connected to the substrate contact 110, thereby enabling the transistors to continue stacking in the first direction while minimizing the accumulation of charge on the transistors due to the floating gate effect.

[0069] Figure 2 It shows in Figure 1 A semiconductor structure that is a further extension of the existing semiconductor structure. (Refer to...) Figure 2As shown, this semiconductor structure contains multiple memory cells, which are arranged sequentially along a first direction. When multiple memory cells are arranged, the bit line components 220 of the multiple memory cells can be connected to form a bit line 221 extending along the first direction. By arranging multiple memory cells in the first direction, the memory cells can be stacked in the height direction, increasing the transistor stacking density.

[0070] Figure 3 It shows in Figure 1 A semiconductor structure that is a further extension of the existing semiconductor structure. (Refer to...) Figure 3 As shown, this semiconductor structure contains multiple memory cells arranged sequentially along a second direction. When multiple memory cells are arranged, their gate word line components 240 can be connected to form word lines 241 extending along the second direction. Arranging multiple memory cells in the second direction allows for the stacking of memory cells in that direction, increasing the transistor stacking density.

[0071] Figure 4 It shows in Figure 1 A semiconductor structure that is a further extension of the existing semiconductor structure. (Refer to...) Figure 4 As shown, in this semiconductor structure, there are multiple memory cells along both a first direction and a second direction. Multiple bit line components 220 of the multiple memory cells arranged along the first direction are connected to form bit lines 221, and multiple gate word line components 240 of the multiple memory cells arranged along the second direction are connected to form word lines 241. Figure 4 In the semiconductor structure shown, transistors are stacked in multiple layers in both the height and horizontal directions, and precise control of each transistor can be achieved through bit line 221 and word line 241.

[0072] In this semiconductor structure, the memory cells are stacked on a plane defined by a first direction and a second direction, and can also be stacked in a third direction to further increase the stacking density of the memory cells. (Refer to...) Figure 4 As shown, in the third direction, the base contact 110 has opposing two side surfaces, and storage cells are connected to both side surfaces of the base contact 110. Optionally, in order to facilitate the simultaneous manufacture of storage cells on both sides of the base contact 110, the storage cells on both sides of the base contact 110 are symmetrically arranged along the base contact 110. Figure 4 This demonstrates that while stacking transistors in the height direction, each active layer 210 is also connected to the substrate contact 110, thus effectively overcoming the floating gate effect caused by stacking memory cells in the vertical direction.

[0073] Reference Figures 1-4As shown, bit line component 220 is disposed on the side of active layer 210 away from substrate contact 110. Capacitor 230 is also disposed on the side of active layer 210 away from substrate contact 110. Bit line component 220 is electrically connected to active layer 210 via bit line contact 250, and capacitor 230 is electrically connected to active layer 210 via capacitor contact 260. The materials of bit line contact 250 and capacitor contact 260 may include, but are not limited to, polysilicon.

[0074] Figures 1-4 The semiconductor device shown will be transferred to the top and / or bottom surface of the active layer 210 to obtain memory cells that can be stacked in three dimensions. However, the stacked memory cells also change the transistors from the traditional vertical placement to the horizontal placement, and the traditional ion implantation method used for vertically placed transistors is not conducive to the formation of... Figures 1-4 The transistors are placed laterally in the semiconductor structure described above. To address this issue, the active layer 210 in the semiconductor structure disclosed herein also has the following doping structure.

[0075] Reference Figure 5 and Figure 6 As shown, Figure 5 It also shows Figure 1 The cross section in the AA' direction contains a doped structure of the active layer 210, which lies on a plane defined by the first direction and the third direction. Figure 6 It shows Figure 1 The active layer 210 has a doped structure in the BB' cross section, which lies on a plane defined by a first direction and a second direction. The active layer 210 includes a first doped region 2101 and a second doped region 2102. The first doped region 2101 has a first doping type, and the second doped region 2102 has a second doping type opposite to the first doping type. The first doped region 2101 constitutes the source / drain region. (Refer to...) Figure 6 As shown, the active layer 210 may have multiple first doped regions 2101 spaced apart by second doped regions 2102, and a channel may be formed between the multiple first doped regions 2101. Furthermore, the first doping type can be either N-type or P-type doping, and the second doping type can be either N-type or P-type doping. Figure 5 and Figure 6 In the specific example, the first doping type is N-type doping, and the second doping type is P-type doping.

[0076] Reference Figure 5The second doped region 2102 of the active layer 210 is in contact with the substrate contact 110, and the first doped region 2101 is located on the side of the second doped region 2102 away from the substrate contact 110, to facilitate electrical connection to the bit line component 220 and the capacitor 230. It is understood that the bit line component 220 and the capacitor 230 may also be located on the side of the active layer 210 away from the substrate contact 110. (Refer to...) Figure 6 There are two first doped regions 2101, corresponding to the source region and the drain region respectively. The two first doped regions 2101 are arranged along the second direction to form a channel along the second direction in the second doped region 2102. The gate 2401 is located above the channel to control the conduction and depletion of electrons in the channel.

[0077] The first doped region 2101 and the second doped region 2102 of the active layer 210 can be formed by ion diffusion. Specifically, the active layer precursor 310 can be placed in an ion atmosphere to be doped, and ions can diffuse into the active layer precursor 310 through a concentration difference, so that specific parts of the active layer precursor 310 are doped with specific ions. In actual operation, a portion of the active layer precursor 310 can be exposed to the doped ion atmosphere by masking to perform the first ion diffusion, forming the first doped region 2101 as the source / drain region. Then, the source / drain region is masked, and the second ion diffusion is performed to form the second doped region 2102. Ion diffusion can achieve doping of the active layer precursor 310 along a third direction, and it can spontaneously form a gradient concentration doping. The doping concentration is high in the region near the diffusion surface and low in the region far from the diffusion surface. Therefore, the doping concentration is low in the region of the first doped region 2101 and the boundary between the second doped region 2102, forming a lightly doped drain region.

[0078] The substrate contact 110 in this semiconductor structure is made of a doped semiconductor material having a second doping type. The material of the substrate contact 110 may include, but is not limited to, p-type doped silicon material, to electrically connect the second doped region 2102 to the substrate 100 and prevent electrons from accumulating in the active layer 210.

[0079] Additionally, refer to Figure 5As shown, the gate word line component 240 includes a gate 2401 and a word line connection portion 2402. The gate 2401 is stacked on the top surface of the active layer 210, and the word line connection portion 2402 is disposed on the side of the gate 2401 away from the active layer 210. It can be understood that the word line connection portion 2402 is used to connect with a word line connection portion 2402 in an adjacent memory cell to form a word line 241. In some other embodiments, the gate word line component 240 may also be disposed on the bottom surface of the active layer 210. Additionally, the memory cell has a gate dielectric layer 270, which is disposed between the gate 2401 and the active layer 210 to insulate and space the gate 2401 from the active layer 210.

[0080] Figure 7 A schematic diagram of another semiconductor structure of this disclosure is shown, with reference to... Figure 7 As shown, the semiconductor structure also includes a substrate 100, substrate contacts 110, and memory cells. Figure 1 The difference lies in the semiconductor structure. Figure 7 The memory cell in the semiconductor structure includes two capacitors 230 controlled by the same bit line component 220. It is understood that, corresponding to the two capacitors 230, the active layer 210 also has an additional source / drain region and the resulting additional channel. It is understood that the plurality of source / drain regions in the active layer 210 are arranged along a second direction to facilitate control of the two capacitors 230 by a gate word line component 240 extending along the second direction. The capacitor 230 may include an upper electrode, a dielectric layer, and a lower electrode, with the dielectric layer located between the upper and lower electrodes. The materials of the upper and lower electrodes may include, but are not limited to, materials such as titanium nitride, tantalum, tungsten, ruthenium, titanium nitride, tantalum nitride, and tungsten nitride, or one or more of these. The material of the dielectric layer may include, but is not limited to, materials such as silicon dioxide, hafnium oxide, zirconium oxide, lanthanum oxide, and aluminum oxide, or one or more of these.

[0081] Reference Figure 8 As shown, another embodiment of this disclosure also provides a method for preparing... Figure 4 The method for preparing the semiconductor structure includes steps S1 to S5.

[0082] Step S1: Form an active layer precursor with opposing top and bottom surfaces located on the substrate.

[0083] The active layer precursor is the substrate of the active layer. The active layer can be formed by doping the substrate in a predetermined region. The material of the active layer precursor can be, but is not limited to, monocrystalline silicon. For example, the material of the active layer precursor can also be other semiconductor materials, including polycrystalline silicon.

[0084] In some specific examples of this embodiment, the step of forming an active layer precursor on a substrate includes: providing a substrate, the substrate including a substrate and a multilayer precursor material layer and a multilayer filler material layer disposed on the substrate, the precursor material layer and the filler material layer being alternately stacked; etching the precursor material layer in the substrate and removing the filler material layer to form the substrate and the multilayer active layer precursor on the substrate.

[0085] One structural schematic diagram of the provided substrate can be referred to. Figure 9 As shown, a substrate 100 has two layers of precursor material 300 and two layers of filler material 400 stacked on it. The precursor material layers 300 and filler material layers 400 are alternately stacked, and the two precursor material layers 300 are arranged along a first direction. A support material layer 500 is also provided on the substrate to connect the precursor material layers 300 and the substrate 100. The support material layer 500 is used to fix the precursor material layers 300 to the substrate 100 and maintain the position of the precursor material layers 300. Optionally, the support material layer 500 is made of the same material as the precursor material layers 300.

[0086] The substrate is etched and the filler material layer 400 is removed so that the precursor material layer 300 forms a multilayer active layer precursor 310 on the substrate 100. Figure 10 For the reason Figure 9 The diagram shows the etched structure. The active layer precursor 310 is connected to the support material layer 500. Multiple active layer precursors 310 are arranged along a first direction. Each layer also contains multiple active layer precursors 310, with multiple active layer precursors 310 within the same layer arranged along a second direction. The multiple active layer precursors 310 are stacked in both the first and second directions. A spacing is provided between two rows of active layer precursors 310 in the third direction for subsequent formation of the substrate contact 110.

[0087] Step S2: Form gate word line components on the top and / or bottom surfaces of the active layer precursor 310.

[0088] The method may include forming a gate dielectric layer on the top and / or bottom surface of the active layer precursor 310 before forming the gate word line component. When the active layer precursor 310 is made of silicon, silicon oxide can be formed on the surface of the active layer precursor 310 by oxidation to obtain the gate dielectric layer.

[0089] The step of forming gate word line components on the top and / or bottom surface of the active layer precursor 310 includes: forming word lines 241 extending along a second direction. Figure 11 For the reason Figure 10 The structure in the diagram is formed by the character line 241.

[0090] Reference Figure 11 As shown, word line 241 includes multiple gate word line components located on the top and / or bottom surfaces of each active layer precursor 310. Each gate word line component may include a gate and a word line connection portion, and the gate and word line connection portions in each gate word line component are made of the same material. Adjacent word line connections are interconnected in a second direction to form a connected word line 241. The word line 241 can be formed by depositing a conductive material on the active layer precursor 310 and removing the conductive material outside the word line 241 region by etching. Figure 11 In the semiconductor structure shown, word lines 241 are formed only on the top surface of each active layer precursor 310. In some other specific examples, word lines 241 may also be formed on both the top and bottom surfaces of each active layer precursor 310.

[0091] Step S3: Form a substrate contact 110 that connects the substrate 100 and the active layer precursor 310.

[0092] Figure 12 For the reason Figure 11 The diagram shows the structure after the substrate contact 110 is formed. The substrate contact 110 can be formed by depositing the material of the substrate contact 110 on the side of the active layer precursor 310. (Refer to...) Figure 12 As shown, the substrate contact 110 is formed in the space between the two rows of active layer precursors 310.

[0093] The material of the substrate contact 110 may include a doped semiconductor material, for example, the substrate contact 110 may be selected from a polycrystalline silicon material having a second doping type.

[0094] Step S4, forming bit line components and capacitor 230 electrically connected to the active layer precursor 310.

[0095] The step of arranging and distributing the multilayer active layer precursors 310 along a first direction to form bit line components electrically connected to the active layer precursors 310 includes: forming bit lines 221 extending along the first direction, the bit lines 221 including a plurality of bit line components electrically connected to each active layer precursor 310 respectively.

[0096] Figure 13 For the reason Figure 12 The diagram shows the structure forming bit line 221 and capacitor 230. (Refer to...) Figure 13 As shown, bit line 221 and capacitor 230 are formed on the side of active layer precursor 310 away from substrate contact 110. Furthermore, before forming the bit line component and capacitor 230, the process includes forming bit line contact 250 and capacitor contact 260 at the end of active layer 210 away from substrate contact 110. The materials of bit line contact 250 and capacitor contact 260 may include polysilicon.

[0097] Step S5: Doping the active layer precursor 310 to form the active layer 210.

[0098] After doping to form an active layer 210, the following can be prepared: Figure 4 The semiconductor structure shown shows that the doped region distribution in the active layer 210 is visible in... Figures 5-6 .

[0099] The step of doping the active layer precursor 310 to form the active layer 210 includes: performing a first ion diffusion at the location of the active layer precursor 310 electrically connected to the bit line component 220 and the capacitor 230 to form a first doped region 2101 having a first doping type, the first doped region 2101 constituting the source / drain region of the active layer 210, the source / drain region of the active layer 210 being electrically connected to the bit line component 220 and the capacitor 230; and performing a second ion diffusion at the location of the active layer precursor 310 connected to the substrate contact 110 to form a second doped region 2102 having a second doping type opposite to the first doping type.

[0100] During the first ion diffusion, the side of the active layer precursor 310 closest to the substrate contact 110 can be shielded, allowing ions to diffuse into the active layer precursor 310 from the portion electrically connected to the bit line component 220 and the capacitor 230, forming multiple first doped regions 2101 electrically connected to the bit line component 220 and the capacitor 230, respectively. During the second ion diffusion, the surface of the active layer precursor 310 other than the side used to contact the substrate contact 110 can be shielded, and ions diffuse inward along the side of the active layer precursor 310 used to contact the substrate contact 110, forming a second doped region 2102. The first doped region 2101 and the second doped region 2102 formed by ion diffusion have a doping concentration gradient. For example, in the first doped region 2101, the doping concentration gradually decreases inward along the surface electrically connected to the bit line component 220 and the capacitor 230. In the second doped region 2102, the doping concentration gradually decreases from the surface inwards from the contact member 110 on the substrate. This results in a lightly doped drain region being formed at the channel of the active layer 210.

[0101] The active layer 210 has two or more first doped regions 2101, which respectively contact the bit line contact 250 and the capacitor contact 260 to be electrically connected to the bit line component 220 and the capacitor 230. The multiple first doped regions 2101 are spaced apart by second doped regions 2102. Optionally, the second doped regions 2102 in the active layer 210 contact the substrate contact 110, and the first doped regions 2101 are located on the side of the second doped regions 2102 away from the substrate contact 110.

[0102] The semiconductor structure disclosed herein includes a substrate contact and a memory cell. The memory cell includes a substrate, an active layer, a gate word line component, a bit line component, and a capacitor. The active layer is disposed on the substrate and has opposing top and bottom surfaces. The gate word line component is disposed on the top and / or bottom surface of the active layer. The bit line component is electrically connected to the source / drain regions in the active layer. The capacitor is electrically connected to the source / drain regions in the active layer. The substrate contact is connected to the substrate, and the side surface of the active layer is connected to the substrate contact. By disposing the gate word line component on the top and / or bottom surface of the active layer and connecting the side surface of the active layer to the substrate contact, the active layers can be stacked in three dimensions while overcoming the floating gate effect of transistors, thereby increasing the device density of the semiconductor memory device.

[0103] Please note that the above embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure.

[0104] It should be understood that, unless otherwise expressly stated herein, there is no strict order in which the steps are executed, and these steps may be executed in other orders. Moreover, at least some of the steps may include multiple sub-steps or multiple stages, which are not necessarily completed at the same time, but may be executed at different times, and the execution order of these sub-steps or stages is not necessarily sequential, but may be executed in turn or alternately with other steps or at least some of the sub-steps or stages of other steps.

[0105] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0106] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

Claims

1. A semiconductor structure, characterized in that, It includes a substrate, substrate contacts, and a storage unit, wherein the storage unit includes: An active layer is arranged in an array along a first direction and a second direction on the substrate, and the active layer has a top surface and a bottom surface opposite to each other. A gate word line component, wherein the gate word line component is disposed on the top surface and / or bottom surface of the active layer; Bit line components, the bit line components being electrically connected to the source / drain regions in the active layer; A capacitor, which is electrically connected to the source / drain region in the active layer; The substrate contact is in contact with the substrate along the first direction, and the side of the active layer is connected to the substrate contact; Wherein, the first direction is perpendicular to the surface of the substrate, and the second direction intersects with the first direction.

2. The semiconductor structure according to claim 1, characterized in that, There are a plurality of said memory cells along the first direction, wherein the bit line components in the plurality of said memory cells are connected to form a bit line extending along the first direction.

3. The semiconductor structure according to claim 2, characterized in that, The storage unit is provided on both sides of the substrate contact.

4. The semiconductor structure according to claim 3, characterized in that, The storage cells on both sides of the substrate contact are symmetrically arranged along the substrate contact.

5. The semiconductor structure according to claim 2, characterized in that, There are a plurality of said memory cells along the second direction, wherein the gate word line components of the plurality of said memory cells are connected to form a word line extending along the second direction.

6. The semiconductor structure according to any one of claims 1 to 5, characterized in that, The bit line component and the capacitor are disposed on the side of the active layer away from the substrate contact.

7. The semiconductor structure according to claim 6, characterized in that, A bit line contact is provided between the bit line component and the active layer; and / or, A capacitor contact is provided between the capacitor and the active layer.

8. The semiconductor structure according to any one of claims 1 to 5 and 7, characterized in that, The gate word line component includes a gate and a word line connection portion. The gate is stacked on the top surface and / or bottom surface of the active layer, and the word line connection portion is disposed on the side of the gate away from the active layer.

9. The semiconductor structure according to claim 8, characterized in that, The active layer includes a first doped region and a second doped region. The first doped region has a first doping type, and the second doped region has a second doping type opposite to the first doping type. The first doped region is disposed on the side of the second doped region away from the substrate contact. The first doped region constitutes the source / drain region.

10. The semiconductor structure according to claim 9, characterized in that, The substrate contact is made of a doped semiconductor material, the second doped region is in contact with the substrate contact, and the doping type of the doped semiconductor material is the second doping type.

11. The semiconductor structure according to any one of claims 1-5, 7 and 9-10, characterized in that, The storage unit includes two or more capacitors controlled by the same bit line component.

12. A method for fabricating a semiconductor structure, characterized in that, The steps include the following: An active layer precursor is formed on a substrate and arranged in an array along a first direction and a second direction, the active layer precursor having opposing top and bottom surfaces; Gate word line components are formed on the top and / or bottom surfaces of the active layer precursor; A substrate contact is formed, the substrate contact being connected to the active layer precursor and connected to the substrate along the first direction; Forming bitline components and capacitors electrically connected to the active layer precursor; and The active layer precursor is doped to form an active layer, the source / drain regions of which are electrically connected to the bit line component and the capacitor; Wherein, the first direction is perpendicular to the surface of the substrate, and the second direction intersects with the first direction.

13. The method for preparing a semiconductor structure according to claim 12, characterized in that, The step of doping the active layer precursor to form an active layer includes: A first ion diffusion is performed at the location where the active layer precursor is electrically connected to the bit line component and the capacitor to form a first doped region having a first doping type, the first doped region constituting the source / drain region of the active layer; and a second ion diffusion is performed at the location where the active layer precursor is connected to the substrate contact to form a second doped region having a second doping type, the second doping type being the opposite of the first doping type.

14. The method for fabricating a semiconductor structure according to claim 12 or 13, characterized in that, The steps for forming an active layer precursor located on a substrate include: A substrate is provided, the substrate comprising a base and a multilayer precursor material layer and a multilayer filler material layer located on the base, the precursor material layer and the filler material layer being alternately stacked; The filler material layer is removed, and the precursor material layer in the substrate is etched to form a multilayer active layer precursor located on the substrate.

15. The method for preparing a semiconductor structure according to claim 14, characterized in that, The step of arranging the multiple active layer precursors along the first direction to form a bit line component electrically connected to the active layer precursors includes: A bit line is formed extending along the first direction, the bit line comprising a plurality of bit line components electrically connected to each of the active layer precursors.

16. The method for preparing a semiconductor structure according to claim 14, characterized in that, Each layer contains multiple active layer precursors, and the multiple active layer precursors located in the same layer are arranged and distributed along the second direction. The step of forming gate word line components on the top surface and / or bottom surface of the active layer precursors includes: A word line extending along the second direction is formed, the word line including a plurality of gate word line components located on the top and / or bottom surfaces of each of the active layer precursors.

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