A NVM storage unit

Abstract

The present invention is applicable to the field of storage technology, and provides an NVM storage unit, which includes a substrate, four sub-unit modules arranged on the substrate, and a PN junction diode, each of the sub-unit modules includes an NMOS tube and an N-well capacitor whose first end is connected to the gate of the NMOS tube, and the N-well capacitors and the PN junction diodes in the four sub-unit modules share an N-well. The PN junction diode of the NVM storage unit in the present invention can provide holes under the reverse bias of the N-well, so as to prevent the N-well capacitor from entering the deep depletion region during programming, so as to improve the efficiency of programming and reduce the programming voltage, thereby reducing the size requirements of the NVM storage unit for the programming high voltage, thereby reducing the area of ​​the NVM storage unit, so that it is suitable for most chips.

Description

Technical Field

[0001] The present invention belongs to the field of storage technology, and in particular relates to a NVM storage unit. Background Art

[0002] As a non-volatile memory, NVM is generally divided into two types: stack type and planar type. Representative devices of the stack type are EEPROM (electrically erasable programmable read-only memory) and FLASH (flash memory). Both devices require special processes. The main feature is that the unit area is extremely small. They are generally used to store data. Representative devices of the planar type are MTP (multi-time programmable memory) and OTP (one-time programmable memory). Both devices only need to use standard CMOS processes. The main features are low cost and strong compatibility. They are generally used to store a small amount of configuration parameters and programs.

[0003] As modern devices require more and more parameters to be configured and the startup programs are getting larger and larger, general MTP storage units no longer have cost advantages. Especially when used in some low-cost embedded MCU chips, the area of ​​the MTP memory formed by the MTP storage unit has occupied more than 1 / 3 of the chip, which is not suitable for most chips. Summary of the invention

[0004] An embodiment of the present invention provides a NVM storage unit, aiming to solve the problem that the existing planar NVM storage unit has a large area and cannot be applied to most chips.

[0005] An embodiment of the present invention provides an NVM storage unit, which includes a substrate, four sub-unit modules arranged on the substrate, and a PN junction diode, each of the sub-unit modules includes an NMOS tube and an N-well capacitor whose first end is connected to the gate of the NMOS tube, and the N-well capacitors and the PN junction diodes in the four sub-unit modules share an N-well; the drains of the NMOS tubes in the four sub-unit modules serve as four drain ends of the NVM storage unit respectively, the sources of the two NMOS tubes in the same column of the four sub-unit modules are connected together to serve as a source end of the NVM storage unit, and the second ends of the two N-well capacitors in the same row of the four sub-unit modules are connected to each other; the anode of the PN junction diode is connected to the second ends of the two N-well capacitors in the same row of the first group, and the cathode of the PN junction diode is connected to the second ends of the two N-well capacitors in the same row of the second group to serve as the control end of the NVM storage unit.

[0006] Furthermore, an N-well is arranged in the middle region of the substrate, a first active region is arranged in the N-well, a first N+ doped region is arranged at a position away from the middle region of the first active region, and the first N+ doped region constitutes four N-well capacitors.

[0007] Furthermore, a P+ doped region is arranged in the middle region of the first N+ doped region, and the P+ doped region and the part of the first N+ doped region around it constitute the PN junction diode; the parts of the first N+ doped regions on both sides of the P+ doped region are respectively connected together through an electrical connection structure to realize the connection of the PN junction diode with the four N-well capacitors respectively, and the middle region of the P+ doped region is provided with an electrical connection structure as the control end of the NVM storage unit.

[0008] Furthermore, a second active region and a third active region separated from the first active region are respectively arranged on both sides of the substrate, a second N+ type doped region is arranged in the second active region, and a third N+ type doped region is arranged in the third active region; the second N+ type doped region constitutes the two NMOS tubes in the same column of the first group, and the third N+ type doped region constitutes the two NMOS tubes in the same column of the second group.

[0009] Furthermore, the two end regions of the second N+ type doped region respectively serve as the drains of the two NMOS tubes in the same column of the first group, and are respectively provided with an electrical connection structure as two of the drain ends of the NVM storage unit, and the middle region of the second N+ type doped region serves as the source of the two NMOS tubes in the same column of the first group, and are connected together by setting an electrical connection structure to serve as one of the source ends of the NVM storage unit; the two end regions of the third N+ type doped region respectively serve as the drains of the two NMOS tubes in the same column of the second group, and are respectively provided with an electrical connection structure as the other two drain ends of the NVM storage unit, and the middle region of the third N+ type doped region serves as the source of the two NMOS tubes in the same column of the second group, and are connected together by setting an electrical connection structure to serve as the other source end of the NVM storage unit.

[0010] Furthermore, the end regions of the second N+ doped region and the third N+ doped region are respectively connected to the first N+ doped region through a polycrystalline gate region to achieve connection between the NMOS tubes in the four sub-unit modules and the N-well capacitors.

[0011] Furthermore, the electrical connection structure includes a contact hole and a metal line disposed on the contact hole.

[0012] Furthermore, the second active region and the third active region are symmetrically arranged on both sides of the first active region; the second N+ type doped region and the third N+ type doped region are symmetrically arranged on both sides of the first N+ type doped region.

[0013] The beneficial effect achieved by the present invention is as follows: by setting four sub-unit modules and a PN junction diode, and making the four N-well capacitors and the PN junction diode in the four sub-unit modules share one N-well, the PN junction diode can provide holes under the reverse bias of the N-well, so as to prevent the N-well capacitor from entering the deep depletion region during programming, so as to improve the programming efficiency and reduce the programming voltage, thereby reducing the size requirements of the NVM storage unit for the programming high voltage, thereby reducing the area of ​​the NVM storage unit and making it suitable for most chips. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 is a schematic diagram of a planar structure of an NVM storage unit provided by an embodiment of the present invention;

[0015] Figure 2 is an electrical schematic diagram of an NVM storage unit provided by an embodiment of the present invention;

[0016] Figure 3 It is a schematic diagram of ports of each unit during read and write operations of a storage array formed by a plurality of NVM storage units provided by an embodiment of the present invention;

[0017] Among them, 100, N well; 101, first active area; 102, first N+ type doping area; 103, P+ type doping area; 104, contact hole; 105, metal line; 106, second active area; 107, second N+ type doping area; 108, third active area; 109, third N+ type doping area; 110, polycrystalline gate; 200, sub-unit module; 201, NMOS tube; 202, N well capacitor; 203, PN junction diode. DETAILED DESCRIPTION

[0018] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0019] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0020] It should be noted that when an element is considered to be "connected" to another element, it can be directly connected to the other element, or connected to the other element through an intermediate element. The "connection" in the following embodiments should be understood as "electrical connection", "communication connection", etc. if the connected circuits, modules, units, etc. have electrical signals or data transmission between each other.

[0021] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, the terms used in this specification include any and all combinations of the relevant listed items.

[0022] An embodiment of the present invention provides a NVM storage unit, combined with Figure 1 and Figure 2 As shown, it includes a substrate (not shown in the figure), four sub-unit modules 200 arranged on the substrate, and a PN junction diode 203. Each sub-unit module 200 includes an NMOS tube 201 (N-type metal-oxide-semiconductor) and an N-well capacitor 202 whose first end is connected to the gate of the NMOS tube 201. The N-well capacitors 202 and the PN junction diode 203 in the four sub-unit modules 200 share an N-well 100; the drains of the NMOS tubes 201 in the four sub-unit modules 200 are respectively used as four drain ends of the NVM storage unit, the sources of the two NMOS tubes 201 in the same column of the four sub-unit modules 200 are connected together to serve as a source end of the NVM storage unit, and the second ends of the two N-well capacitors 202 in the same row of the four sub-unit modules 200 are connected to each other; the positive electrode of the PN junction diode 203 is connected to the second ends of the two N-well capacitors 202 in the same row of the first group, and the negative electrode of the PN junction diode 203 is connected to the second ends of the two N-well capacitors 202 in the same row of the second group to serve as the control end of the NVM storage unit.

[0023] In this embodiment, an N-well 100 is disposed in the middle region of the substrate, a first active region 101 is disposed in the N-well 100 , a first N+ doped region 102 is disposed away from the middle region of the first active region 101 , and the first N+ doped region 102 constitutes four N-well capacitors 202 .

[0024] In this embodiment, a P+ doping region 103 is provided in the middle area of ​​the first N+ doping region 102, and the P+ doping region 103 and the surrounding part of the first N+ doping region 102 constitute a PN junction diode 203; parts of the first N+ doping region 102 on both sides of the P+ doping region 103 are respectively connected together through an electrical connection structure to realize the connection of the PN junction diode 203 with the four N-well capacitors 202 respectively, and an electrical connection structure is provided in the middle area of ​​the P+ doping region 103 to serve as the control end of the NVM storage unit.

[0025] The N+ doping in the first N+ doping region 102 and the P+ doping in the P+ doping region 103 are simultaneously implanted into the first active region 101 to form a PN junction diode 203 .

[0026] In this embodiment, a second active region 106 and a third active region 108 separated from the first active region 101 are respectively arranged on both sides of the substrate, a second N+ type doping region 107 is arranged in the second active region 106, and a third N+ type doping region 109 is arranged in the third active region 108; the second N+ type doping region 107 constitutes a first group of two NMOS tubes 201 in the same column, and the third N+ type doping region 109 constitutes a second group of two NMOS tubes 201 in the same column.

[0027] The N+ type doping in the second N+ type doping region 107 and the third N+ type doping region 109 are both implanted by implantation.

[0028] In this embodiment, the two end regions of the second N+ doped region 107 serve as the drains of the two NMOS tubes 201 in the same column of the first group, and are respectively provided with an electrical connection structure to serve as two drain ends of the NVM storage unit. The middle region of the second N+ doped region 107 serves as the source of the two NMOS tubes 201 in the same column of the first group, and are connected together by providing an electrical connection structure to serve as one source end of the NVM storage unit; the two end regions of the third N+ doped region 109 serve as the drains of the two NMOS tubes 201 in the same column of the second group, and are respectively provided with an electrical connection structure to serve as the other two drain ends of the NVM storage unit. The middle region of the third N+ doped region 109 serves as the source of the two NMOS tubes 201 in the same column of the second group, and are connected together by providing an electrical connection structure to serve as the other source end of the NVM storage unit.

[0029] In this embodiment, the end regions of the second N+ doping region 107 and the third N+ doping region 109 are respectively connected to the first N+ doping region 102 through a polycrystalline gate 110 region to achieve the connection between the NMOS tube 201 and the N well capacitor 202 in the four sub-unit modules 200.

[0030] The polycrystalline gate 110 region is used to store charges.

[0031] In this embodiment, the electrical connection structure includes a contact hole 104 and a metal line 105 disposed on the contact hole 104 .

[0032] In this embodiment, the second active region 106 and the third active region 108 are symmetrically disposed on both sides of the first active region 101 ; the second N+ doping region 107 and the third N+ doping region 109 are symmetrically disposed on both sides of the first N+ doping region 102 .

[0033] In this embodiment, the NVM storage cell uses hot electron injection for cell programming and uses hot hole injection caused by band-to-band tunneling for erasure. This is because the hot electron injection requires a low programming high voltage and a smaller well area can be used. The hot holes caused by the band-to-band tunneling effect can use a simpler high-voltage switching circuit to avoid crosstalk between cells, thereby further reducing the area of ​​the NVM memory.

[0034] The beneficial effects achieved by this embodiment are as follows: by providing four sub-unit modules 200 and a PN junction diode 203, and making the four N-well capacitors 202 and the PN junction diode 203 in the four sub-unit modules 200 share one N-well 100, the PN junction diode 203 can provide holes under the reverse bias of the N-well 100, thereby preventing the N-well capacitor 202 from entering the deep depletion region during programming, so as to improve the programming efficiency and reduce the programming voltage, thereby reducing the size requirements of the NVM storage unit for the programming high voltage, thereby reducing the area of ​​the NVM storage unit and making it suitable for most chips.

[0035] In order to better understand the NVM storage unit in the present invention, a storage array (NVM memory) formed by the NVM storage unit is taken as an example for explanation below.

[0036] like Figure 3 The diagram shows a port diagram of each position unit (NVM storage unit) during read and write operations of a storage array formed by multiple NVM storage units, wherein S0 is a read and write operation unit, X1, X2, and X3 are non-operation units, GLS is a control terminal set of each unit in the first row, SLS is a source terminal set of each unit in the first row, GLX is a control terminal set of each unit in the second row, SLX is a source terminal set of each unit in the second row, GLn is a control terminal set of each unit in the last row, SLn is a source terminal set of each unit in the third row, BLS is a drain terminal set of each unit in the first column; BLX is a drain terminal set of each unit in the second column; BLn is a drain terminal set of each unit in the last column; a source terminal set of each unit in at least one row is also provided between GLS and GLn; a ​​source terminal set of each unit in at least one row is also provided between SLS and SLn; a ​​drain terminal set of each unit in at least one column is also provided between BLS and BLn, and no limitation is made here.

[0037] The voltage status table of different ports in each location unit in the above storage array is shown in Table 1:

[0038] Table 1: Voltage status table

[0039]

[0040] Among them, VREAD is the read voltage, which uses 2V in this embodiment, VDD is the power supply voltage, which uses 3.3V in this embodiment, HV is the write high voltage, which uses 8V in this embodiment, and F is floating.

[0041] During read and write operations, for the rows and columns selected for reading, GLS is connected to VREAD, BLS is connected to a fixed voltage of 1V, and SLS is connected to 0 voltage. For cells storing different data, the stored data is determined by comparing the read current size.

[0042] During the read operation, for columns that are not selected for reading, BLX is floating, for rows that are not selected for reading, GLX is connected to 0 voltage and SLX is connected to VDD to prevent leakage current from cells in the erased state to affect the cells being read.

[0043] During programming operation, for the rows and columns that need to be programmed, GLS and BLS are connected to HV, and SLS is connected to VDD to avoid excessive programming current. Through the hot electron injection effect, electrons tunnel to the floating gate to reduce the threshold voltage of the cell.

[0044] During programming operation, for columns that do not need programming, BLX is left floating to avoid generating hot electrons. For rows that do not need programming, GLX and SLX are connected to VDD to suppress hot electrons and hot holes from tunneling to the floating gate.

[0045] During the erase operation, for the rows and columns that need to be erased, BLS is connected to HV, GLS and SLS are connected to 0 voltage, BLS and substrate PN junction diode 203 generate a large number of electron-hole pairs due to the high voltage, and GLS is connected to 0 potential to attract hot holes into the floating gate, increasing the threshold voltage of the storage cell.

[0046] During the erase operation, for the columns that do not need to be erased, BLX is floated to avoid the generation of electron-hole pairs. For the rows that are not selected for erasure, GLX and SLX are connected to VDD to suppress hot holes and hot electrons from entering the floating gate.

[0047] The above writing method can effectively ensure the anti-interference performance of the unit.

[0048] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0049] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the attached claims.

Claims

1. A NVM storage cell, It is characterized in that The invention comprises a substrate, four sub-unit modules arranged on the substrate and a PN junction diode, each of the sub-unit modules comprises an NMOS tube and an N-well capacitor whose first end is connected to the gate of the NMOS tube, and the N-well capacitors and the PN junction diodes in the four sub-unit modules share an N-well; the drains of the NMOS tubes in the four sub-unit modules are respectively used as four drain ends of the NVM storage unit, the sources of the two NMOS tubes in the same column of the four sub-unit modules are connected together to serve as a source end of the NVM storage unit, and the second ends of the two N-well capacitors in the same row of the four sub-unit modules are connected to each other; the positive electrode of the PN junction diode is connected to the second ends of the two N-well capacitors in the same row of the first group, and the negative electrode of the PN junction diode is connected to the second ends of the two N-well capacitors in the same row of the second group to serve as the control end of the NVM storage unit.

2. The NVM storage unit according to claim 1, It is characterized in that An N-well is arranged in the middle area of ​​the substrate, a first active area is arranged in the N-well, a first N+ doped area is arranged at a position of the first active area away from the middle area, and the first N+ doped area constitutes four N-well capacitors.

3. The NVM storage unit as claimed in claim 2, It is characterized in that A P+ doping region is arranged in the middle area of ​​the first N+ doping region, and the P+ doping region and part of the first N+ doping region around it constitute the PN junction diode; parts of the first N+ doping regions on both sides of the P+ doping region are respectively connected together through an electrical connection structure to realize the connection of the PN junction diode with the four N-well capacitors respectively, and an electrical connection structure is arranged in the middle area of ​​the P+ doping region to serve as the control end of the NVM storage unit.

4. The NVM storage unit as claimed in claim 3, It is characterized in that A second active region and a third active region spaced apart from the first active region are respectively arranged on both sides of the substrate, a second N+ type doped region is arranged in the second active region, and a third N+ type doped region is arranged in the third active region; the second N+ type doped region constitutes a first group of two NMOS tubes in the same column, and the third N+ type doped region constitutes a second group of two NMOS tubes in the same column.

5. The NVM storage unit as claimed in claim 4, It is characterized in that The two end regions of the second N+ doped region are respectively used as drains of the two NMOS transistors in the same column of the first group, and are respectively provided with one of the electrical connection structures to serve as two drain ends of the NVM storage unit, and the middle region of the second N+ doped region is used as the source of the two NMOS transistors in the same column of the first group, and are connected together by providing one of the electrical connection structures to serve as one of the source ends of the NVM storage unit; The two end regions of the third N+ type doped region respectively serve as the drains of the two NMOS tubes in the same column of the second group, and are respectively provided with an electrical connection structure to serve as the other two drain ends of the NVM storage unit. The middle region of the third N+ type doped region serves as the source of the two NMOS tubes in the same column of the second group, and are connected together by providing an electrical connection structure to serve as the other source end of the NVM storage unit.

6. The NVM storage unit as claimed in claim 5, It is characterized in that The end regions of the second N+ doping region and the third N+ doping region are respectively connected to the first N+ doping region through a polycrystalline gate region to achieve connection between the NMOS tubes in the four sub-unit modules and the N-well capacitors.

7. The NVM storage unit as claimed in claim 6, It is characterized in that The electrical connection structure includes a contact hole and a metal line arranged on the contact hole.

8. The NVM storage unit as claimed in claim 7, It is characterized in that The second active region and the third active region are symmetrically arranged on both sides of the first active region; the second N+ type doping region and the third N+ type doping region are symmetrically arranged on both sides of the first N+ type doping region.

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