Array substrate, display panel and display device

Abstract

This invention discloses an array substrate, a display panel, and a display device. The array substrate includes a substrate, a semiconductor layer, and multiple metal layers. The semiconductor layer and the multiple metal layers are stacked on one side of the substrate, and multiple pixel circuits are formed in the semiconductor layer and the multiple metal layers. Each pixel circuit includes a driving transistor and a dual-gate transistor connected to the gate of the driving transistor. The semiconductor layer includes a first semiconductor portion connected to the dual-gate node of the dual-gate transistor. The multiple metal layers include a first metal layer, which includes a first metal portion. The vertical projections of the first metal portion and the first semiconductor portion on the substrate overlap. The first metal portion is used to receive a set level signal, and the first metal portion and the first semiconductor portion form a capacitor. The technical solution of this invention helps to alleviate the leakage problem of the pixel circuit, thereby improving the display effect.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to an array substrate, a display panel, and a display device. Background Technology

[0002] With the continuous development of display technology, people have increasingly higher requirements for the performance of display panels. A display panel includes light-emitting devices and pixel circuits. The pixel circuits drive the light-emitting devices to emit light, enabling the display panel to perform its display function. Currently, pixel circuits in existing display panels commonly suffer from leakage current, which affects the brightness of the light-emitting devices and thus the display effect of the panel. Summary of the Invention

[0003] This invention provides an array substrate, a display panel, and a display device to alleviate leakage current problems in pixel circuits, thereby improving display performance.

[0004] In a first aspect, embodiments of the present invention provide an array substrate, comprising:

[0005] Base;

[0006] A semiconductor layer and a multilayer metal layer are stacked on one side of the substrate. The semiconductor layer and the multilayer metal layer form a plurality of pixel circuits. The pixel circuits include driving transistors and dual-gate transistors connected to the gates of the driving transistors.

[0007] The semiconductor layer includes a first semiconductor portion connected to the dual-gate node of the dual-gate transistor. The multilayer metal layer includes a first metal layer, which includes a first metal portion. The vertical projections of the first metal portion and the first semiconductor portion on the substrate overlap. The first metal portion is used to receive a set level signal, and the first metal portion and the first semiconductor portion form a capacitor.

[0008] Optionally, the first metal layer further includes scan lines, and the semiconductor layer further includes a second semiconductor portion and a third semiconductor portion of the dual-gate transistor;

[0009] The vertical projection of the scan line on the substrate overlaps with the vertical projections of the second semiconductor portion and the third semiconductor portion on the substrate, respectively, and the first semiconductor portion, the second semiconductor portion and the third semiconductor portion are connected to the dual-gate node of the dual-gate transistor;

[0010] Preferably, the first metal layer is the layer among the multilayer metal layers that is closest to the semiconductor layer.

[0011] Optionally, the scan line includes a main body and a branch, the branch being connected to the main body, the branch and the second semiconductor portion having overlapping vertical projections on the substrate, and the main body and the third semiconductor portion having overlapping vertical projections on the substrate;

[0012] The first end of the first semiconductor portion, the first end of the second semiconductor portion, and the first end of the third semiconductor portion are connected to the dual-gate node of the dual-gate transistor, and the second end of the second semiconductor portion or the second end of the third semiconductor portion is connected to the gate of the driving transistor.

[0013] Preferably, the second semiconductor portion and the main body portion extend along a first direction, the branch portion and the third semiconductor portion extend along a second direction, the first direction and the second direction intersect, and the first semiconductor portion is located on the side of the second semiconductor portion away from the main body portion.

[0014] Optionally, the first semiconductor portion includes a first sub-semiconductor portion and a second sub-semiconductor portion. A first end of the first sub-semiconductor portion is connected to the dual-gate node of the dual-gate transistor, and a second end of the first sub-semiconductor portion is connected to the first end of the second sub-semiconductor portion. The extending directions of the first sub-semiconductor portion and the second sub-semiconductor portion intersect, and the vertical projection of the first metal portion on the substrate overlaps with the vertical projections of the first sub-semiconductor portion and the second sub-semiconductor portion on the substrate, respectively.

[0015] Preferably, the first sub-semiconductor portion extends along the second direction, and the second sub-semiconductor portion extends along the first direction.

[0016] Optionally, the third semiconductor section includes a third sub-semiconductor section and a fourth sub-semiconductor section;

[0017] The first end of the first semiconductor portion, the first end of the second semiconductor portion, and the first end of the third sub-semiconductor portion are connected to the dual-gate node of the dual-gate transistor. The second end of the third sub-semiconductor portion is connected to the first end of the fourth sub-semiconductor portion. The second end of the second semiconductor portion or the second end of the fourth sub-semiconductor portion is connected to the gate of the driving transistor.

[0018] The vertical projection of the scan line on the substrate overlaps with the vertical projections of the second semiconductor portion and the fourth sub-semiconductor portion on the substrate, respectively.

[0019] Optionally, the scan line and the third sub-semiconductor portion extend along a first direction, and the first semiconductor portion, the second semiconductor portion and the fourth sub-semiconductor portion extend along a second direction, wherein the first direction and the second direction intersect.

[0020] The first semiconductor portion is located on the side of the third sub-semiconductor portion away from the scan line. Optionally, the multilayer metal layer further includes an initialization signal line and a power supply line; the scan line in the array substrate and the vertical projection of the semiconductor layer of the dual-gate transistor on the substrate overlap; the initialization signal line is used to provide an initialization voltage to the pixel circuit to initialize the pixel circuit; the power supply line is used to provide a power supply voltage to the pixel circuit;

[0021] The first metal part is connected to the scan line, and the signal on the scan line serves as the set level signal; or, the first metal part is connected to the initialization signal line, and the signal on the initialization signal line serves as the set level signal; or, the first metal part is connected to the power line, and the signal on the power line serves as the set level signal.

[0022] Optionally, the pixel circuit includes a first transistor connected between the first terminal and the gate of the driving transistor, the first transistor being used to compensate for the threshold voltage of the driving transistor, and the first transistor being the dual-gate transistor; and / or,

[0023] The pixel circuit includes a second transistor, the first terminal of which is connected to an initialization signal line, and the second terminal of which is connected to the gate of the driving transistor. The second transistor is used to write the voltage on the initialization signal line into the gate of the driving transistor. The second transistor is the dual-gate transistor.

[0024] In a second aspect, embodiments of the present invention provide a display panel including the array substrate described in the first aspect.

[0025] Thirdly, embodiments of the present invention provide a display device including the display panel described in the second aspect.

[0026] The array substrate, display panel, and display device provided in this invention embodiment include a pixel circuit comprising a driving transistor and a dual-gate transistor connected to the gate of the driving transistor. A first semiconductor portion in the semiconductor layer is connected to the dual-gate node of the dual-gate transistor. The vertical projections of the first semiconductor portion and the first metal portion in the first metal layer onto the substrate overlap to form a capacitor. When a set level signal is applied to the first metal portion, the capacitor formed by the overlap of the first metal portion and the first semiconductor portion stabilizes the potential of the dual-gate node, thereby making the potential of the dual-gate node of the dual-gate transistor less susceptible to jumps caused by coupling with other signals. This helps to keep the potentials of the dual-gate node of the dual-gate transistor and the gate of the driving transistor close, thereby alleviating the leakage problem between the dual-gate node of the dual-gate transistor and the gate of the driving transistor, and improving the display effect of the display panel.

[0027] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0028] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0029] Figure 1 This is a top view of an array substrate provided in an embodiment of the present invention;

[0030] Figure 2 yes Figure 1 A magnified view of a partial structure of the pixel circuit in the image;

[0031] Figure 3 yes Figure 2 The cross-sectional view obtained by cutting the pixel circuit along the cutting line BB';

[0032] Figure 4 This is a schematic diagram of the circuit structure of a pixel circuit provided in an embodiment of the present invention;

[0033] Figure 5 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention;

[0034] Figure 6 yes Figure 1 An enlarged view of another local structure of the pixel circuit in the image;

[0035] Figure 7 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention;

[0036] Figure 8 This is a schematic diagram of the driving timing of a pixel circuit provided in an embodiment of the present invention;

[0037] Figure 9 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention. Detailed Implementation

[0038] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0039] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0040] As described in the background section, pixel circuits in existing display panels commonly suffer from leakage current, which affects the brightness of the light-emitting device and thus the display effect. The inventors have discovered that the specific reasons for this problem are as follows: Pixel circuits typically include a driving transistor for driving the light-emitting device, and a dual-gate transistor connected to the gate of the driving transistor. The dual-gate transistor consists of two sub-transistors, and the node between these two sub-transistors is called the dual-gate node. Because the potential of the dual-gate node is easily affected by scanning signals input to the pixel circuit, for example, when the potential of certain scanning signals changes, the potential of the dual-gate node is coupled and changes, creating a potential difference between the dual-gate node and the gate of the driving transistor. This results in leakage current between the dual-gate node of the dual-gate transistor and the gate of the driving transistor, causing a change in the gate potential of the driving transistor. This alters the magnitude of the driving current flowing through the light-emitting device, affecting its brightness and consequently the display effect of the display panel.

[0041] To address the above-mentioned problems, embodiments of the present invention provide an array substrate. Figure 1 This is a top view of an array substrate provided in an embodiment of the present invention; Figure 2 yes Figure 1 A magnified view of a partial structure of the pixel circuit in the image; Figure 3 yes Figure 2 The cross-sectional view obtained by cutting the pixel circuit along the cutting line BB'; Figure 4This is a schematic diagram of the circuit structure of a pixel circuit provided in an embodiment of the present invention; Figure 5 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention. (In conjunction with...) Figures 1 to 5 The array substrate provided in this embodiment of the invention includes a substrate 10, a semiconductor layer 20, and multiple metal layers. The semiconductor layer 20 and the multiple metal layers are stacked on one side of the substrate 10. A plurality of pixel circuits 100 are formed in the semiconductor layer 20 and the multiple metal layers. Each pixel circuit 100 includes a driving transistor DT and a dual-gate transistor connected to the gate of the driving transistor DT.

[0042] The semiconductor layer 20 includes a first semiconductor portion 210, which is connected to the dual gate node of the dual gate transistor. The multilayer metal layer includes a first metal layer 30, which includes a first metal portion 310. The vertical projections of the first metal portion 310 and the first semiconductor portion 210 on the substrate 10 overlap. The first metal portion 310 is used to receive a set level signal Vx, and the first metal portion 310 and the first semiconductor portion 210 form a capacitor.

[0043] Specifically, the substrate 10 can provide buffering, protection, or support for the array substrate. The substrate 10 can be a flexible substrate, such as a flexible substrate made of materials like polyimide (PI), polyethylene naphthalate (PEN), or polyethylene terephthalate (PET), or it can be a rigid substrate made of materials like glass. A semiconductor layer 20 and multiple metal layers are sequentially disposed on one side of the substrate 10. The multiple metal layers are isolated from each other by insulating layers. The semiconductor layer 20 can be an active layer, which can be formed of materials such as polycrystalline silicon or metal oxides.

[0044] The array substrate has a display area AA and a non-display area NAA. Multiple pixel circuits 100 located in the display area AA are formed in the semiconductor layer 20 and multiple metal layers. The pixel circuits 100 drive corresponding light-emitting devices D1 in the display panel to emit light. The light-emitting device D1 can be an organic light-emitting diode (OLED) or a micro-LED, etc. Each pixel circuit 100 is composed of at least thin-film transistors, including a driving transistor DT and a dual-gate transistor connected to the gate of the driving transistor DT. The driving transistor DT can generate a driving current according to the data voltage, thereby driving the light-emitting device D1 to emit light at a corresponding brightness. The dual-gate transistor connected to the gate of the driving transistor DT can be a transistor used for threshold voltage compensation of the driving transistor DT, or it can be a transistor used for initializing the gate voltage of the driving transistor DT.

[0045] In this embodiment, a dual-gate transistor connected to the gate of the driving transistor DT is used as an example for threshold voltage compensation of the driving transistor DT. Exemplarily, this dual-gate transistor can be a first transistor T1, connected between the first terminal and the gate of the driving transistor DT. The first transistor T1 includes a first dual-gate transistor T1-1 and a second dual-gate transistor T1-2. The first terminal of the second dual-gate transistor T1-2 is connected to the first terminal of the driving transistor DT, the second terminal of the second dual-gate transistor T1-2 is connected to the first terminal of the first dual-gate transistor T1-1, and the second terminal of the first dual-gate transistor T1-1 is connected to the gate of the driving transistor DT. The dual-gate node of the dual-gate transistor can be the dual-gate node N1 of the first transistor T1, that is, the intermediate node between the second terminal of the second dual-gate transistor T1-2 and the first terminal of the first dual-gate transistor T1-1. For example, when the semiconductor layer 20 of the first transistor T1 includes a second semiconductor portion 220 and a third semiconductor portion 230, the semiconductor layer 20 of the first dual-gate transistor T1-1 includes the second semiconductor portion 220, and the semiconductor layer 20 of the second dual-gate transistor T1-2 includes the third semiconductor portion 230. The second semiconductor portion 220 and the third semiconductor portion 230 are connected at the intersection. The dual-gate node N1 of the first transistor T1 can be located in the region where the second semiconductor portion 220 and the third semiconductor portion 230 are connected at the intersection. The first semiconductor portion 210 is connected to the dual-gate node N1 of the first transistor T1.

[0046] The first metal layer 30 can be any metal layer in a multilayer metal layer. The vertical projections of the first metal portion 310 and the first semiconductor portion 210 onto the substrate 10 overlap. Therefore, in the direction perpendicular to the substrate 10, the first metal portion 310 and the first semiconductor portion 210 overlap and form a capacitor structure. The capacitor structure formed by the overlapping of the first metal portion 310 and the first semiconductor portion 210 can also be considered as a thin-film transistor T0 (see [link to relevant documentation]). Figure 5 The first semiconductor part 210 is connected to one end of the dual gate node N1 of the first transistor T1, which can be used as the source or drain of the thin film transistor T0. The first metal part 310 can be used as the gate of the thin film transistor T0, so that the gate of the thin film transistor T0 is connected to the set level signal Vx.

[0047] The thin-film transistor T0 has an internal capacitor. The capacitor structure formed by the overlapping of the first metal portion 310 and the first semiconductor portion 210 can be regarded as the internal capacitor of the thin-film transistor T0, for example, the first capacitor C1 (see...). Figure 4The first metal portion 310 and the first semiconductor portion 210 serve as the two plates of the first capacitor C1, with one plate of the first capacitor C1 connected to the dual-gate node N1 of the first transistor T1, and the other plate connected to a setting level signal Vx. The setting level signal Vx can be a signal used to control the conduction of the thin-film transistor T0. When the setting level signal Vx is not connected to the gate of the first metal portion 310 (i.e., the thin-film transistor T0), the conductivity of the first semiconductor portion 210 is weak, the capacitance of the first capacitor C1 is small, and the storage capacity of the first capacitor C1 is limited. By connecting the first metal part 310 to the set level signal Vx, the conductivity of the first semiconductor part 210 can be enhanced, thereby increasing the capacitance value of the first capacitor C1. The first capacitor C1 can then store voltage, stabilizing the potential of the dual-gate node N1 of the first transistor T1. This makes the potential of the dual-gate node N1 of the first transistor T1 less susceptible to jumps caused by coupling with other signals, helping to keep the gate potentials of the dual-gate node N1 of the first transistor T1 and the gate of the driving transistor DT close. This alleviates the leakage problem between the dual-gate node N1 of the first transistor T1 and the gate of the driving transistor DT, thereby improving the display effect of the display panel and reducing the flickering phenomenon caused by leakage.

[0048] In summary, the technical solution of this invention, by setting the pixel circuit to include a driving transistor and a dual-gate transistor connected to the gate of the driving transistor, a first semiconductor portion in the semiconductor layer connected to the dual-gate node of the dual-gate transistor, and the vertical projections of the first semiconductor portion and the first metal portion in the first metal layer onto the substrate overlapping to form a capacitor, when a set level signal is applied to the first metal portion,

[0049] The capacitor formed by the overlapping of the first metal part and the first semiconductor part plays a role in stabilizing the potential of the dual-gate node, so that the potential of the dual-gate node of the dual-gate transistor is not easily affected by the coupling of other signals and will not jump. This helps to keep the potential of the dual-gate node of the dual-gate transistor and the gate potential of the driving transistor close, thereby alleviating the leakage problem between the dual-gate node of the dual-gate transistor and the gate of the driving transistor and improving the display effect of the display panel.

[0050] Combination Figures 1 to 5Based on the above embodiments, the first metal layer 30 can be configured as the layer closest to the semiconductor layer 20 among the multilayer metal layers. When the first metal layer 30 is the layer closest to the semiconductor layer 20 among the multilayer metal layers, the first metal layer 30 also includes the gate of the thin-film transistor in the pixel circuit 100. Optionally, the pixel circuit 100 also includes a storage capacitor Cst, and the first metal layer 30 may further include the lower electrode of the storage capacitor Cst. For example, the semiconductor layer 20 of the driving transistor DT includes a fourth semiconductor portion 240, and the first metal layer 30 also includes a second metal portion 320. The vertical projections of the second metal portion 320 and the fourth semiconductor portion 240 on the substrate overlap, and the second metal portion 320 can serve as the gate of the driving transistor DT and the lower electrode of the storage capacitor Cst. In the fabrication process of the array substrate, after forming the semiconductor layer 20, an insulating layer is formed on the side of the semiconductor layer 20 away from the substrate 10. Then, a first metal layer 30 is formed on the side of the insulating layer away from the semiconductor layer 20, such that the vertical projections of the first metal portion 310 and the first semiconductor portion 210 on the substrate 10 overlap, and the vertical projections of the second metal portion 320 and the fourth semiconductor portion 240 on the substrate overlap. After forming the first metal layer 30, the semiconductor layer 20 is made conductive through a doping process, so that the portion of the semiconductor layer 20 that does not overlap with the first metal layer 30 is conductive, and the portion of the semiconductor layer 20 that overlaps with the first metal layer 30 is semiconductor. This allows the semiconductor portion in the semiconductor layer 20 to overlap with the metal portion in the first metal layer 30 to form a thin-film transistor and the capacitor structure in the embodiments of the present invention. For example, the second metal portion 320 and the fourth semiconductor portion 240 overlap to form a driving transistor DT, and the first metal portion 310 and the first semiconductor portion 210 overlap to form a first capacitor C1.

[0051] The technical solution of this embodiment, by setting the first metal layer 30 to be the layer closest to the semiconductor layer 20 in the multilayer metal layers, can, on the one hand, allow the first metal part 310 and the first semiconductor part 210 to overlap and form the first capacitor C1, thereby stabilizing the dual-gate node potential of the dual-gate transistor through the first capacitor C1. On the other hand, compared with the scheme where the first metal layer 30 is any other metal layer in the multilayer metal layers, setting the first metal layer 30 to be the layer closest to the semiconductor layer 20 in the multilayer metal layers can reduce the distance between the first metal part 310 and the first semiconductor part 210, that is, reduce the distance between the two plates of the first capacitor C1 formed by the overlap of the first metal part 310 and the first semiconductor part 210. With the facing area of ​​the first metal part 310 and the first semiconductor part 210 remaining unchanged, setting the first metal layer 30 to be the layer closest to the semiconductor layer 20 in the multilayer metal layers can make the capacitance value of the first capacitor C1 larger. For example, the multilayer metal layer also includes a second metal layer 40, in which the upper plate of the storage capacitor Cst is disposed. With the facing area of ​​the first metal part 310 and the first semiconductor part 210 remaining unchanged, compared with the scheme where the first metal part 310 is located in the second metal layer 40, setting the first metal part 310 in the layer closest to the semiconductor layer 20 can increase the capacitance value of the first capacitor C1 by about 80%.

[0052] Combination Figures 1 to 5 Optionally, the first metal layer 30 further includes a scan line 330, and the semiconductor layer 20 further includes a second semiconductor portion 220 and a third semiconductor portion 230 of a dual-gate transistor; the second semiconductor portion 220 includes a first region, the third semiconductor portion 230 includes a second region, the vertical projection of the scan line 330 on the substrate 10 overlaps with the vertical projection of the first region of the second semiconductor portion 220 on the substrate 10, and overlaps with the vertical projection of the second region of the third semiconductor portion 230 on the substrate 10, and the first semiconductor portion 210, the second semiconductor portion 220 and the third semiconductor portion 230 are connected to the dual-gate node of the dual-gate transistor.

[0053] Specifically, the scan line 330 is used to transmit a scan signal, which can control the thin-film transistors in the pixel circuit to be turned on or off. The first region is a portion of the second semiconductor section 220, and the second region is a portion of the third semiconductor section 230. The scan line 330 overlaps with the first region of the second semiconductor section 220 and the second region of the third semiconductor section 230 to form two sub-transistors in the dual-gate transistor. The portion of the scan line 330 that overlaps with the first region of the second semiconductor section 220 forms the gate of one sub-transistor, and the portion of the scan line 330 that overlaps with the second region of the third semiconductor section 230 forms the gate of the other sub-transistor. The portions of the second semiconductor section 220 and the third semiconductor section 230 that do not overlap with the scan line 330 form the source / drain regions of the two sub-transistors. The area where the first semiconductor section 210, the second semiconductor section 220, and the third semiconductor section 230 meet and connect is the dual-gate node of the dual-gate transistor, so that the first metal section 310 and the first semiconductor section 210 overlap to form a thin-film transistor connecting the dual-gate node.

[0054] Combination Figures 1 to 5 Furthermore, the scan line 330 includes a main body portion 331 and a branch portion 332. The branch portion 332 is connected to the main body portion 331. The vertical projections of the branch portion 332 and the second semiconductor portion 220 on the substrate 10 overlap, and the vertical projections of the main body portion 331 and the third semiconductor portion 230 on the substrate 10 overlap. The first end of the first semiconductor portion 210, the first end of the second semiconductor portion 220, and the first end of the third semiconductor portion 230 converge and connect to the dual-gate node of the dual-gate transistor. The second end of the second semiconductor portion 220 or the second end of the third semiconductor portion 230 is connected to the gate of the driving transistor DT.

[0055] For example, the first transistor T1, which is a dual-gate transistor used for threshold voltage compensation of the driving transistor DT, will still be used for explanation. The gate of the first transistor T1 is connected to the first scan line S1, and the scan line 330 can serve as the first scan line S1. The semiconductor layer 20 of the first dual-gate transistor T1-1 can be the second semiconductor portion 220, and the semiconductor layer 20 of the second dual-gate transistor T1-2 can be the third semiconductor portion 230. The first dual-gate transistor T1-1 can be formed by the overlap of the branch portion 332 of the scan line 330 and the second semiconductor portion 220, and the second dual-gate transistor T1-2 can be formed by the overlap of the main body portion 331 of the scan line 330 and the third semiconductor portion 230. The area where the first end of the first semiconductor section 210, the first end of the second semiconductor section 220, and the first end of the third semiconductor section 230 meet and connect can be the dual-gate node N1 of the first transistor T1. The second end of the second semiconductor section 220 can be connected to the gate of the driving transistor DT, that is, connected to the second metal section 320 (the connection between the second semiconductor section 220 and the second metal section 320 is not shown in the figure). The second end of the third semiconductor section 230 can be connected to the first terminal of the driving transistor DT, that is, connected to the first end of the fourth semiconductor section 240.

[0056] Combination Figures 1 to 5 Optionally, the second semiconductor portion 220 and the main body portion 331 extend along a first direction X, and the branch portion 332 and the third semiconductor portion 230 extend along a second direction Y. The first direction X and the second direction Y intersect, and the first semiconductor portion 210 is located on the side of the second semiconductor portion 220 away from the main body portion 331. Exemplarily, the first direction X and the second direction Y can be perpendicular, and the third semiconductor portion 230 is located on one side of the branch portion 332. The second metal portion 320 is located on one side of the main body portion 331, and both the first semiconductor portion 210 and the second semiconductor portion 220 are located on the other side of the main body portion 331, with the first semiconductor portion 210 located on the side of the second semiconductor portion 220 away from the main body portion 331.

[0057] Combination Figures 1 to 5 Furthermore, the first semiconductor portion 210 includes a first sub-semiconductor portion 211 and a second sub-semiconductor portion 212. The first end of the first sub-semiconductor portion 211 is connected to the dual-gate node of the dual-gate transistor, and the second end of the first sub-semiconductor portion 211 is connected to the first end of the second sub-semiconductor portion 212. The extending directions of the first sub-semiconductor portion 211 and the second sub-semiconductor portion 212 intersect, and the vertical projection of the first metal portion 310 on the substrate 10 overlaps with the vertical projections of the first sub-semiconductor portion 211 and the second sub-semiconductor portion 212 on the substrate 10.

[0058] For example, the vertical projection of the first metal portion 310 onto the substrate 10 can cover the vertical projections of the first sub-semiconductor portion 211 and the second sub-semiconductor portion 212 onto the substrate 10. Optionally, the first sub-semiconductor portion 211 extends along the second direction Y, and the second sub-semiconductor portion 212 extends along the first direction X. The extending directions of the first sub-semiconductor portion 211 and the third semiconductor portion 230 can be the same, and the second sub-semiconductor portion 212, the second semiconductor portion 220, and the fourth semiconductor portion 240 are all located on the same side of the first sub-semiconductor portion 211 and the third semiconductor portion 230, and the second sub-semiconductor portion 212 is located on the side of the second semiconductor portion 220 away from the main body portion 331.

[0059] Figure 6 yes Figure 1 A magnified view of another local structure of the pixel circuit. Combined with... Figure 4 and Figure 6 In another embodiment, the third semiconductor section 230 may include a third sub-semiconductor section 231 and a fourth sub-semiconductor section 232. The first end of the first semiconductor section 210, the first end of the second semiconductor section 220, and the first end of the third sub-semiconductor section 231 are connected to the dual-gate node of the dual-gate transistor. The second end of the third sub-semiconductor section 231 is connected to the first end of the fourth sub-semiconductor section 232. The second end of either the second semiconductor section 220 or the second end of the fourth sub-semiconductor section 232 is connected to the gate of the driving transistor DT. A second region of the third semiconductor section 230 is located within the fourth sub-semiconductor section 232, and the second region is a portion of the fourth sub-semiconductor section 232. The vertical projection of the scan line 330 onto the substrate 10 overlaps with the vertical projections of the first region of the second semiconductor section 220 and the second region of the fourth sub-semiconductor section 232 onto the substrate 10.

[0060] For example, the first transistor T1, which is a dual-gate transistor used for threshold voltage compensation of the driving transistor DT, will still be used for explanation. The gate of the first transistor T1 is connected to the first scan line S1, and the scan line 330 can serve as the first scan line S1. The semiconductor layer 20 of the first dual-gate transistor T1-1 can be the second semiconductor portion 220, and the semiconductor layer 20 of the second dual-gate transistor T1-2 can be the third semiconductor portion 230. The first dual-gate transistor T1-1 can be formed by the overlap of the scan line 330 and the second semiconductor portion 220, and the second dual-gate transistor T1-2 can be formed by the overlap of the scan line 330 and the third semiconductor portion 230. The area where the first end of the first semiconductor section 210, the first end of the second semiconductor section 220, and the first end of the third sub-semiconductor section 231 meet and connect can be the dual-gate node N1 of the first transistor T1. The second end of the second semiconductor section 220 can be connected to the gate of the driving transistor DT, that is, connected to the second metal section 320 (not shown in the figure). The second end of the fourth sub-semiconductor section 232 can be connected to the first electrode of the driving transistor DT, that is, connected to the first end of the fourth semiconductor section 240.

[0061] Combination Figure 4 and Figure 6 Furthermore, scan line 330 and third sub-semiconductor portion 231 extend along a first direction X, and first semiconductor portion 210, second semiconductor portion 220, and fourth sub-semiconductor portion 232 extend along a second direction Y, with the first direction X and the second direction Y intersecting. First semiconductor portion 210 is located on the side of third sub-semiconductor portion 231 away from scan line 330. Exemplarily, the first direction X and the second direction Y can be perpendicular, the first semiconductor portion 210, second semiconductor portion 220, and fourth sub-semiconductor portion 232 extend in the same direction, and the fourth sub-semiconductor portion 232 is located on the same side of first semiconductor portion 210 and second semiconductor portion 220. Second metal portion 320 is located on one side of scan line 330, and first semiconductor portion 210 and third sub-semiconductor portion 231 are located on the other side of scan line 330, with first semiconductor portion 210 located on the side of third sub-semiconductor portion 231 away from scan line 330.

[0062] See Figures 2 to 6Based on the above embodiments, since the capacitor structure formed by the overlapping of the first metal portion 310 and the first semiconductor portion 210 can also be regarded as a thin-film transistor, the set level signal Vx connected to the first metal portion 310 can be a signal used to control the conduction of the thin-film transistor. For example, when the capacitor structure formed by the overlapping of the first metal portion 310 and the first semiconductor portion 210 can be regarded as a P-type transistor, the set level signal Vx can be a low-level signal. This enhances the conductivity of the first semiconductor portion 210 when a low-level signal is connected to the first metal portion 310, thereby increasing the capacitance value of the first capacitor C1, allowing the first capacitor C1 to function as a voltage storage device. Similarly, when the capacitor structure formed by the overlapping of the first metal portion 310 and the first semiconductor portion 210 can be regarded as an N-type transistor, the set level signal Vx can be a high-level signal. This enhances the conductivity of the first semiconductor portion 210 when a high-level signal is connected to the first metal portion 310, thereby increasing the capacitance value of the first capacitor C1, allowing the first capacitor C1 to function as a voltage storage device.

[0063] Figure 7 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention. See also... Figure 7 Optionally, the pixel circuit 100 further includes a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a storage capacitor Cst. The gate of the first transistor T1 is connected to the first scan line S1. The gate of the second transistor T2 is connected to the second scan line S2. The first terminal of the second transistor T2 is connected to the initialization signal line Vref, and the second terminal of the second transistor T2 is connected to the gate of the driving transistor DT. The second transistor T2 is used to write the voltage on the initialization signal line Vref to the gate of the driving transistor DT. The gate of the third transistor T3 is connected to the first scan line S1. The first terminal of the third transistor T3 is connected to the data line Data, and the second terminal of the third transistor T3 is connected to the second terminal of the driving transistor DT. The third transistor T3 is used to write the data voltage on the data line Data to the gate of the driving transistor DT. The gates of the fourth transistor T4 and the fifth transistor T5 are connected to the light emission control signal line EM. The fourth transistor T4, the driving transistor DT, the fifth transistor T5, and the light-emitting device D1 are connected in series between the first power line ELVDD and the second power line ELVSS. The gate of the sixth transistor T6 is connected to the third scan line S3, the first terminal of the sixth transistor T6 is connected to the initialization signal line Vref, and the second terminal of the sixth transistor T6 is connected to the first terminal of the light-emitting device D1. The sixth transistor T6 is used to write the voltage on the initialization signal line Vref into the first terminal of the light-emitting device D1. The first terminal of the storage capacitor Cst is connected to the first power supply line ELVDD, and the second terminal of the storage capacitor Cst is connected to the gate of the driving transistor DT.

[0064] Figure 8This is a schematic diagram of the driving timing of a pixel circuit provided in an embodiment of the present invention. Figure 8 The driving timing shown can be applied to drivers. Figure 7 The pixel circuit in the pixel circuit 100 operates. Each transistor in the pixel circuit 100 can be either a P-type transistor or an N-type transistor. The following section discusses this in conjunction with... Figure 7 and Figure 8 Taking the example that all transistors in the pixel circuit 100 are P-type transistors, the working principle of the pixel circuit 100 will be explained.

[0065] For example, the operation phases of the pixel circuit 100 include an initialization phase t0, a data writing phase t1, and a light emission phase t2.

[0066] During the initialization phase t0, a high-level signal arrives on the first scan line S1, while low-level signals arrive on the second and third scan lines S2 and S3, and a high-level signal arrives on the light emission control signal EM. The second transistor T2 and the sixth transistor T6 are turned on, while the remaining transistors are turned off. The initialization voltage on the initialization signal line Vref is written to the gate of the driving transistor DT through the second transistor T2 to initialize the gate voltage of the driving transistor DT and control the driving transistor DT to turn on. The initialization voltage on the initialization signal line Vref is also written to the first terminal of the light-emitting device D1 through the sixth transistor T6 to initialize the voltage at the first terminal of the light-emitting device D1.

[0067] During the data writing phase t1, a low-level signal arrives on the first scan line S1, while high-level signals arrive on the second scan line S2 and the third scan line S3. The light emission control signal EM remains high. The first transistor T1, the third transistor T3, and the driving transistor DT are turned on, while the remaining transistors are turned off. The data voltage on the data line Data is sequentially written to the gate of the driving transistor DT through the third transistor T3, the driving transistor DT, and the first transistor T1 until the voltage difference between the gate and the second terminal of the driving transistor DT reaches the threshold voltage of the driving transistor DT. At this point, the driving transistor DT is turned off, making its gate voltage a voltage related to both the data voltage and the threshold voltage of the driving transistor DT, thus achieving data voltage writing and threshold voltage compensation for the driving transistor DT. Simultaneously, the storage capacitor Cst stores the gate voltage of the driving transistor DT.

[0068] During the light-emitting stage t2, the signals on the first scan line S1, the second scan line S2, and the third scan line S3 are all high-level signals, while the low-level signal on the light-emitting control signal EM arrives. The fourth transistor T4, the fifth transistor T5, and the driving transistor DT are turned on, while the remaining transistors are turned off. A discharge path is formed between the first power line ELVDD and the second power line ELVSS. The driving transistor DT generates a driving current according to its gate voltage to drive the light-emitting device D1 to emit light at the corresponding brightness.

[0069] In related technologies, when the data writing stage t1 ends and the light emission stage t2 begins, the signal on the first scan line S1 changes from a low level signal to a high level signal. The potential of the dual-gate node N1 of the first transistor T1 is easily coupled by the signal on the first scan line S1, causing the potential of the dual-gate node N1 of the first transistor T1 to be pulled high. This results in a potential difference between the dual-gate node N1 of the first transistor T1 and the gate of the driving transistor DT, causing leakage current from the dual-gate node N1 of the first transistor T1 to the gate of the driving transistor DT. This causes the gate of the driving transistor DT to rise, resulting in a decrease in the driving current flowing through the light-emitting device D1, which reduces the brightness of the light-emitting device D1 and thus affects the display effect of the display panel.

[0070] Compared with related technologies, the technical solution of this embodiment uses the overlapping of the first metal part 310 and the first semiconductor part 210 to form a first capacitor C1. When the first metal part 310 is connected to a set level signal, the first capacitor C1 can stabilize the potential of the dual gate node N1, making the potential of the dual gate node N1 less susceptible to coupling from signals on the first scan line S1 and causing jumps. This helps to keep the gate potential of the dual gate node N1 and the driving transistor DT close, thereby alleviating the leakage problem of the pixel circuit 100 and improving the display effect of the display panel.

[0071] See Figure 2 , Figure 3 , Figures 6 to 8 Based on the above embodiments, optionally, the multilayer metal layer further includes an initialization signal line Vref, which is used to provide an initialization voltage to the pixel circuit 100 to initialize the pixel circuit 100. The first metal part 310 is connected to the initialization signal line Vref, and the signal on the initialization signal line Vref serves as a set level signal Vx.

[0072] Figure 2 , Figure 3 , Figure 6 and Figure 7Both cases illustrate the case where the first metal portion 310 is connected to the initialization signal line Vref, and the signal on the initialization signal line Vref serves as a set level signal. The initialization signal line Vref can be a signal line connected to the second transistor T2 in the pixel circuit 100. The multilayer metal layers in the array substrate also include a second metal layer 40 and a third metal layer 50. The second metal layer 40 is located on the side of the first metal layer 30 away from the substrate 10, and the third metal layer 50 is located on the side of the second metal layer 40 away from the substrate 10. The initialization signal line Vref can be disposed in the second metal layer 40, and the third metal layer 50 includes a connection portion 510. The first metal portion 310 and the initialization signal line Vref can be electrically connected through the connection portion 510. When the driving transistor DT is a P-type transistor, and the capacitor structure formed by the overlapping of the first metal portion 310 and the first semiconductor portion 210 can be considered as a P-type transistor, the initialization voltage signal on the initialization signal line Vref is a low-level signal. This initializes the gate voltage of the driving transistor DT and allows the first metal portion 310 to be connected to a low-level signal, thereby enhancing the conductivity of the first semiconductor portion 210 and increasing the capacitance value of the first capacitor C1, enabling the first capacitor C1 to stabilize the dual-gate node potential of the dual-gate transistor. Similarly, when the driving transistor DT is an N-type transistor, and the capacitor structure formed by the overlapping of the first metal portion 310 and the first semiconductor portion 210 can be considered as an N-type transistor, the initialization voltage signal on the initialization signal line Vref is a high-level signal. This initializes the gate voltage of the driving transistor DT and allows the first metal portion 310 to be connected to a high-level signal, thereby enhancing the conductivity of the first semiconductor portion 210 and increasing the capacitance value of the first capacitor C1, enabling the first capacitor C1 to stabilize the dual-gate node potential of the dual-gate transistor.

[0073] See Figure 2 , Figure 3 , Figures 6 to 8In another embodiment, the first metal layer 30 further includes a scan line 330, which overlaps with the vertical projection of the semiconductor layer 20 of the dual-gate transistor onto the substrate 10. The first metal portion 310 can be connected to the scan line 330, and the signal on the scan line 330 can be used as a set level signal. Specifically, the scan line 330 can be the first scan line S1. The signal connected to the first scan line S1 during the data writing stage t1 is a low-level signal. When the first transistor T1 is a P-type transistor and the capacitor structure formed by the overlapping of the first metal part 310 and the first semiconductor part 210 can be regarded as a P-type transistor, or when the first transistor T1 is an N-type transistor and the capacitor structure formed by the overlapping of the first metal part 310 and the first semiconductor part 210 can be regarded as an N-type transistor, the signal on the first scan line S1 can enhance the conductivity of the first semiconductor part 210 throughout the entire data writing stage t1, thereby increasing the capacitance value of the first capacitor C1, so that the first capacitor C1 plays the role of stabilizing the dual-gate node potential of the dual-gate transistor. This helps to prevent the potential of the dual-gate node N1 of the first transistor T1 from jumping at the beginning of the light-emitting stage t2.

[0074] Combination Figure 7 and Figure 8 In another embodiment, the multilayer metal layer also includes power lines for providing power voltage to the pixel circuit 100. The first metal portion 310 is connected to the power lines, and the signal on the power lines serves as a set level signal. Exemplarily, the power lines can be a first power line ELVDD or a second power line ELVSS. The first power line ELVDD is connected to a first power voltage, and the second power line ELVSS is connected to a second power voltage. The first power voltage is positive, and the second power voltage is negative or zero. When the capacitor structure formed by the overlapping of the first metal portion 310 and the first semiconductor portion 210 can be considered a P-type transistor, the first metal portion 310 can be connected to the second power line ELVSS, and the second power voltage signal on the second power line ELVSS can be a low-level signal. This allows the first capacitor C1 formed by the first metal portion 310 and the first semiconductor portion 210 to store voltage, thereby stabilizing the dual-gate node potential of the dual-gate transistor. When the capacitor structure formed by the overlapping of the first metal part 310 and the first semiconductor part 210 can be regarded as an N-type transistor, the first metal part 310 can be connected to the first power line ELVDD, and the first power supply voltage signal on the first power line ELVDD is a high-level signal, which enables the first capacitor C1 formed by the first metal part 310 and the first semiconductor part 210 to store voltage, thereby stabilizing the dual-gate node potential of the dual-gate transistor.

[0075] Figure 9 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention. See also... Figure 9In this embodiment, the second transistor T2 is configured as a dual-gate transistor. Correspondingly, the dual-gate transistor connected to the gate of the driving transistor DT can also be the second transistor T2. The second transistor T2 includes a third dual-gate transistor T2-1 and a fourth dual-gate transistor T2-2. The first terminal of the fourth dual-gate transistor T2-2 is connected to the initialization signal line Vref, and the second terminal of the fourth dual-gate transistor T2-2 is connected to the first terminal of the third dual-gate transistor T2-1. The second terminal of the third dual-gate transistor T2-1 is connected to the gate of the driving transistor DT. The dual-gate node of the dual-gate transistor can be the dual-gate node N2 of the second transistor T2, that is, the intermediate node between the second terminal of the fourth dual-gate transistor T2-2 and the first terminal of the third dual-gate transistor T2-1.

[0076] By setting the first semiconductor section 210 to connect to the dual-gate node N2 of the second transistor T2, the vertical projections of the first semiconductor section 210 and the first metal section 130 on the substrate 10 overlap, so that the first metal section 310 and the first semiconductor section 210 overlap to form a first capacitor C1. When the first metal section 310 is connected to the set level signal Vx, the first capacitor C1 can store voltage, so as to stabilize the potential of the dual-gate node N2 through the first capacitor C1, making the potential of the dual-gate node N2 of the second transistor T2 less likely to be coupled by other signals and cause jumps. This helps to keep the gate potential of the dual-gate node N2 and the driving transistor DT close, thereby alleviating the leakage problem between the gate of the dual-gate node N2 of the second transistor T2 and the gate of the driving transistor DT, and improving the display effect of the display panel.

[0077] Furthermore, combined Figure 2 , Figure 6 and Figure 9 The gate of the second transistor T2 is connected to the second scan line S2, and scan line 330 can serve as the second scan line S2. One of the semiconductor layers 20 of the third dual-gate transistor T2-1 and the fourth dual-gate transistor T2-2 can be the second semiconductor portion 220, and the other can be the third semiconductor portion 230. The second end of the second semiconductor portion 220 or the second end of the third semiconductor portion 230 is connected to the gate of the driving transistor DT (in this embodiment, the third semiconductor portion 230 is not connected to the fourth semiconductor portion 240 of the driving transistor DT).

[0078] This invention also provides a display panel, which may be an organic light-emitting diode (OLED) display panel or a micron-scale light-emitting diode (Micro-LED) display panel, etc. The display panel provided in this invention includes the array substrate provided in any of the above embodiments, and therefore possesses the corresponding functional structures and beneficial effects of the array substrate, which will not be elaborated further here.

[0079] This invention also provides a display device, including the display panel provided in the above embodiments, and thus possesses the corresponding functional structure and beneficial effects of the display panel, which will not be repeated here. The display device provided in this invention can be a mobile phone, or any electronic product with display function, including but not limited to the following categories: television, laptop, desktop monitor, tablet computer, digital camera, smart bracelet, smart glasses, in-vehicle display, medical equipment, industrial control equipment, touch interactive terminal, etc. This invention does not impose any special limitations on these categories.

[0080] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. An array substrate, characterized by, The application relates to a display panel, comprising: a substrate; a semiconductor layer and a multilayer metal layer arranged on one side of the substrate, the semiconductor layer and the multilayer metal layer being provided with a plurality of pixel circuits, the pixel circuit comprising a driving transistor and a double-gate transistor connected to the gate of the driving transistor; wherein the semiconductor layer comprises a first semiconductor part connected to a double-gate node of the double-gate transistor, the multilayer metal layer comprises a first metal layer, the first metal layer comprises a first metal part, the vertical projection of the first metal part and the first semiconductor part on the substrate is overlapped, the first metal part is used for accessing a set level signal, and the first metal part and the first semiconductor part form a capacitor; wherein the first metal layer further comprises a scan line, the semiconductor layer further comprises a second semiconductor part and a third semiconductor part of the double-gate transistor; the vertical projection of the scan line on the substrate is overlapped with the vertical projection of the second semiconductor part and the third semiconductor part on the substrate respectively, and the first semiconductor part, the second semiconductor part and the third semiconductor part are connected to the double-gate node of the double-gate transistor; wherein the scan line comprises a main part and a branch part, the branch part is connected to the main part, the vertical projection of the branch part and the second semiconductor part on the substrate is overlapped, and the vertical projection of the main part and the third semiconductor part on the substrate is overlapped; the first end of the first semiconductor part, the first end of the second semiconductor part and the first end of the third semiconductor part are connected to the double-gate node of the double-gate transistor, and the second end of the second semiconductor part or the second end of the third semiconductor part is connected to the gate of the driving transistor.

2. The array substrate of claim 1, wherein, The first metal layer is the layer closest to the semiconductor layer in the multilayer metal layer.

3. The array substrate of claim 1, wherein, The second semiconductor part and the main part extend along a first direction, the branch part and the third semiconductor part extend along a second direction, the first direction and the second direction intersect, and the first semiconductor part is located on the side of the second semiconductor part away from the main part.

4. The array substrate of claim 3, wherein, The first semiconductor part comprises a first sub-semiconductor part and a second sub-semiconductor part, the first end of the first sub-semiconductor part is connected to the double-gate node of the double-gate transistor, the second end of the first sub-semiconductor part is connected to the first end of the second sub-semiconductor part, the extension directions of the first sub-semiconductor part and the second sub-semiconductor part intersect, and the vertical projection of the first metal part on the substrate is overlapped with the vertical projection of the first sub-semiconductor part and the second sub-semiconductor part on the substrate respectively.

5. The array substrate of claim 4, wherein, The first sub-semiconductor part extends along the second direction, and the second sub-semiconductor part extends along the first direction.

6. The array substrate of claim 1, wherein, The third semiconductor part comprises a third sub-semiconductor part and a fourth sub-semiconductor part; The first end of the first semiconductor part, the first end of the second semiconductor part and the first end of the third semiconductor part are connected to a double-gate node of the double-gate transistor, the second end of the third semiconductor part is connected to the first end of the fourth semiconductor part, and the second end of the second semiconductor part or the second end of the fourth semiconductor part is connected to the gate of the driving transistor; The vertical projection of the scan line on the substrate intersects with the vertical projection of the second semiconductor part and the fourth semiconductor part on the substrate.

7. The array substrate of claim 6, wherein, The scan line and the third semiconductor part extend along a first direction, and the first semiconductor part, the second semiconductor part and the fourth semiconductor part extend along a second direction, the first direction and the second direction intersect; The first semiconductor part is located on the side of the third semiconductor part away from the scan line.

8. The array substrate according to any one of claims 1-7, wherein, The multi-layer metal layer further comprises an initialization signal line and a power supply line; the vertical projection of the scan line on the substrate intersects with the vertical projection of the semiconductor layer of the double-gate transistor on the substrate; the initialization signal line is used to provide an initialization voltage to the pixel circuit to initialize the pixel circuit; The power supply line is used to provide a power supply voltage to the pixel circuit; The first metal part is connected to the scan line, and the signal on the scan line is used as the set level signal; Alternatively, the first metal part is connected to the initialization signal line, and the signal on the initialization signal line is used as the set level signal; Alternatively, the first metal part is connected to the power supply line, and the signal on the power supply line is used as the set level signal.

9. The array substrate according to any one of claims 1-7, wherein, The pixel circuit comprises a first transistor connected between the first electrode and the gate of the driving transistor, the first transistor is used to compensate the threshold voltage of the driving transistor, and the first transistor is the double-gate transistor. And / or, The pixel circuit comprises a second transistor, the first electrode of the second transistor is connected to an initialization signal line, the second electrode of the second transistor is connected to the gate of the driving transistor, the second transistor is used to write the voltage on the initialization signal line to the gate of the driving transistor, and the second transistor is the double-gate transistor.

10. A display panel, characterized by, The array substrate comprises any one of claims 1-9.

11. A display device, characterized by comprising: The display panel comprises claim 10.

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