Short circuit protection circuit and protection method based on h-bridge cascade system

Abstract

The application belongs to the technical field of power electronics, and mainly relates to a short-circuit protection circuit based on an H-bridge cascade system, which comprises a control loop and a hardware detection loop; the control loop is provided with a controller; the hardware detection loop is composed of a plurality of main loop H-bridges, each of which is equipped with a driving circuit and a fault detection loop, and the driving circuit and the fault detection loop are electrically connected with the controller; the fault detection loop is used for detecting the short-circuit fault of the main loop H-bridge, and when there is a short-circuit fault, the fault detection loop is used for sending a fault ERRO_OUT signal to the controller, and the driving circuit is used for receiving the driving signal sent by the controller to perform a blocking action on the main loop H-bridge; in the application, a short-circuit protection circuit for the voltage across the two ends of a directly-sampled switching device is designed for the H-bridge circuit, and the circuit is composed of a control loop and a hardware detection loop, and can quickly realize the short-circuit protection function in the simplest way.

Description

Technical Field

[0001] This invention belongs to the field of power electronics technology, and mainly relates to a short-circuit protection circuit and protection method based on an H-bridge cascaded system. Background Technology

[0002] H-bridge systems are generally composed of common switching devices such as IGBTs or MOS. The system has a large number of power devices and a complex circuit design. Multilevel systems based on H-bridge cascades are generally composed of several single bridges. The more single bridges connected in series, the more difficult it is to reliably guarantee the stability of the system. In particular, when serious faults such as short circuits occur, rapid detection and handling are required to avoid more serious faults.

[0003] Therefore, a fast and accurate short-circuit protection circuit is designed for H-bridge circuits, which can realize the important short-circuit fault protection function with a simple and practical circuit. Summary of the Invention

[0004] This invention provides a short-circuit protection circuit based on an H-bridge cascaded system, which performs short-circuit detection in real time during system operation to ensure rapid fault handling when a short-circuit fault occurs in the system.

[0005] To achieve the above objectives, the present invention provides the following technical solution:

[0006] A short-circuit protection circuit based on an H-bridge cascade system includes a control loop and a hardware detection loop;

[0007] The control loop is equipped with a controller;

[0008] The hardware detection circuit is composed of multiple cascaded main circuit H-bridges. Each main circuit H-bridge is equipped with a drive circuit and a fault detection circuit. The drive circuit and the fault detection circuit are both electrically connected to the controller.

[0009] The fault detection circuit is used to detect short-circuit faults in the main circuit H-bridge. When a short-circuit fault is detected, the fault detection circuit is used to send a fault ERRO_OUT signal to the controller. The drive circuit is used to receive the drive signal sent by the controller and perform a wave blocking action on the main circuit H-bridge.

[0010] Preferably, the main circuit H-bridge is composed of switch Q1, switch Q2, switch Q3 and switch Q4. Switch Q1 and switch Q2 are located on one side of the main circuit H-bridge, and switch Q3 and switch Q4 are located on the other side of the main circuit H-bridge. Switch Q1 and switch Q2 are connected in series, switch Q3 and switch Q4 are connected in series, switch Q1 and switch Q3 are connected in parallel with a DC positive terminal, and switch Q2 and switch Q4 are connected in parallel with a DC negative terminal.

[0011] AC1 is output at the midpoint of the connection between the switching transistors Q1 and Q2, and AC2 is output at the midpoint of the connection between the switching transistors Q3 and Q4. This is used to connect the power terminals that are output to the outside when multiple main circuit H-bridges are cascaded.

[0012] Each of the drive circuits is electrically connected to the gate of the corresponding main circuit H-bridge switching transistors Q1, Q2, Q3 and Q4, respectively, for transmitting the corresponding drive signals G1, G2, G3 and G4.

[0013] Furthermore, the drive signals G1, G2, G3, and G4 are all controlled by the controller to be turned on and off.

[0014] Preferably, the switching transistor Q1 includes a body diode D1, the switching transistor Q2 includes a body diode D2, the switching transistor Q3 includes a body diode D3, and the switching transistor Q4 includes a body diode D4.

[0015] Preferably, the fault detection circuit includes two comparators and multiple passive devices;

[0016] The two comparators are configured as comparator COMP1 and comparator COMP2;

[0017] The plurality of passive devices include resistor R41, capacitor C41, diode D41, resistor R11, capacitor C11, and diode D11;

[0018] The input terminal of comparator COMP1 is connected to the connection line of the switching transistors Q1 and Q2. The positive input terminal of comparator COMP1 is used to receive the signal V1 of the line under test. The negative input terminal of comparator COMP1 is used to receive the reference signal VREF1. The output terminal of comparator COMP1 is connected in series with the gate of the switching transistor Q2 through resistor R11. The capacitor C11 and the diode D11 are connected in series with the negative terminal of the DC power supply. The output terminal of comparator COMP1 is used to output the fault ERRO_OUT signal.

[0019] The input terminal of comparator COMP2 is connected to the connection line of the switching transistors Q3 and Q4. The positive input terminal of comparator COMP2 is used to receive the signal V2 of the line under test, and the negative input terminal of comparator COMP2 is used to receive the reference signal VREF2. The output terminal of comparator COMP2 is connected in series with the gate of the switching transistor Q4 through resistor R41. The capacitor C41 and the diode D41 are connected in series with the negative terminal of the DC power supply. The output terminal of comparator COMP2 is used to output the fault ERRO_OUT signal.

[0020] Preferably, the fault detection signal V1 is used to detect the Vds or Vce level signal of the switching transistor Q2 in the main circuit H-bridge;

[0021] The fault detection signal V2 is used to detect the Vds or Vce level signal of the switching transistor Q4 in the main circuit H-bridge.

[0022] This invention also provides a short-circuit protection method based on an H-bridge cascaded system, used to provide short-circuit protection for a short-circuit protection circuit based on an H-bridge cascaded system as proposed above, preventing the fault from escalating and ensuring stable and reliable system operation; the method includes the following steps:

[0023] S1: After the system is initialized and powered on, the fault detection circuit detects the short-circuit fault of the main circuit H-bridge;

[0024] S2: If a short circuit fault occurs, the fault detection circuit sends the fault ERRO_OUT signal to the controller;

[0025] After receiving the fault ERRO_OUT signal, the controller sends a drive signal to the drive circuit.

[0026] The driving circuit receives the driving signal and performs a wave blocking action on the main circuit H-bridge;

[0027] If there is no short circuit fault, the short circuit protection logic will not be triggered, and the system will operate normally and stably until the entire system shuts down and loses power normally.

[0028] Specifically, S1 includes:

[0029] First, the controller is set to a high level for the fault ERRO_OUT signal, which is considered a normal state. Second, the controller is set to a low level for the fault ERRO_OUT signal, which is considered a short-circuit fault state.

[0030] If neither switch Q2 nor switch Q4 is in a short-circuit state, then both fault detection signals V1 and V2 are detected to be at a high level. Their values ​​are compared with the fault voltage threshold signals VREF1 and VREF2 by comparators COMP1 and COMP2 respectively, and the final output fault ERRO_OUT signal is high level.

[0031] If the switch Q2 is working normally and the switch Q4 is in a short-circuit state, then the fault detection signal V1 is detected to be high and the fault detection signal V2 is detected to be low. Their values ​​are compared with the fault voltage threshold signals VREF1 and VREF2 through comparators COMP1 and COMP2 respectively, and the final output fault ERRO_OUT signal is low.

[0032] If the switch Q4 is working normally and the switch Q2 is in a short-circuit state, then the fault detection signal V1 is detected to be low and the fault detection signal V2 is detected to be high. Their values ​​are compared with the fault voltage threshold signals VREF1 and VREF2 through comparators COMP1 and COMP2 respectively, and the final output fault ERRO_OUT signal is low.

[0033] If both switch Q2 and switch Q4 are short-circuited, then both fault detection signals V1 and V2 are detected to be low. Their values ​​are compared with the fault voltage threshold signals VREF1 and VREF2 by comparators COMP1 and COMP2 respectively, and the final output fault ERRO_OUT signal is low.

[0034] The short-circuit fault refers to the situation where the drive signal G2 or the drive signal G4 is a high-level signal.

[0035] The method further includes step S3:

[0036] S3: After troubleshooting, repeat steps S1 and S2 to perform short-circuit fault detection on the main circuit H-bridge.

[0037] Compared with the prior art, the beneficial effects of the present invention are:

[0038] 1. In this invention, a short-circuit protection circuit for directly sampling the voltage across the switching devices is designed for H-bridge circuits. This circuit consists of a control loop and a hardware detection loop, and can quickly achieve short-circuit protection function in the simplest way.

[0039] 2. This invention details a short-circuit protection logic based on an H-bridge cascade system, which can quickly and efficiently identify and handle short-circuit faults, ensure the system operates quickly, safely and reliably, and prevent losses caused by the expansion of faults. Attached Figure Description

[0040] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0041] Figure 1 This is a system block diagram of a short-circuit protection circuit based on an H-bridge cascaded system according to the present invention;

[0042] Figure 2 In this invention Figure 1 The schematic diagram of the detection circuit. Detailed Implementation

[0043] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0044] like Figure 1 , 2 As shown, a short-circuit protection circuit based on an H-bridge cascade system includes a control loop and a hardware detection loop. The control loop is equipped with a controller. The hardware detection loop consists of multiple cascaded main loop H-bridges. Each main loop H-bridge is equipped with a drive circuit (which can be an IC) and a fault detection loop. Both the drive circuit and the fault detection loop are electrically connected to the controller. The fault detection loop is used to detect short-circuit faults in the main loop H-bridges. When a short-circuit fault is detected, the fault detection loop sends a fault ERRO_OUT signal to the controller. The drive circuit receives the drive signal sent by the controller and performs a blocking action on the main loop H-bridges.

[0045] Furthermore, the switching devices in each main circuit H-bridge consist of switching transistors Q1, Q2, Q3, and Q4. These switching devices can be of various types, such as common MOSFETs and IGBTs. Switches Q1 and Q2 are located on one side of the main circuit H-bridge, while Q3 and Q4 are located on the other side. Switches Q1 and Q2 are connected in series, and Q3 and Q4 are connected in series. Switches Q1 and Q3 are connected in parallel with a positive DC terminal, while Q2 and Q4 are connected in parallel with a negative DC terminal. The switching devices Q1 and Q4... AC1 is output at the midpoint of connection 2; AC2 is output at the midpoint of connection between switching transistors Q3 and Q4; thus, when multiple H-bridges need to be cascaded, only the external power terminals need to be configured and connected appropriately; each drive circuit is electrically connected to the gate of the corresponding main circuit H-bridge switching transistors Q1, Q2, Q3 and Q4 respectively, for transmitting the corresponding drive signals G1, G2, G3 and G4; and drive signals G1, G2, G3 and G4 are all controlled by the controller to be turned on and off.

[0046] Furthermore, switch Q1 includes a body diode D1, switch Q2 includes a body diode D2, switch Q3 includes a body diode D3, and switch Q4 includes a body diode D4; these are used to regulate and rectify the voltage of the circuit.

[0047] Furthermore, the fault detection circuit includes two comparators and multiple passive devices;

[0048] The two comparators are set as comparator COMP1 and comparator COMP2;

[0049] Multiple passive components include resistor R41, capacitor C41, diode D41, resistor R11, capacitor C11, and diode D11;

[0050] The input terminal of comparator COMP1 is connected to the connection line of switching transistors Q1 and Q2. The positive input terminal of comparator COMP1 is used to receive the signal V1 of the line under test, and the negative input terminal of comparator COMP1 is used to receive the reference signal VREF1. The output terminal of comparator COMP1 is connected in series with the gate of switching transistor Q2 through resistor R11. Capacitor C11 and diode D11 are connected in series with the negative terminal of DC power. The output terminal of comparator COMP1 is used to output the fault ERRO_OUT signal.

[0051] The input of comparator COMP2 is connected to the circuit connecting switching transistors Q3 and Q4. The positive input of comparator COMP2 is used to receive the signal V2 from the circuit under test, and the negative input of comparator COMP2 is used to receive the reference signal VREF2. The output of comparator COMP2 is connected in series with the gate of switching transistor Q4 via resistor R41. Capacitor C41 and diode D41 are connected in series with the negative terminal of DC power. The output of comparator COMP2 is used to output the fault ERRO_OUT signal.

[0052] The fault detection delay time of the system can be set by adjusting the resistance values ​​of resistors R41 and R11, as well as the capacitance values ​​of capacitors C41 and C11, to prevent false fault triggering and make the system work more reliably.

[0053] Furthermore, fault detection signal V1 is used to detect the Vds or Vce level signal of switch Q2 in the main circuit H-bridge; fault detection signal V2 is used to detect the Vds or Vce level signal of switch Q4 in the main circuit H-bridge.

[0054] Among them, reference Figure 2 As shown, in this system, to facilitate the design of the detection circuit, only Q2 and Q4 need to be detected to cover all short-circuit faults in the entire main circuit H-bridge. Since the switching transistors Q1, Q2, Q3, and Q4 together form the basic structure of the main circuit H-bridge, any two of the switching transistors Q1, Q2, Q3, and Q4 can also be used for fault detection signals V1 and V2 to detect short-circuit faults. This embodiment is only one implementation method.

[0055] This invention also provides a short-circuit protection method based on an H-bridge cascaded system, used to provide short-circuit protection for a short-circuit protection circuit based on an H-bridge cascaded system as proposed above, preventing the fault from escalating and ensuring stable and reliable system operation; the method includes the following steps:

[0056] S1: After the system is initialized and powered on, the fault detection circuit detects short-circuit faults in the main circuit H-bridge;

[0057] S2: If a short circuit fault occurs, the fault detection circuit sends a fault ERRO_OUT signal to the controller;

[0058] After receiving the fault ERRO_OUT signal, the controller sends a drive signal to the drive circuit;

[0059] The drive circuit receives the drive signal and performs a wave blocking action on the main circuit H-bridge.

[0060] If there is no short circuit fault, the short circuit protection logic will not be triggered, and the system will operate normally and stably until the entire system shuts down and loses power normally.

[0061] Specifically, S1 includes:

[0062] First, the controller is set to a high level for the fault ERRO_OUT signal, which is considered a normal state. Then, the controller is set to a low level for the fault ERRO_OUT signal, which is considered a short-circuit fault state.

[0063] If neither switch Q2 nor switch Q4 is short-circuited, then both fault detection signals V1 and V2 are detected to be high. Their values ​​are compared with the fault voltage threshold signals VREF1 and VREF2 by comparators COMP1 and COMP2 respectively, and the final output fault ERRO_OUT signal is high.

[0064] If switch Q2 is working normally and switch Q4 is short-circuited, then the fault detection signal V1 is detected to be high and the fault detection signal V2 is detected to be low. These values ​​are compared with the fault voltage threshold signals VREF1 and VREF2 by comparators COMP1 and COMP2 respectively, and the final output fault ERRO_OUT signal is low.

[0065] If switch Q4 is working normally and switch Q2 is in a short-circuit state, then the fault detection signal V1 is detected to be low and the fault detection signal V2 is detected to be high. Their values ​​are compared with the fault voltage threshold signals VREF1 and VREF2 through comparators COMP1 and COMP2 respectively, and the final output fault ERRO_OUT signal is low.

[0066] If both switching transistors Q2 and Q4 are short-circuited, then both fault detection signals V1 and V2 are detected to be low. Their values ​​are compared with the fault voltage threshold signals VREF1 and VREF2 by comparators COMP1 and COMP2 respectively, resulting in a low-level output fault ERRO_OUT signal.

[0067] To prevent false fault triggering, the fault detection circuit is only triggered when drive signal G2 or drive signal G4 is high. After the fault is cleared, steps S1 and S2 are repeated to detect short-circuit faults in the main circuit H-bridge. The fault detection delay time can also be set by adjusting the resistance values ​​of resistors R41 and R11, as well as the capacitance values ​​of capacitors C41 and C11, to prevent false fault triggering.

[0068] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A short-circuit protection circuit based on an H-bridge cascade system, characterized in that: Includes control loops and hardware detection loops; The control loop is equipped with a controller; The hardware detection circuit is composed of multiple cascaded main circuit H-bridges. Each main circuit H-bridge is equipped with a drive circuit and a fault detection circuit. The drive circuit and the fault detection circuit are both electrically connected to the controller. The fault detection circuit is used to detect short-circuit faults in the main circuit H-bridge. When a short-circuit fault is detected, the fault detection circuit is used to send a fault ERRO_OUT signal to the controller. The drive circuit is used to receive the drive signal sent by the controller and perform a wave blocking action on the main circuit H-bridge. The main circuit H-bridge is composed of switch Q1, switch Q2, switch Q3 and switch Q4; The fault detection circuit includes two comparators and multiple passive devices; The two comparators are configured as comparator COMP1 and comparator COMP2; The plurality of passive devices include resistor R41, capacitor C41, diode D41, resistor R11, capacitor C11, and diode D11; The input terminal of comparator COMP1 is connected to the connection line of the switching transistors Q1 and Q2. The positive input terminal of comparator COMP1 is used to receive the signal V1 of the line under test. The negative input terminal of comparator COMP1 is used to receive the reference signal VREF1. The output terminal of comparator COMP1 is connected in series with the gate of the switching transistor Q2 through resistor R11. The capacitor C11 and the diode D11 are connected in series with the negative terminal of DC power. The output terminal of comparator COMP1 is used to output the fault ERRO_OUT signal. The input terminal of comparator COMP2 is connected to the connection line of the switching transistors Q3 and Q4. The positive input terminal of comparator COMP2 is used to receive the signal V2 of the line under test, and the negative input terminal of comparator COMP2 is used to receive the reference signal VREF2. The output terminal of comparator COMP2 is connected in series with the gate of the switching transistor Q4 through resistor R41. The capacitor C41 and the diode D41 are connected in series with the negative terminal of DC power. The output terminal of comparator COMP2 is used to output the fault ERRO_OUT signal.

2. The short-circuit protection circuit based on an H-bridge cascaded system according to claim 1, characterized in that: The switching transistors Q1 and Q2 are located on one side of the main circuit H-bridge, and the switching transistors Q3 and Q4 are located on the other side of the main circuit H-bridge. The switching transistors Q1 and Q2 are connected in series, the switching transistors Q3 and Q4 are connected in series, the switching transistors Q1 and Q3 are connected in parallel with a positive DC terminal, and the switching transistors Q2 and Q4 are connected in parallel with a negative DC terminal. AC1 is output at the midpoint of the connection between the switching transistors Q1 and Q2, and AC2 is output at the midpoint of the connection between the switching transistors Q3 and Q4. This is used to connect the power terminals that are output to the outside when multiple main circuit H-bridges are cascaded. Each of the drive circuits is electrically connected to the gate of the corresponding main circuit H-bridge switching transistors Q1, Q2, Q3 and Q4, respectively, for transmitting the corresponding drive signals G1, G2, G3 and G4. Furthermore, the drive signals G1, G2, G3, and G4 are all controlled by the controller to be turned on and off.

3. A short-circuit protection circuit based on an H-bridge cascaded system according to claim 2, characterized in that: The switching transistor Q1 includes a body diode D1, the switching transistor Q2 includes a body diode D2, the switching transistor Q3 includes a body diode D3, and the switching transistor Q4 includes a body diode D4.

4. A short-circuit protection circuit based on an H-bridge cascaded system according to claim 1, characterized in that: The signal V1 of the line to be tested is used to detect the Vds or Vce level signal of the switching transistor Q2 in the main circuit H bridge; The signal V2 of the circuit to be tested is used to detect the Vds or Vce level signal of the switching transistor Q4 in the main circuit H-bridge.

5. A short-circuit protection method based on an H-bridge cascaded system, applicable to the short-circuit protection circuit based on an H-bridge cascaded system as described in any one of claims 1-4, characterized in that: The method includes the following steps: S1: After the system is initialized and powered on, the fault detection circuit detects the short-circuit fault of the main circuit H-bridge; S2: If a short circuit fault occurs, the fault detection circuit sends the fault ERRO_OUT signal to the controller; After receiving the fault ERRO_OUT signal, the controller sends a drive signal to the drive circuit. The driving circuit receives the driving signal and performs a wave blocking action on the main circuit H-bridge; If there is no short circuit fault, the short circuit protection logic will not be triggered, and the system will operate normally and stably until the entire system shuts down and loses power normally.

6. A short-circuit protection method based on an H-bridge cascaded system according to claim 5, characterized in that: S1 specifically includes: First, the controller is set to a high level for the fault ERRO_OUT signal, which is considered a normal state. Second, the controller is set to a low level for the fault ERRO_OUT signal, which is considered a short circuit fault state. If neither switch Q2 nor switch Q4 is short-circuited, then both of the two signals V1 and V2 of the line under test are detected to be high level. Their values ​​are compared with the reference signals VREF1 and VREF2 by comparators COMP1 and COMP2 respectively, and the final output fault ERRO_OUT signal is high level. If the switch Q2 is working normally and the switch Q4 is in a short-circuit state, then the signal V1 of the line to be tested is detected to be high and the signal V2 of the line to be tested is detected to be low. The values ​​are compared with the reference signals VREF1 and VREF2 by comparators COMP1 and COMP2 respectively, and the final output fault ERRO_OUT signal is low. If the switch Q4 is working normally and the switch Q2 is in a short-circuit state, then the signal V1 of the line to be tested is detected to be low and the signal V2 of the line to be tested is detected to be high. The values ​​are compared with the reference signals VREF1 and VREF2 through comparators COMP1 and COMP2 respectively, and the final output fault ERRO_OUT signal is low. If both switch Q2 and switch Q4 are short-circuited, then both of the two signals V1 and V2 of the line under test are detected to be low. Their values ​​are compared with the reference signals VREF1 and VREF2 by comparators COMP1 and COMP2 respectively, and the final output fault ERRO_OUT signal is low.

7. A short-circuit protection method based on an H-bridge cascaded system according to claim 6, characterized in that: The short-circuit fault refers to the situation where the drive signal G2 or the drive signal G4 is a high-level signal.

8. A short-circuit protection method based on an H-bridge cascaded system according to claim 5, characterized in that: The method further includes step S3: S3: After troubleshooting, repeat steps S1 and S2 to perform short-circuit fault detection on the main circuit H bridge.

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