Common mode start-up circuit for fully differential op-amp

Abstract

A common mode starting circuit of a fully differential operational amplifier, by connecting an additional input pair of the fourth PMOS transistor M4 and the fifth PMOS transistor M5 as a control module in parallel on the feedback input pair transistor composed of the second PMOS transistor M2 and the third PMOS transistor M3, the gate of M4 and M5 is connected with the common mode related to the fully differential operational amplifier output to generate a control voltage vc amplifier module, which can help the fully differential operational amplifier to get rid of the degenerate point, and make the circuit stable in the desired normal working state.

Description

Technical Field

[0001] This invention relates to a technique for overcoming the degeneracy point of a fully differential operational amplifier, particularly a common-mode startup circuit for a fully differential operational amplifier. By connecting an additional input pair consisting of PMOS transistors M4 and M5 as a control module in parallel with the feedback input pair consisting of PMOS transistors M2 and M3, and with the gates of M4 and M5 both connected to an amplifier module that generates a control voltage vc related to the common-mode output of the fully differential operational amplifier, the fully differential operational amplifier can overcome its degeneracy point and stabilize the circuit in the desired normal operating state. Background Technology

[0002] In implementation, fully differential op-amps exhibit a degeneracy point, meaning the circuit can remain stably in an undesirable operating state indefinitely. When an initial common-mode anomaly at the op-amp's output causes the feedback input pair to operate in the cutoff or subthreshold region, resulting in extremely low tail currents, the fully differential op-amp will stabilize in an undesirable operating state, leading to a significant deviation between circuit performance and design specifications. For information on the circuit structures of existing fully differential op-amps, please refer to [reference needed]. Figure 1 The left side of the dashed line in the diagram does not consider the dashed box portion (this part is the control module in the common-mode startup circuit of this invention). Here, inp / inn are the differential input signals, vfbp / vfbn are the differential output signals, and vcmo is the reference output common-mode voltage. M0 and M1 are the differential input pair, and M2 and M3 are the feedback input pair. When the circuit is working, IS0 + IS1 + 2ID1 = 2IS3 (typically, IS0 and IS1 are designed to be much larger than ID1 during normal operation). During circuit power-up, vfbn and vfbp are floating points, and their initial values ​​may be arbitrary. There is a possibility that the initial voltages of vfbn and vfbp are very high, causing the feedback input pair M2 and M3 to be cut off or in the subthreshold region, Mbp1 to be in the linear region, and IS1 to be very low. In this type of common-mode feedback loop, the adjustable ID1 is usually limited. To still satisfy IS0 + IS1 + 2ID1 = 2IS3, the drive voltages of class AB (MP6, MN6, MP7, and MN7) will eventually be reduced to lower IS3. The low drive voltage of class AB will keep vfbn and vfbp in a high-voltage state, ultimately keeping the entire circuit in this state indefinitely. This paper proposes a common-mode startup circuit for fully differential op-amps, which can help fully differential op-amps overcome the aforementioned degeneracy point. Summary of the Invention

[0003] This invention addresses the deficiencies or shortcomings of existing technologies by providing a common-mode startup circuit for a fully differential operational amplifier. It involves connecting an additional input pair of PMOS transistors M4 and M5 (consisting of a control module) in parallel with the feedback input pair (composed of PMOS transistors M2 and M3). The gates of M4 and M5 are both connected to an amplifier module that generates a control voltage (vc) related to the common-mode output of the fully differential operational amplifier. This helps the fully differential operational amplifier overcome its degeneracy point, stabilizing the circuit in the desired normal operating state and effectively preventing the circuit from remaining indefinitely in an undesirable operating state.

[0004] The technical solution of the present invention is as follows:

[0005] A common-mode startup circuit for a fully differential operational amplifier is characterized by including an additional input pair consisting of a fourth PMOS transistor M4 and a fifth PMOS transistor M5 connected in parallel as a control module to a feedback input pair consisting of a second PMOS transistor M2 and a third PMOS transistor M3. The gates of M4 and M5 are both connected to an amplifier module that generates a control voltage vc related to the common-mode output of the fully differential operational amplifier.

[0006] The control voltage VC amplifier module includes an amplifier input pair consisting of PMOS transistor M7 (7th) and PMOS transistor M8 (8th). The gate of M7 is connected to the common-mode output terminal (vfbp+vfbn) / 2, and the gate of M8 is connected to the reference common-mode output voltage terminal vcmo. The sources of both M7 and M8 are connected to the drain of PMOS transistor M6 (6th). The source of M6 is connected to the power supply voltage terminal, and the gate of M6 is connected to the first positive bias terminal vbp1. The drain of M7... The source of M8 is grounded. The drain of M8 is connected to the drain and gate of the 9th NMOS transistor M9. The source of M9 is grounded. The gate of M9 is connected to the gate of the 10th NMOS transistor M10. The source of M10 is grounded. The drain of M10, the drain of the 11th PMOS transistor M11, and the drain and gate of the 12th PMOS transistor M12 are interconnected to form the control voltage terminal vc. The sources of M11 and M12 are both connected to the power supply voltage terminal. The gate of M11 is connected to the first positive bias terminal vbp1.

[0007] The sources of transistors M2, M3, M4, and M5 are all connected to the drain of the second bias PMOS transistor Mbp1. The source of Mbp1 is connected to the power supply voltage terminal, and the gate of Mbp1 is connected to the first positive bias terminal vbp1. The gate of M2 is connected to the positive terminal of the differential output vfbp, and the gate of M3 is connected to the negative terminal of the differential output vfbn. The gates of M4 and M5 are both connected to the control voltage terminal vc. The drains of M2 and M4 are both connected to the drain of the fourth NMOS transistor MN3. The gate of MN3 is interconnected with the gate of the third NMOS transistor MN2 and then connected to the first negative bias terminal. Terminals vbn1, MN3, and MN2 are all grounded at their sources. M3 and M5 are both drained and connected to the drain of MN2. The drain of MN2 is connected to the drain of PMOS transistor M0 (number 0). The drain of MN3 is connected to the drain of PMOS transistor M1 (number 1). The sources of M0 and M1 are both connected to the drain of the first bias PMOS transistor Mbp0. The source of Mbp0 is connected to the power supply voltage terminal. The gate of Mbp0 is connected to the first positive bias terminal vbp1. The gate of M0 is connected to the positive differential input terminal inp and the negative differential input terminal inn.

[0008] The drain of MN2 is connected to the source of the first NMOS transistor MN0, and the drain of MN3 is connected to the source of the second NMOS transistor MN1. The gates of MN0 and MN1 are interconnected and then connected to the second negative bias terminal vbn2. The drain of MN1 is interconnected with the gate of the seventh NMOS transistor MN6 and then connected to the drain of MN6 through the 12th capacitor C12. The drain of MN0 is interconnected with the gate of the eighth NMOS transistor MN7 and then connected to the drain of MN7 through the 22nd capacitor C22. The sources of both MN6 and MN7 are grounded. The drain of MN7 is interconnected with the drain of the eighth PMOS transistor MP7 to form the differential output positive terminal vfbp. The drain of MN6 is interconnected with the drain of the seventh PMOS transistor MP6 to form the differential output negative terminal vfbn. The sources of both MP6 and MP7 are connected to the power supply voltage terminal. The gate of MP6 is connected to the differential output negative terminal vfbn through the 11th capacitor C11, and the gate of MP7 is connected to the differential output positive terminal vfbp through the 21st capacitor C21.

[0009] The drain of MN0 is connected to the drain of the fifth PMOS transistor MP4 and the source of the fifth NMOS transistor MN4. The source of MP4 and the drain of MN4 are interconnected and then connected to the gate of MP7. The drain of MN1 is connected to the drain of the sixth PMOS transistor MP5 and the source of the sixth NMOS transistor MN5. The source of MP5 and the drain of MN5 are interconnected and then connected to the gate of MP6. The gates of MP4 and MN5 are both connected to the third positive bias terminal vbp3. The gates of MN4 and MP5 are interconnected and then connected to the third negative bias terminal vbn3.

[0010] The gate of MP7 is connected to the drain of the third PMOS transistor MP2. The source of MP2 is connected to the drain of the first PMOS transistor MP0. The source of MP0 is connected to the power supply voltage terminal. The gate of MP6 is connected to the drain of the fourth PMOS transistor MP3. The source of MP3 is connected to the drain of the second PMOS transistor MP1. The source of MP1 is connected to the power supply voltage terminal. The gates of MP2 and MP3 are interconnected and then connected to the second positive bias terminal vbp2. The gates of MP0 and MP1 are interconnected and then connected to the amplifier output terminal. The negative input terminal of the amplifier is connected to the output common-mode terminal (vfbp+vfbn) / 2. The positive input terminal of the amplifier is connected to the reference output common-mode voltage terminal vcmo.

[0011] The VC voltage controls the switching state of M4 and M5. M7 and M8 have a positive offset voltage VOS. When (VFBN+VFBP) / 2 is outside VOS, the VC outputs a lower voltage to turn on M4 and M5. Otherwise, it outputs a higher voltage to turn off M4 and M5.

[0012] Let IS0 be the current flowing through Mbp0, IS1 be the current flowing through Mbp1, ID1 be the current flowing through MP0 and MP1, and IS3 be the current flowing through MN2 and MN3. Then IS0 + IS1 + 2ID1 = 2IS3.

[0013] The technical effects of this invention are as follows: This invention provides a common-mode startup circuit for a fully differential operational amplifier, from... Figure 2 The simulation results show that when the output common-mode voltage is high, the addition of the common-mode startup circuit can help the op-amp get rid of the degeneracy point, stabilize the fully differential op-amp in the desired state, and not affect the normal operation of the op-amp. Attached Figure Description

[0014] Figure 1 This is a schematic diagram of a common-mode startup circuit structure for implementing the fully differential operational amplifier of this invention.

[0015] Figure 2 yes Figure 1 A schematic diagram of the simulation results of the circuit's operating state. Figure 2 The horizontal axis represents time, and the vertical axis, from bottom to top, represents voltage V (mV), V (V), and V (V). Figure 2 The first curve from bottom to top, representing a surge followed by a decline, is the “vfbp-vfbn” waveform; the second straight line is the “inp-inn” waveform; the third rising and leveling line is the “vc” waveform; the fourth straight line is the “vcmo” waveform; and the fifth falling and declining line is the “(vfbp+vfbn) / 2” waveform.

[0016] The reference numerals in the attached diagram are listed below: M0~M8 - PMOS transistors 0 to 8 (M0 and M1 form a differential input pair, M2 and M3 form a feedback input pair, M4 and M5 within the left dashed box form the control module, and the module to the right of the dividing dashed line is the control voltage VC amplifier module); M9~M10 - NMOS transistors 9 to 10; M11~M12 - PMOS transistors 11 to 12; Mbp0~Mbp1 - First bias PMOS transistors to second bias PMOS transistors; MP0~MP7 - First PMOS transistors to eighth PMOS transistors; MN0~MN7 - First NMOS transistors to eighth NMOS transistors; C11~C12 - 11th NMOS transistor... Capacitors C21 to C22 are capacitors C21 to C22; inp is the positive terminal of the differential input; inn is the negative terminal of the differential input; vfbp is the positive terminal of the differential output; vfbn is the negative terminal of the differential output; vc is the control voltage terminal; vcmo is the reference output common-mode voltage terminal; (vfbp+vfbn) / 2 is the differential output related terminal or the output common-mode terminal; vbp1 to vbp3 are the first to third positive bias terminals; vbn1 to vbn3 are the first to third negative bias terminals; CMFB is the common-mode feedback node; ISO is the first current; IS1 is the second current (the tail current of feedback input transistors M2 and M3); ID1 is the third current; IS3 is the fourth current. Detailed Implementation

[0017] The following is in conjunction with the attached diagram ( Figures 1-2 The invention will be described in the following sections and examples.

[0018] Figure 1 This is a schematic diagram of a common-mode startup circuit structure for implementing the fully differential operational amplifier of this invention. Figure 2 yes Figure 1 A schematic diagram showing the simulation results of the circuit's operating state. (Reference) Figures 1 to 2As shown, a common-mode startup circuit for a fully differential operational amplifier is characterized by including an additional input pair consisting of PMOS transistors M4 and M5 connected in parallel as a control module to the feedback input pair consisting of PMOS transistors M2 (2nd) and M3 (3rd). The gates of M4 and M5 are both connected to an amplifier module that generates a control voltage vc related to the common-mode output of the fully differential operational amplifier. The amplifier module that generates the control voltage vc includes an amplifier input pair consisting of PMOS transistors M7 (7th) and M8 (8th). The gate of M7 is connected to the output common-mode terminal (vfbp+vfbn) / 2, and the gate of M8 is connected to the reference output common-mode voltage terminal vcmo. The sources of M7 and M8 are both connected to the drain of PMOS transistor M6 (6th). The source of M6 is connected to the power supply voltage terminal, and the gate of M6 is connected to the first positive bias terminal vbp1. The drain of M7... The source of M8 is grounded. The drain of M8 is connected to the drain and gate of the 9th NMOS transistor M9. The source of M9 is grounded. The gate of M9 is connected to the gate of the 10th NMOS transistor M10. The source of M10 is grounded. The drain of M10, the drain of the 11th PMOS transistor M11, and the drain and gate of the 12th PMOS transistor M12 are interconnected to form the control voltage terminal vc. The sources of M11 and M12 are both connected to the power supply voltage terminal. The gate of M11 is connected to the first positive bias terminal vbp1.

[0019] The sources of transistors M2, M3, M4, and M5 are all connected to the drain of the second bias PMOS transistor Mbp1. The source of Mbp1 is connected to the power supply voltage terminal, and the gate of Mbp1 is connected to the first positive bias terminal vbp1. The gate of M2 is connected to the positive terminal of the differential output vfbp, and the gate of M3 is connected to the negative terminal of the differential output vfbn. The gates of M4 and M5 are both connected to the control voltage terminal vc. The drains of M2 and M4 are both connected to the drain of the fourth NMOS transistor MN3. The gate of MN3 is interconnected with the gate of the third NMOS transistor MN2 and then connected to the first negative bias terminal. Terminals vbn1, MN3, and MN2 are all grounded at their sources. M3 and M5 are both drained and connected to the drain of MN2. The drain of MN2 is connected to the drain of PMOS transistor M0 (number 0). The drain of MN3 is connected to the drain of PMOS transistor M1 (number 1). The sources of M0 and M1 are both connected to the drain of the first bias PMOS transistor Mbp0. The source of Mbp0 is connected to the power supply voltage terminal. The gate of Mbp0 is connected to the first positive bias terminal vbp1. The gate of M0 is connected to the positive differential input terminal inp and the negative differential input terminal inn. The drain of MN2 is connected to the source of the first NMOS transistor MN0, and the drain of MN3 is connected to the source of the second NMOS transistor MN1. The gates of MN0 and MN1 are interconnected and then connected to the second negative bias terminal vbn2. The drain of MN1 is interconnected with the gate of the seventh NMOS transistor MN6 and then connected to the drain of MN6 through the 12th capacitor C12. The drain of MN0 is interconnected with the gate of the eighth NMOS transistor MN7 and then connected to the drain of MN7 through the 22nd capacitor C22. The sources of both MN6 and MN7 are grounded. The drain of MN7 is interconnected with the drain of the eighth PMOS transistor MP7 to form the differential output positive terminal vfbp. The drain of MN6 is interconnected with the drain of the seventh PMOS transistor MP6 to form the differential output negative terminal vfbn. The sources of both MP6 and MP7 are connected to the power supply voltage terminal. The gate of MP6 is connected to the differential output negative terminal vfbn through the 11th capacitor C11, and the gate of MP7 is connected to the differential output positive terminal vfbp through the 21st capacitor C21.

[0020] The drain of MN0 is connected to the drain of the fifth PMOS transistor MP4 and the source of the fifth NMOS transistor MN4. The source of MP4 and the drain of MN4 are interconnected and then connected to the gate of MP7. The drain of MN1 is connected to the drain of the sixth PMOS transistor MP5 and the source of the sixth NMOS transistor MN5. The source of MP5 and the drain of MN5 are interconnected and then connected to the gate of MP6. The gates of MP4 and MN5 are both connected to the third positive bias terminal vbp3. The gates of MN4 and MP5 are interconnected and then connected to the third negative bias terminal vbn3. The gate of MP7 is connected to the drain of the third PMOS transistor MP2. The source of MP2 is connected to the drain of the first PMOS transistor MP0. The source of MP0 is connected to the power supply voltage terminal. The gate of MP6 is connected to the drain of the fourth PMOS transistor MP3. The source of MP3 is connected to the drain of the second PMOS transistor MP1. The source of MP1 is connected to the power supply voltage terminal. The gates of MP2 and MP3 are interconnected and connected to the second positive bias terminal vbp2. The gates of MP0 and MP1 are interconnected and connected to the amplifier output terminal. The negative input terminal of the amplifier is connected to the output common-mode terminal (vfbp+vfbn) / 2. The positive input terminal of the amplifier is connected to the reference output common-mode voltage terminal vcmo. The voltage vc controls the switching state of M4 and M5. M7 and M8 have a positive offset voltage vos. When 1 / 2 (vfbn+vfbp) is higher than vcmo and above vos, vc outputs a lower voltage to turn on M4 and M5. Otherwise, it outputs a higher voltage to turn off M4 and M5. Let IS0 be the current flowing through Mbp0, IS1 be the current flowing through Mbp1, ID1 be the current flowing through MP0 and MP1, and IS3 be the current flowing through MN2 and MN3. Then IS0 + IS1 + 2ID1 = 2IS3.

[0021] Figure 1 The dashed line in the middle represents the common-mode startup circuit, an innovative feature of this invention. This circuit helps the circuit overcome the degeneracy point state, stabilizing the fully differential op-amp in the desired state. The left dashed box contains the control section, where the VC voltage controls the switching states of M4 and M5. The right dashed box contains the amplifier that generates the VC voltage; M7 and M8 are the amplifier input pair, with 1 / 2(Vfbn + Vfbp) and VcMo as inputs. Through circuit design (such as appropriate size selection, use of different threshold MOSFETs, and the use of source decoupling resistors), M7 and M8 can have a positive offset voltage VOS. When 1 / 2(Vfbn + Vfbp) is higher than VcMo and above VOS, VC outputs a lower voltage to turn on M4 and M5; otherwise, it outputs a higher voltage to turn off M4 and M5.

[0022] The specific principle is as follows: If the voltages Vfbn and Vfbp are high at startup, most of the current in M6 controlled by Vbp1 flows through the path of M8 controlled by Vcmo. After comparing the current in M11 controlled by Vbp1 with the current reflected by M10, current flows through M12, resulting in a lower VC value. This provides a lower control voltage for M4 and M5 within the left dashed box, allowing Mbp1 to operate in the saturation region. IS1 is at its normal value, and the common-mode negative feedback loop and the overall feedback loop of the op-amp take effect. The entire op-amp gradually establishes a steady state: Vcmo ≈ 1 / 2(Vfbn + Vfbp), inp - inn = Vfbp - Vfbn. As 1 / 2(Vfbn + Vfbp) gradually approaches Vcmo, the current in Mbp2 controlled by Vbp1 within the right dashed box gradually flows through the M7 branch, M10 experiences no current, and VC gradually establishes itself at the power supply voltage value. M4 and M5 within the left dashed box are turned off, without affecting the op-amp's operating state.

[0023] from Figure 2 Simulation results show that when the output common-mode voltage is high, the addition of the common-mode startup circuit can help the op-amp get rid of the degeneracy point and eventually completely shut down VC without affecting the normal operation of the op-amp.

[0024] It should be noted that the above embodiments only describe the circuit of a fully differential op-amp with a PMOS pair as input. For conventional fully differential op-amps, an NMOS pair can also be used as the input. Based on similar principles, those skilled in the art can also configure a control module and a control voltage generating amplifier for a fully differential op-amp with an NMOS pair as input to help it overcome an initial low common-mode voltage and stabilize in an undesirable state.

[0025] Contents not described in detail in this specification are prior art known to those skilled in the art. It is hereby indicated that the above description is intended to help those skilled in the art understand this invention, but does not limit the scope of protection of this invention. Any equivalent substitutions, modifications, improvements, and / or simplifications of the above descriptions that do not depart from the essential content of this invention fall within the scope of protection of this invention.

Claims

1. A common-mode startup circuit for a fully differential operational amplifier, characterized in that, Includes an additional input pair consisting of PMOS transistors M4 and M5 connected in parallel with the feedback input pair consisting of PMOS transistor M2 and PMOS transistor M3 as a control module. The gates of M4 and M5 are both connected to the amplifier module that generates the control voltage vc related to the common mode output of the fully differential op-amp. The amplifier module that generates the control voltage VC includes an amplifier input pair consisting of PMOS transistor M7 (7th) and PMOS transistor M8 (8th). The gate of M7 is connected to the output common-mode terminal (VFBP+). vfbn) / 2, the gate of M8 is connected to the reference output common-mode voltage terminal vcmo, the sources of M7 and M8 are both connected to the drain of the 6th PMOS transistor M6, the source of M6 is connected to the power supply voltage terminal, the gate of M6 is connected to the first positive bias terminal vbp1, the drain of M7 is grounded, the drain of M8 is connected to the drain and gate of the 9th NMOS transistor M9 respectively, the source of M9 is grounded, the gate of M9 is connected to the gate of the 10th NMOS transistor M10, the source of M10 is grounded, the drain of M10, the drain of the 11th PMOS transistor M11, the drain and gate of the 12th PMOS transistor M12 are interconnected to form the control voltage terminal vc, the sources of M11 and M12 are both connected to the power supply voltage terminal, and the gate of M11 is connected to the first positive bias terminal vbp1.

2. A common-mode startup circuit for a fully differential operational amplifier according to claim 1, characterized in that, The sources of transistors M2, M3, M4, and M5 are all connected to the drain of the second bias PMOS transistor Mbp1. The source of Mbp1 is connected to the power supply voltage terminal, and the gate of Mbp1 is connected to the first positive bias terminal vbp1. The gate of M2 is connected to the positive terminal of the differential output vfbp, and the gate of M3 is connected to the negative terminal of the differential output vfbn. The gates of M4 and M5 are both connected to the control voltage terminal vc. The drains of M2 and M4 are both connected to the drain of the fourth NMOS transistor MN3. The gate of MN3 is interconnected with the gate of the third NMOS transistor MN2 and then connected to the first negative bias terminal. Terminals vbn1, MN3, and MN2 are all grounded at their sources. M3 and M5 are both drained and connected to the drain of MN2. The drain of MN2 is connected to the drain of PMOS transistor M0 (number 0). The drain of MN3 is connected to the drain of PMOS transistor M1 (number 1). The sources of M0 and M1 are both connected to the drain of the first bias PMOS transistor Mbp0. The source of Mbp0 is connected to the power supply voltage terminal. The gate of Mbp0 is connected to the first positive bias terminal vbp1. The gate of M0 is connected to the positive differential input terminal inp. The gate of M1 is connected to the negative differential input terminal inn.

3. A common-mode startup circuit for a fully differential operational amplifier according to claim 2, characterized in that, The drain of MN2 is connected to the source of the first NMOS transistor MN0, and the drain of MN3 is connected to the source of the second NMOS transistor MN1. The gates of MN0 and MN1 are interconnected and then connected to the second negative bias terminal vbn2. The drain of MN1 is interconnected with the gate of the seventh NMOS transistor MN6 and then connected to the drain of MN6 through the 12th capacitor C12. The drain of MN0 is interconnected with the gate of the eighth NMOS transistor MN7 and then connected to the drain of MN7 through the 22nd capacitor C22. The sources of both MN6 and MN7 are grounded. The drain of MN7 is interconnected with the drain of the eighth PMOS transistor MP7 to form the differential output positive terminal vfbp. The drain of MN6 is interconnected with the drain of the seventh PMOS transistor MP6 to form the differential output negative terminal vfbn. The sources of both MP6 and MP7 are connected to the power supply voltage terminal. The gate of MP6 is connected to the differential output negative terminal vfbn through the 11th capacitor C11, and the gate of MP7 is connected to the differential output positive terminal vfbp through the 21st capacitor C21.

4. A common-mode startup circuit for a fully differential operational amplifier according to claim 3, characterized in that, The drain of MN0 is connected to the drain of the fifth PMOS transistor MP4 and the source of the fifth NMOS transistor MN4. The source of MP4 and the drain of MN4 are interconnected and then connected to the gate of MP7. The drain of MN1 is connected to the drain of the sixth PMOS transistor MP5 and the source of the sixth NMOS transistor MN5. The source of MP5 and the drain of MN5 are interconnected and then connected to the gate of MP6. The gates of MP4 and MN5 are both connected to the third positive bias terminal vbp3. The gates of MN4 and MP5 are interconnected and then connected to the third negative bias terminal vbn3.

5. A common-mode startup circuit for a fully differential operational amplifier according to claim 4, characterized in that, The gate of MP7 is connected to the drain of the third PMOS transistor MP2. The source of MP2 is connected to the drain of the first PMOS transistor MP0. The source of MP0 is connected to the power supply voltage terminal. The gate of MP6 is connected to the drain of the fourth PMOS transistor MP3. The source of MP3 is connected to the drain of the second PMOS transistor MP1. The source of MP1 is connected to the power supply voltage terminal. The gates of MP2 and MP3 are interconnected and then connected to the second positive bias terminal vbp2. The gates of MP0 and MP1 are interconnected and then connected to the amplifier output terminal. The negative input terminal of the amplifier is connected to the output common-mode terminal (vfbp + vfbn) / 2. The positive input terminal of the amplifier is connected to the reference output common-mode voltage terminal vcmo.

6. A common-mode startup circuit for a fully differential operational amplifier according to claim 5, characterized in that, The VC voltage controls the switching state of M4 and M5. M7 and M8 have a positive offset voltage VOS. When (VFBN+VFBP) / 2 is higher than VCMO above VOS, VC outputs a lower voltage to turn on M4 and M5. Otherwise, it outputs a higher voltage to turn off M4 and M5.

7. A common-mode startup circuit for a fully differential operational amplifier according to claim 6, characterized in that, wherein... The current flowing through Mbp0 is IS0, the current flowing through Mbp1 is IS1, the current flowing through MP0 and MP1 is ID1, and the current flowing through MN2 and MN3 is IS3. .

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