A sensor and signal processing circuit therefor

Abstract

The application discloses a signal processing circuit, which is applied to the technical field of circuits and comprises a detector, the detector being a charge amplifier and being used for converting an input charge signal into a voltage signal and amplifying the output, or the detector being a capacitance voltage converter and being used for performing capacitance voltage conversion to output a voltage signal for reflecting a current capacitance value of a capacitance sensitive part connected with the detector, and a charge multiplication circuit connected with the detector and used for increasing a gain coefficient of the detector by feeding back an output of the detector to an input of the detector. The scheme of the application can effectively improve the gain of the charge amplifier and the capacitance voltage converter, and guarantee the low-frequency response performance and the anti-interference capability of the circuit. The application further provides a sensor with the corresponding technical effects.

Description

Technical Field

[0001] This invention relates to the field of circuit technology, and in particular to a sensor and its signal processing circuit. Background Technology

[0002] Current single-ended charge amplifiers or single-ended capacitor voltage converters typically include an operational amplifier, a feedback capacitor, and a feedback resistor, forming a parallel voltage-amplifying integrator circuit. The charge amplifier can achieve charge / voltage conversion, while the capacitor voltage converter can achieve capacitance / voltage conversion. In contrast, current differential charge amplifiers or differential capacitor voltage converters consist of two corresponding symmetrical single-ended circuits.

[0003] Currently, most charge amplifiers or capacitor-to-voltage converters improve their gain by reducing the feedback capacitor. However, reducing the feedback capacitor increases the low-frequency cutoff frequency of the charge amplifier or capacitor-to-voltage converter, resulting in a poorer low-frequency response. Furthermore, a small capacitor makes the circuit more susceptible to interference, thus reducing its anti-interference capability.

[0004] In summary, how to effectively improve the gain of charge amplifiers and capacitor-to-voltage converters while ensuring the low-frequency response performance and anti-interference capability of the circuit is a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0005] The purpose of this invention is to provide a sensor and its signal processing circuit to effectively improve the gain of the charge amplifier and capacitor voltage converter, while ensuring the low-frequency response performance and anti-interference capability of the circuit.

[0006] To solve the above-mentioned technical problems, the present invention provides the following technical solution:

[0007] A signal processing circuit, comprising:

[0008] The detector is a charge amplifier used to convert an input charge signal into a voltage signal and amplify the output; or the detector is a capacitor-to-voltage converter used to perform capacitor-to-voltage conversion to output a voltage signal that reflects the current capacitance value of the capacitor-sensitive part connected to the detector.

[0009] A charge multiplier circuit connected to the detector for increasing the gain coefficient of the detector by feeding back the output of the detector to the input of the detector.

[0010] Preferably, the charge multiplication circuit is specifically used for:

[0011] A multiplied current signal proportional to the output current signal of the detector is fed back to the input terminal of the detector to increase the gain coefficient of the detector by increasing the input current or input charge of the detector.

[0012] Preferably, the detector is a single-ended charge amplifier, and the charge multiplication circuit specifically includes: a first resistor, a second resistor, a first capacitor, and a first operational amplifier;

[0013] The first end of the first resistor serves as the input terminal of the charge multiplier circuit and is connected to the output terminal of the single-ended charge amplifier. The second end of the first resistor is connected to the first end of the second resistor and the negative input terminal of the first operational amplifier. The positive input terminal of the first operational amplifier is connected to the reference voltage terminal. The output terminal of the first operational amplifier is connected to the second end of the second resistor and the second end of the first capacitor. The first end of the first capacitor serves as the output terminal of the charge multiplier circuit and is connected to the input terminal of the single-ended charge amplifier.

[0014] Preferably, the single-ended charge amplifier includes: a second operational amplifier, a second capacitor, and a third resistor;

[0015] The negative input terminal of the second operational amplifier is connected to the first terminal of the second capacitor and the first terminal of the third resistor, respectively, and the connection terminal serves as the input terminal of the single-ended charge amplifier. The positive input terminal of the second operational amplifier is connected to the reference voltage terminal. The output terminal of the second operational amplifier is connected to the second terminal of the second capacitor and the second terminal of the third resistor, respectively, and the connection terminal serves as the output terminal of the single-ended charge amplifier.

[0016] Preferably, the detector is a differential charge amplifier, which includes a positive charge amplifier and a negative charge amplifier, and the charge multiplication circuit specifically includes a third capacitor and a fourth capacitor;

[0017] The first terminal of the third capacitor is connected to the output terminal of the positive charge amplifier, the second terminal of the third capacitor is connected to the input terminal of the negative charge amplifier, the first terminal of the fourth capacitor is connected to the input terminal of the positive charge amplifier, and the second terminal of the fourth capacitor is connected to the output terminal of the negative charge amplifier.

[0018] Preferably, the positive charge amplifier includes: a third operational amplifier, a fifth capacitor, and a fourth resistor; the negative charge amplifier includes: a fourth operational amplifier, a sixth capacitor, and a fifth resistor;

[0019] The positive input terminal of the third operational amplifier is connected to the reference voltage terminal, the negative input terminal of the third operational amplifier is connected to the first terminal of the fifth capacitor and the first terminal of the fourth resistor respectively, and the connection terminal serves as the input terminal of the positive charge amplifier. The output terminal of the third operational amplifier is connected to the second terminal of the fifth capacitor and the second terminal of the fourth resistor respectively, and the connection terminal serves as the output terminal of the positive charge amplifier.

[0020] The positive input terminal of the fourth operational amplifier is connected to the reference voltage terminal, the negative input terminal of the fourth operational amplifier is connected to the first terminal of the sixth capacitor and the first terminal of the fifth resistor respectively, and the connection terminal serves as the input terminal of the negative charge amplifier. The output terminal of the fourth operational amplifier is connected to the second terminal of the sixth capacitor and the second terminal of the fifth resistor respectively, and the connection terminal serves as the output terminal of the negative charge amplifier.

[0021] Preferably, the detector is a single-ended capacitor voltage converter, and the charge multiplication circuit specifically includes: a sixth resistor, a seventh resistor, a seventh capacitor, and a fifth operational amplifier;

[0022] The first end of the sixth resistor serves as the input terminal of the charge multiplier circuit and is connected to the output terminal of the single-ended capacitor voltage converter. The second end of the sixth resistor is connected to the first end of the seventh resistor and the negative input terminal of the fifth operational amplifier. The positive input terminal of the fifth operational amplifier is connected to the reference voltage terminal. The output terminal of the fifth operational amplifier is connected to the second end of the seventh resistor and the second end of the seventh capacitor. The first end of the seventh capacitor serves as the output terminal of the charge multiplier circuit and is connected to the input terminal of the single-ended capacitor voltage converter.

[0023] Preferably, the single-ended capacitor voltage converter includes: a sixth operational amplifier, an eighth capacitor, and an eighth resistor;

[0024] The negative input terminal of the sixth operational amplifier is connected to the first terminal of the eighth capacitor and the first terminal of the eighth resistor, and the connection terminal serves as the input terminal of the single-ended capacitor voltage converter. The positive input terminal of the sixth operational amplifier is connected to the reference voltage terminal. The output terminal of the sixth operational amplifier is connected to the second terminal of the eighth capacitor and the second terminal of the eighth resistor, and the connection terminal serves as the output terminal of the single-ended capacitor voltage converter.

[0025] Preferably, the detector is a differential capacitor voltage converter, which includes a positive capacitor voltage converter and a negative capacitor voltage converter, and the charge multiplication circuit specifically includes a ninth capacitor and a tenth capacitor;

[0026] The first terminal of the ninth capacitor is connected to the output terminal of the positive capacitor voltage converter, the second terminal of the ninth capacitor is connected to the input terminal of the negative capacitor voltage converter, the first terminal of the tenth capacitor is connected to the input terminal of the positive capacitor voltage converter, and the second terminal of the tenth capacitor is connected to the output terminal of the negative capacitor voltage converter.

[0027] Preferably, the positive capacitor voltage converter includes: a seventh operational amplifier, an eleventh capacitor, and a ninth resistor; the negative capacitor voltage converter includes: an eighth operational amplifier, a twelfth capacitor, and a tenth resistor;

[0028] The positive input terminal of the seventh operational amplifier is connected to the first DC voltage terminal, the negative input terminal of the seventh operational amplifier is connected to the first terminal of the eleventh capacitor and the first terminal of the ninth resistor respectively, and the connection terminal serves as the input terminal of the positive capacitor voltage converter. The output terminal of the seventh operational amplifier is connected to the second terminal of the eleventh capacitor and the second terminal of the ninth resistor respectively, and the connection terminal serves as the output terminal of the positive capacitor voltage converter.

[0029] The positive input terminal of the eighth operational amplifier is connected to the second DC voltage terminal, the negative input terminal of the eighth operational amplifier is connected to the first terminal of the twelfth capacitor and the first terminal of the tenth resistor respectively, and the connection terminal serves as the input terminal of the negative capacitor voltage converter. The output terminal of the eighth operational amplifier is connected to the second terminal of the twelfth capacitor and the second terminal of the tenth resistor respectively, and the connection terminal serves as the output terminal of the negative capacitor voltage converter.

[0030] The voltage at the first DC terminal has the same amplitude as the voltage at the second DC terminal, but opposite polarities.

[0031] A sensor comprising the signal processing circuitry described in any of the preceding claims.

[0032] The detector provided by the embodiments of this invention can be a charge amplifier or a capacitor-to-voltage converter. The charge amplifier converts the input charge signal into a voltage signal and amplifies the output. The capacitor-to-voltage converter performs capacitor-to-voltage conversion to output a voltage signal reflecting the current capacitance value of the capacitor-sensitive part connected to the detector. This application includes a charge multiplier circuit, which feeds the detector's output back to the input and increases the detector's gain coefficient. Since the feedback capacitor is not reduced as in conventional solutions, the low-frequency response performance and anti-interference capability of the circuit are not compromised. In summary, the solution of this application can effectively improve the gain of the charge amplifier and capacitor-to-voltage converter while ensuring the low-frequency response performance and anti-interference capability of the circuit. Attached Figure Description

[0033] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0034] Figure 1a This is a schematic diagram of the structure of a signal processing circuit according to the present invention;

[0035] Figure 1b This is a block diagram illustrating the principle of a charge multiplication circuit according to a specific embodiment of the present invention.

[0036] Figure 2 This is a schematic diagram of a single-ended charge amplifier and a charge multiplier circuit according to a specific embodiment of the present invention.

[0037] Figure 3a This is a simulation circuit diagram for a specific scenario where the detector is a single-ended charge amplifier.

[0038] Figure 3b This is a simulation waveform diagram of a single-ended charge amplifier detector in a specific scenario where no charge multiplier circuit is connected.

[0039] Figure 3c This is a simulation waveform diagram of a single-ended charge amplifier detector in a specific scenario where a charge multiplier circuit is connected.

[0040] Figure 4 This is a schematic diagram of the differential charge amplifier and charge multiplier circuit according to a specific embodiment of the present invention;

[0041] Figure 5a This is a schematic diagram of a simulation circuit when the detector is a differential charge amplifier in a specific scenario.

[0042] Figure 5b This is a simulation waveform and frequency response diagram of a differential charge amplifier detector in a specific scenario where no charge multiplier circuit is connected.

[0043] Figure 5c This is a simulation waveform and frequency response diagram of a differential charge amplifier detector in a specific scenario after a charge multiplier circuit is connected.

[0044] Figure 6 This is a schematic diagram of a single-ended capacitor voltage converter and a charge multiplier circuit according to a specific embodiment of the present invention.

[0045] Figure 7This is a schematic diagram of a differential capacitor voltage converter and a charge multiplier circuit according to a specific embodiment of the present invention. Detailed Implementation

[0046] The core of this invention is to provide a signal processing circuit that can effectively improve the gain of the charge amplifier and capacitor voltage converter, while ensuring the low-frequency response performance and anti-interference capability of the circuit.

[0047] To enable those skilled in the art to better understand the present invention, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. Obviously, the described embodiments are merely some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0048] Please refer to Figure 1a , Figure 1a This is a schematic diagram of a signal processing circuit according to the present invention. The signal processing circuit may include:

[0049] Detector 10; Detector 10 is a charge amplifier used to convert the input charge signal into a voltage signal and amplify the output; or detector 10 is a capacitor voltage converter used to perform capacitor voltage conversion to output a voltage signal that reflects the current capacitance value of the capacitor sensing part connected to detector 10.

[0050] A charge multiplier circuit 20 connected to detector 10 is used to increase the gain coefficient of detector 10 by feeding back the output of detector 10 to the input of detector 10.

[0051] Specifically, the detector 10 in this application can be a charge amplifier or a capacitor-to-voltage converter. When selecting a charge amplifier, it can be a single-ended charge amplifier or a differential charge amplifier. Similarly, when selecting a capacitor-to-voltage converter, it can be a single-ended capacitor-to-voltage converter or a differential capacitor-to-voltage converter.

[0052] A charge amplifier can convert an input charge signal into a voltage signal and amplify the output. When the detector 10 is a single-ended charge amplifier, the specific structure of the single-ended charge amplifier can be selected according to the actual situation. For example, in one specific embodiment of the present invention, see [reference needed]. Figure 2 A single-ended charge amplifier may include: a second operational amplifier OP2, a second capacitor C2, and a third resistor R3;

[0053] The negative input terminal of the second operational amplifier OP2 is connected to the first terminal of the second capacitor C2 and the first terminal of the third resistor R3, and the connection terminal serves as the input terminal of the single-ended charge amplifier. The positive input terminal of the second operational amplifier OP2 is connected to the reference voltage terminal Vref. The output terminal of the second operational amplifier OP2 is connected to the second terminal of the second capacitor C2 and the second terminal of the third resistor R3, and the connection terminal serves as the output terminal of the single-ended charge amplifier.

[0054] The single-ended charge amplifier in this embodiment has a relatively simple structure and high reliability. The negative input terminal of the second operational amplifier OP2 is the input terminal of the single-ended charge amplifier, used to connect to the pre-amplifier circuit. The specific structure of this pre-amplifier circuit can vary; for example, it can be a piezoelectric sensor. The output terminal of the second operational amplifier OP2 is the output terminal of the single-ended charge amplifier. Figure 2 The middle part is marked as U01.

[0055] The charge multiplier circuit 20 of this application is connected to the detector 10, which can feed back the output of the detector 10 to the input and increase the gain coefficient of the detector 10. The specific circuit structure of the charge multiplier circuit 20 can be set and adjusted as needed.

[0056] In one specific embodiment of the present invention, the charge multiplication circuit 20 can be specifically used for:

[0057] A multiplied current signal proportional to the output current signal of the detector 10 is fed back to the input terminal of the detector 10, so as to increase the gain coefficient of the detector 10 by increasing the input current or input charge of the detector 10.

[0058] This implementation takes into account that the charge multiplier circuit 20 can receive the output current signal of the detector 10, and then amplify the output current signal of the detector 10 proportionally to obtain a multiplied current signal, which is then fed back to the input terminal of the detector 10 to effectively improve the gain of the detector 10. For example Figure 1b This is a block diagram illustrating the principle of a charge multiplication circuit according to a specific embodiment of the present invention. Figure 1b In this embodiment, detector 10 is specifically a capacitor voltage converter for capacitor voltage conversion. The charge multiplication circuit 20 specifically includes a current amplification stage and a current feedback stage. Through current amplification and current feedback, a multiplied current signal proportional to the input current signal is fed back to the input terminal of the capacitor voltage converter, thereby increasing the input charge of the capacitor voltage converter and thus improving the voltage gain of the capacitor voltage converter.

[0059] The specific circuit structure of the charge multiplier circuit 20 can be set and adjusted as needed. For example, in one specific embodiment of the present invention, when the detector 10 is a single-ended charge amplifier, see [reference needed]. Figure 2 The charge multiplier circuit 20 may specifically include: a first resistor R1, a second resistor R2, a first capacitor C1, and a first operational amplifier OP1;

[0060] The first end of the first resistor R1 serves as the input terminal of the charge multiplier circuit 20 and is connected to the output terminal of the single-ended charge amplifier. The second end of the first resistor R1 is connected to the first end of the second resistor R2 and the negative input terminal of the first operational amplifier OP1. The positive input terminal of the first operational amplifier OP1 is connected to the reference voltage terminal. The output terminal of the first operational amplifier OP1 is connected to the second end of the second resistor R2 and the second end of the first capacitor C1. The first end of the first capacitor C1 serves as the output terminal of the charge multiplier circuit 20 and is connected to the input terminal of the single-ended charge amplifier.

[0061] It should be noted that in some traditional charge amplifiers or capacitor-to-voltage converters, the gain of the charge amplifier or capacitor-to-voltage converter may be increased by adding an amplifier circuit in the subsequent stage. However, this method of adding a subsequent amplifier circuit requires more electronic components, reduces the reliability of the circuit, and also increases the cost.

[0062] In this embodiment of the present application, when the detector 10 is a single-ended charge amplifier, the charge multiplication circuit 20 includes two resistors, one capacitor and one operational amplifier, which has a very simple structure and high reliability.

[0063] Specifically, Figure 2 In this implementation, a charge multiplier circuit 20 is added between the output and input of the single-ended charge amplifier to amplify the current. The multiplier capacitor is fed back to the input terminal, that is, through the first capacitor C1, to the input terminal of the single-ended charge amplifier, thereby improving the circuit gain.

[0064] for Figure 2 In this implementation, if the charge multiplier circuit 20 is not provided, the gain A of the single-ended charge amplifier can be expressed as: A = Ci / C2. Here, Ci represents the input capacitance of the single-ended charge amplifier. Figure 2 Not shown in the image.

[0065] After setting up the charge multiplier circuit 20, the amplification factor AC = 1*(R2 / R1), and the feedback factor F1 = AC*C1 / C2. The multiplication amplification gain B1 = 1 / (1-F1). After adding the charge multiplier circuit 20, the overall transfer function H = Ci / C2*1 / (1-F1).

[0066] For example, if R1 = 30kΩ, R2 = 20kΩ, C1 = 2.7nF, and C2 = 2.2nF, then the amplification factor AC = 1*(R2 / R1) = 0.6, the feedback factor F1 = AC*C1 / C2 = 0.2, and the multiplication gain B1 = 1 / (1-F1) = 12.5. That is, after setting the charge multiplier circuit 20, the gain of the circuit after multiplication is increased by 12.5 times compared with the circuit without multiplication.

[0067] See also Figure 3a , Figure 3b as well as Figure 3c , Figure 3a This is a simulation circuit diagram of a detector 10 as a single-ended charge amplifier in a specific scenario. Figure 3b This is a simulation waveform diagram of detector 10 as a single-ended charge amplifier when the charge multiplier circuit 20 is not connected. Figure 3c The detector 10 is a simulation waveform diagram of a single-ended charge amplifier after the charge multiplier circuit 20 is connected.

[0068] It needs to be emphasized that, Figure 3a In the circuit, a switch S31 is set between the first capacitor C1 and the second operational amplifier OP2. By controlling the on / off state of this switch, it can be determined whether the charge multiplication circuit 20 is connected.

[0069] Figure 3b and Figure 3c In the diagram, the same charge simulation input is set, and the multiplication feedback curve represents the voltage at the output terminal of the first operational amplifier OP1. It can be seen that after the charge multiplier circuit 20 is connected, the output voltage U01 of the single-ended charge amplifier increases, which means that the charge multiplier circuit 20 effectively increases the gain coefficient of the single-ended charge amplifier.

[0070] When detector 10 is a differential charge amplifier, the specific differential charge amplifier structure can be selected according to actual conditions. For example, in one specific embodiment of the present invention, see [reference needed]. Figure 4 The differential charge amplifier may include a positive charge amplifier and a negative charge amplifier. The positive charge amplifier includes: a third operational amplifier OP3, a fifth capacitor C5, and a fourth resistor R4; the negative charge amplifier includes: a fourth operational amplifier OP4, a sixth capacitor C6, and a fifth resistor R5.

[0071] The positive input terminal of the third operational amplifier OP3 is connected to the reference voltage terminal. The negative input terminal of the third operational amplifier OP3 is connected to the first terminal of the fifth capacitor C5 and the first terminal of the fourth resistor R4, and the connection terminal serves as the input terminal of the positive charge amplifier. The output terminal of the third operational amplifier OP3 is connected to the second terminal of the fifth capacitor C5 and the second terminal of the fourth resistor R4, and the connection terminal serves as the output terminal of the positive charge amplifier.

[0072] The positive input terminal of the fourth operational amplifier OP4 is connected to the reference voltage terminal. The negative input terminal of the fourth operational amplifier OP4 is connected to the first terminal of the sixth capacitor C6 and the first terminal of the fifth resistor R5, and the connection terminal serves as the input terminal of the negative charge amplifier. The output terminal of the fourth operational amplifier OP4 is connected to the second terminal of the sixth capacitor C6 and the second terminal of the fifth resistor R5, and the connection terminal serves as the output terminal of the negative charge amplifier.

[0073] Differential voltage output can be achieved through positive and negative charge amplifiers, and then the differential voltages can be summed through a subsequent differential superposition circuit. Of course... Figure 4 The differential superposition circuit of the subsequent stage is not shown. The input terminal of the positive charge amplifier is marked as U01, and the input terminal of the negative charge amplifier is marked as U02. Figure 4 The implementation method is a commonly used differential charge amplifier structure, which is easy to implement. Of course, in other implementation methods, other types of differential charge amplifiers can be provided according to actual needs.

[0074] When detector 10 is a differential charge amplifier, charge multiplication circuit 20 may specifically include: third capacitor C3 and fourth capacitor C4;

[0075] The first terminal of the third capacitor C3 is connected to the output terminal of the positive charge amplifier, and the second terminal of the third capacitor C3 is connected to the input terminal of the negative charge amplifier. The first terminal of the fourth capacitor C4 is connected to the input terminal of the positive charge amplifier, and the second terminal of the fourth capacitor C4 is connected to the output terminal of the negative charge amplifier.

[0076] It should be noted that in some traditional charge amplifiers or capacitor-to-voltage converters, the gain of the charge amplifier or capacitor-to-voltage converter may be increased by adding an amplifier circuit in the subsequent stage. However, this method of adding a subsequent amplifier circuit requires more electronic components, reduces the reliability of the circuit, and also increases the cost.

[0077] In this embodiment of the present application, when the detector 10 is a differential charge amplifier, the charge multiplier circuit 20 includes two capacitors. The structure is very simple and the reliability is very high. Compared with the traditional method of adding an amplifier circuit in the later stage, it can greatly reduce the cost and the number of electronic components required.

[0078] In practical applications, the values ​​of the third capacitor C3 and the fourth capacitor C4 are usually set to be the same. Similarly, in the implementation methods described below, the values ​​of the ninth capacitor C9 and the tenth capacitor C10 are usually set to be the same.

[0079] for Figure 4In the implementation of the method, the gain BZ can be expressed as: BZ=20log[Cf / (Cf-CB)], where Cf=C5=C6, CB=C3=C4;

[0080] BZ = 20log[Cf / (Cf-CB)], where Cf = Cf1 = Cf2, CB = CB1 = CB2;

[0081] Taking the derivation of the gain function of a single-sided charge amplifier as an example, for instance, the derivation is performed using the gain function of a positive charge amplifier:

[0082] U01 = (Qi + Qf) / C5, where Qi is the input parameter and Qf is the feedback parameter.

[0083] Since the feedback parameter Qf = U01 * C3, therefore, U01 = (Qi + U01 * C3) / C5.

[0084] achievable

[0085] If C3 = 0, then U01 = Qi / C5, and Qi / C5 is represented by Uo. + It can be seen that Uo + This indicates the gain of the single-sided charge amplifier when the charge multiplier circuit 20 is not set.

[0086] The multiplication factor G1 can be expressed as

[0087] If the multiplication factor G1 is required to be 10, then 1 - C3 / C5 = Uo + / U01=1 / G1.

[0088] Therefore, C3 / C5 = 0.9.

[0089] For example, in a specific context, Cf = C5 = C6 = 1000p, CB = C3 = C4 = 10p.

[0090] The multiplication factor G = Cf / (Cf-CB) = 100. Converting this to logarithm gives 40 dB.

[0091] For example, in another specific case, Cf = C5 = C6 = 1000p, CB = C3 = C4 = 950p.

[0092] The multiplication factor G = Cf / (Cf-CB) = 20. Converting to logarithm, it is 26 dB.

[0093] See also Figure 5a , Figure 5b as well as Figure 5c , Figure 5aThis is a simulation circuit diagram of a specific application where detector 10 is a differential charge amplifier. Figure 5b When the charge multiplier circuit 20 is not connected, the detector 10 is a simulation waveform and frequency response diagram of the differential charge amplifier. Figure 5c After the charge multiplier circuit 20 is connected, the detector 10 is a simulation waveform and frequency response diagram of the differential charge amplifier.

[0094] It needs to be emphasized that, Figure 5a In the circuit, the on / off state of switches S51 and S52, which are connected to the third capacitor C3 and the fourth capacitor C4 respectively, determines whether to connect the charge multiplication circuit 20. Figure 5b and Figure 5c In the diagram, curves 1 and 2 represent the outputs of the positive and negative charge amplifiers, respectively, and curve 4 represents... Figure 5a The voltage at point J1 in Figure 5 is shown in Figure 5, where a common-mode negative feedback circuit consisting of four resistors is set up, with the connection terminal marked J1. Curve 0 refers to the output of the differential superposition circuit.

[0095] Depend on Figure 5b It can be seen that without the charge multiplier circuit 20, the passband output is 5.93dB. Figure 5c It can be seen that after connecting the charge multiplier circuit 20, the passband output is 24.98dB. Therefore, the multiplication contribution of the charge multiplier circuit 20, BZ = 24.98dB - 5.93dB = 19.05dB, is consistent with the calculation result of the theoretical function.

[0096] In one specific embodiment of the present invention, see [reference needed]. Figure 6 The single-ended capacitor voltage converter may include: the sixth operational amplifier OP6, the eighth capacitor C8, and the eighth resistor R8;

[0097] The negative input terminal of the sixth operational amplifier OP6 is connected to the first terminal of the eighth capacitor C8 and the first terminal of the eighth resistor R8, and the connection terminal serves as the input terminal of the single-ended capacitor voltage converter. The positive input terminal of the sixth operational amplifier OP6 is connected to the reference voltage terminal. The output terminal of the sixth operational amplifier OP6 is connected to the second terminal of the eighth capacitor C8 and the second terminal of the eighth resistor R8, and the connection terminal serves as the output terminal of the single-ended capacitor voltage converter.

[0098] It can be seen that the structure of a single-ended capacitor voltage converter can be the same as that of a single-ended charge amplifier, only the application is different, that is, the signal received from the preceding circuit is different. Figure 6 The single-ended capacitor voltage converter in the implementation method is also relatively simple in structure, highly reliable, and easy to implement.

[0099] See also Figure 6When detector 10 is a single-ended capacitor voltage converter, charge multiplication circuit 20 may specifically include: sixth resistor R6, seventh resistor R7, seventh capacitor C7 and fifth operational amplifier OP5.

[0100] The first end of the sixth resistor R6 serves as the input terminal of the charge multiplier circuit 20 and is connected to the output terminal of the single-ended capacitor voltage converter. The second end of the sixth resistor R6 is connected to the first end of the seventh resistor R7 and the negative input terminal of the fifth operational amplifier OP5. The positive input terminal of the fifth operational amplifier OP5 is connected to the reference voltage terminal. The output terminal of the fifth operational amplifier OP5 is connected to the second end of the seventh resistor R7 and the second end of the seventh capacitor C7. The first end of the seventh capacitor C7 serves as the output terminal of the charge multiplier circuit 20 and is connected to the input terminal of the single-ended capacitor voltage converter.

[0101] Similarly, for a single-ended capacitor voltage converter, the charge multiplier circuit 20 is also composed of two resistors, one capacitor, and one operational amplifier. Therefore, after setting up the charge multiplier circuit 20, the multiplication and amplification gain can be referred to the description above, and will not be repeated here.

[0102] See also Figure 7 When detector 10 is a differential capacitor voltage converter, it may include a positive capacitor voltage converter and a negative capacitor voltage converter. The positive capacitor voltage converter may include: the seventh operational amplifier OP7, the eleventh capacitor C11, and the ninth resistor R9; the negative capacitor voltage converter includes: the eighth operational amplifier OP8, the twelfth capacitor C12, and the tenth resistor R10.

[0103] The positive input terminal of the seventh operational amplifier OP7 is connected to the first DC voltage terminal. The negative input terminal of the seventh operational amplifier OP7 is connected to the first terminal of the eleventh capacitor C11 and the first terminal of the ninth resistor R9, and the connection terminal serves as the input terminal of the positive capacitor voltage converter. The output terminal of the seventh operational amplifier OP7 is connected to the second terminal of the eleventh capacitor C11 and the second terminal of the ninth resistor R9, and the connection terminal serves as the output terminal of the positive capacitor voltage converter.

[0104] The positive input terminal of the eighth operational amplifier OP8 is connected to the second DC voltage terminal. The negative input terminal of the eighth operational amplifier OP8 is connected to the first terminal of the twelfth capacitor C12 and the first terminal of the tenth resistor R10, and the connection terminal serves as the input terminal of the negative capacitor voltage converter. The output terminal of the eighth operational amplifier OP8 is connected to the second terminal of the twelfth capacitor C12 and the second terminal of the tenth resistor R10, and the connection terminal serves as the output terminal of the negative capacitor voltage converter.

[0105] The voltage at the first DC terminal has the same amplitude as the voltage at the second DC terminal, but opposite polarities.

[0106] Specifically, Figure 7In this implementation, the circuit structure of the differential capacitor voltage converter and the differential charge amplifier is largely the same. The difference is that the positive input terminal of the seventh operational amplifier OP7 is connected to the first DC voltage terminal, and the positive input terminal of the eighth operational amplifier OP8 is connected to the second DC voltage terminal. This is because... Figure 7 The differential capacitor voltage converter needs to receive DC excitation to convert the capacitor voltage and output a voltage signal reflecting the current capacitance value of the capacitor sensing element connected to detector 10. Of course, in other embodiments, the solution of this application can also be applied to differential capacitor voltage converters using AC excitation, that is, to increase the gain by using charge multiplier circuit 20.

[0107] exist Figure 7 In the implementation of the method, the detector 10 is a differential capacitor voltage converter, which includes a positive capacitor voltage converter and a negative capacitor voltage converter. The charge multiplication circuit 20 specifically includes a ninth capacitor C9 and a tenth capacitor C10.

[0108] The first terminal of the ninth capacitor C9 is connected to the output terminal of the positive capacitor voltage converter, and the second terminal of the ninth capacitor C9 is connected to the input terminal of the negative capacitor voltage converter. The first terminal of the tenth capacitor C10 is connected to the input terminal of the positive capacitor voltage converter, and the second terminal of the tenth capacitor C10 is connected to the output terminal of the negative capacitor voltage converter.

[0109] In this embodiment of the present application, when the detector 10 is a differential capacitor voltage converter, the charge multiplier circuit 20 includes two capacitors, which has a very simple structure and high reliability. Compared with the traditional method of adding an amplifier circuit in the later stage, it can greatly reduce the cost and the number of electronic components required.

[0110] Figure 7 In the implementation method, the gain function of the positive and negative capacitor voltage converter can also be expressed as BZ = 20log[Cf / (Cf-CB)], the principle of which is the same as above, and will not be repeated here.

[0111] Using the technical solution provided in this embodiment of the invention, detector 10 can be a charge amplifier or a capacitor-to-voltage converter. The charge amplifier converts the input charge signal into a voltage signal and amplifies the output. The capacitor-to-voltage converter performs capacitor-to-voltage conversion to output a voltage signal reflecting the current capacitance value of the capacitor-sensitive part connected to detector 10. This application provides a charge multiplier circuit 20, which feeds back the output of detector 10 to the input and increases the gain coefficient of detector 10. Since the feedback capacitor is not reduced as in conventional solutions, the low-frequency response performance and anti-interference capability of the circuit are not reduced. In summary, the solution of this application can effectively improve the gain of the charge amplifier and capacitor-to-voltage converter, and ensure the low-frequency response performance and anti-interference capability of the circuit.

[0112] Corresponding to the above-described embodiments of the signal processing circuit, this embodiment of the invention also provides a sensor, which may include the signal processing circuit as described in any of the above embodiments. These circuits can be referred to in correspondence with each other as described above, and will not be repeated here.

[0113] It should also be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes the element.

[0114] The various embodiments described in this specification are presented in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. Those skilled in the art will further recognize that the units and algorithm steps of the examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of each example have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.

[0115] This article uses specific examples to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the technical solutions and core ideas of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made to the present invention without departing from the principles of the present invention, and these improvements and modifications also fall within the protection scope of the present invention.

Claims

1. A signal processing circuit, characterized in that, include: The detector is a charge amplifier used to convert the input charge signal into a voltage signal and amplify the output. Alternatively, the detector may be a capacitor-to-voltage converter used to perform capacitor-to-voltage conversion to output a voltage signal that reflects the current capacitance value of the capacitor-sensitive part connected to the detector. A charge multiplier circuit connected to the detector for increasing the gain coefficient of the detector by feeding back the output of the detector to the input of the detector; The charge multiplier circuit is specifically used for: A multiplied current signal proportional to the output current signal of the detector is fed back to the input terminal of the detector to increase the gain coefficient of the detector by increasing the input current or input charge of the detector.

2. The signal processing circuit according to claim 1, characterized in that, The detector is a single-ended charge amplifier, and the charge multiplication circuit specifically includes: a first resistor, a second resistor, a first capacitor, and a first operational amplifier; The first end of the first resistor serves as the input terminal of the charge multiplier circuit and is connected to the output terminal of the single-ended charge amplifier. The second end of the first resistor is connected to the first end of the second resistor and the negative input terminal of the first operational amplifier. The positive input terminal of the first operational amplifier is connected to the reference voltage terminal. The output terminal of the first operational amplifier is connected to the second end of the second resistor and the second end of the first capacitor. The first end of the first capacitor serves as the output terminal of the charge multiplier circuit and is connected to the input terminal of the single-ended charge amplifier.

3. The signal processing circuit according to claim 2, characterized in that, The single-ended charge amplifier includes: a second operational amplifier, a second capacitor, and a third resistor; The negative input terminal of the second operational amplifier is connected to the first terminal of the second capacitor and the first terminal of the third resistor, respectively, and the connection terminal serves as the input terminal of the single-ended charge amplifier. The positive input terminal of the second operational amplifier is connected to the reference voltage terminal. The output terminal of the second operational amplifier is connected to the second terminal of the second capacitor and the second terminal of the third resistor, respectively, and the connection terminal serves as the output terminal of the single-ended charge amplifier.

4. The signal processing circuit according to claim 1, characterized in that, The detector is a differential charge amplifier, which includes a positive charge amplifier and a negative charge amplifier. The charge multiplication circuit specifically includes a third capacitor and a fourth capacitor. The first terminal of the third capacitor is connected to the output terminal of the positive charge amplifier, the second terminal of the third capacitor is connected to the input terminal of the negative charge amplifier, the first terminal of the fourth capacitor is connected to the input terminal of the positive charge amplifier, and the second terminal of the fourth capacitor is connected to the output terminal of the negative charge amplifier.

5. The signal processing circuit according to claim 4, characterized in that, The positive charge amplifier includes a third operational amplifier, a fifth capacitor, and a fourth resistor; the negative charge amplifier includes a fourth operational amplifier, a sixth capacitor, and a fifth resistor. The positive input terminal of the third operational amplifier is connected to the reference voltage terminal, the negative input terminal of the third operational amplifier is connected to the first terminal of the fifth capacitor and the first terminal of the fourth resistor respectively, and the connection terminal serves as the input terminal of the positive charge amplifier. The output terminal of the third operational amplifier is connected to the second terminal of the fifth capacitor and the second terminal of the fourth resistor respectively, and the connection terminal serves as the output terminal of the positive charge amplifier. The positive input terminal of the fourth operational amplifier is connected to the reference voltage terminal, the negative input terminal of the fourth operational amplifier is connected to the first terminal of the sixth capacitor and the first terminal of the fifth resistor respectively, and the connection terminal serves as the input terminal of the negative charge amplifier. The output terminal of the fourth operational amplifier is connected to the second terminal of the sixth capacitor and the second terminal of the fifth resistor respectively, and the connection terminal serves as the output terminal of the negative charge amplifier.

6. The signal processing circuit according to claim 1, characterized in that, The detector is a single-ended capacitor voltage converter, and the charge multiplication circuit specifically includes: a sixth resistor, a seventh resistor, a seventh capacitor, and a fifth operational amplifier; The first end of the sixth resistor serves as the input terminal of the charge multiplier circuit and is connected to the output terminal of the single-ended capacitor voltage converter. The second end of the sixth resistor is connected to the first end of the seventh resistor and the negative input terminal of the fifth operational amplifier. The positive input terminal of the fifth operational amplifier is connected to the reference voltage terminal. The output terminal of the fifth operational amplifier is connected to the second end of the seventh resistor and the second end of the seventh capacitor. The first end of the seventh capacitor serves as the output terminal of the charge multiplier circuit and is connected to the input terminal of the single-ended capacitor voltage converter.

7. The signal processing circuit according to claim 6, characterized in that, The single-ended capacitor voltage converter includes: a sixth operational amplifier, an eighth capacitor, and an eighth resistor; The negative input terminal of the sixth operational amplifier is connected to the first terminal of the eighth capacitor and the first terminal of the eighth resistor, and the connection terminal serves as the input terminal of the single-ended capacitor voltage converter. The positive input terminal of the sixth operational amplifier is connected to the reference voltage terminal. The output terminal of the sixth operational amplifier is connected to the second terminal of the eighth capacitor and the second terminal of the eighth resistor, and the connection terminal serves as the output terminal of the single-ended capacitor voltage converter.

8. The signal processing circuit according to claim 1, characterized in that, The detector is a differential capacitor voltage converter, which includes a positive capacitor voltage converter and a negative capacitor voltage converter. The charge multiplication circuit specifically includes a ninth capacitor and a tenth capacitor. The first terminal of the ninth capacitor is connected to the output terminal of the positive capacitor voltage converter, the second terminal of the ninth capacitor is connected to the input terminal of the negative capacitor voltage converter, the first terminal of the tenth capacitor is connected to the input terminal of the positive capacitor voltage converter, and the second terminal of the tenth capacitor is connected to the output terminal of the negative capacitor voltage converter.

9. The signal processing circuit according to claim 8, characterized in that, The positive capacitor voltage converter includes: a seventh operational amplifier, an eleventh capacitor, and a ninth resistor; the negative capacitor voltage converter includes: an eighth operational amplifier, a twelfth capacitor, and a tenth resistor. The positive input terminal of the seventh operational amplifier is connected to the first DC voltage terminal, the negative input terminal of the seventh operational amplifier is connected to the first terminal of the eleventh capacitor and the first terminal of the ninth resistor respectively, and the connection terminal serves as the input terminal of the positive capacitor voltage converter. The output terminal of the seventh operational amplifier is connected to the second terminal of the eleventh capacitor and the second terminal of the ninth resistor respectively, and the connection terminal serves as the output terminal of the positive capacitor voltage converter. The positive input terminal of the eighth operational amplifier is connected to the second DC voltage terminal, the negative input terminal of the eighth operational amplifier is connected to the first terminal of the twelfth capacitor and the first terminal of the tenth resistor respectively, and the connection terminal serves as the input terminal of the negative capacitor voltage converter. The output terminal of the eighth operational amplifier is connected to the second terminal of the twelfth capacitor and the second terminal of the tenth resistor respectively, and the connection terminal serves as the output terminal of the negative capacitor voltage converter. The voltage at the first DC voltage terminal has the same amplitude as the voltage at the second DC voltage terminal, but opposite polarities.

10. A sensor, characterized in that, Includes the signal processing circuit as described in any one of claims 1 to 9.

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