Gate voltage bootstrap switching circuit

Abstract

Embodiments of the present disclosure provide a gate voltage bootstrap switching circuit. The gate voltage bootstrap switching circuit comprises a sample-and-hold circuit, a gate voltage bootstrap control circuit, and an overvoltage control circuit. The sample-and-hold circuit samples an input voltage to generate an output voltage under the control of a sample control signal. The gate voltage bootstrap control circuit generates the sample control signal according to the input voltage, a first clock signal, a second clock signal, a first voltage, a second voltage, and an overvoltage control signal from the overvoltage control circuit. The overvoltage control circuit generates the overvoltage control signal according to the output voltage under the control of the sample control signal. Wherein, the overvoltage control signal is used to control a first voltage difference between the sample control signal and the input voltage to be less than or equal to the first voltage, and control a second voltage difference between the sample control signal and the output voltage to be less than or equal to the first voltage in the case that the input voltage is greater than the output voltage.

Description

Technical Field

[0001] The embodiments of this disclosure relate to the field of circuit technology, and more specifically, to gate voltage bootstrap switching circuits. Background Technology

[0002] The sample-and-hold (S&H) circuit is a key module in the design of an analog-to-digital converter (ADC). It is also known as a sampling switch. The linearity of the sampling switch significantly affects the dynamic performance of the ADC, especially core parameters such as spurious-free dynamic range (SFDR). A simple sample-and-hold circuit is shown below. Figure 1 As shown. This sample-and-hold circuit includes a switching transistor NM0. The output Vout of the sample-and-hold circuit can be coupled to a load capacitor Cload. During the hold phase, the clock signal CLK is low, and the switching transistor NM0 is off. During the sampling phase, the clock signal CLK is high (equal to the supply voltage), and the switching transistor NM0 is on. Because the input voltage Vin changes over time, the gate-drain voltage Vout of the switching transistor NM0... GD (or gate-source voltage V) GS The on-resistance R of the switching transistor NM0 changes over time, causing this change and leading to switching linearity issues, which in turn affect the linearity-related parameters of the ADC. on With V GD (or V) GS The relationship is as follows: As can be seen from the above formula, in order to make R on The voltage V of the switching transistor must remain constant over time. GD (or V) GS It does not change over time. With the continuous evolution of technology, sample-and-hold circuits based on gate-voltage bootstrap switching technology have emerged. Sample-and-hold circuits based on gate-voltage bootstrap switching technology can also be called gate-voltage bootstrap switching circuits. Summary of the Invention

[0003] The embodiments described herein provide a gate voltage bootstrap switching circuit.

[0004] According to a first aspect of this disclosure, a gate voltage bootstrap switching circuit is provided. The gate voltage bootstrap switching circuit includes: a sample-and-hold circuit, a gate voltage bootstrap control circuit, and an overvoltage control circuit. The sample-and-hold circuit is configured to sample an input voltage from an input voltage terminal under the control of a sampling control signal to generate an output voltage and to provide the output voltage to an output voltage terminal. The gate voltage bootstrap control circuit is configured to generate a sampling control signal based on the input voltage, a first clock signal from a first clock signal terminal, a second clock signal from a second clock signal terminal, a first voltage from a first voltage terminal, a second voltage from a second voltage terminal, and an overvoltage control signal from the overvoltage control circuit, and to provide the sampling control signal to the sample-and-hold circuit and the overvoltage control circuit via a first node. The overvoltage control circuit is configured to generate an overvoltage control signal based on the output voltage under the control of the sampling control signal and to provide the overvoltage control signal to the gate voltage bootstrap control circuit via a second node. The overvoltage control signal is used to control the first voltage difference between the sampling control signal and the input voltage to be less than or equal to the first voltage when the input voltage is greater than the output voltage, and to control the second voltage difference between the sampling control signal and the output voltage to be less than or equal to the first voltage.

[0005] In some embodiments of this disclosure, the overvoltage control circuit includes: a first transistor. The control electrode of the first transistor is coupled to a first node. The first electrode of the first transistor is coupled to an output voltage terminal. The second electrode of the first transistor is coupled to a second node.

[0006] In some embodiments of this disclosure, the sample-and-hold circuit includes a second transistor. The control electrode of the second transistor is coupled to a first node. The first electrode of the second transistor is coupled to an output voltage terminal. The second electrode of the second transistor is coupled to an input voltage terminal.

[0007] In some embodiments of this disclosure, the gate voltage bootstrap control circuit includes: a third to an eighth transistor, a reset circuit, a pull-down circuit, and a holding circuit. The control electrode of the third transistor is coupled to a first clock signal terminal. The first electrode of the third transistor is coupled to a first voltage terminal. The second electrode of the third transistor is coupled to the second electrode of the fourth transistor, the control electrode of the sixth transistor, and the second electrode of the seventh transistor. The control electrode of the fourth transistor is coupled to the first clock signal terminal. The first electrode of the fourth transistor is coupled to a second node. The control electrode of the fifth transistor is coupled to the first node. The first electrode of the fifth transistor is coupled to the first electrode of the sixth transistor and the third node. The second electrode of the fifth transistor is coupled to the first voltage terminal. The second electrode of the sixth transistor is coupled to the first node. The control electrode of the seventh transistor is coupled to the first node. The first electrode of the seventh transistor is coupled to the second node. The control electrode of the eighth transistor is coupled to the first node. The first electrode of the eighth transistor is coupled to the second node. The second electrode of the eighth transistor is coupled to an input voltage terminal. The reset circuit is configured to reset the voltage of the first node to a second voltage during the holding phase under the control of a second clock signal. The pull-down circuit is configured to pull down the voltage of the second node to the second voltage during the holding phase under the control of the second clock signal. The holding circuit is configured to hold the voltage of the third node at the first voltage during the holding phase, and to hold the third voltage difference between the second and third nodes during the sampling phase.

[0008] In some embodiments of this disclosure, the reset circuit includes a ninth transistor and a tenth transistor. The control electrode of the ninth transistor is coupled to a first voltage terminal. The first electrode of the ninth transistor is coupled to the second electrode of the tenth transistor. The second electrode of the ninth transistor is coupled to a first node. The control electrode of the tenth transistor is coupled to a second clock signal terminal. The first electrode of the tenth transistor is coupled to a second voltage terminal.

[0009] In some embodiments of this disclosure, the pull-down circuit includes an eleventh transistor. The control terminal of the eleventh transistor is coupled to a second clock signal terminal. The first terminal of the eleventh transistor is coupled to a second voltage terminal. The second terminal of the eleventh transistor is coupled to a second node.

[0010] In some embodiments of this disclosure, the holding circuit includes a first capacitor. A first terminal of the first capacitor is coupled to a third node. A second terminal of the first capacitor is coupled to a second node.

[0011] In some embodiments of this disclosure, the first clock signal and the second clock signal are inverse signals of each other.

[0012] According to a second aspect of this disclosure, a gate-voltage bootstrap switching circuit is provided. The gate-voltage bootstrap switching circuit includes: a first transistor to an eleventh transistor, and a first capacitor. The control electrode of the first transistor is coupled to the control electrode of a second transistor. The first electrode of the first transistor is coupled to an output voltage terminal. The second electrode of the first transistor is coupled to the second terminal of the first capacitor. The control electrode of the second transistor is coupled to the second electrodes of a sixth transistor, a seventh transistor, and a ninth transistor. The first electrode of the second transistor is coupled to the output voltage terminal. The second electrode of the second transistor is coupled to an input voltage terminal. The control electrode of a third transistor is coupled to a first clock signal terminal. The first electrode of the third transistor is coupled to a first voltage terminal. The second electrode of the third transistor is coupled to the second electrode of a fourth transistor, the control electrode of the sixth transistor, and the second electrode of the seventh transistor. The control electrode of the fourth transistor is coupled to the first clock signal terminal. The first electrode of the fourth transistor is coupled to the second electrode of the eleventh transistor and the second terminal of the first capacitor. The control electrode of a fifth transistor is coupled to the second electrode of the ninth transistor. The first electrode of the fifth transistor is coupled to the first electrode of the sixth transistor and the first terminal of the first capacitor. The second electrode of the fifth transistor is coupled to the first voltage terminal. The first electrode of the seventh transistor is coupled to the second terminal of the first capacitor. The control electrode of an eighth transistor is coupled to the control electrode of the second transistor. The first terminal of the eighth transistor is coupled to the second terminal of the first capacitor. The second terminal of the eighth transistor is coupled to the input voltage terminal. The control terminal of the ninth transistor is coupled to the first voltage terminal. The first terminal of the ninth transistor is coupled to the second terminal of the tenth transistor. The control terminal of the tenth transistor is coupled to the second clock signal terminal. The first terminal of the tenth transistor is coupled to the second voltage terminal. The control terminal of the eleventh transistor is coupled to the second clock signal terminal. The first terminal of the eleventh transistor is coupled to the second voltage terminal. The first clock signal and the second clock signal are inverted signals.

[0013] In some embodiments of this disclosure, the first transistor, the second transistor, the fourth transistor, and the seventh to eleventh transistors are N-type transistors, and the third transistor, the fifth transistor, and the sixth transistor are P-type transistors. Attached Figure Description

[0014] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. It should be understood that the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure, wherein: Figure 1 This is a circuit diagram of a sample-and-hold circuit; Figure 2 This is a circuit diagram of a gate voltage bootstrap switching circuit; Figure 3 This is a schematic block diagram of a gate voltage bootstrap switching circuit according to an embodiment of the present disclosure; Figure 4This is an exemplary circuit diagram of a gate voltage bootstrap switching circuit according to embodiments of the present disclosure; and Figure 5 This is another exemplary circuit diagram of a gate voltage bootstrap switching circuit according to an embodiment of the present disclosure.

[0015] In the accompanying diagram, markers with the same last two digits correspond to the same elements. It should be noted that the elements in the diagram are schematic and not drawn to scale. Detailed Implementation

[0016] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are also within the scope of protection of this disclosure.

[0017] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this subject matter pertains. It will be further understood that terms such as those defined in commonly used dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the specification and in the relevant art, and shall not be interpreted in an idealized or overly formal form unless otherwise explicitly defined herein. As used herein, the statement of “connecting” or “coupling” two or more parts together shall mean that these parts are directly joined together or joined through one or more intermediate components.

[0018] In all embodiments of this disclosure, since the source and drain (emitter and collector) of the transistor are symmetrical, and the conduction current directions between the source and drain (emitter and collector) of N-type and P-type transistors are opposite, the controlled middle terminal of the transistor is referred to as the control terminal, and the remaining two terminals of the transistor are referred to as the first terminal and the second terminal, respectively. The transistors used in the embodiments of this disclosure are primarily switching transistors. Furthermore, terms such as "first" and "second" are used only to distinguish one component (or part of a component) from another component (or another part of a component).

[0019] Figure 2 A circuit diagram of a gate-voltage bootstrap switching circuit 200 is shown. In the gate-voltage bootstrap switching circuit 200, transistor MN7 is equivalent to... Figure 1The switching transistor MN0 is used. Transistors PM1, PM2, and PM3 are PMOS transistors. Transistors NM1, NM2, NM3, NM4, NM5, NM6, NM7, and NM8 are NMOS transistors. When the first clock signal Clk is low and the second clock signal Clkb is high, the gate voltage bootstrap switching circuit 200 is in a holding state. Transistors NM2, PM1, PM2, NM3, and NM4 are turned on. Transistors PM3, NM1, NM5, NM6, and NM7 are turned off. The upper plate of capacitor C1 is charged to the power supply voltage AVDD, and the lower plate of capacitor C1 is coupled to ground voltage GND.

[0020] When the first clock signal Clk is high and the second clock signal Clkb is low, the gate voltage bootstrap switching circuit 200 is in the sampling phase. Transistor NM2 is off, transistor NM6 is on, and the lower plate of capacitor C1 is coupled to the input voltage terminal Vin. Since there is no discharge path for the charge stored on capacitor C1, the voltage at the upper plate of capacitor C1 becomes Vin + AVDD. At the same time, transistors PM3, NM6, and NM7 are on, causing the gate voltage of transistor NM7 to become Vin + AVDD. This ensures that the gate-drain voltage V of transistor NM7 is maintained. GD The voltage is consistently AVDD, which improves the linearity of the on-resistance of transistor NM7. Since the gate voltage Vboost of transistor NM7 bootstraps to Vin + AVDD each time it is sampled, the switching circuit based on this principle can be called a bootstrap switching circuit or a gate voltage bootstrap switching circuit.

[0021] but Figure 2 The NM7 transistor in the image has a voltage withstand capability issue. For typical CMOS devices, a gate-source voltage V0 is generally required to be within acceptable limits. GS It should be less than 1.1 times the supply voltage. For example, for an NMOS device with a withstand voltage of 1.8V, its V... GS The normal operating voltage should be less than 1.98V. For the gate voltage bootstrap switching circuit 200, if the input voltage Vin < the output voltage Vout, the voltage V at node A will be... A = Vin, then Vboost = Vin + AVDD, V of transistor NM7 GD = AVDD, V of transistor NM7 GS =Vboost – Vout = Vin + AVDD – Vout < AVDD. This ensures that transistor NM7 operates in the safe region. If Vin > Vout, V A= Vin, then Vboost = Vin + AVDD, V GD = Vboost – Vin = AVDD, V GS = Vboost – Vout = Vin + AVDD – Vout > AVDD. In this case, the gate oxide layer of transistor NM7 is at risk of instantaneous breakdown, leading to circuit failure. This greatly reduces the reliability of the gate voltage bootstrap switch circuit 200, and may even directly cause the gate voltage bootstrap switch circuit 200 to fail.

[0022] The current traditional method for solving the overvoltage problem in gate bootstrap switching circuits is to modify the main switching transistor (e.g., Figure 2 The NM7 transistor in the circuit uses a MOS device with a thicker gate oxide layer and stronger voltage withstand capability. For example, when the power supply voltage is 1.8V, a 5V MOS transistor is used as the main switch transistor in the gate voltage bootstrap switching circuit. However, this method has the following limitations: (I) Some manufacturers' technological capabilities do not support the production of devices with multiple voltage withstand capabilities.

[0023] (II) Even if manufacturers' process technology supports the production of devices with various voltage withstand capabilities, this method increases the number of mask layers in the chip using the gate voltage bootstrap switching circuit, thus increasing the chip cost.

[0024] (III) Typically, for linearity considerations, the on-resistance of the main switch transistor is required to be small, so the area of ​​the main switch transistor is usually large. If a MOSFET with a thicker gate oxide layer and stronger voltage withstand capability is used as the main switch transistor, the area of ​​the main switch transistor will be further increased. On the one hand, this increases the cost of the chip using this gate voltage bootstrap switching circuit; on the other hand, due to the increased area of ​​the main switch transistor, the parasitic capacitance of the main switch transistor increases, and the influence of various parasitic effects will gradually become a bottleneck limiting the circuit performance.

[0025] Embodiments of this disclosure provide a gate voltage bootstrap switching circuit. Figure 3 A schematic block diagram of a gate voltage bootstrap switching circuit 300 according to an embodiment of the present disclosure is shown. The gate voltage bootstrap switching circuit 300 may include: a sample-and-hold circuit 310, a gate voltage bootstrap control circuit 320, and an overvoltage control circuit 330. Figure 3 The example also shows the load capacitor Cload.

[0026] The sample-and-hold circuit 310 can be coupled to the gate voltage bootstrap control circuit 320 and the overvoltage control circuit 330. The sample-and-hold circuit 310 can be configured to sample the input voltage Vin from the input voltage terminal Vin under the control of the sampling control signal to generate the output voltage Vout, and provide the output voltage Vout to the output voltage terminal Vout.

[0027] The gate voltage bootstrap control circuit 320 can be coupled to the sample-and-hold circuit 310 and the overvoltage control circuit 330. The gate voltage bootstrap control circuit 320 can be configured to generate a sampling control signal based on the input voltage Vin, a first clock signal Clk from the first clock signal terminal Clk, a second clock signal Clkb from the second clock signal terminal Clkb, a first voltage V1 from the first voltage terminal V1, a second voltage V2 from the second voltage terminal V2, and an overvoltage control signal from the overvoltage control circuit 330. The gate voltage bootstrap control circuit 320 is also configured to provide the sampling control signal to the sample-and-hold circuit 310 and the overvoltage control circuit 330 via the first node N1.

[0028] The overvoltage control circuit 330 can be coupled to the sample-and-hold circuit 310 and the gate voltage bootstrap control circuit 320. The overvoltage control circuit 330 can be configured to generate an overvoltage control signal based on the output voltage Vout under the control of the sampling control signal, and provide the overvoltage control signal to the gate voltage bootstrap control circuit 320 via the second node N2. Specifically, the overvoltage control signal is used to control a first voltage difference between the sampling control signal and the input voltage Vin to be less than or equal to a first voltage V1, and a second voltage difference between the sampling control signal and the output voltage Vout to be less than or equal to the first voltage V1, when the input voltage Vin is greater than the output voltage Vout.

[0029] In some embodiments of this disclosure, the first clock signal Clk and the second clock signal Clkb are inverted signals. The first voltage V1 is equal to the power supply voltage. The second voltage terminal V2 is grounded.

[0030] In the gate voltage bootstrap switch circuit 300 according to an embodiment of the present disclosure, the reliability of the gate voltage bootstrap switch circuit 300 can be improved by limiting the first voltage difference between the sampling control signal and the input voltage Vin and the second voltage difference between the sampling control signal and the output voltage Vout to not exceed the power supply voltage through the overvoltage control circuit 330.

[0031] Figure 4 An exemplary circuit diagram of a gate voltage bootstrap switching circuit 300 according to an embodiment of the present disclosure is shown. Figure 4In the example, the overvoltage control circuit 330 may include a first transistor M1. The control electrode of the first transistor M1 is coupled to a first node N1, the first terminal of the first transistor M1 is coupled to the output voltage terminal Vout, and the second terminal of the first transistor M1 is coupled to a second node N2.

[0032] The sample-and-hold circuit 310 may include a second transistor M2. The control terminal of the second transistor M2 is coupled to the first node N1, the first terminal of the second transistor M2 is coupled to the output voltage terminal Vout, and the second terminal of the second transistor M2 is coupled to the input voltage terminal Vin.

[0033] The gate voltage bootstrap control circuit 320 may include: a third transistor M3 to an eighth transistor M8, a reset circuit 340, a pull-down circuit 350, and a holding circuit 360. Specifically, the control electrode of the third transistor M3 is coupled to the first clock signal terminal Clk, the first electrode of the third transistor M3 is coupled to the first voltage terminal V1, and the second electrode of the third transistor M3 is coupled to the second electrode of the fourth transistor M4, the control electrode of the sixth transistor M6, and the second electrode of the seventh transistor M7. The control electrode of the fourth transistor M4 is coupled to the first clock signal terminal Clk. The first electrode of the fourth transistor M4 is coupled to the second node N2. The control electrode of the fifth transistor M5 is coupled to the first node N1. The first electrode of the fifth transistor M5 is coupled to the first electrode of the sixth transistor M6 and the third node N3. The second electrode of the fifth transistor M5 is coupled to the first voltage terminal. The second electrode of the sixth transistor M6 is coupled to the first node N1. The control electrode of the seventh transistor M7 is coupled to the first node N1. The first electrode of the seventh transistor M7 is coupled to the second node N2. The control electrode of the eighth transistor M8 is coupled to the first node N1. The first terminal of the eighth transistor M8 is coupled to the second node N2. The second terminal of the eighth transistor M8 is coupled to the input voltage terminal Vin.

[0034] The reset circuit 340 can be coupled to the second clock signal terminal Clkb, the first voltage terminal V1, the second voltage terminal V2, and the first node N1. The reset circuit 340 can be configured to reset the voltage of the first node N1 to the second voltage V2 during the holding phase under the control of the second clock signal Clkb.

[0035] The pull-down circuit 350 can be coupled to the second clock signal terminal Clkb, the second voltage terminal V2, and the second node N2. The pull-down circuit 350 can be configured to pull down the voltage of the second node N2 to the second voltage V2 during the holding phase under the control of the second clock signal Clkb.

[0036] The holding circuit 360 can be coupled to the second node N2 and the third node N3. The holding circuit 360 can be configured to hold the voltage of the third node N3 at a first voltage V1 during the holding phase, and to hold the third voltage difference between the second node N2 and the third node N3 during the sampling phase.

[0037] exist Figure 4 In the example, the first transistor, the second transistor M2, the fourth transistor M4, the seventh transistor M7, and the eighth transistor M8 are N-type transistors, while the third transistor M3, the fifth transistor M5, and the sixth transistor M6 are P-type transistors. The first voltage V1 is equal to the power supply voltage. The second voltage terminal V2 is grounded.

[0038] During the hold phase, the first clock signal Clk is low and the second clock signal Clkb is high, and the gate voltage bootstrap switch circuit 300 is in a hold state. Since the first clock signal Clk is low, the third transistor M3 is turned on, and the fourth transistor M4 is turned off. The control electrode of the sixth transistor M6 is coupled to the first voltage terminal V1 (which is high) via the third transistor M3, therefore the sixth transistor M6 is turned off. The reset circuit 340 resets the voltage of the first node N1 to the second voltage V2 (low level), therefore, the fifth transistor M5 is turned on, and the seventh transistor M7, the eighth transistor M8, the second transistor M2, and the first transistor M1 are turned off. The third node N3 is coupled to the first voltage terminal V1 via the fifth transistor M5. The pull-down circuit 350 pulls the voltage of the second node N2 down to the second voltage V2. The hold circuit 360 holds the voltage of the second node N2 at the second voltage V2 (0 V) and holds the voltage of the third node N3 at the first voltage V1.

[0039] During the sampling phase, the first clock signal Clk is high and the second clock signal Clkb is low, and the gate voltage bootstrap switch circuit 300 is in the sampling phase. The reset circuit 340 and the pull-down circuit 350 stop working under the control of the second clock signal Clkb. Since the first clock signal Clk is low, the third transistor M3 is off and the fourth transistor M4 is on. The control electrode of the sixth transistor M6 is coupled to the second node N2 via the fourth transistor M4. The voltage of the second node N2 is low, so the sixth transistor M6 is on. The first node N1 is coupled to the third node N3 via the sixth transistor M6, and the voltage of the first node N1 is equal to the voltage of the third node N3. Since the voltage of the first node N1 is high at this time, the fifth transistor M5 is off, and the seventh transistor M7, the eighth transistor M8, the second transistor M2, and the first transistor M1 are on. The first transistor M1 and the eighth transistor M8 are connected in parallel and are both connected to the second node N2. The first transistor M1 and the eighth transistor M8 are coupled to the input voltage Vin and the output voltage Vout, respectively, so that the voltage of the second node N2 is always the minimum value of Vin and Vout.

[0040] When the input voltage Vin < output voltage Vout, the input voltage Vin is supplied to the second node N2 via the eighth transistor M8. Since the holding circuit 360 is configured to hold the third voltage difference between the second node N2 and the third node N3, the voltage of the third node N3 becomes Vin + V1. Since the sixth transistor M6 is turned on, the gate voltage of the second transistor M2 becomes Vin + V1. The V of the second transistor M2 GD = V1, and the V of the second transistor M2 GS = Vin + V1 – Vout < V1. Thus, the second transistor M2 operates in the safe region.

[0041] When the input voltage Vin > output voltage Vout, the output voltage Vout is supplied to the second node N2 via the first transistor M1. Since the holding circuit 360 is configured to hold the third voltage difference between the second node N2 and the third node N3, the voltage of the third node N3 becomes Vout + V1. Since the sixth transistor M6 is turned on, the gate voltage of the second transistor M2 becomes Vout + V1. The V of the second transistor M2 GD = Vboost – Vin = Vout + V1 – Vin < V1, and the V of the second transistor M2 GS = Vboost – Vout = Vout + V1 – Vout = V1. Thus, the second transistor M2 operates in the safe region.

[0042] Therefore, the gate bootstrap switch circuit 300 according to the embodiment of the present disclosure can operate in the safe region in both cases where the input voltage Vin < output voltage Vout and the input voltage Vin > output voltage Vout, and has high reliability.

[0043] Figure 5 shows Figure 4 an exemplary circuit diagram of the gate bootstrap switch circuit 300 shown. In the Figure 5 example, the reset circuit 340 may include: a ninth transistor M9 and a tenth transistor M10. Wherein, the control electrode of the ninth transistor M9 is coupled to the first voltage terminal V1. The first electrode of the ninth transistor M9 is coupled to the second electrode of the tenth transistor M10. The second electrode of the ninth transistor M9 is coupled to the first node N1. The control electrode of the tenth transistor M10 is coupled to the second clock signal terminal Clkb. The first electrode of the tenth transistor M10 is coupled to the second voltage terminal V2.

[0044] The pull-down circuit 350 may include: an eleventh transistor M11. The control terminal of the eleventh transistor M11 is coupled to the second clock signal terminal Clkb. The first terminal of the eleventh transistor M11 is coupled to the second voltage terminal V2. The second terminal of the eleventh transistor M11 is coupled to the second node N2.

[0045] The holding circuit 360 may include: a first capacitor C1. A first terminal of the first capacitor C1 is coupled to a third node N3. A second terminal of the first capacitor C1 is coupled to a second node N2.

[0046] exist Figure 5 In the example, the first transistor, the second transistor M2, the fourth transistor M4, and the seventh through eleventh transistors M7 through M11 are N-type transistors, while the third transistor M3, the fifth transistor M5, and the sixth transistor M6 are P-type transistors. The first voltage V1 is equal to the power supply voltage. The second voltage terminal V2 is grounded.

[0047] During the hold phase, the first clock signal Clk is low and the second clock signal Clkb is high, and the gate voltage bootstrap switch circuit 300 is in a hold state. Since the first clock signal Clk is low, the third transistor M3 is turned on, and the fourth transistor M4 is turned off. The control electrode of the sixth transistor M6 is coupled to the first voltage terminal V1 (which is high) via the third transistor M3, therefore the sixth transistor M6 is turned off. Since the second clock signal Clkb is high, the tenth transistor M10 is turned on. The control electrode of the ninth transistor M9 is coupled to the first voltage terminal V1, therefore the ninth transistor M9 is turned on. The ninth transistor M9 and the tenth transistor M10 are turned on, resetting the voltage of the first node N1 to the second voltage V2 (low). Thus, the fifth transistor M5 is turned on, and the seventh transistor M7, the eighth transistor M8, the second transistor M2, and the first transistor M1 are turned off. The third node N3 is coupled to the first voltage terminal V1 via the fifth transistor M5. Since the second clock signal Clkb is at a high level, the eleventh transistor M11 is turned on, pulling down the voltage of the second node N2 to the second voltage V2. The holding circuit 360 holds the voltage of the second node N2 at the second voltage V2 (0 V) and holds the voltage of the third node N3 (the first terminal of the first capacitor C1) at the first voltage V1.

[0048] In the sampling phase, the first clock signal Clk is at a high level and the second clock signal Clkb is at a low level, and the gate voltage bootstrapping switch circuit 300 is in the sampling phase. Since the second clock signal Clkb is at a low level, the tenth transistor M10 is cut off, so the voltage of the first node N1 is not affected by the second voltage terminal V2. Since the second clock signal Clkb is at a low level, the eleventh transistor M11 is cut off, so the voltage of the second node N2 is not affected by the second voltage terminal V2. Since the first clock signal Clk is at a low level, the third transistor M3 is cut off and the fourth transistor M4 is turned on. The control electrode of the sixth transistor M6 is coupled to the second node N2 via the fourth transistor M4, and the voltage of the second node N2 is at a low level, so the sixth transistor M6 is turned on. The first node N1 is coupled to the third node N3 via the sixth transistor M6, and the voltage of the first node N1 is equal to the voltage of the third node N3. Since the voltage of the first node N1 is at a high level at this time, the fifth transistor M5 is cut off, and the seventh transistor M7, the eighth transistor M8, the second transistor M2 and the first transistor M1 are turned on. The first transistor M1 and the eighth transistor M8 are connected in parallel and both are connected to the second node N2. The first transistor M1 and the eighth transistor M8 are respectively coupled to the input voltage Vin and the output voltage Vout, so that the voltage of the second node N2 is always the minimum value of Vin and Vout.

[0049] When the input voltage Vin < the output voltage Vout, the input voltage Vin is supplied to the second node N2 via the eighth transistor M8. Since the charge stored in the first capacitor C1 has no discharge path, the voltage of the third node N3 equipotentially jumps to Vin + V1. Since the sixth transistor M6 is turned on, the gate voltage of the second transistor M2 becomes Vin + V1. The V of the second transistor M2 GD = V1, the V of the second transistor M2 GS = Vin + V1 – Vout < V1. Thus the second transistor M2 operates in the safe region.

[0050] When the input voltage Vin > the output voltage Vout, the output voltage Vout is supplied to the second node N2 via the first transistor M1. Since the charge stored in the first capacitor C1 has no discharge path, the voltage of the third node N3 equipotentially jumps to Vout + V1. Since the sixth transistor M6 is turned on, the gate voltage of the second transistor M2 becomes Vout + V1. The V of the second transistor M2 GD = Vboost – Vin = Vout + V1 – Vin < V1, the V of the second transistor M2 GS=Vboost – Vout =Vout + V1 – Vout = V1. This ensures the second transistor M2 operates in the safe region.

[0051] Therefore, the gate voltage bootstrap switching circuit 300 according to the embodiments of this disclosure can operate in the safe region in both cases where the input voltage Vin < the output voltage Vout and the input voltage Vin > the output voltage Vout, and has high reliability.

[0052] Those skilled in the art will understand that, based on the above inventive concept, Figure 4 or Figure 5 Any modifications to the circuit shown should also fall within the scope of this disclosure. In such modifications, the transistor and voltage terminals may also have the same characteristics as described above. Figure 4 or Figure 5 The examples shown have different settings.

[0053] In summary, the gate-voltage bootstrap switching circuit according to the embodiments of this disclosure maintains the rise rate of the gate voltage of the main switch in sync with the rise rate of the smaller of the output voltage Vout and the input voltage Vin, thereby avoiding the phenomenon that the gate-source voltage of the main switch is greater than the power supply voltage, thus realizing a more reliable and safer gate-voltage bootstrap switching circuit.

[0054] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of apparatuses and methods according to various embodiments of the present disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of an instruction containing one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0055] Unless otherwise expressly indicated by the context, the singular form of words used herein and in the appended claims includes the plural form, and vice versa. Thus, when referring to the singular, the plural form of the corresponding term is generally included. Similarly, the terms “comprising” and “including” shall be interpreted as including rather than exclusively. Likewise, the terms “including” and “or” shall be interpreted as including unless such interpretation is expressly prohibited herein. Where the term “example” is used herein, particularly when it follows a set of terms, the “example” is merely exemplary and illustrative and should not be considered exclusive or extensive.

[0056] Further aspects and scope of adaptation become apparent from the description provided herein. It should be understood that various aspects of this application may be implemented individually or in combination with one or more other aspects. It should also be understood that the descriptions and specific embodiments herein are for illustrative purposes only and are not intended to limit the scope of this application.

[0057] Several embodiments of this disclosure have been described in detail above. However, it is obvious that those skilled in the art can make various modifications and variations to the embodiments of this disclosure without departing from the spirit and scope of this disclosure. The scope of protection of this disclosure is defined by the appended claims.

Claims

1. A gate voltage bootstrap switching circuit, comprising: Sample and hold circuit, gate voltage bootstrap control circuit, and overvoltage control circuit. The sample-and-hold circuit is configured to sample the input voltage from the input voltage terminal under the control of a sampling control signal to generate an output voltage, and to provide the output voltage to the output voltage terminal. The gate voltage bootstrap control circuit is configured to generate the sampling control signal based on the input voltage, a first clock signal from a first clock signal terminal, a second clock signal from a second clock signal terminal, a first voltage from a first voltage terminal, a second voltage from a second voltage terminal, and an overvoltage control signal from the overvoltage control circuit, and to provide the sampling control signal to the sample-and-hold circuit and the overvoltage control circuit via a first node; The overvoltage control circuit is configured to generate the overvoltage control signal based on the output voltage under the control of the sampling control signal, and to provide the overvoltage control signal to the gate voltage bootstrap control circuit via the second node; Wherein, the overvoltage control signal is used to control the first voltage difference between the sampling control signal and the input voltage to be less than or equal to the first voltage when the input voltage is greater than the output voltage, and to control the second voltage difference between the sampling control signal and the output voltage to be less than or equal to the first voltage; The overvoltage control circuit includes a first transistor, and the sample-and-hold circuit includes a second transistor.

2. The gate voltage bootstrap switching circuit according to claim 1, wherein, The control electrode of the first transistor is coupled to the first node, the first electrode of the first transistor is coupled to the output voltage terminal, and the second electrode of the first transistor is coupled to the second node.

3. The gate voltage bootstrap switching circuit according to claim 1, wherein, The control electrode of the second transistor is coupled to the first node, the first electrode of the second transistor is coupled to the output voltage terminal, and the second electrode of the second transistor is coupled to the input voltage terminal.

4. The gate voltage bootstrap switching circuit according to claim 1, wherein, The gate voltage bootstrap control circuit includes: the third to eighth transistors, a reset circuit, a pull-down circuit, and a holding circuit. The control electrode of the third transistor is coupled to the first clock signal terminal, the first electrode of the third transistor is coupled to the first voltage terminal, and the second electrode of the third transistor is coupled to the second electrode of the fourth transistor, the control electrode of the sixth transistor, and the second electrode of the seventh transistor. The control terminal of the fourth transistor is coupled to the first clock signal terminal, and the first terminal of the fourth transistor is coupled to the second node; The control electrode of the fifth transistor is coupled to the first node, the first electrode of the fifth transistor is coupled to the first electrode of the sixth transistor and the third node, and the second electrode of the fifth transistor is coupled to the first voltage terminal. The second terminal of the sixth transistor is coupled to the first node; The control electrode of the seventh transistor is coupled to the first node, and the first electrode of the seventh transistor is coupled to the second node; The control electrode of the eighth transistor is coupled to the first node, the first electrode of the eighth transistor is coupled to the second node, and the second electrode of the eighth transistor is coupled to the input voltage terminal. The reset circuit is configured to reset the voltage of the first node to the second voltage during the holding phase under the control of the second clock signal; The pull-down circuit is configured to pull down the voltage of the second node to the second voltage during the hold phase under the control of the second clock signal; The holding circuit is configured to hold the voltage of the third node at the first voltage during the holding phase, and to hold the third voltage difference between the second node and the third node during the sampling phase.

5. The gate voltage bootstrap switching circuit according to claim 4, wherein, The reset circuit includes: a ninth transistor and a tenth transistor. Wherein, the control electrode of the ninth transistor is coupled to the first voltage terminal, the first electrode of the ninth transistor is coupled to the second electrode of the tenth transistor, and the second electrode of the ninth transistor is coupled to the first node; The control electrode of the tenth transistor is coupled to the second clock signal terminal, and the first electrode of the tenth transistor is coupled to the second voltage terminal.

6. The gate voltage bootstrap switching circuit according to claim 4, wherein, The pull-down circuit includes: an eleventh transistor, The control electrode of the eleventh transistor is coupled to the second clock signal terminal, the first electrode of the eleventh transistor is coupled to the second voltage terminal, and the second electrode of the eleventh transistor is coupled to the second node.

7. The gate voltage bootstrap switching circuit according to claim 4, wherein, The holding circuit includes: a first capacitor, Wherein, the first end of the first capacitor is coupled to the third node, and the second end of the first capacitor is coupled to the second node.

8. The gate voltage bootstrap switching circuit according to any one of claims 1 to 7, wherein, The first clock signal and the second clock signal are inverted signals.

9. A gate voltage bootstrap switching circuit, comprising: The first to eleventh transistors, and the first capacitor, Wherein, the control electrode of the first transistor is coupled to the control electrode of the second transistor, the first electrode of the first transistor is coupled to the output voltage terminal, and the second electrode of the first transistor is coupled to the second terminal of the first capacitor. The control electrode of the second transistor is coupled to the second electrode of the sixth transistor, the control electrode of the seventh transistor, and the second electrode of the ninth transistor; the first electrode of the second transistor is coupled to the output voltage terminal; and the second electrode of the second transistor is coupled to the input voltage terminal. The control terminal of the third transistor is coupled to the first clock signal terminal, the first terminal of the third transistor is coupled to the first voltage terminal, and the second terminal of the third transistor is coupled to the second terminal of the fourth transistor, the control terminal of the sixth transistor, and the second terminal of the seventh transistor. The control terminal of the fourth transistor is coupled to the first clock signal terminal, and the first terminal of the fourth transistor is coupled to the second terminal of the eleventh transistor and the second terminal of the first capacitor. The control electrode of the fifth transistor is coupled to the second electrode of the ninth transistor, the first electrode of the fifth transistor is coupled to the first electrode of the sixth transistor and the first terminal of the first capacitor, and the second electrode of the fifth transistor is coupled to the first voltage terminal. The first terminal of the seventh transistor is coupled to the second terminal of the first capacitor; The control electrode of the eighth transistor is coupled to the control electrode of the second transistor, the first electrode of the eighth transistor is coupled to the second terminal of the first capacitor, and the second electrode of the eighth transistor is coupled to the input voltage terminal. The control terminal of the ninth transistor is coupled to the first voltage terminal, and the first terminal of the ninth transistor is coupled to the second terminal of the tenth transistor; The control terminal of the tenth transistor is coupled to the second clock signal terminal, and the first terminal of the tenth transistor is coupled to the second voltage terminal; The control terminal of the eleventh transistor is coupled to the second clock signal terminal, and the first terminal of the eleventh transistor is coupled to the second voltage terminal. The first clock signal and the second clock signal are inverted signals.

10. The gate voltage bootstrap switching circuit according to claim 9, wherein, The first transistor, the second transistor, the fourth transistor, and the seventh to eleventh transistors are N-type transistors, and the third transistor, the fifth transistor, and the sixth transistor are P-type transistors.

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