Voltage controlled oscillator and phase locked loop

Abstract

A voltage-controlled oscillator and a phase-locked loop, the voltage-controlled oscillator comprising: a resonant circuit having a first output terminal and a second output terminal; a current source; a negative resistance circuit comprising a first transistor and a second transistor, both being NMOS transistors, the NMOS transistors having a P-type well region in a substrate and an N-type well region surrounding the P-type well region, a drain of the first transistor and a gate of the second transistor being connected to the first output terminal, a gate of the first transistor and a drain of the second transistor being connected to the second output terminal, a body terminal of the first transistor and a source being connected and connected to the current source, and a body terminal of the second transistor and a source being connected and connected to the current source. By arranging the N-type well region in the substrate of the NMOS transistor, the body terminal and the source can be connected without affecting the potential connection mode of the substrate of the NMOS transistor, thereby improving or eliminating the substrate bias effect, and at the same time, the influence of external substrate noise is isolated, and both of the above aspects are conducive to improving the phase noise.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a voltage-controlled oscillator and a phase-locked loop. Background Technology

[0002] An oscillator is a circuit that can convert direct current energy into periodic alternating current signals without external signal excitation. If the operating state of the oscillator and the component parameters of the oscillation circuit are controlled by the input control voltage, then the oscillator constitutes a voltage-controlled oscillator.

[0003] A voltage-controlled oscillator (VCO) is an oscillator whose oscillation frequency is adjustable and controlled by an input control voltage. The VCO is a core component of a phase-locked loop (PLL) circuit. VCOs are widely used in clock synchronization circuits in microprocessors, frequency synthesizers in wireless communication transceivers, clock recovery circuits (CRC) in fiber optic communications, and multi-phase sampling circuits.

[0004] The main performance indicator of a voltage-controlled oscillator is phase noise (PN). Summary of the Invention

[0005] The problem solved by the embodiments of the present invention is to provide a voltage-controlled oscillator and a phase-locked loop to improve the phase noise of the voltage-controlled oscillator.

[0006] To address the aforementioned problems, this invention provides a voltage-controlled oscillator, comprising: a resonant circuit having a first output terminal and a second output terminal; a current source; and a negative resistance circuit including a first transistor and a second transistor, both of which are NMOS transistors. The substrate of the NMOS transistor has a P-type well region and an N-type well region surrounding the P-type well region. The P-type well region has a body terminal. The drain of the first transistor and the gate of the second transistor are both connected to the first output terminal. The gate of the first transistor and the drain of the second transistor are both connected to the second output terminal. The body terminal and source of the first transistor are connected and both connected to the current source. The body terminal and source of the second transistor are connected and both connected to the current source.

[0007] Optionally, the N-type well region is floated.

[0008] Optionally, the N-type well region includes: a first N-type well region located at the bottom of the P-type well region, wherein the projection of the P-type well region in the first N-type well region is located inside the first N-type well region, and the first N-type well region is a deep N-type well region; and a second N-type well region surrounding the P-type well region, wherein the second N-type well region is connected to the corresponding first N-type well region, and the ion doping concentration of the second N-type well region is less than the ion doping concentration of the first N-type well region.

[0009] Optionally, the exposed N-type well region on the substrate surface has an N-type contact region, which serves as an external terminal for the corresponding N-type well region.

[0010] Optionally, the P-type well region of the NMOS transistor further has a first P-type contact region isolated from the source, the first P-type contact region serving as the body terminal of the corresponding P-type well region.

[0011] Optionally, the substrate of the NMOS transistor is a P-type substrate.

[0012] Optionally, the substrate of each NMOS transistor has a second P-type contact region isolated from the N-type well region, and the second P-type contact region is used as an external terminal of the corresponding substrate.

[0013] Optionally, the P-type substrate is grounded.

[0014] Optionally, the resonant circuit includes an inductor and a capacitor connected in parallel; the two ends of the inductor are coupled to the first output terminal and the second output terminal, respectively; the two ends of the capacitor are coupled to the first output terminal and the second output terminal, respectively.

[0015] Optionally, the capacitor may include one or both of a variable capacitor and a capacitor matrix.

[0016] Accordingly, embodiments of the present invention also provide a phase-locked loop, including the voltage-controlled oscillator provided in embodiments of the present invention.

[0017] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0018] In the voltage-controlled oscillator provided in this embodiment of the invention, the negative resistance circuit includes a first transistor and a second transistor, both of which are NMOS transistors. The substrate of the NMOS transistor has a P-type well region and an N-type well region surrounding the P-type well region. The P-type well region has a bulk terminal. The bulk terminal and source of the first transistor are connected and share the current source. The bulk terminal and source of the second transistor are also connected and share the current source. By setting an N-type well region in the substrate of the NMOS transistor, the P-type well region of the NMOS transistor and the substrate are isolated. That is, the bulk substrate (i.e., the P-type well region) of the NMOS transistor is isolated from the external substrate. This allows the bulk terminal and source of the NMOS transistor to be connected without affecting the potential connection mode of the substrate (i.e., the external substrate). The potential difference (i.e., Vbs) between the bulk terminal and the source is zero, which can improve or eliminate the substrate bias effect of the NMOS transistor. At the same time, isolating the P-type well region and the substrate through the N-type well region is beneficial to isolating the influence of external substrate noise. Both of these aspects are beneficial to improving the phase noise of the voltage-controlled oscillator. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of the circuit structure of a voltage-controlled oscillator;

[0020] Figure 2 This is a schematic diagram of a semiconductor structure.

[0021] Figure 3 This is a schematic diagram of the circuit structure of an embodiment of the voltage-controlled oscillator of the present invention;

[0022] Figure 4 yes Figure 3 A schematic diagram of an embodiment of the NMOS transistor in the negative resistance circuit shown;

[0023] Figure 5 yes Figure 3 The equivalent circuit diagram of the NMOS transistor in the negative resistance circuit shown is when it is floating in the N-type well region. Detailed Implementation

[0024] Currently, the phase noise of voltage-controlled oscillators (VCOs) still needs improvement. The following analysis, using a VCO as an example, explains why the phase noise still needs to be improved.

[0025] Figure 1 This is a schematic diagram of the circuit structure of a voltage-controlled oscillator.

[0026] Traditional capacitor-inductor voltage-controlled oscillators (LC voltage-controlled oscillators) consist of a resonant circuit composed of an inductor and a capacitor, and a negative resistance circuit composed of cross-coupled transistor pairs.

[0027] refer to Figure 1 The voltage-controlled oscillator includes: a resonant circuit (not shown), the resonant circuit having a first output terminal OP and a second output terminal ON, and the resonant circuit including an inductor L and a capacitor C connected in parallel (e.g., ...). Figure 1 (shown in the dashed box); tail current source 10; negative resistance circuit (not shown), including a first NMOS transistor (i.e., NM1) and a second NMOS transistor (i.e., NM2), the drain D of the first NMOS transistor and the gate G of the second NMOS transistor are connected to the first output terminal OP, the gate G of the first NMOS transistor and the drain D of the second NMOS transistor are connected to the second output terminal ON, the body B of the first NMOS transistor is grounded, the source S of the first NMOS transistor is connected to the tail current source 10, the body B of the second NMOS transistor is grounded, and the source S of the second NMOS transistor is connected to the tail current source 10.

[0028] Reference Figure 2 , Figure 2 This is a schematic diagram of a semiconductor structure.

[0029] refer to Figure 2 The semiconductor structure includes: a substrate 20; a first gate structure 25 and a second gate structure 35 disposed on the substrate 20; a first N-type heavily doped (N+) region 21 located in the substrate 20 on one side of the first gate structure 25; a second N-type heavily doped region 22 located in the substrate 20 on the other side of the first gate structure 25; a first P-type heavily doped (P+) region 23 located in the substrate 20 on the side of the second N-type heavily doped region 22 away from the first gate structure 25; a third N-type heavily doped region 31 located in the substrate 20 on one side of the second gate structure 35; a fourth N-type heavily doped region 32 located in the substrate 20 on the other side of the second gate structure 35; and a second P-type heavily doped region 33 located in the substrate 20 on the side of the fourth N-type heavily doped region 32 away from the second gate structure 35.

[0030] The first gate structure 25, the first N-type heavily doped region 21, the second N-type heavily doped region 22 and the first P-type heavily doped region 23 constitute the first transistor 20; the second gate structure 35, the third N-type heavily doped region 31, the fourth N-type heavily doped region 32 and the second P-type heavily doped region 33 constitute the second transistor 30.

[0031] In this configuration, the first N-type heavily doped region 21 serves as the drain of the first transistor 20, the second N-type heavily doped region 22 serves as the source of the first transistor 20, and the first P-type heavily doped region 23 serves as the body terminal of the first transistor 20; the third N-type heavily doped region 31 serves as the drain of the second transistor 30, the fourth N-type heavily doped region 32 serves as the source of the second transistor 30, and the second P-type heavily doped region 33 serves as the body terminal of the second transistor 30.

[0032] Specifically, taking the first transistor 20 as either the first NMOS transistor or the second NMOS transistor in the voltage-controlled oscillator, and the second transistor 30 as a transistor in an external circuit, as an example, the reasons why the phase noise of the current voltage-controlled oscillator needs to be improved are explained.

[0033] Since the first P-type heavily doped region 23 and the second P-type heavily doped region 33 are located in the same substrate 20 and are not isolated by other doped regions or isolation structures, the body terminals of the first NMOS transistor and the second NMOS transistor are connected to the body terminals of the transistors in the external circuit. Accordingly, due to the limitations of the current semiconductor structure, the body terminals B of the first NMOS transistor and the second NMOS transistor must be grounded to VSS.

[0034] Therefore, as Figure 1 As shown, due to the limitations of current semiconductor structures, when the source S of the first NMOS transistor and the source S of the second NMOS transistor need to be connected to the tail current source 10, the source S and body B of the first NMOS transistor are at different potentials, and the source S and body B of the second NMOS transistor are also at different potentials. This results in a significant substrate bias effect of the NMOS transistor in the negative resistance circuit, which in turn affects the performance of the NMOS transistor and correspondingly degrades the phase noise of the voltage-controlled oscillator.

[0035] Moreover, such as Figure 2 As shown, the first NMOS transistor and the second NMOS transistor have the same body substrate (i.e., substrate 20) as the transistors in the external circuit. Therefore, the noise jitter of substrate 20 will directly affect the performance of the first NMOS transistor and the second NMOS transistor, thereby deteriorating the phase noise of the voltage-controlled oscillator.

[0036] To address the aforementioned technical problem, this invention provides a voltage-controlled oscillator, comprising: a resonant circuit having a first output terminal and a second output terminal; a current source; and a negative resistance circuit including a first transistor and a second transistor, both of which are NMOS transistors. The substrate of the NMOS transistor has a P-type well region and an N-type well region surrounding the P-type well region. The P-type well region has a body terminal. The drain of the first transistor and the gate of the second transistor are both connected to the first output terminal. The gate of the first transistor and the drain of the second transistor are both connected to the second output terminal. The body terminal and source of the first transistor are connected and both connected to the current source. The body terminal and source of the second transistor are connected and both connected to the current source.

[0037] In the voltage-controlled oscillator provided in this embodiment of the invention, the negative resistance circuit includes a first transistor and a second transistor, both of which are NMOS transistors. The substrate of the NMOS transistor has a P-type well region and an N-type well region surrounding the P-type well region. The P-type well region has a bulk terminal. The bulk terminal and source of the first transistor are connected and share the current source. The bulk terminal and source of the second transistor are also connected and share the current source. By setting an N-type well region in the substrate of the NMOS transistor, the P-type well region of the NMOS transistor and the substrate are isolated. That is, the bulk substrate (i.e., the P-type well region) of the NMOS transistor is isolated from the external substrate. This allows the bulk terminal and source of the NMOS transistor to be connected without affecting the potential connection mode of the substrate (i.e., the external substrate). The potential difference (i.e., Vbs) between the bulk terminal and the source is zero, which can improve or eliminate the substrate bias effect of the NMOS transistor. At the same time, isolating the P-type well region and the substrate through the N-type well region is beneficial to isolating the influence of external substrate noise. Both of these aspects are beneficial to improving the phase noise of the voltage-controlled oscillator.

[0038] To make the above-mentioned objects, features and advantages of the embodiments of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0039] Figure 3 This is a circuit structure diagram of an embodiment of the voltage-controlled oscillator of the present invention. Figure 4 yes Figure 3 The diagram shows a schematic representation of an embodiment of the NMOS transistor in the negative resistance circuit.

[0040] The voltage-controlled oscillator includes: a resonant circuit 20 having a first output terminal OP and a second output terminal ON; a current source 30; and a negative resistance circuit (not shown) including a first transistor 41 and a second transistor 42, both of which are NMOS transistors. The substrate 100 of the NMOS transistor has a P-type well region 140 and an N-type well region 110 surrounding the P-type well region 140. The P-type well region 140 has a body terminal Bulk. The drain D of the first transistor 41 and the gate G of the second transistor 42 are both connected to the first output terminal OP. The gate G of the first transistor 41 and the drain D of the second transistor 42 are both connected to the second output terminal ON. The body terminal Bulk of the first transistor 41 and its source S are connected and both connected to the current source 30. The body terminal Bulk of the second transistor 42 and its source S are connected and both connected to the current source 30.

[0041] In this embodiment, by providing an N-type well region 110 in the substrate 100 of the NMOS transistor in the negative resistance circuit, the P-type well region 140 of the NMOS transistor and the substrate 100 are isolated. That is, the N-type well region 110 isolates the body substrate (i.e., the P-type well region 140, which is also the internal substrate of the NMOS transistor) and the external substrate. This allows the body terminal Bulk and the source S of the NMOS transistor to be connected without affecting the potential connection mode of the substrate 100 (i.e., the external substrate). The potential difference (i.e., Vbs) between the body terminal Bulk and the source S is zero, which can improve or eliminate the substrate bias effect of the NMOS transistor. At the same time, isolating the P-type well region 140 and the substrate 100 by the N-type well region 110 is beneficial to isolating the influence of external substrate noise. Both of these aspects are beneficial to improving the phase noise of the voltage-controlled oscillator.

[0042] A voltage-controlled oscillator is an important component of a phase-locked loop (PLL) and is used to provide the oscillation frequency.

[0043] In this embodiment, the voltage-controlled oscillator is a capacitor-inductor voltage-controlled oscillator (i.e., an LC voltage-controlled oscillator).

[0044] The resonant circuit 20 is used to generate an oscillation frequency, thereby generating an oscillation signal for a voltage-controlled oscillator.

[0045] In this embodiment, the resonant circuit 20 has a first output terminal OP and a second output terminal ON, which are used to connect to the negative resistance circuit.

[0046] In this embodiment, the resonant circuit 20 is an inductor-capacitor resonant circuit (i.e., an LC resonant circuit).

[0047] Therefore, the resonant circuit 20 includes an inductor L and a capacitor C connected in parallel (e.g., ...). Figure 3(As shown in the dashed box).

[0048] The oscillation frequency is one of the main parameters for evaluating the performance of a voltage-controlled oscillator (VCO). The oscillation frequency of a VCO is mainly determined by the inductance L and capacitance C in the resonant circuit 20.

[0049] Specifically, the two ends of the inductor L are coupled to the first output terminal OP and the second output terminal ON, respectively, and the two ends of the capacitor C are coupled to the first output terminal OP and the second output terminal ON, respectively.

[0050] In this embodiment, the capacitor C includes one or both of a variable capacitor and a capacitor matrix. A capacitor matrix is ​​beneficial for expanding the frequency adjustable range of the voltage-controlled oscillator.

[0051] The capacitor matrix may include one or both of a fixed capacitor array and a variable capacitor array. The fixed capacitor array is connected between the first output terminal OP and the second output terminal ON. The variable capacitor array is coupled between the first output terminal OP and the second output terminal ON.

[0052] like Figure 3 As shown, as an example, the case where the capacitor C is a variable capacitor is illustrated.

[0053] The current source 30 is used to generate the operating current of the voltage-controlled oscillator, thereby enabling the voltage-controlled oscillator to operate normally.

[0054] In this embodiment, the current source 30 is the tail current source. By using the tail current source, the influence of power supply noise on the voltage-controlled oscillator is reduced, which in turn helps to make the frequency of the output signal of the voltage-controlled oscillator more stable.

[0055] The negative resistance circuit includes a first transistor 41 and a second transistor 42. The negative resistance circuit is composed of cross-coupled transistors and is used to provide negative resistance to compensate for the energy loss in the resonant circuit 20 (i.e. to offset the positive resistance generated by the resonant circuit 20), thereby ensuring that the voltage-controlled oscillator can work continuously.

[0056] Therefore, the drain D of the first transistor 41 and the gate G of the second transistor 42 are both connected to the first output terminal OP, and the gate G of the first transistor 41 and the drain D of the second transistor 42 are both connected to the second output terminal ON.

[0057] In this embodiment, the cross-coupled transistor refers to a structure composed of two MOS transistors of the same size and type connected in a cross-coupled manner. Therefore, the first transistor 41 and the second transistor 42 have the same channel conduction type, and both the first transistor 41 and the second transistor 42 are NMOS transistors.

[0058] Accordingly, the voltage-controlled oscillator is provided with negative resistance through a back-to-back cross positive feedback connection of the first transistor 41 and the second transistor 42.

[0059] Reference Figure 4 , Figure 4 yes Figure 3 This is a schematic diagram of an embodiment of the semiconductor structure corresponding to the NMOS transistor in the negative resistance circuit shown. The first transistor 41 and the second transistor 42 are both NMOS transistors. Figure 4 This can be a schematic diagram representing the semiconductor structure corresponding to either the first transistor 41 or the second transistor 42.

[0060] In this embodiment, the substrate 100 is a planar substrate.

[0061] In this embodiment, the substrate 100 is made of silicon. In other embodiments, the substrate may also be made of other materials such as germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium ionide. The substrate may also be other types of substrates such as silicon-on-insulator substrate or germanium-on-insulator substrate.

[0062] In this embodiment, the substrates 100 of the first transistor 41 and the second transistor 41 are both P-type substrates (P-Sub), that is, the substrate 100 of the NMOS transistor is a P-type substrate, meaning that the substrate 100 is doped with P-type ions. The P-type ions include B ions, Ga ions, or In ions.

[0063] Specifically, the P-type substrate is grounded.

[0064] The substrate 100 of the NMOS transistor has a P-well region 140 and an N-well region 110 surrounding the P-well region 140, the P-well region 140 having a body terminal Bulk.

[0065] The P-type well region 140 serves as the body substrate of the NMOS transistor, providing the channel for the NMOS transistor. Therefore, the P-type well region 140 has a body terminal (Bulk) for providing an external terminal for the P-type well region 140.

[0066] In this embodiment, the doped ions in the P-type well region 140 are P-type ions.

[0067] In this embodiment, the N-type well region 110 surrounds the P-type well region 140. The N-type well region 110 is used to provide an independent body substrate for the NMOS transistor and is beneficial for isolating the influence of external substrate noise.

[0068] The conductivity type of the doped ions in the N-type well region 110 is different from that of the doped ions in the substrate 100, thereby isolating the P-type well region 140 of the NMOS transistor from the substrate 100. In other words, the body substrate and the outer substrate of the NMOS transistor are isolated.

[0069] The doped ions in the N-type well region 110 are N-type ions. Among them, N-type ions include P ions, As ions, or Sb ions.

[0070] In this embodiment, the N-type well region 110 includes: a first N-type well region 111 located at the bottom of the P-type well region 140, wherein the projection of the P-type well region 140 in the first N-type well region 111 is located inside the first N-type well region 111, and the first N-type well region 111 is a deep N-type well (DNW) region; and a second N-type well region 112 surrounding the P-type well region 140, wherein the second N-type well region 112 is connected to the corresponding first N-type well region 111, and the ion doping concentration of the second N-type well region 112 is less than the ion doping concentration of the first N-type well region 111.

[0071] The first N-type well region 111 is formed by a deep N-well process.

[0072] Specifically, the bottom of the second N-type well region 112 is connected to the corresponding first N-type well region 111. In other embodiments, the sidewall of the second N-type well region may also be connected to the sidewall of the first N-type well region.

[0073] The second N-type well region 112 is connected to the corresponding first N-type well region 111, thereby surrounding the P-type well region 140 through the second N-type well region 112 and the first N-type well region 111.

[0074] In this embodiment, the exposed N-type well region 110 on the surface of the substrate 100 has an N-type contact region 113, which serves as an external terminal of the corresponding N-type well region 110.

[0075] The N-type contact region 113 is used as an electrical connection location for applying a potential to the N-type well region 110.

[0076] In this embodiment, the N-type contact region 113 is an N-type heavily doped (N+) region, and the ion doping concentration of the N-type contact region 113 is greater than the doping concentration of the N-type well region 110, so as to reduce the contact resistance of the N-type contact region 113.

[0077] Specifically, the N-type contact region 113 is located in the second N-type well region 112, and the ion doping concentration of the N-type contact region 113 is greater than the ion doping concentration of the second N-type well region 112.

[0078] In this embodiment, the N-type well region 110 is floating.

[0079] Reference Figure 4 and Figure 5 , Figure 5 This is the equivalent circuit diagram of the NMOS transistor in the negative resistance circuit when it is floating in the N-type well region 110.

[0080] Because the substrate 100 has a P-type well region 140 and an N-type well region 110 surrounding the P-type well region 140, a reverse-biased diode rwdio (e.g., ...) is correspondingly introduced between the P-type well region 140 and the N-type well region 110 (specifically a deep N-type well region) located below the P-type well region 140. Figure 4 As shown), and the reverse bias diode dnwdio between the N-type well region 110 (specifically a deep N-type well region) below the P-type well region 140 and the substrate 100 (as shown). Figure 4 As shown), the equivalent capacitances of the reverse-biased diodes rwdio and dnwdio are respectively the first parasitic capacitance C1 (as shown). Figure 5 (as shown) and the second parasitic capacitance C2 (as shown) Figure 5 (As shown).

[0081] Ideally, when a higher oscillation frequency is required, simply reducing the relevant capacitors in the voltage-controlled oscillator (VCO) is sufficient. However, the parasitic capacitances of the VCO can easily lead to errors between the actual frequency of the VCO and the calculated frequency obtained during simulation. Specifically, the first parasitic capacitance C1 and the second parasitic capacitance C2 are redundant capacitors of the VCO and exhibit non-linear changes, thus easily causing errors between the actual frequency of the VCO and the calculated frequency obtained during simulation.

[0082] When the N-type well region 110 is connected to a fixed potential, the equivalent capacitance formed by the reverse-biased diodes rwdio and dnwdio is the first parasitic capacitance C1. In this embodiment, by floating the N-type well region 110, a first parasitic capacitance C1 and a second parasitic capacitance C2 are obtained in series. The equivalent series capacitance of the reverse-biased diodes rwdio and dnwdio is C1*C2 / (C1+C2). This equivalent series capacitance is less than the capacitance of the first parasitic capacitance C1, thereby reducing the parasitic capacitance of the substrate 100, and thus reducing the impact on the actual frequency of the voltage-controlled oscillator and the phase noise of the voltage-controlled oscillator.

[0083] In this embodiment, a gate structure 200 is formed on the substrate 100, and the gate structure 200 is used as the gate G of the NMOS crystal.

[0084] The gate structure 200 can be a polysilicon gate structure or a metal gate structure.

[0085] In this embodiment, an active doped region 210s is formed in the P-type well region 140 on one side of the gate structure 200, and a drain doped region 210d is formed in the P-type well region 140 on the other side of the gate structure 200.

[0086] The source doped region 210s serves as the source S of the NMOS transistor, and the drain doped region 210d serves as the drain D of the NMOS transistor.

[0087] In this embodiment, both the source doped region 210s and the drain doped region 210d are N-type heavily doped (N+) regions.

[0088] In this embodiment, the P-type well region 140 of the NMOS transistor also has a first P-type contact region 145 isolated from the source S, and the first P-type contact region 145 is used as the body terminal of the corresponding P-type well region 140.

[0089] The first P-type contact region 145 is used as an electrical connection location for applying a potential to the P-type well region 140.

[0090] In this embodiment, the first P-type contact region 145 is a heavily doped (P+) P-type region, and the ion doping concentration of the first P-type contact region 145 is greater than the doping concentration of the P-type well region 140, so as to reduce the contact resistance of the first P-type contact region 145.

[0091] In this embodiment, the body terminal Bulk and the source terminal S of the first transistor 41 are connected and are both connected to the current source 30, and the body terminal Bulk and the source terminal S of the second transistor 42 are connected and are both connected to the current source 30.

[0092] Since the N-type well region 110 isolates the body substrate and the external substrate of the NMOS transistor, the body terminal Bulk and the source S of the NMOS transistor can be connected without affecting the potential connection mode of the substrate 100 (i.e., the external substrate). The potential difference (i.e., Vbs) between the body terminal Bulk and the source S is zero, which can improve or eliminate the substrate bias effect of the NMOS transistor, thereby improving the phase noise of the voltage-controlled oscillator.

[0093] It should be noted that in this embodiment, both the first transistor 41 and the second transistor 42 are NMOS transistors.

[0094] When both the first transistor and the second transistor are PMOS transistors, since an N-type well region is usually formed in the substrate of the PMOS transistor, and the N-type well region has a body terminal, and the PMOS transistor has an independent body substrate, it is easy to connect the body terminal and the source of the PMOS transistor without affecting the potential connection method of the substrate 100.

[0095] In this embodiment, the substrate 100 of the NMOS transistor also has a second P-type contact region 130 that is isolated from the N-type well region 110. The second P-type contact region 130 is used as an external terminal of the corresponding substrate 100.

[0096] The second P-type contact area 130 is used as an electrical connection location for applying a potential to the substrate 100.

[0097] In this embodiment, the substrate 100 is grounded, therefore, the second P-type contact area 130 is grounded VSS.

[0098] As can be seen from the above analysis, when the body terminal Bulk and the source terminal S of the NMOS transistor in the negative resistance circuit can be connected, the substrate 100 can still be grounded to VSS.

[0099] In this embodiment, the second P-type contact region 130 is a heavily doped (P+) P-type region, and the ion doping concentration of the second P-type contact region 130 is greater than the ion doping concentration of the substrate 100, so as to reduce the contact resistance of the second P-type contact region 130.

[0100] Accordingly, embodiments of the present invention also provide a phase-locked loop, wherein the phase-locked loop includes the voltage-controlled oscillator provided in embodiments of the present invention.

[0101] In this embodiment, since the phase noise of the voltage-controlled oscillator is relatively small, the frequency of the output signal of the voltage-controlled oscillator is more stable and the jitter is smaller, which in turn makes the phase noise of the phase-locked loop smaller, which is beneficial for generating a high-speed clock signal with low phase noise.

[0102] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A voltage-controlled oscillator, characterized in that, include: A resonant circuit, the resonant circuit having a first output terminal and a second output terminal; Current source; The negative resistance circuit includes a first transistor and a second transistor, both of which are NMOS transistors. The substrate of the NMOS transistor is a P-type substrate; the P-type substrate is grounded; The NMOS transistor has a P-type well region in its substrate and an N-type well region surrounding the P-type well region. The N-type well region is used to isolate the P-type well region of the NMOS transistor from the substrate. The N-type well region is floating. The P-type well region has a body terminal. The N-type well region exposed on the substrate surface has an N-type contact region, which is used as an external terminal of the corresponding N-type well region. The drain of the first transistor and the gate of the second transistor are both connected to the first output terminal, the gate of the first transistor and the drain of the second transistor are both connected to the second output terminal, the body terminal and the source terminal of the first transistor are connected together and are both connected to the current source, and the body terminal and the source terminal of the second transistor are connected together and are both connected to the current source.

2. The voltage-controlled oscillator as described in claim 1, characterized in that, The N-type well region includes: a first N-type well region located at the bottom of the P-type well region, wherein the projection of the P-type well region in the first N-type well region is located inside the first N-type well region, and the first N-type well region is a deep N-type well region. A second N-type well region surrounds the P-type well region, and the second N-type well region is connected to the corresponding first N-type well region. The ion doping concentration of the second N-type well region is less than that of the first N-type well region.

3. The voltage-controlled oscillator as described in claim 1, characterized in that, The NMOS transistor also has a first P-type contact region isolated from the source in its P-type well region, and the first P-type contact region serves as the body terminal of the corresponding P-type well region.

4. The voltage-controlled oscillator as described in claim 1, characterized in that, The substrates of the NMOS transistors each have a second P-type contact region isolated from the N-type well region, and the second P-type contact region is used as an external terminal of the corresponding substrate.

5. The voltage-controlled oscillator as described in claim 1, characterized in that, The resonant circuit includes an inductor and a capacitor connected in parallel. The two ends of the inductor are respectively coupled to the first output terminal and the second output terminal; The two ends of the capacitor are respectively coupled to the first output terminal and the second output terminal.

6. The voltage-controlled oscillator as described in claim 5, characterized in that, The capacitor includes one or both of the following: a variable capacitor and a capacitor matrix.

7. A phase-locked loop, characterized in that, The voltage-controlled oscillator includes any one of claims 1 to 6.

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