A multi-core processor, a multi-core processor processing method and related devices

Abstract

A multi-core processor, a processing method and a related device, wherein the multi-core processor (100) comprises a master processing core (101) and a slave processing core (102) coupled to the master processing core (101); the master processing core (101) has a first instruction space, and the slave processing core (102) has a second instruction space; the master processing core (101) is configured to execute a first code segment in a target program, the target program further comprising a second code segment; the first code segment is a code segment compatible with the first instruction space, and the second code segment is a code segment compatible with the second instruction space; the master processing core (101) is configured to send an address of the second code segment to the slave processing core (102) through a configuration interface of the slave processing core (102); the slave processing core (102) comprising the configuration interface is configured to receive the address of the second code segment through the configuration interface; and the slave processing core (102) is configured to load and execute the second code segment according to the address of the second code segment. The processing method can improve the flexibility and processing efficiency of the multi-core processor.

Description

Technical Field

[0001] This application relates to the field of processor technology, and in particular to a multi-core processor, a multi-core processor processing method, and related equipment. Background Technology

[0002] With continuous research and development in recent years, multi-core architecture, represented by multi-core processors, has gradually replaced single-core processors as the main way to improve processor performance. A multi-core processor integrates multiple processor cores on a single chip. These processor cores have the same or different functions and structures, and are integrated into the same chip in an efficient way. Applications are allocated to different microprocessor cores for parallel processing in an efficient partitioning manner, thereby improving the performance of the microprocessor system.

[0003] From the perspective of the processor core architecture, multi-core processors are divided into homogeneous multi-core processors and heterogeneous multi-core processors. Homogeneous and heterogeneous are the two main structural forms of multi-core processors. In a homogeneous multi-core processor chip, all cores have identical structures, and each core has equal status. A heterogeneous multi-core processor chip uses multiple cores with different functions. It typically consists of a master core responsible for management and scheduling and slave cores responsible for computation, or it may consist of multiple cores performing different computational functions such as fixed-point, floating-point, and special-purpose calculations. From an application perspective, most current homogeneous multi-core processors consist of general-purpose processor cores, each of which can execute tasks independently, similar to the structure of a general-purpose single-core processor. Heterogeneous multi-core processors typically integrate multiple types of processor cores, including a central processing unit (CPU), a digital signal processor (DSP), a graphics processing unit (GPU), a field-programmable gate array (FPGA), and a network processor. The central processing unit core often acts as the master core, controlling other slave processor cores and performing general-purpose calculations, while the other slave processor cores are used to accelerate specific applications to meet different needs, thereby improving the overall computing performance of the processor.

[0004] In summary, heterogeneous multi-core processors can distribute different types of computing tasks across different types of processor cores for parallel processing, thus providing a more flexible and efficient processing mechanism for applications with diverse needs. However, due to the heterogeneity among the multiple processor cores in a heterogeneous multi-core processor—such as different architectures, instruction sets, and interfaces—it is difficult for the main processor core to flexibly and effectively schedule and control the slave processor cores. Therefore, providing a flexible and efficient communication mechanism between processor cores is an urgent problem to be solved. Summary of the Invention

[0005] This invention provides a multi-core processor, a multi-core processor processing method, and related equipment to improve the flexibility and processing efficiency of multi-core processors.

[0006] In a first aspect, embodiments of the present invention provide a multi-core processor, which may include a main processing core and a slave processing core coupled to the main processing core; the main processing core has a first instruction space, and the slave processing core has a second instruction space; wherein, the main processing core is configured to: execute a first code segment in a target program, the target program further including a second code segment; the first code segment is a code segment compatible with the first instruction space, and the second code segment is a code segment compatible with the second instruction space; send the address of the second code segment to the slave processing core through a configuration interface of the slave processing core; the slave processing core including the configuration interface is configured to: receive the address of the second code segment through the configuration interface; load the second code segment according to the address of the second code segment and execute the second code segment.

[0007] This invention provides a processing architecture and method for achieving efficient collaboration among multiple processing cores in a multi-core processor, specifically including hardware and software designs. From a hardware perspective, this invention adds a configurable interface to each slave processing core for the master processing core to configure and control. From a software perspective, the master processing core executes a first code segment in the target program that is compatible with its own instruction space (this target program consists of multiple heterogeneous code segments, and at least includes a second code segment), and uses the aforementioned configuration interface to indicate the address of the second code segment compatible with its own instruction space to the slave processing cores. This allows the slave processing core to execute tasks compatible with itself in the target program using only its own independent instruction space and computing power. In other words, under the overall design architecture of the multi-core processor described above, the master processing core can control the slave processing cores through the configuration interface, and the slave processing cores execute the code segment based on their own independent instruction space under the control of the master processing core. This achieves the function of efficient execution of heterogeneous fused code within the same processor, controlled by the master processing core and executed collaboratively by the master processing core and one or more slave processing cores.

[0008] In one possible implementation, the main processing core is further configured to: send state configuration parameters required for executing the second code segment to the slave processing core through the configuration interface; the slave processing core is further configured to: configure parameters according to the state configuration parameters received by the configuration interface. Further, in this embodiment of the invention, the main processing core configures the necessary conditions (e.g., state parameters of relevant registers) for the slave processing core when executing the second code segment through the aforementioned configuration interface, enabling the slave processing core to execute tasks compatible with itself in the target program using only its own independent instruction space and computing power, without needing to obtain relevant conditions from the main processing core by sharing or occupying the main processor's instruction space. This ensures that the program logic between the main and slave processing cores is unified and self-consistent, while the instruction spaces remain independent and do not generate semantic conflicts. In the overall design architecture of the multi-core processor described above, the main processing core configures the necessary states of the relevant processing components for the slave processing cores to execute the corresponding heterogeneous code segments. The slave processing cores can then execute the code segments based on their own independent instruction spaces under the control of the main processing core. This achieves the function of executing heterogeneous fused code efficiently in the same processor, controlled by the main processing core and executed collaboratively by the main processing core and one or more slave processing cores.

[0009] In one possible implementation, the main processing core is further configured to: send code execution instructions to the slave processing core through the configuration interface; the slave processing core is specifically configured to: after receiving the code execution instructions through the configuration interface, load the second code segment according to the address of the second code segment and execute the second code segment. In this embodiment of the invention, after configuring the slave processing core, the main processing core can send code execution instructions to the slave processing core, thereby activating the slave processing core to execute the second code segment.

[0010] In one possible implementation, the main processing core is further configured to configure the task exit conditions of the slave processing core through the configuration interface. The exit conditions include one or more of the following: task interruption conditions, task termination conditions, illegal operation of the slave processing core, and priority that the slave processing core cannot process. The slave processing core is further configured to determine whether to stop executing the second code segment based on the task exit conditions during the execution of the second code segment. In this embodiment of the invention, the main processing core further configures the exit conditions of the slave processing core through the configuration interface, that is, it determines relevant conditions such as interruption, termination, illegal operation, and inaccessible address during code execution, so that the behavior of the slave processing core during the execution of the second code segment is constrained by the main processing core, that is, under the control of the main processing core, to prevent the slave processing core from overstepping its authority or boundaries.

[0011] In one possible implementation, the second code segment is a task created as a function in the target program; the main processing core is further configured to: configure the slave processing core to execute the second code segment via a function call through the configuration interface. In this embodiment of the invention, the second code segment is a function part of the target program. When the main processing core needs to execute the second code segment during the execution of the target program, it configures and calls the slave processing core in a synchronous function call manner. It is understood that, according to the attributes and characteristics of the function, when the slave processing core executes the second code segment, it is necessary to suspend the code segments being executed in the main processing core and / or other slave processing cores, wait for the second code segment on the slave processing core to complete execution and obtain the execution result, before further executing or resuming the execution of code segments in the target program that are compatible with other processing cores (including the main processing core and other slave processing cores).

[0012] In one possible implementation, the second code segment is a task created as a thread in the target program; the main processing core is further configured to: configure the slave processing core to execute the second code segment via a thread call through the configuration interface. In this embodiment of the invention, the second code segment is a heterogeneous thread in the target program. When the main processing core needs to execute the second code segment during the execution of the target program, it configures and calls the slave processing core in an asynchronous thread call manner. It is understood that, based on the attributes and characteristics of threads, when the slave processing core executes the second code segment, it is not necessary to suspend the code segments being executed in the main processing core and / or other slave processing cores, that is, it is not necessary to wait for the second code segment on the slave processing core to finish executing. Code segments in the target program that are compatible with other processing cores (including the main processing core and other slave processing cores) can still be executed in parallel. It is understood that the thread and the threads in the main processing core or other slave processing cores can belong to the same process, and multiple threads can share some resources under their respective processes.

[0013] In one possible implementation, the second code segment is a task created as a process in the target program; the main processing core is further configured to: configure the slave processing core to execute the second code segment via a process call through the configuration interface. In this embodiment of the invention, the second code segment is a heterogeneous process in the target program. When the main processing core needs to execute the second code segment during the execution of the target program, it configures and calls the slave processing core in an asynchronous or synchronous process call manner. Specifically, based on the attributes and characteristics of asynchronous process calls, when a slave processing core is executing a second code segment, it is not necessary to suspend the code segments being executed on the main processing core and / or other slave processing cores. That is, it is not necessary to wait for the second code segment on the slave processing core to complete execution; code segments in the target program compatible with other processing cores (including the main processing core and other slave processing cores) can still be executed in parallel. However, based on the attributes and characteristics of synchronous process calls, when a slave processing core is executing a second code segment, it is necessary to suspend the code segments being executed on the main processing core and / or other slave processing cores, waiting for the second code segment on the slave processing core to complete execution and obtain the execution result before further execution or resumption of code segments in the target program compatible with other processing cores (including the main processing core and other slave processing cores). It is understandable that this process and processes in the main processing core or other slave processing cores cannot share related resources; therefore, the main processing core needs to pre-configure the relevant data structures (page tables) of the Memory Management Unit (MMU) for the slave processing cores.

[0014] In one possible implementation, the second code segment is a task created in the form of a virtual machine within the target program; the main processing core is further configured to: configure the slave processing core to execute the second code segment via a virtual machine call through the configuration interface. In this embodiment of the invention, the second code segment serves as a heterogeneous virtual machine within the target program. When the main processing core needs to execute the second code segment during the execution of the target program, it configures and calls the slave processing core using an asynchronous virtual machine call. Specifically, based on the attributes and characteristics of asynchronous virtual machine calls, when a slave processor is executing a second code segment, it is not necessary to suspend the code segments being executed on the main processor and / or other slave processors. That is, it is not necessary to wait for the second code segment on the slave processor to complete execution; code segments in the target program compatible with other processors (including the main processor and other slave processors) can still be executed in parallel. However, based on the attributes and characteristics of synchronous virtual machine calls, when a slave processor is executing a second code segment, it is necessary to suspend the code segments being executed on the main processor and / or other slave processors, waiting for the second code segment on the slave processor to complete execution and obtain the execution result before further execution or resumption of code segments in the target program compatible with other processors (including the main processor and other slave processors). It is understandable that before configuring a slave processor, the main processor needs to load the virtual machine image of the slave processor into shared memory, and this virtual machine cannot share resources with virtual machines in the main processor or other slave processors. Optionally, the main processor can also set a physical memory range for the slave processor.

[0015] In one possible implementation,

[0016] The state configuration parameters corresponding to the second code segment include one or more of the following: configuration parameters associated with the second code segment stored in a general-purpose register, configuration parameters associated with the second code segment stored in a system register, and state setting parameters that affect the behavior of the slave processor running the second code segment. In this embodiment of the invention, the master processor writes the configuration parameters associated with the target code segment into a general-purpose register or a system register through the slave processor's configuration interface. For example, this includes the types and initial values ​​of some variables, or it configures the target slave processor with any other state setting parameters that may affect the behavior of the target slave processor running the second code segment through the configuration interface.

[0017] In one possible implementation, the state configuration parameter corresponding to the second code segment is either a parameter accessed via address read / write or an instruction control parameter. In this embodiment, the specific configuration method for the state configuration parameter of the second code segment can be to indicate the memory address of the state configuration parameter value to the slave processing core via address access, so that the slave processing core can read its corresponding state configuration parameter according to the access address; alternatively, the state configuration parameter can also be configured for the slave processing core via instruction indication, that is, the state configuration parameter value can be directly indicated via instruction. This is because some types of processing cores do not allow configuration via instruction control, meaning that external devices do not have permission to control the processing core via instructions. Therefore, the above method can be applied to chip products with different requirements.

[0018] In one possible implementation, the main processing core and the slave processing cores share on-core resources and / or off-core resources. The on-core resources include computing resources, and the off-core resources include one or more of a memory management unit, cache, and memory. In this embodiment of the invention, the main processing core and one or more slave processing cores may share only on-core resources, only off-core resources, or both. That is, multi-core processors with different architectures can be designed according to the requirements of processors under different architectures. For example, the second code segment can be loaded into the shared memory between the main processing core and the slave processing cores, meaning both can access it based on the same access address.

[0019] In one possible implementation, the slave processing core is further configured to: store the execution result of the second code segment; the master processing core is further configured to read the execution result from the slave processing core through the configuration interface, and continue executing the target program according to the execution result. In this embodiment of the invention, after executing the second code segment, the slave processing core can store the execution result in its internal register, so that the master processing core can subsequently read the execution result stored in the slave processing core through the configuration interface, and thus participate in the subsequent execution of the target program.

[0020] Secondly, this application provides a processing method for a multi-core processor, applied to a multi-core processor, wherein the multi-core processor may include a main processing core and slave processing cores coupled to the main processing core; the main processing core has a first instruction space, and the slave processing cores have a second instruction space; the method includes:

[0021] The first code segment in the target program is executed by the main processing core, and the target program further includes a second code segment; the first code segment is a code segment compatible with the first instruction space, and the second code segment is a code segment compatible with the second instruction space;

[0022] The address of the second code segment is sent from the main processing core to the slave processing core;

[0023] The process involves receiving the address of the second code segment from the processing core, loading the second code segment based on its address, and executing the second code segment.

[0024] In one possible implementation, the method further includes: sending state configuration parameters required for executing the second code segment to the slave processing core via the main processing core; and configuring parameters via the state configuration parameters received by the slave processing core.

[0025] In one possible implementation, the method further includes: sending a code execution instruction to the slave processing core through the main processing core; the step of loading and executing the second code segment according to the address of the second code segment includes: after the slave processing core receives the code execution instruction, loading and executing the second code segment according to the address of the second code segment.

[0026] In one possible implementation, the method further includes: configuring a task exit condition for the slave processing core via the main processing core, the exit condition including one or more of a task interruption condition, a task termination condition, an illegal operation of the slave processing core, and a priority that the slave processing core cannot process; and determining whether to stop executing the second code segment based on the task exit condition during the execution of the second code segment via the slave processing core.

[0027] In one possible implementation, the second code segment is a task created in the form of a function in the target program; the method further includes: configuring the slave processing core to execute the second code segment in the form of a function call through the main processing core.

[0028] In one possible implementation, the second code segment is a task created in the form of a thread in the target program; the method further includes: configuring the slave processing core to execute the second code segment in the form of a thread call through the main processing core.

[0029] In one possible implementation, the second code segment is a task created as a process in the target program; the method further includes: configuring the slave processing core to execute the second code segment as a process call through the main processing core.

[0030] In one possible implementation, the second code segment is a task created in the form of a virtual machine in the target program; the method further includes: configuring the slave processing core to execute the second code segment in the form of a virtual machine call through the main processing core.

[0031] In one possible implementation, the state configuration parameters corresponding to the second code segment include one or more of the following: configuration parameters associated with the second code segment stored in a general-purpose register, configuration parameters associated with the second code segment stored in a system register, and state setting parameters that affect the behavior of running the second code segment from the processing core.

[0032] In one possible implementation, the state configuration parameter corresponding to the second code segment is a parameter accessed via address read / write or an instruction control parameter.

[0033] In one possible implementation, the main processing core and the at least one or more slave processing cores share in-core resources and / or out-of-core resources, wherein the in-core resources include computing resources and the out-of-core resources include one or more of memory management units, caches, and memory.

[0034] In one possible implementation, the method further includes: storing the execution result of the second code segment through the slave processing core; reading the execution result from the slave processing core through the main processing core, and continuing to execute the target program based on the execution result.

[0035] Thirdly, this application provides a multi-core processor, which may include: a main processing core having a first instruction space, configured to: execute a first code segment in a target program, the target program further including a second code segment, the first code segment being a code segment compatible with the first instruction space, the second code segment being a code segment compatible with a second instruction space; and call a slave processing core coupled to the main processing core and having the second instruction space to execute the second code segment.

[0036] This invention provides a processing architecture and method for achieving efficient collaboration among multiple processing cores in a multi-core processor. The main processing core executes a first code segment in a target program that is compatible with its own instruction space (the target program consists of multiple heterogeneous code segments, and at least includes a second code segment). It then uses the aforementioned configuration interface to indicate the address of the second code segment, compatible with its own instruction space, to the slave processing cores. This allows the slave processing cores to execute tasks compatible with itself within the target program using only their own independent instruction space and computing power. In other words, within the overall design architecture of the multi-core processor, the main processing core can control and invoke the slave processing cores, while the slave processing cores, under the control and invocation of the main processing core, execute the code segment based on their own independent instruction space. This achieves the function of efficient execution of heterogeneous fused code within the same processor, controlled by the main processing core and executed collaboratively by the main processing core and one or more slave processing cores.

[0037] In one possible implementation, the main processing core is specifically used to: invoke the slave processing core to execute the second code segment through the slave processing core's configuration interface.

[0038] In one possible implementation, the main processing core is specifically used to: execute the first code segment in the target program using the first instruction space; the slave processing core is specifically used to: execute the second code segment in the target program using the second instruction space.

[0039] In one possible implementation, the first code snippet and the second code snippet are code snippets compiled by different compilers.

[0040] In one possible implementation, the first instruction space is Complex Instruction Set Computing (CISC), and the second instruction space is Reduced Instruction Set Computing (RISC).

[0041] Fourthly, this application provides a multi-core processor, which may include: an application to a multi-core processor, the multi-core processor including a main processing core and slave processing cores coupled to the main processing core; the main processing core having a first instruction space and the slave processing core having a second instruction space; the method includes:

[0042] The first code segment in the target program is executed by the main processing core, and the target program further includes a second code segment. The first code segment is a code segment compatible with the first instruction space, and the second code segment is a code segment compatible with the second instruction space.

[0043] The second code segment is executed by the slave processing core invoked by the main processing core.

[0044] The second code segment in the target program is executed from the processing core.

[0045] In one possible implementation, the step of calling the slave processing core to execute the second code segment through the main processing core includes: calling the slave processing core to execute the second code segment through the configuration interface of the slave processing core by the main processing core.

[0046] In one possible implementation, executing the first code segment in the target program through the main processing core includes: executing the first code segment in the target program through the main processing core using the first instruction space;

[0047] The execution of the second code segment in the target program via the slave processing core includes: executing the second code segment in the target program via the slave processing core using the second instruction space.

[0048] In one possible implementation, the first code snippet and the second code snippet are code snippets compiled by different compilers.

[0049] In one possible implementation, the first instruction space is Complex Instruction Set Computing (CISC), and the second instruction space is Reduced Instruction Set Computing (RISC).

[0050] Fifthly, this application provides a semiconductor chip that may include a multi-core processor provided by any of the implementations of the first aspect described above.

[0051] Sixthly, this application provides a semiconductor chip that may include a multi-core processor provided by any of the implementations of the third aspect above.

[0052] In a seventh aspect, this application provides a semiconductor chip that may include: a multi-core processor provided by any of the implementations of the first aspect above, an internal memory coupled to the multi-core processor, and an external memory.

[0053] Eighthly, this application provides a semiconductor chip that may include: a multi-core processor provided by any of the implementations of the third aspect above, an internal memory coupled to the multi-core processor, and an external memory.

[0054] Ninthly, this application provides a system-on-a-chip (SoC) chip, which includes a multi-core processor, internal memory coupled to the multi-core processor, and external memory provided by any implementation of the first aspect above. The SoC chip may be composed of chips or may include chips and other discrete devices.

[0055] In a tenth aspect, this application provides a system-on-a-chip (SoC) chip, which includes a multi-core processor, internal memory coupled to the multi-core processor, and external memory provided by any implementation of the first aspect described above. The SoC chip may be composed of chips or may include chips and other discrete devices.

[0056] Eleventhly, this application provides a chip system including a multi-core processor provided by any implementation of the first aspect above. In one possible design, the chip system further includes a memory for storing program instructions and data necessary or related to the operation of the multi-core processor. The chip system may be composed of chips or may include chips and other discrete devices.

[0057] In a twelfth aspect, this application provides a chip system comprising a multi-core processor provided in any of the implementations of the third aspect above. In one possible design, the chip system further includes a memory for storing program instructions and data necessary or related to the operation of the multi-core processor. This chip system may be composed of chips or may include chips and other discrete devices.

[0058] In a thirteenth aspect, this application provides a processing apparatus having the function of implementing any of the multi-core processor processing methods described in the first aspect above. This function can be implemented in hardware or by hardware executing corresponding software. The hardware or software includes one or more modules corresponding to the aforementioned function.

[0059] In a fourteenth aspect, this application provides a processing apparatus having the function of implementing any of the multi-core processor processing methods described in the third aspect above. This function can be implemented in hardware or by hardware executing corresponding software. The hardware or software includes one or more modules corresponding to the aforementioned function.

[0060] In a fifteenth aspect, this application provides a terminal including a multi-core processor, which is a multi-core processor provided in any of the implementations of the first aspect described above. The terminal may also include a memory coupled to the multi-core processor, which stores necessary program instructions and data for the terminal. The terminal may also include a communication interface for communicating with other devices or communication networks.

[0061] In a sixteenth aspect, this application provides a terminal including a multi-core processor, which is a multi-core processor provided in any of the implementations of the third aspect described above. The terminal may also include a memory coupled to the multi-core processor, which stores necessary program instructions and data for the terminal. The terminal may also include a communication interface for communicating with other devices or communication networks.

[0062] In a seventeenth aspect, this application provides a computer-readable storage medium storing a computer program that, when executed by a multi-core processor, implements the processing method flow of the multi-core processor as described in any one of the second aspects above.

[0063] In an eighteenth aspect, this application provides a computer-readable storage medium storing a computer program that, when executed by a multi-core processor, implements the processing method flow of the multi-core processor as described in any one of the fourth aspects above.

[0064] In a nineteenth aspect, embodiments of the present invention provide a computer program including instructions that, when executed by a multi-core processor, cause the multi-core processor to execute the processing method flow of the multi-core processor described in any of the second aspects above.

[0065] In a twentieth aspect, embodiments of the present invention provide a computer program including instructions that, when executed by a multi-core processor, cause the multi-core processor to execute the processing method flow of the multi-core processor described in any of the fourth aspects above. Attached Figure Description

[0066] Figure 1 This is a schematic diagram of the architecture of a multi-core processor in coprocessor mode provided in an embodiment of the present invention.

[0067] Figure 2 This is a schematic flowchart illustrating another method for translating a high-level program into processor-recognizable instructions, as provided in an embodiment of the present invention.

[0068] Figure 3 This is a schematic diagram of the architecture of a multi-core processor with a multi-mode processor mode provided in an embodiment of the present invention.

[0069] Figure 4 This is a schematic diagram of the structure of a multi-core processor provided in an embodiment of the present invention.

[0070] Figure 5 This invention provides a schematic flowchart of heterogeneous program synthesis and compilation.

[0071] Figure 6This is a schematic diagram of the structure of a processing core provided in an embodiment of the present invention.

[0072] Figure 7 This is a schematic diagram of an architecture for a multi-core processor to share external resources, provided as an embodiment of the present invention.

[0073] Figure 8 This is a schematic diagram of another architecture for a multi-core processor to exclusively enjoy external resources, provided in an embodiment of the present invention.

[0074] Figure 9 This is a flowchart illustrating a multi-core processor processing method provided in an embodiment of the present invention.

[0075] Figure 10 This is a schematic diagram of another multi-core processor provided in an embodiment of the present invention.

[0076] Figure 11 This is a flowchart illustrating another multi-core processor processing method provided in an embodiment of the present invention. Detailed Implementation

[0077] The embodiments of the present invention will now be described with reference to the accompanying drawings. The terms "first," "second," "third," and "fourth," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish different objects, not to describe a specific order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or devices. The reference to "embodiment" herein means that a specific feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0078] As used in this specification, the terms "component," "module," "system," etc., are used to refer to computer-related entities, hardware, firmware, combinations of hardware and software, software, or software in execution. For example, a component can be, but is not limited to, a process running on a processor, a processor, an object, an executable file, an execution thread, a program, and / or a computer. As illustrated, applications running on computing devices and computing devices can both be components. One or more components may reside in a process and / or an execution thread, and components may be located on a single computer and / or distributed among two or more computers. Furthermore, these components can be executed from various computer-readable media on which various data structures are stored. Components can communicate, for example, via local and / or remote processes based on signals having one or more data packets (e.g., data from two components interacting with another component between a local system, a distributed system, and / or a network, such as the Internet interacting with other systems via signals).

[0079] First, some of the terms used in this application will be explained to facilitate understanding by those skilled in the art.

[0080] (1) Application Binary Interface (ABI): Every operating system provides an Application Binary Interface (ABI) for applications running on that system. The ABI contains the programming conventions that applications must adhere to when running on that system. The ABI always includes a set of system calls and methods for using these system calls, as well as rules regarding the memory addresses a program can use and the use of machine registers. From an application's perspective, the ABI is both part of the system architecture and a key aspect of the hardware architecture; therefore, violating either constraint can lead to serious program errors. In many cases, the linker needs to do significant work to comply with the ABI's conventions. For example, the ABI requires each application to contain a table of all addresses of static data used by routines within the program; the linker creates this table by collecting address information from all modules linked to the program. The definition of standard procedure calls is a frequent influence of the ABI on the linker.

[0081] (2) General-purpose registers can be used to transfer and temporarily store data, participate in arithmetic and logical operations, and save the results of the operations. In addition, they each have some special functions.

[0082] (3) Intellectual Property Core (IP Core) is short for integrated circuit core with intellectual property rights. An IP core is a pre-designed, even verified, integrated circuit, device, or component with a specific function. Based on its hardware description level implementation, IP cores can be divided into three categories: soft cores, hard cores, and solid cores.

[0083] Soft core: Primarily describes the functionality and is submitted to the user in HDL (Hardware Description Language) text format.

[0084] Solid core: Primarily describes the architecture, falling between soft core and hard core, and is provided to the user in the form of a gate-level netlist.

[0085] The core technology is based on physical description and has been verified by the manufacturing process. It is provided to users with a physical structure mask diagram of the circuit and a complete set of process documents.

[0086] (4) The main functions of the Memory Management Unit (MMU) are to translate virtual memory addresses into physical addresses; control access permissions; and set up a buffer for virtual memory space.

[0087] (5) Field Programmable Gate Array (FPGA) is a further development based on programmable devices such as Programmable Array Logic (PAL) and Generic Array Logic (GAL). It emerged as a semi-custom circuit in the field of Application Specific Integrated Circuit (ASIC), solving the shortcomings of custom circuits and overcoming the limitation of the limited gate count of the original programmable devices.

[0088] (6) Pointers: In C, variables are stored in memory, which is essentially an array of ordered bytes, each with a unique memory address. The CPU locates the address of a specific data object stored in memory through memory addressing. Here, a data object refers to a numerical value or string of a specific data type stored in memory; each has its own address, and a pointer is a variable that stores this address. In other words, a pointer is a variable that stores the address of another variable.

[0089] (7) Multi-core processors: Due to the limitations of semiconductor manufacturing processes, it is no longer realistic to continue producing high-performance single-core processors, and there are no solutions to the resulting power consumption and heat dissipation problems. In this situation, more and more semiconductor manufacturers tend to manufacture multi-core processors with lower power consumption and balanced performance to improve the overall performance of the processor. According to whether the core architecture is the same, they can be divided into homogeneous multi-core and heterogeneous multi-core.

[0090] (8) An integrated circuit (IC) is a miniature electronic device or component. Using certain processes, the transistors, resistors, capacitors, inductors, and other components required for a circuit, along with their interconnections, are fabricated on a small piece or several small pieces of semiconductor wafers or dielectric substrates, and then packaged in a casing to form a miniature structure with the required circuit function; that is, an IC chip is an integrated circuit formed by placing a large number of microelectronic components (transistors, resistors, capacitors, etc.) on a plastic substrate to make a chip.

[0091] (9) Computer instructions are the instructions and commands that direct the machine to work. A program is a series of instructions arranged in a certain order, and the process of executing a program is the working process of a computer. An instruction set is a set of instructions used by the CPU to calculate and control the computer system. Each CPU is designed with a set of instructions that work in conjunction with its hardware circuitry. The strength of the instructions is also an important indicator of the CPU. The instruction set is one of the most effective tools for improving the efficiency of a microprocessor. Common instruction set architectures (ISAs) include Complex Instruction Set Computing (CISC) and Reduced Instruction Set Computing (RISC). The typical representative of CISC is x86, and the typical representatives of RISC are the Advanced RISC Machine (ARM) architecture and the Microprocessor without interlocked pipelined stages (MIPS) architecture.

[0092] (10) Instruction space is the set of all instructions. Since an instruction is represented as a number, the range of values ​​for this number in modern CPUs is often fixed, or at least subject to length constraints. These constraints limit the number of instructions. In CPU design, instruction space is a valuable resource because it must be allocated not only to the instructions currently used by the CPU but also to future, past, and potential instructions, which significantly restricts the number of usable instructions. Forcibly expanding this space would increase the cost of CPU decoding, making instruction space a crucial design constraint in CPU architecture design. It should be noted that instruction space and instruction set represent the same concept but emphasize different design constraints. Instruction set emphasizes the semantics and expressive power of all instructions, while instruction space emphasizes the number of instructions and the various engineering implementation costs caused by this number.

[0093] (11) Halt instruction: This is a pause instruction that puts the processor into a paused state. In the paused state, the CPU does not perform any operations, and this instruction does not affect any flags. When the HALT instruction is executed, the IP is frozen in hardware, and the program is suspended until a condition arises that allows it to exit the paused state.

[0094] (12) A process is often defined as the execution of a program. A process can be viewed as an independent program with its own complete data space and code space in memory. The data and variables owned by a process belong only to itself.

[0095] (13) A thread is a program that runs independently within a process. In other words, a thread exists within a process. A process consists of one or more threads, each sharing the same code and global data, but each having its own stack. Since each thread has its own stack, local variables are private to each thread. Because all threads share the same code and global data, they are more tightly coupled than processes and more prone to interaction than individual processes. Interaction between threads is easier because they inherently share some memory for communication: the process's global data.

[0096] First, to facilitate understanding of the embodiments of the present invention, the specific technical problem to be solved by this application is further analyzed and proposed. Currently, there are various technical solutions for implementing multi-core processors; two examples are listed below.

[0097] Option 1: Coprocessor mode technical solution

[0098] like Figure 1 As shown, Figure 1This is a schematic diagram of a multi-core processor architecture in a coprocessor mode provided by an embodiment of the present invention. In this coprocessor mode, the slave processor is designed as a coprocessor of the master processor, and the two systems share the same instruction space and the same off-core resources (such as MMU, bus, cache and other structures).

[0099] like Figure 2 As shown, Figure 2 This invention provides another flowchart illustrating the translation of high-level programs into processor-recognizable instructions. From a software perspective, this model does not distinguish between master and slave processors; they are simply different functions of the same processor. Instructions from the slave processor must be incorporated into the compiler of the master processor. When instructions from the slave and master processors are used interchangeably, software solutions become difficult to isolate. Taking floating-point coprocessors as an example, the diversity of floating-point coprocessors places a heavy burden on compilers. Typically, compilers need to define different platform parameters and compile different binary programs to handle multiple coprocessor types. Therefore, the variety of coprocessors in engineering can easily lead to diverse compiler versions, resulting in incompatible generated binary programs.

[0100] The disadvantages of this first option are: the coprocessor mode requires the coprocessor to occupy the main processor's instruction space (and if the coprocessor has similar functions to the main processor, the main processor cannot handle a large number of repetitive instructions), and the coprocessor cannot run in parallel with the main processor. Furthermore, the coprocessor has a large amount of state, which means that when the main processor switches threads, it has to back up even more state.

[0101] Option 2: Multi-mode technical solution

[0102] like Figure 3 As shown, Figure 3 This is a schematic diagram of a multi-core processor architecture with a multi-mode processor mode provided by an embodiment of the present invention. A single processor can have multiple different modes (such as mode 1, mode 2, mode 3, etc.). The multi-mode multi-core processor is an improvement on the coprocessor mode. To save instruction space, the coprocessor is configured as a "mode" of the main processor. This is merely an optimization of the instruction space and does not involve significant hardware changes. For example, the Thumb instructions (a subset of the ARM instruction set) under the RISC microprocessor (Advanced RISC Machines, ARM) architecture can be considered a typical example of a multi-mode processor.

[0103] The drawbacks of this second approach are: while the multi-mode approach improves the problem of insufficient instruction space, the coprocessor still cannot run in parallel with the main processor. Furthermore, in practical implementations, the "mode change" usually treats both as the same processor, meaning there are still many shared concepts. This approach is generally unsuitable for multi-core processors that have their own dedicated instruction space.

[0104] In summary, the technical deficiencies in the existing technology mainly include the following aspects:

[0105] 1. Do the master processor and slave processor have independent instruction spaces?

[0106] 2. The question of whether the main processor and the slave processor can run in parallel.

[0107] 3. State backup issue between the master processor and slave processor.

[0108] Therefore, the technical problems to be solved by this application may include the following:

[0109] 1. The master processor and slave processor can share each other's computing power, but can still maintain their own independent instruction space; 2. The master processor can, but is not required to, run in parallel with the slave processor; 3. The master processor does not need to back up the state of the slave processor.

[0110] Based on the above, this application provides a multi-core processor. Please refer to [link / reference]. Figure 4 , Figure 4 This is a schematic diagram of a multi-core processor 10 provided in an embodiment of the present invention. The multi-core processor 10 can be located in any electronic device, such as a computer, mobile phone, tablet, or other similar devices. Specifically, the multi-core processor 10 can be a chip, a chipset, or a circuit board carrying a chip or chipset. The chip, chipset, or circuit board carrying the chip or chipset can operate under necessary software drivers.

[0111] The multi-core processor 10 may include a main processing core 101 and one or more slave processing cores 102 coupled to the main processing core 101. Figure 5Taking N slave processing cores 102 as an example, these include slave processing core 1 (Core1), slave processing core 2 (Core2), slave processing core 3 (Core3), slave processing core 4 (Core4), ... slave processing core (N-1) (Core(N-1)) and slave processing core N (CoreN). Each of these N slave processing cores 102 includes a configuration interface, namely configuration interface 1, configuration interface 2, configuration interface 3, ... configuration interface N-1, configuration interface N. The master processing core 101 can perform related configuration and control on the corresponding slave processing cores 102 through the above configuration interfaces. Optionally, the master processing core 101 and the one or more slave processing cores 102 may be located in one IC. For example, the master processing core 101 and the one or more slave processing cores 102 may be located in one IC, or the master processing core 101 may be located in one IC, and some or all of the one or more slave processing cores 102 may be located in another IC. This embodiment of the invention does not specifically limit this. It is understandable that the main processing core 101 and the N slave processing cores 102 can communicate via a bus or other means. Figure 4 The connections shown do not impose restrictions on the coupling relationships between them.

[0112] The main processing core 101 and the N slave processing cores 102 each have independent instruction spaces. The main processing core 101 has a first instruction space, and the slave processing cores 102 have a second instruction space. That is, the main processing core 101 and each of the slave processing cores 102 do not share or occupy each other's instruction spaces, and their instructions do not conflict with each other. Optionally, the main processing core 101 and any one of the N slave processing cores 102 are heterogeneous, meaning that the first instruction space of the main processing core 101 and the second instruction space of any one of the slave processing cores 102 are different. The N slave processing cores 102 can be homogeneous, heterogeneous, or partially homogeneous and partially heterogeneous. That is, the second instruction spaces of the N slave processing cores 102 can be the same or different, or partially the same and partially different. This embodiment of the invention does not specifically limit this. For example, in one application scenario, the main processing core 101 is a general-purpose processor core, and the N slave processing cores 102 are processing cores with specific functions, such as the main processing core being a general-purpose CPU, and the slave processing cores 102 being GPUs, FPGAs, DSPs, etc. That is, each slave processing core 102 has its own unique structure, and therefore each slave processing core has its own unique instruction set. The specific instruction set determines the specific application of each slave processing core, thus enabling each slave processing core to handle a type of program it excels at (i.e., the different code snippets in this application). Therefore, the main processing core 101 can distribute different types of computing tasks to different types of slave processing cores 102 for parallel processing, thereby simultaneously implementing the functions of different specific applications within the same processor, providing a more flexible and efficient processing mechanism for applications with different needs. Optionally, the first instruction space is Complex Instruction Set Computing (CISC), and the second instruction space is Reduced Instruction Set Computing (RISC). For example, both the main processing core 101 and the N slave processing cores 102 are CPU cores, but they support different instruction sets. For instance, the main processing core 101 supports the x86 instruction set, while the slave processing cores 102 support the ARM instruction set. Therefore, the main processing core 101 can be used to install and run general-purpose computer operating systems such as Windows and Linux, which can also be called desktop operating systems. The slave processing cores 102, under the control of the main processing core 101, can run applications based on the ARM instruction set, such as Android and iOS, which can also be called applications based on embedded operating systems. In other words, the main processing core 101, with its computer operating system installed, can support general-purpose computer applications, while the slave processing cores 102, supporting the ARM instruction set, can support general mobile device applications under the control of the main processing core. Thus, both PC and mobile functions are implemented within the same processor, the multi-core processor 10.

[0113] Based on the above-described hardware and software architecture of the multi-core processor, in this embodiment of the invention, the specific functions implemented by the multi-core processor 10 may include the following:

[0114] The main processing core 101 is used to execute a first code segment in a target program. The target program includes multiple heterogeneous code segments, at least including the first code segment and a second code segment. The first code segment is a code segment compatible with a first instruction space of the main processing core 101. A status configuration request is sent to the target slave processing core via a target configuration interface. The status configuration request includes the address of the second code segment. Optionally, the status configuration request also includes status configuration parameters required to execute the second code segment. The one or more slave processing cores 102 include the target slave processing core 102-4-4 (assuming...). Figure 6 The second code segment is compatible with the second instruction space of the target slave processing core 102-4 (hereinafter referred to as such, and will not be repeated hereafter). The target slave processing core 102-4 is used to configure the target through the target configuration interface (i.e.,...). Figure 6 The configuration interface 4 (which will not be described again later) receives the state configuration request and configures the parameters according to the state configuration parameters; according to the instruction pointer of the second code segment, it loads and executes the second code segment. It should be noted that in this embodiment of the invention, there are no specific limitations on the order in which the main processing core 101 executes the first code segment and the target processing cores 102-4 execute the second code segment, nor on the number of code segments (e.g., multiple first code segments or multiple second code segments). It can be understood that the first code segment and the second code segment can also be executed in parallel.

[0115] Specifically, when the multi-core processor 10 is executing a heterogeneous fused executable target program through the main processing core 101, and needs to execute a second code segment (which is a compiled executable code segment), the main processing core 101 can select a matching target slave processing core 102-4 from its coupled multiple slave processing cores 102, and send a relevant configuration request to the target slave processing core 102-4 through the target configuration interface 4 of the main processing core 101, so as to indicate to the target slave processing core 102-4 the address of the second code segment to be executed, as well as the initial environment and preconditions for executing the second code segment, so that the target slave processing core 102-4 executes its compatible second code segment under the control of the main processing core 101. The target program comprises multiple heterogeneous code segments, which are binary programs compiled by different compilers and compatible with different instruction spaces. For example, the target program includes binary programs (executable code segments) compatible with the x86 instruction set, binary programs (executable code segments) compatible with the ARM instruction set, and binary programs (executable code segments) compatible with the MIPS instruction set. The first code segment is the binary program compatible with the x86 instruction set, and the second code segment is either the binary program compatible with the ARM instruction set or the binary program compatible with the MIPS instruction set. The target slave processing core is a slave processing core among the one or more slave processing cores that is compatible with the second code segment, meaning that the instruction space of the target slave processing core is compatible with the second code segment. Furthermore, the address of the second code segment is the instruction pointer of the second code segment. For example, the target slave processing core can fetch an instruction from the address pointed to by the instruction pointer at the arrival of each instruction fetch cycle, and increment the instruction pointer to point to the address of the next instruction, until the second code segment is executed. Optionally, the state configuration parameters corresponding to the second code segment include one or more of the following: configuration parameters associated with the second code segment stored in the general-purpose registers of the target slave processing core, configuration parameters associated with the second code segment stored in the system registers of the target slave processing core, and state setting parameters that affect the behavior of the target slave processor in running the second code segment. For example, the configuration parameters stored in the general-purpose registers are data related to ordinary operations, such as the type and initial value of variables; the configuration parameters stored in the system registers are system-related data, such as global variables and the global clock; and some state parameters may affect the computational behavior of the target slave processing core 102-4 in running the second code segment, but may not necessarily be represented as registers for the second code segment. For example, when performing an addition, if there is a carry, the processing core needs to remember the carry state and will add the carry next time. This carry may not necessarily be a register, and the state configuration parameters may also include the aforementioned state setting parameters.

[0116] It should be noted that, since the main processing core 101 needs to configure the status of the target slave processing cores 102-4 through the target configuration interface, in this embodiment of the invention, the main processing core 101 needs to know the ABI and related characteristics of the registers of each of the one or more slave processing cores 102. In this way, when the main processing core needs to call the slave processing core, it can set the status configuration parameters for it according to the relevant characteristics and programming conventions, so that the slave processing core can execute the second code segment using only its own instruction space, without having to obtain the relevant status configuration parameters required to execute the second code segment by sharing or occupying the instruction space of the main processing core.

[0117] Regarding how the aforementioned heterogeneous fusion executable target program is compiled, embodiments of the present invention provide a specific solution, such as... Figure 5 As shown, Figure 5 This invention provides a schematic flowchart for heterogeneous program synthesis and compilation. For the above-described model, firstly, a unified high-level program (e.g., a program containing multiple programming languages) written for the main processing core and slave processing cores is provided. Then, each is compiled into its own independent object file (main processing core object file and slave processing core object file) using its respective pure compiler (including the compiler corresponding to the main processing core and the compiler corresponding to the slave processing core). Finally, these are linked together by a linker to form a synthesized program, which is the target program in this invention. That is, the software of the main and slave processing cores can be independently compiled by their respective compilers, and then integrated together as the target program through linking (e.g., by calling functions, creating threads, creating processes, or creating virtual machines). The object files are, for example, .o files. .o files are a type of retargetable file, usually saved in executable and linkable (ELF) format, containing entry markers and descriptions for each function. When the program needs to be executed, linking is required; linking combines multiple .o files into a single executable file. When multiple programming languages ​​are compiled together, they can be compiled separately into .o files and then linked into an executable file. It is understood that the compilation process of the target program in the embodiments of the present invention can be performed in the multi-core processor 101 (e.g., in the main processing core), or it can be executed on a device or equipment other than the multi-core processor 101. That is, as long as it includes the compilers corresponding to the above-mentioned programming languages, the specific location of compilation in the embodiments of the present invention is not specifically limited.

[0118] This invention, through standardized design of the master-slave processing core interface, logically integrates the multiple cores of a multi-core processor when processing software, providing the target program with a complete and unified software execution environment. Whether calling a slave processing core using an accelerator or directly switching to another instruction space, this can be achieved through the processing core's configuration interface, making multi-core processor calls resemble function calls, thread creation, and virtual machine creation. This allows the master processing core to directly manage slave processing cores without needing in-depth knowledge of the slave processing core's solution.

[0119] In one possible implementation, the main processing core 101 is further configured to send code execution instructions to the target slave processing core 102-4 via the target configuration interface 4. Specifically, the target slave processing core 102-4, after receiving the code execution instructions via the target configuration interface 4, loads and executes the second code segment according to its address (e.g., instruction pointer). In this embodiment, after configuring the target slave processing core 102-4, the main processing core 101 can send code execution instructions to it, thereby activating the target slave processing core to execute the second code segment. It is understood that the main processing core calls the target slave processing core through the code execution instructions, causing the target slave processing core to run. This code execution instruction can be considered to simulate the behavior of the main processing core's call instruction, except that this behavior does not occur on the main processing core, nor is it implemented through the main processing core's implementation model.

[0120] In one possible implementation, the main processing core 101 is further configured via a target configuration interface to configure the task exit conditions of the slave processing core 102. These exit conditions include one or more of the following: task interruption conditions, task termination conditions, illegal operation by the slave processing core, and an unprocessable priority for the slave processing core. The target slave processing core 102-4 is further configured to: determine whether to stop executing the second code segment based on the exit conditions during the execution of the second code segment. For example, if the target slave processing core 102-4 encounters a preset task interruption condition, performs an illegal operation (such as accessing an inaccessible address), or enters a set unprocessable priority, the target slave processing core 102-4 may stop executing the second code segment. In this embodiment of the invention, the main processing core further configures the exit conditions of the target slave processing core via a target configuration interface, i.e., judging relevant conditions such as interruption, termination, illegal operation, and inaccessible address during code execution, so that the behavior of the target slave processing core during the execution of the second code segment is constrained by the main processing core, i.e., under the control of the main processing core, to prevent the target slave processing core from overstepping its authority or boundaries. Optionally, the main processing core can wait for the slave processing core to stop, encounter an exception, or enter a specific state before continuing other operations. Alternatively, it can continue its own operations until the slave processing core terminates, then asynchronously notify the main processing core to perform the next operation.

[0121] This invention provides a processing architecture and method for achieving efficient collaboration among multiple processing cores in a multi-core processor, specifically including hardware and software designs. From a hardware perspective, this invention adds a configurable interface to each slave processing core for configuration and control by the master processing core. From a software perspective, the master processing core executes a first code segment in the target program that is compatible with its own instruction space (the target program consists of multiple heterogeneous code segments, and at least includes a second code segment). The master processing core then configures the necessary conditions for the slave processing core to execute the second code segment using the aforementioned configuration interface. This allows the target slave processing core to execute tasks compatible with itself in the target program using only its own independent instruction space and computing power, without needing to obtain relevant conditions from the master processing core by sharing or occupying the master processor's instruction space. This ensures that the program logic between the master processing core and the target slave processing core is unified and self-consistent, while the instruction spaces remain independent and do not generate semantic conflicts. In the overall design architecture of the multi-core processor described above, the main processing core configures the necessary states for the slave processing cores to execute the corresponding heterogeneous code segments. The slave processing cores then execute the code segments based on their own independent instruction spaces. This achieves the function of controlling the execution of heterogeneous fused code by the main processing core and having the main processing core and one or more slave processing cores work together to execute the code efficiently in the same processor.

[0122] In one possible implementation, embodiments of the present invention provide a structure for a slave processing core that implements the above-described configuration interface functionality, such as... Figure 6 As shown, Figure 6 This is a schematic diagram of a slave processing core 102 provided in an embodiment of the present invention. The slave processing core 102 includes a configuration interface 1021, one or more decoding and calculation units 1022, one or more state units 1023, and a storage system 1024. The configuration interface 1021 may further include a configuration unit 10211 and an exit management unit 10212. That is, by adding a configuration interface 1021 to the slave processing core, the master processing core 101 can change the working state of the slave processing core through the configuration unit 10211 in the configuration interface 1021, such as the current contents of the registers and the privilege level, and then use a "code execution instruction" to make the slave processing core start execution from a preset state. Furthermore, the configuration unit 10211 can also modify the state and trapout management conditions of the slave processing core 102. In other words, the master processing core 101 can set the slave processing core to any desired state through the configuration interface 1021 of the slave processing core 102, stop it when it oversteps its privileges, obtain its current state, and then restart.

[0123] In one possible implementation, the state configuration parameter corresponding to the second code segment is either a parameter accessed via address read / write or an instruction control parameter. In this embodiment, the specific configuration method for the state configuration parameter of the second code segment can be to indicate the memory address of the state configuration parameter value to the target slave processing core via address access, so that the target slave processing core can read its corresponding state configuration parameter according to the access address; alternatively, the state configuration parameter can also be configured for the target slave processing core via instruction indication, that is, the state configuration parameter value can be directly indicated via instruction. This is because some types of processing cores do not allow configuration via instruction control, meaning that external devices do not have permission to control the processing core via instructions. Therefore, the above-mentioned address read / write method can be applied to chip products with different requirements.

[0124] In one possible implementation, the main processing core 101 and the at least one or more slave processing cores 102 share in-core resources and / or out-of-core resources. The in-core resources include computing resources, and the out-of-core resources include one or more of a memory management unit, cache, and memory. In this embodiment of the invention, the main processing core and one or more slave processing cores may share only in-core resources, only out-of-core resources, or both. That is, multi-core processors with different architectures can be designed according to the requirements of processors under different architectures. For example, the second code segment can be loaded into the shared memory between the main processing core and the slave processing cores, meaning both can access it based on the same access address. Figure 7 As shown, Figure 7 This is a schematic diagram of an architecture for a multi-core processor sharing external resources, provided by an embodiment of the present invention. In this architecture, multiple groups of master processing cores and corresponding slave processing cores can be included. Each group of master and slave processing cores can reside on the same IC and share external resources (including MMU, cache, etc.). When a master processing core within the same group needs to utilize the computing power of a slave processing core, the master processing core can call the slave processing core through a slave processing core configuration interface, thereby achieving the goal of unified management of all resources on a multi-architecture computing system. Figure 8 As shown, Figure 8 This is a schematic diagram of another architecture for a multi-core processor to exclusively utilize external resources, provided by an embodiment of the present invention. In this architecture, there are one or more main processing cores and multiple slave processing cores. The main processing cores can be used for management and scheduling, while the slave processing cores can be used for specific performance acceleration. Each of the main processing cores and slave processing cores independently possesses external resources (including MMU, cache, etc.). When a main processing core needs the computing power of a slave processing core or needs to run an application that supports a slave processing core, the main processing core can call the slave processing core through the slave processing core configuration interface, thereby achieving the goal of unified management of all resources on a multi-architecture computing system. Optionally, in the above... Figure 7 or Figure 8 In this architecture, the main processing core and the slave processing cores can also share memory, external devices, etc. via a bus. That is to say, this application does not specifically limit the connection relationship and architecture between the main processing core and one or more slave processing cores, as long as the main processing core can access the configuration interface of the slave processor, and the main processing core can dynamically modify the state of the slave processing core through the configuration interface of the slave processing core.

[0125] In one possible implementation, the target slave processing core 102-4 is further used to store the execution result of the second code segment; the main processing core 101 is used to read the execution result from the target slave processing core 102-4 through the target configuration interface 4, and continue to execute the target program according to the execution result. In this embodiment of the invention, after the target slave processing core finishes executing the second code segment, it can store the execution result in the internal register of the target slave processing core, so that the main processing core can subsequently read the execution result stored in the slave processing core through the configuration interface, and then participate in the subsequent execution of the target program.

[0126] In the process of the main processing core 101 calling the target to execute the second code segment from processing cores 102-4, the specific calling flow and related configuration flow will vary depending on the different configuration forms of the second code segment in the target program. In this application, based on any of the multi-core processor 10 architectures provided above, flexible software solutions can be supported, specifically including the following four calling methods:

[0127] Method 1: The main processing core calls the target via a function to execute the second code segment from the processing core.

[0128] The second code segment is a task created in the target program in the form of heterogeneous functions; the main processing core 101 is also used to configure the target slave processing core 102-4 to execute the second code segment in the form of synchronous function calls through the target configuration interface 4. Assuming that memory address A stores code segment a of the main processing core 101 (corresponding to the first code segment in this application), and memory address B stores code segment b of the target slave processing core 102-4 (corresponding to the second code segment in this application), the main processing core 101 is executing code segment a in the target program, and now needs to execute the function in code segment b. Its execution process (i.e., heterogeneous synchronous call flow) is as follows:

[0129] 1. The main processing core 101 sets the state of the relevant registers in the target slave processing core 102-4 (i.e., the state configuration parameters in the state configuration request in this application) through the target configuration interface 4 of the target slave processing core 102-4 according to the ABI protocol agreed upon with code fragment b;

[0130] 2. The main processing core 101 sets the execution pointer (i.e., the instruction pointer in the status configuration request in this application) to B through the target configuration interface 4 of the target processing core 102-4;

[0131] 3. The main processing core 101 synchronously calls the target slave processing cores 102-4 through the target configuration interface 4, for example, by sending code execution instructions;

[0132] 4. The target switches from the ready state to the running state in processing core 102-4, executing code snippet b;

[0133] 5. Once the target has finished processing in processing core 102-4, it enters the Halt instruction, traps out, and returns to the ready state;

[0134] 6. The main processing core 101 reads the value of the return register from the configuration interface 4 of the target processing core 102-4 to obtain the execution result;

[0135] This first method is a peer-to-peer software call format, also known as the synchronous function call mode. In the synchronous function call mode, the software libraries of the two heterogeneous processing cores (including the main processing core and the target slave processing core) are compiled independently. The linker is responsible for adding synchronous call bridging code before the functions in the target slave processing core, setting registers and synchronous call code in it. In this way, calling the heterogeneous slave processing core can achieve the same effect as calling a function.

[0136] In summary, in the above-described synchronous function call format, the second code segment, as a function within the target program, is configured and invoked by the target slave processing core when the main processing core needs to execute the second code segment during the execution of the target program. It is understandable that, based on the function's attributes and characteristics, when the target slave processing core executes the second code segment, the code segments currently being executed in the main processing core and / or other slave processing cores need to be suspended, waiting for the second code segment on the target slave processing core to complete execution and obtain its result before further execution or resumption of code segments in the target program compatible with other processing cores (including the main processing core and other slave processing cores).

[0137] Method 2: The main processing core invokes the target to execute the second code segment via a thread.

[0138] The second code segment is a task created in the target program in the form of heterogeneous threads; the main processing core 101 is also used to: configure the target slave processing core 102-4 to execute the second code segment in the form of asynchronous thread calls through the target configuration interface 4. Assuming that memory address A stores code segment a of the main processing core 101 (corresponding to the first code segment in this application), and memory address B stores code segment b of the target slave processing core 102-4 (corresponding to the second code segment in this application), the main processing core 101 is executing code segment a in the target program, and now needs to execute the function in code segment b. Its execution process (i.e., heterogeneous asynchronous call flow) is as follows:

[0139] 1. The main processing core 101 creates a heterogeneous thread and initializes the state of the target processing cores 102-4 according to the thread protocol (i.e., the state configuration parameters in the state configuration request in this application);

[0140] 2. The main processing core 101 sets the execution pointer (i.e., the instruction pointer in the status configuration request in this application) to B through the target configuration interface 4 of the target processing core 102-4;

[0141] 3. The main processing core 101 asynchronously calls the slave processing core through the slave processing core's configuration interface, for example, by sending code execution instructions;

[0142] 4. The target switches from the ready state to the running state in processing core 102-4, executing code snippet b;

[0143] 5. Once the target has finished processing in processing core 102-4 or an anomaly occurs, it will trap out and return to the ready state;

[0144] 6. When the main processing core 101 enters the target processing core 102-4, it is due to the Trapped Out exception handling, the termination of the processing thread, or an exception.

[0145] Method two is a peer-to-peer software call, also known as an asynchronous thread call. In this mode, the thread library adds code at its entry point: setting registers and executing asynchronous calls from the target processing core, and calling functions from the heterogeneous library. In this way, the heterogeneous slave processing core can be treated as a single software thread used by the main processing core. If there are more than one heterogeneous core thread, a timer (Trapped out) can be used to target the slave processing core, and then the main processing core's scheduler can schedule other threads to execute. In heterogeneous systems, the operating system can allocate application threads to different processing cores according to their characteristics (for example, assigning threads with heavy computation to cores good at handling computation instructions, and threads with heavy load / store instructions to cores good at handling memory access instructions), allowing each processing core to utilize its strengths. This comprehensively improves program efficiency and, to some extent, eliminates differences in execution time between different threads due to their inherent characteristics.

[0146] In summary, in the above function call format, the second code segment acts as a heterogeneous thread within the target program. When the main processing core needs to execute the second code segment during the execution of the target program, it configures and invokes the target slave processing core asynchronously. It is understandable that, based on the attributes and characteristics of threads, when the target slave processing core is executing the second code segment, it is not necessary to suspend the code segments currently being executed on the main processing core and / or other slave processing cores; that is, it is not necessary to wait for the second code segment on the target slave processing core to complete execution. Code segments in the target program compatible with other processing cores (including the main processing core and other slave processing cores) can still be executed in parallel. It is also understandable that this thread and threads in the main processing core or other slave processing cores can belong to the same process, and multiple threads can share some resources within their respective processes.

[0147] Method 3: The main processing core invokes the target through a process to execute the second code segment from the processing core.

[0148] The second code segment is a task created in the target program as a heterogeneous process; the main processing core 101 is also used to: configure the target slave processing core 102-4 to execute the second code segment in an asynchronous or synchronous process call manner through the target configuration interface 4. Assuming that memory address A stores code segment a of the main processing core 101 (corresponding to the first code segment in this application), and memory address B stores code segment b of the target slave processing core 101-4 (corresponding to the second code segment in this application), the main processing core 101 is executing code segment a in the target program, and now needs to execute the function in code segment b. With the privilege level control of the main processing core 101, its execution process (i.e., heterogeneous synchronous call flow) is as follows:

[0149] 1. The main processing core 101 loads the process (second code segment) from the processing core into memory and establishes the MMU-related data structures (page tables);

[0150] 2. The main processing core 101 sets the privilege level of the slave processing core to user mode and configures any system call. The corresponding task exit conditions (Trapped Out) include IO, MMU exceptions, etc.

[0151] 3. The main processing core 101 sets the register state of the slave processing core according to the process protocol of the slave processing core architecture (i.e., the state configuration parameters in the state configuration request in this application);

[0152] 4. The main processing core 101 sets the execution pointer (i.e., the instruction pointer in the status configuration request in this application) to B through the target configuration interface 4 of the target processing core 102-4. It should be noted that during the process call, the above-mentioned execution pointer (i.e., instruction pointer) can refer to the initial address of the second code segment executed by the target processing core 102-4. Subsequently, since the process or virtual machine may enter a loop of (execution → pause → execution → pause) during operation, when the target processing core 102-4 returns from the paused state to the execution state, the main processing core may need to re-indicate the execution pointer to the target processing core 102-4. Of course, the execution pointer can also be determined by the target processing core 102-4 itself. Therefore, the instruction pointer in the status configuration request in this application can point to the initial address of the second code segment in this mode, or it can point to the interrupt address when the second code segment returns from the paused state to the execution state. This embodiment of the invention does not specifically limit this.

[0153] 5. The main processing core 101 synchronously calls the slave processing core in kernel mode;

[0154] 6. Enter the running state from processing core 101 and execute user-mode functions as a process;

[0155] 7. The target initiates any system call or system interrupt from the processing core 102-4, or accesses an illegal address, resulting in a Trapped out error.

[0156] 8. When the main processing core 101 returns from the call, it obtains the reason for the trappedout from the configuration interface of the target processing core 102-4, enters the normal process to handle the relevant exception or system call request, sets the processing result in the register of the target processing core 102-4, and resynchronizes the call to the target processing core 102-4 or terminates the process of the target processing core 102-4.

[0157] Method three is a cross-level simulated call format, also known as a synchronous thread call format. In this mode, the system software (e.g., the operating system) of the main processing core 101 can create a process for the target slave processing core 102-4. When this process is scheduled, the operating system of the main processing core 101 can configure its MMU and other infrastructure to set conditions so that the target slave processing core 102-4 traps out when it encounters related interrupts or system calls, becoming the interrupt handler of the main processing core 101. This allows the target slave processing core 102-4 to run within the context of the main operating system. If the target slave processing core 102-4 shares the computing resources of the main processing core 101, a synchronous mode can be configured to stop the main processing core 101 until the target slave processing core 102-4 is trapped out. It can be understood that if the target slave processing core 102-4 does not need to share the computing resources or results of the main processing core, an asynchronous mode can be configured. Heterogeneous asynchronous processes can be analogous to the heterogeneous synchronous call process described above.

[0158] In summary, in the above process invocation methods, the second code segment, as a heterogeneous process within the target program, is configured and invoked by the target slave processing core when the main processing core needs to execute the second code segment during the execution of the target program, either through asynchronous or synchronous process invocation. Specifically, based on the attributes and characteristics of asynchronous process invocation, when the target slave processing core executes the second code segment, it is not necessary to suspend the code segments currently being executed on the main processing core and / or other slave processing cores; that is, it is not necessary to wait for the second code segment on the target slave processing core to complete execution. Code segments in the target program compatible with other processing cores (including the main processing core and other slave processing cores) can still be executed in parallel. Conversely, based on the attributes and characteristics of synchronous process invocation, when the target slave processing core executes the second code segment, it is necessary to suspend the code segments currently being executed on the main processing core and / or other slave processing cores, waiting for the second code segment on the target slave processing core to complete execution and obtain the execution result before further execution or resumption of the execution of code segments in the target program compatible with other processing cores (including the main processing core and other slave processing cores). It is understandable that this process cannot share relevant resources with processes in the main processing core or other slave processing cores. Therefore, the main processing core needs to pre-configure the relevant data structures (page tables) of the Memory Management Unit (MMU) for the target slave processing core.

[0159] Method 4: The main processing core calls the target slave processing core via a virtual machine.

[0160] The second code segment is a task created in the target program in the form of a heterogeneous virtual machine; the main processing core 101 is also used to: configure the target slave processing core 102-4 to execute the second code segment in the form of asynchronous or synchronous virtual machine calls via the target configuration interface 4. Assuming that memory address A stores code segment a of the main processing core 101 (corresponding to the first code segment in this application), and memory address B stores code segment b of the target slave processing core 102-4 (corresponding to the second code segment in this application), the main processing core 101 is executing code segment a in the target program, and now needs to execute the function in code segment b. The execution process (i.e., the heterogeneous synchronous call process) is as follows:

[0161] 1. The hypervisor of the main processing core 101 loads the system image (which may include the bootloader before system startup) from the processing core into memory and can control its physical memory range if necessary;

[0162] 2. The main processing core 101 is set to switch the privilege level of the processing core 102-4 to kernel mode, and any Hypervisor call, I / O access requiring intervention, and timing are configured as one of the trapped out conditions;

[0163] 3. The main processing core 101 sets the register state of the slave processing core (including the send state configuration request in this application) according to the process protocol of the target slave processing core 102-4 architecture;

[0164] 4. The main processing core 101 sets the execution pointer (i.e., the instruction pointer in the status configuration request in this application) to B through the target configuration interface 4 of the target processing core 102-4. It should be noted that during the virtual machine call, the above-mentioned execution pointer (i.e., instruction pointer) can refer to the initial address of the second code segment executed by the target processing core 102-4. Subsequently, since the process or virtual machine may enter a loop of (execution → pause → execution → pause) during operation, when the target processing core 102-4 returns from the paused state to the execution state, the main processing core may need to re-indicate the execution pointer to the target processing core 102-4. Of course, the execution pointer can also be determined by the target processing core 102-4 itself. Therefore, the instruction pointer in the status configuration request in this application can point to the initial address of the second code segment in this mode, or it can point to the interrupt address when the second code segment returns from the paused state to the execution state. This embodiment of the invention does not specifically limit this.

[0165] 5. The main processing core 101 synchronously calls the target processing cores 102-4 in Hypervisor mode, for example, by sending code execution instructions;

[0166] 6. Enter the running state from processing core 101, and execute the virtual machine operating system functions as a virtual machine;

[0167] 7. A Hypervisor call is initiated from processing core 101, or any I / O event or system exception occurs that the target cannot be handled by processing core 102-4, resulting in a Trapped out;

[0168] 8. When the main processing core 101 returns from the call, it obtains the reason for the Trapped out from the configuration interface of the target processing core 102-4, enters the normal process to handle the relevant exception or system call request, sets the processing result in the register of the target processing core 102-4, and resynchronizes the call to the target processing core 102-4 or terminates the virtual machine of the target processing core 102-4.

[0169] Method four is a cross-level simulated call format, also known as a synchronous virtual machine call format. In this mode, the target's runtime environment from processing core 102-4 can be prepared by the hypervisor. As long as the relevant Trapped-out conditions are set, the target from processing core 102-4 can be run as a virtual machine. It is understandable that an asynchronous mode can also be configured, and heterogeneous asynchronous processes can be analogous to the heterogeneous synchronous call process described above.

[0170] In summary, in the above virtual machine invocation methods, the second code segment acts as a heterogeneous virtual machine within the target program. When the main processing core needs to execute the second code segment during the execution of the target program, it configures and invokes the target slave processing core using asynchronous virtual machine invocation. Specifically, based on the attributes and characteristics of asynchronous virtual machine invocation, when the target slave processing core is executing the second code segment, it is not necessary to suspend the code segments currently being executed on the main processing core and / or other slave processing cores. That is, it is not necessary to wait for the second code segment on the target slave processing core to complete execution. Code segments in the target program compatible with other processing cores (including the main processing core and other slave processing cores) can still be executed in parallel. However, based on the attributes and characteristics of synchronous virtual machine invocation, when the target slave processing core is executing the second code segment, it is necessary to suspend the code segments currently being executed on the main processing core and / or other slave processing cores, waiting for the second code segment on the target slave processing core to complete execution and obtain the execution result before further execution or resumption of the execution of code segments in the target program compatible with other processing cores (including the main processing core and other slave processing cores). Understandably, before configuring a target slave processor, the main processor needs to load the virtual machine image of the target slave processor into shared memory. This virtual machine cannot share related resources with virtual machines in the main processor or other slave processors. Optionally, the main processor can also set a physical memory range for the target slave processor.

[0171] The embodiments of the present invention can leverage the heterogeneity of the cores in a multi-core processor to simultaneously execute applications with different requirements, thus satisfying diverse needs. For example, the multi-core processors in the embodiments of the present invention can be widely used in high-performance computers, desktop computers, smart terminals and other consumer electronics products, as well as in equipment manufacturing, national defense and military industries, and other fields.

[0172] Please see Figure 9 , Figure 9 This is a flowchart illustrating a processing method for a multi-core processor according to an embodiment of the present invention. The processing method is applied to a multi-core processor, which includes a main processing core and slave processing cores coupled to the main processing core. The main processing core has a first instruction space, and the slave processing cores have a second instruction space. The processing method is applicable to the aforementioned... Figures 6-10 The method can include any type of multi-core processor and a device containing the multi-core processor (such as a mobile phone, computer, server, etc.). The method may include the following steps S201-S203, wherein...

[0173] Step S201: Execute a first code segment in the target program through the main processing core. The target program further includes a second code segment. The first code segment is a code segment compatible with the first instruction space, and the second code segment is a code segment compatible with the second instruction space.

[0174] Step S202: Send the address of the second code segment to the slave processing core through the main processing core.

[0175] Step S203: Receive the address of the second code segment from the processing core, load the second code segment according to the address of the second code segment, and execute the second code segment.

[0176] In one possible implementation, the method further includes: sending state configuration parameters required for executing the second code segment to the slave processing core via the main processing core; and configuring parameters via the state configuration parameters received by the slave processing core.

[0177] In one possible implementation, the method further includes: sending a code execution instruction to the slave processing core through the main processing core; the step of loading and executing the second code segment according to the address of the second code segment includes: after the slave processing core receives the code execution instruction, loading and executing the second code segment according to the address of the second code segment.

[0178] In one possible implementation, the method further includes: configuring a task exit condition for the slave processing core via the main processing core, the exit condition including one or more of a task interruption condition, a task termination condition, an illegal operation of the slave processing core, and a priority that the slave processing core cannot process; and determining whether to stop executing the second code segment based on the task exit condition during the execution of the second code segment via the target slave processing core.

[0179] In one possible implementation, the second code segment is a task created in the form of a function in the target program; the method further includes: configuring the target slave processing core to execute the second code segment in the form of a function call through the main processing core.

[0180] In one possible implementation, the second code segment is a task created in the form of a thread in the target program; the method further includes: configuring the target slave processing core to execute the second code segment in the form of a thread call through the main processing core.

[0181] In one possible implementation, the second code segment is a task created as a process in the target program; the method further includes: configuring the target slave processing core to execute the second code segment as a process call when executing the second code segment via the main processing core.

[0182] In one possible implementation, the second code segment is a task created in the form of a virtual machine in the target program; the method further includes: configuring the target slave processing core to execute the second code segment in the form of a virtual machine call through the main processing core.

[0183] In one possible implementation, the state configuration parameters corresponding to the second code segment include one or more of the following: configuration parameters associated with the second code segment stored in a general-purpose register, configuration parameters associated with the second code segment stored in a system register, and state setting parameters that affect the behavior of running the second code segment from the processing core.

[0184] In one possible implementation, the state configuration parameter corresponding to the second code segment is a parameter accessed via address read / write or an instruction control parameter.

[0185] In one possible implementation, the main processing core and the at least one or more slave processing cores share in-core resources and / or out-of-core resources, wherein the in-core resources include computing resources and the out-of-core resources include one or more of memory management units, caches, and memory.

[0186] In one possible implementation, the method further includes: storing the execution result of the second code segment through the slave processing core; reading the execution result from the slave processing core through the main processing core, and continuing to execute the target program based on the execution result.

[0187] It should be noted that the specific process flow of the multi-core processor processing method described in the embodiments of the present invention can be found in the above. Figures 4-8 The relevant descriptions in the embodiments of the invention described herein will not be repeated here.

[0188] Based on the above, this application provides a multi-core processor. Please refer to [link / reference]. Figure 10 , Figure 10 This is a schematic diagram of another multi-core processor provided in an embodiment of the present invention. The multi-core processor 20 may include a main processing core 201 and slave processing cores 202 (which may include one or more). Figure 10 Taking one as an example, the multi-core processor 20 can be located in any electronic device, such as a computer, mobile phone, tablet, or other similar devices. Specifically, the multi-core processor 20 can be a chip, a chipset, or a circuit board housing a chip or chipset. The chip, chipset, or circuit board housing a chip or chipset can operate under the necessary software drivers.

[0189] The multi-core processor 20 may include: a main processing core 201 having a first instruction space, configured to: execute a first code segment in a target program, the target program further including a second code segment, wherein the first code segment is a code segment compatible with the first instruction space, and the second code segment is a code segment compatible with the second instruction space;

[0190] The second code segment is executed by calling the slave processing core 202, which is coupled to the main processing core 201 and has the second instruction space.

[0191] In one possible implementation, the main processing core 201 is specifically used to: call the slave processing core 202 to execute the second code segment through the configuration interface of the slave processing core 202.

[0192] In one possible implementation, the main processing core 201 is specifically used to: execute the first code segment in the target program using the first instruction space; the slave processing core 202 is specifically used to: execute the second code segment in the target program using the second instruction space.

[0193] In one possible implementation, the first code snippet and the second code snippet are code snippets compiled by different compilers.

[0194] In one possible implementation, the first instruction space is Complex Instruction Set Computing (CISC), and the second instruction space is Reduced Instruction Set Computing (RISC).

[0195] It should be noted that the functions of the multi-core processor described in the embodiments of the present invention can be found in the above description. Figures 4-8 The relevant descriptions in the embodiments of the invention described herein will not be repeated here.

[0196] Please see Figure 11 , Figure 11 This is a flowchart illustrating another processing method for a multi-core processor provided in an embodiment of the present invention. This multi-core processor processing method is applied to a multi-core processor, which includes a main processing core and slave processing cores coupled to the main processing core. The main processing core has a first instruction space, and the slave processing cores have a second instruction space. Furthermore, this multi-core processor processing method is applicable to the aforementioned... Figures 4-8 The method can include any type of multi-core processor and a device containing the multi-core processor (such as a mobile phone, computer, server, etc.). The method may include the following steps S401-S403, wherein...

[0197] Step S401: Execute a first code segment in the target program through the main processing core. The target program further includes a second code segment. The first code segment is a code segment compatible with the first instruction space, and the second code segment is a code segment compatible with the second instruction space.

[0198] Step S402: The second code segment is executed by calling the slave processing core through the main processing core.

[0199] Step S403: Execute the second code segment in the target program from the processing core.

[0200] In one possible implementation, the step of calling the slave processing core to execute the second code segment through the main processing core includes: calling the slave processing core to execute the second code segment through the configuration interface of the slave processing core by the main processing core.

[0201] In one possible implementation, executing the first code segment in the target program through the main processing core includes: executing the first code segment in the target program through the main processing core using the first instruction space;

[0202] The execution of the second code segment in the target program via the slave processing core includes: executing the second code segment in the target program via the slave processing core using the second instruction space.

[0203] In one possible implementation, the first code snippet and the second code snippet are code snippets compiled by different compilers.

[0204] In one possible implementation, the first instruction space is Complex Instruction Set Computing (CISC), and the second instruction space is Reduced Instruction Set Computing (RISC).

[0205] It should be noted that the specific process flow of the multi-core processor processing method described in the embodiments of the present invention can be found in the above. Figures 4-8 The relevant descriptions in the embodiments of the invention described herein will not be repeated here.

[0206] This invention also provides a computer-readable storage medium, wherein the computer-readable storage medium may store a program, which, when executed by a multi-core processor, includes some or all of the steps described in any of the above method embodiments.

[0207] This invention also provides a computer program that includes instructions that, when executed by a multi-core processor, enable the multi-core processor to perform some or all of the steps of any multi-core processor processing method.

[0208] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0209] It should be noted that, for the sake of simplicity, the foregoing method embodiments are all described as a series of actions. However, those skilled in the art should understand that this application is not limited to the described order of actions, as some steps may be performed in other orders or simultaneously according to this application. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are preferred embodiments, and the actions and modules involved are not necessarily essential to this application.

[0210] In the several embodiments provided in this application, it should be understood that the disclosed apparatus can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of the units described above is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical or other forms.

[0211] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0212] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0213] If the integrated units described above are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which can be a personal computer, server, or network device, specifically a processor in the computer device) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium may include various media capable of storing program code, such as a USB flash drive, portable hard drive, magnetic disk, optical disk, read-only memory (ROM), or random access memory (RAM).

[0214] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. A multi-core processor, characterized in that, It includes a main processing core and slave processing cores coupled to the main processing core; the main processing core has a first instruction space, and the slave processing core has a second instruction space; wherein, The main processing core is used for: Execute a first code segment in the target program, the target program further comprising a second code segment; the first code segment is a code segment compatible with the first instruction space, and the second code segment is a code segment compatible with the second instruction space; The address of the second code segment is sent to the slave processing core through the configuration interface of the slave processing core; If the second code snippet is a task created in the form of a function, then the slave processing core is called through the configuration interface in a synchronous function call manner; The slave processing core, including the configuration interface, is used for: The address of the second code fragment is received through the configuration interface; The second code snippet is loaded based on its address, and if the second code snippet is a task created as a function, it is executed as a function call.

2. The processor according to claim 1, characterized in that, The main processing core is also used for: The configuration interface is used to send the state configuration parameters required for executing the second code segment to the slave processing core. The processing core is also used to: configure parameters according to the status configuration parameters received from the configuration interface.

3. The processor according to claim 1, characterized in that, The main processing core is also used for: The configuration interface is used to send code execution instructions to the slave processing core; The slave processing core is specifically used to: after receiving the code execution instruction through the configuration interface, load the second code segment according to the address of the second code segment and execute the second code segment.

4. The processor according to claim 1, characterized in that, The main processing core is also configured to configure the task exit conditions of the slave processing core through the configuration interface. The exit conditions include one or more of the following: task interruption conditions, task termination conditions, illegal operation of the slave processing core, and priority that the slave processing core cannot process. The slave processing core is further configured to: during the execution of the second code segment, determine whether to stop executing the second code segment based on the task exit condition.

5. The processor according to any one of claims 1-4, characterized in that, If the second code fragment is a task created as a thread in the target program; the main processing core is further configured to: The configuration interface allows the slave processing core to be configured to execute the second code segment via a thread call.

6. The processor according to any one of claims 1-4, characterized in that, If the second code fragment is a task created as a process in the target program; the main processing core is further configured to: The configuration interface allows the slave processing core to be configured to execute the second code segment via a process call.

7. The processor according to any one of claims 1-4, characterized in that, If the second code fragment is a task created in the form of a virtual machine in the target program; the main processing core is further used for: The configuration interface allows the slave processing core to be configured to execute the second code segment via a virtual machine call.

8. The processor according to claim 2, characterized in that, The state configuration parameters corresponding to the second code segment include one or more of the following: configuration parameters associated with the second code segment stored in a general-purpose register, configuration parameters associated with the second code segment stored in a system register, and state setting parameters that affect the behavior of running the second code segment from the processing core.

9. The processor according to claim 2, characterized in that, The status configuration parameter corresponding to the second code segment is either a parameter accessed via address read / write or an instruction control parameter.

10. The processor according to any one of claims 1-4, characterized in that, The main processing core and the slave processing core share in-core resources and / or out-of-core resources. The in-core resources include computing resources, and the out-of-core resources include one or more of memory management units, caches, and memory.

11. The processor according to any one of claims 1-4, characterized in that, The processing core is also used for: Store the execution result of the second code segment; The main processing core is also used to read the execution result from the slave processing core through the configuration interface, and continue to execute the target program according to the execution result.

12. A processing method for a multi-core processor, characterized in that, The invention is applied to a multi-core processor, which includes a main processing core and slave processing cores coupled to the main processing core. The main processing core has a first instruction space, and the slave processing core has a second instruction space; the method includes: The first code segment in the target program is executed by the main processing core, and the target program further includes a second code segment; the first code segment is a code segment compatible with the first instruction space, and the second code segment is a code segment compatible with the second instruction space; The address of the second code segment is sent from the main processing core to the slave processing core; If the second code snippet is a task created in the form of a function, then the slave processing core is called through the configuration interface of the slave processing core in the form of synchronous function calls; The process involves receiving the address of the second code segment from the processing core, loading the second code segment based on its address, and executing the second code segment as a function call.

13. The method according to claim 12, characterized in that, The method further includes: The main processing core sends the state configuration parameters required to execute the second code segment to the slave processing core; Parameters are configured using the state configuration parameters received from the processing core.

14. The method according to claim 12, characterized in that, The method further includes: The main processing core sends code execution instructions to the slave processing core; The step of loading and executing the second code segment according to its address includes: After receiving the code execution instruction from the processing core, the second code segment is loaded and executed according to its address.

15. The method according to claim 12, characterized in that, The method further includes: The main processing core configures the task exit conditions for the slave processing core. The exit conditions include one or more of the following: task interruption condition, task termination condition, illegal operation of the slave processing core, and priority that the slave processing core cannot process. During the execution of the second code segment from the processing core, a decision is made based on the task exit condition to determine whether to stop executing the second code segment.

16. The method according to any one of claims 12-15, characterized in that, If the second code fragment is a task created as a thread in the target program, the method further includes: The main processing core is configured to execute the slave processing core in the form of a thread call when executing the second code segment.

17. The method according to any one of claims 12-15, characterized in that, If the second code fragment is a task created as a process in the target program, the method further includes: The main processing core is configured to execute the slave processing core in the form of a process call when executing the second code segment.

18. The method according to any one of claims 12-15, characterized in that, If the second code fragment is a task created in the form of a virtual machine in the target program; the method further includes: The main processing core is configured to execute the slave processing core in the form of a virtual machine call when executing the second code segment.

19. The method according to claim 13, characterized in that, The state configuration parameters corresponding to the second code segment include one or more of the following: configuration parameters associated with the second code segment stored in a general-purpose register, configuration parameters associated with the second code segment stored in a system register, and state setting parameters that affect the behavior of running the second code segment from the processing core.

20. The method according to claim 13, characterized in that, The status configuration parameter corresponding to the second code segment is either a parameter accessed via address read / write or an instruction control parameter.

21. The method according to any one of claims 12-15, characterized in that, The main processing core and one or more of the slave processing cores share in-core resources and / or out-of-core resources. The in-core resources include computing resources, and the out-of-core resources include one or more of memory management units, caches, and memory.

22. The method according to any one of claims 12-15, characterized in that, The method further includes: The execution result of the second code segment is stored through the processing core; The main processing core reads the execution result from the slave processing core and continues to execute the target program based on the execution result.

23. A multi-core processor, characterized in that, include: The main processing core, which has a first instruction space, is used for: The first code segment in the target program is executed, and the target program further includes a second code segment, wherein the first code segment is a code segment compatible with the first instruction space, and the second code segment is a code segment compatible with the second instruction space; If the second code segment is a task created in the form of a function, then the second code segment is executed by calling the slave processing core in a synchronous function call manner through the configuration interface of the slave processing core. The slave processing core is a processing core coupled to the main processing core and having the second instruction space.

24. The multi-core processor according to claim 23, characterized in that, The main processing core is specifically used to: execute the first code segment in the target program using the first instruction space; The processing core is specifically used to: execute the second code segment in the target program using the second instruction space.

25. The multi-core processor according to any one of claims 23-24, characterized in that, The first code snippet and the second code snippet are code snippets compiled by different compilers.

26. The multi-core processor according to any one of claims 23-24, characterized in that, The first instruction space is Complex Instruction Set Computing (CISC), and the second instruction space is Reduced Instruction Set Computing (RISC).

27. A processing method for a multi-core processor, characterized in that, The invention is applied to a multi-core processor, which includes a main processing core and slave processing cores coupled to the main processing core. The main processing core has a first instruction space, and the slave processing core has a second instruction space; the method includes: The first code segment in the target program is executed by the main processing core, and the target program further includes a second code segment. The first code segment is a code segment compatible with the first instruction space, and the second code segment is a code segment compatible with the second instruction space. The main processing core calls the slave processing core to execute the second code segment; wherein, if the second code segment is a task created in the form of a function, the main processing core calls the slave processing core through the configuration interface of the slave processing core in a synchronous function call manner; In the case where the second code segment is a task created in the form of a function, the second code segment in the target program is executed by the processing core in the form of a function call.

28. The method according to claim 27, characterized in that, The execution of the first code segment in the target program through the main processing core includes: executing the first code segment in the target program through the first instruction space using the main processing core; The execution of the second code segment in the target program via the slave processing core includes: executing the second code segment in the target program via the slave processing core using the second instruction space.

29. The method according to any one of claims 27-28, characterized in that, The first code snippet and the second code snippet are code snippets compiled by different compilers.

30. The method according to any one of claims 27-28, characterized in that, The first instruction space is Complex Instruction Set Computing (CISC), and the second instruction space is Reduced Instruction Set Computing (RISC).

31. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a multi-core processor, implements the method described in any one of claims 12-22, or implements the method described in any one of claims 27-30.

32. A computer program product, characterized in that, The computer program product includes instructions that, when executed by a multi-core processor, cause the multi-core processor to perform the method as described in any one of claims 12-22, or to implement the method as described in any one of claims 27-30.

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