System and method for storage management

Abstract

Embodiments of the present disclosure provide a method and system for storage management. The method comprises: receiving a request for allocating target node data to a storage space, wherein the storage space comprises a buffer and an external memory, the target node data comprises attribute data and structure data, and represents a target node of a graph having a plurality of nodes and edges; determining a node degree associated with the target node data; and allocating the target node data to the storage space based on the determined node degree.

Description

[0001] Cross-reference to related applications

[0002] This disclosure claims priority and priority benefit to U.S. Patent Application No. 16 / 789,271, filed February 12, 2020, which is incorporated herein by reference. Background Technology

[0003] Graph processing deals with datasets that are graphs and contain multiple data entities. In a graph, each data entity can be stored as nodes and edges. Nodes represent objects, such as people, actions, vehicles, etc. Relationships between multiple nodes are represented by edges between nodes. Therefore, datasets can be analyzed by performing graph processing on nodes and their edges.

[0004] To process graphs, they are typically loaded into the processor's (e.g., CPU's) cache at their actual size. However, as graphs continue to grow, their size may exceed the cache's storage capacity.

[0005] Furthermore, as a pointer-based data structure, the relationships between multiple nodes in a graph are described by pointers, but the reliance on pointer tracking places strict requirements on cache latency and bandwidth. Summary of the Invention

[0006] Embodiments of this disclosure provide a storage management method. The method includes: receiving a request to allocate target node data to a storage space, wherein the storage space includes a buffer and external memory, the target node data includes attribute data and structural data, and represents a target node in a graph having multiple nodes and edges; determining the node degree associated with the target node data; and allocating the target node data in the storage space based on the determined node degree.

[0007] Embodiments of this disclosure also provide a computing system. The system may include: external memory for storing a set of instructions; and a processor including a buffer and circuitry configured to execute the set of instructions to cause the computing system to perform the following operations: receiving a request to allocate target node data to storage space, wherein the storage space includes the buffer and the external memory, the target node data includes attribute data and structural data, and represents a target node in a graph having multiple nodes and edges; determining the node degree associated with the target node data; and allocating the target node data in the storage space based on the determined node degree.

[0008] It should be understood that, as described above, the foregoing general description and the following detailed description are exemplary and explanatory only, and do not limit the embodiments of this disclosure. Attached Figure Description

[0009] The following detailed description and accompanying drawings illustrate embodiments and aspects of this disclosure. Various features shown in the figures are not drawn to scale.

[0010] Figure 1 A schematic diagram of exemplary figures according to some embodiments of the present disclosure is shown.

[0011] Figure 2A An exemplary matrix-form graphical representation is shown according to some embodiments of the present disclosure.

[0012] Figure 2B A structural diagram of exemplary figures according to some embodiments of the present disclosure is shown.

[0013] Figure 3 A schematic diagram of an exemplary computing system according to some embodiments of the present disclosure is shown.

[0014] Figure 4 A schematic diagram of an exemplary neural network accelerator architecture according to some embodiments of the present disclosure is shown.

[0015] Figure 5A A schematic diagram of an exemplary management unit according to some embodiments of the present disclosure is shown.

[0016] Figure 5B A schematic diagram illustrating exemplary node allocation according to some embodiments of the present disclosure is shown.

[0017] Figure 6 A flowchart of a method for performing storage management in graph processing according to some embodiments of the present disclosure is shown. Detailed Implementation

[0018] Specific aspects of this disclosure are described in more detail below. In the event of any conflict with terms or definitions incorporated by reference, the terms and definitions provided herein shall prevail.

[0019] Embodiments of this disclosure provide systems and methods for memory management in graph processing. In some embodiments, a node is allocated to a buffer or external memory based on its degree. For example, nodes with a degree greater than a given threshold are allocated to a buffer. Since nodes with higher degrees are accessed more frequently, allocating valuable buffer space to nodes with higher degrees according to the systems and methods of embodiments of this disclosure can improve buffer efficiency. In some embodiments of this disclosure, node attribute data is allocated to a buffer, while node structure data is allocated separately to external memory. Therefore, pointer-chasing in the buffer can be avoided, and storage space can be better utilized.

[0020] Figure 1Figure 100 illustrates an exemplary embodiment according to some disclosed embodiments. The figure is a data structure comprising multiple nodes and multiple edges between nodes. A node is an object associated with attribute data. Attribute data includes characteristics or features belonging to the object (person or thing), particularly characteristics or features unique to the object (person or thing). For example, in a social network, a node is a person, and the person is associated with attribute data, such as user ID, name, gender, age, etc. As another example, a node is a bus stop, and the bus stop is associated with attribute data, such as buses stopping at the bus stop, bus arrival times, etc. Nodes can also be associated with structural data, which describes the edges between nodes. For example, structural data includes the direction of the edges and the weights of the edges. Figure 1 As shown, nodes 0-4 can be people in a social network, and the edges between two nodes can indicate the links between the two people. For example, edge 102 indicates that node 0 and node 1 have added each other as friends. Figure 1 An example of edge 102-112 is shown.

[0021] although Figure 1 Graph 100 is represented as an undirected graph, but a graph can also be directed. In the bus station example, the edge from the first bus station to the second bus station can be a directed edge, and the graph consisting of bus stations and edges is a directed graph. Furthermore, the edges can be weighted. For example, the edge from the first bus station to the second bus station can be weighted to indicate the number of passengers on the edge.

[0022] Figure 100 can be represented as a data structure, such as a matrix (e.g., a compressed sparse row (CSR) matrix), a table, a linked list, etc. Figure 2A A graphical representation of an exemplary matrix 200 according to some embodiments of the present disclosure is shown.

[0023] In some embodiments, such as Figure 2A As shown, matrix 200 can be used to represent Figure 1 Figure 100 shows the matrix elements, where the values ​​of the matrix elements indicate the edges between two nodes. For example, node 0 has an edge connected to node 1, so the values ​​of matrix elements (1,0) and (0,1) are 1. Matrix 200 can be further compressed into a CSR matrix.

[0024] Understandably, tables, linked lists, and other formats can also be used to represent graphs. To provide greater versatility, Figure 2B Figure 210 is shown as a structural diagram according to some embodiments of the present disclosure. Figure 210 may be presented in any suitable form. Figure 2B This is merely an illustration of Figure 210.

[0025] Each node in Figure 210 may include attribute data 202 and structure data 204. In some embodiments, attribute data 202 includes the node's node ID, one or more attributes of the node, and a pointer to the node's structure data 204. For example, the node ID indicates the identifier of the node (e.g., node 0, 1, 2, 3, or 4). One or more attributes may be associated with characteristics of the node. As described above, in the example of a social network, one or more attributes include the node's name, gender, age, etc., and are represented numerically. The pointer in attribute data 202 is used to locate the node's structure data 204. For example, the pointer includes the address of structure data 204, which, as described above, describes the edges between nodes. Figure 2B As shown, node 0 has one edge connecting to node 1, node 1 has two edges connecting to nodes 2 and 4, node 2 has three edges connecting to nodes 1, 3, and 4, node 3 has two edges connecting to nodes 2 and 4, and node 4 has a tree-like network of edges connecting to nodes 1, 2, and 3. The number of edges connecting a node is also called the node degree. For example, node 0 has a node degree of 1, and node 2 has a node degree of 3.

[0026] Figure 3 A schematic diagram of a computing system 300 according to some embodiments of the present disclosure is shown. The computing system 300 includes a processing device 302 and dynamic random access memory (DRAM) 304. DRAM 304, as off-chip memory (also referred to as external memory 304), can be used as main memory to store data and is accessed by the processing device 302. The processing device 302 may be a central processing unit (CPU) or an accelerator for graph processing / neural network processing, and the processing device 302 includes a management unit 306, a cache 308 (also referred to as a buffer 308), and a bus 310. When the computing system 300 includes multiple processing devices, the cache 308 may include caches for multiple processing devices. It is understood that the processing device 302 may also include other components, such as an arithmetic logic unit (ALU), peripheral devices, interfaces, etc.

[0027] In some embodiments, the processing device 302 is a neural network accelerator. Figure 4 An exemplary neural network accelerator architecture 400 according to some embodiments of the present disclosure is shown. In the context of this disclosure, neural network accelerators are also referred to as machine learning accelerators or deep learning accelerators. In some embodiments, accelerator architecture 400 may be referred to as neural network processing unit (NPU) architecture 400. Figure 4 As shown, the accelerator architecture 400 includes multiple cores 402, a command processor 404, a direct memory access (DMA) unit 408, a Joint Test Action Group (JTAG) / Test Access End (TAP) controller 410, a peripheral interface 412, a bus 414, etc.

[0028] It is understood that core 402 can perform algorithmic operations based on communication data. Core 402 may include one or more processing elements, which may include a single instruction multiple data (SIMD) architecture, comprising one or more processing units configured to perform one or more operations (e.g., multiplication, addition, multiplication-accumulation, etc.) based on commands received from command processor 404. To perform operations on the communicated data packets, core 402 may include one or more processing elements for processing information in the data packets. Each processing element may include any number of processing units. According to some embodiments of this disclosure, accelerator architecture 400 includes multiple cores 402, for example, four cores. In some embodiments, the multiple cores 402 are communicatively coupled to each other. For example, the multiple cores 402 may be connected to a unidirectional ring bus that supports an efficient pipeline for large neural network models. Reference will be made below. Figure 4 Provide a detailed description of the architecture of the Core 402.

[0029] Command processor 404 can interact with host unit 420 and pass relevant commands and data to the corresponding cores 402. In some embodiments, command processor 404 interacts with host unit under the supervision of kernel mode driver (KMD). In some embodiments, command processor 404 modifies the relevant commands to each core 402 so that multiple cores 402 can work in parallel as much as possible. The modified commands can be stored in an instruction buffer. In some embodiments, command processor 404 is configured to coordinate the parallel execution of one or more cores 402.

[0030] DMA unit 408 can assist in transferring data between host memory 421 and accelerator architecture 400. For example, DMA unit 408 assists in loading data or instructions from host memory 421 into the local memory of core 402. DMA unit 408 can also assist in transferring data between multiple accelerators. DMA unit 408 can allow off-chip devices to access on-chip and off-chip memory without causing host CPU interrupts. Furthermore, DMA unit 408 can assist in transferring data between components of accelerator architecture 400. For example, DMA unit 408 assists in transferring data between multiple cores 402 or within each core. Therefore, DMA unit 408 can also generate memory addresses and initiate memory read or write cycles. DMA unit 408 may also include several hardware registers that can be written to and read by one or more processors, including memory address registers, byte count registers, one or more control registers, and other types of registers. These registers can specify a combination of source, destination, transfer direction (reading from or writing to an input / output (I / O) device), transfer unit size, and the number of bytes transferred in a burst. It should be understood that accelerator architecture 400 may include a second DMA unit that can be used to transfer data between other accelerator architectures, allowing multiple accelerator architectures to communicate directly without involving the host CPU.

[0031] The JTAG / TAP controller 410 can specify a dedicated debug port (e.g., a JTAG interface) to implement a serial communication interface for low-overhead access to the accelerator without direct external access to the system address and data bus. The JTAG / TAP controller 410 can also have an on-chip test access interface (e.g., a TAP interface) that implements a protocol to access a set of test registers that represent chip logic levels and the device capabilities of individual components.

[0032] If a peripheral interface 412 (such as a PCIe interface) is present, it is used (and usually is) as an inter-chip bus to provide communication between the accelerator and other devices.

[0033] Bus 414 (e.g., I) 2The C-bus includes on-chip buses and inter-chip buses. As required by the system architecture, the on-chip bus interconnects all internal components. While not all components are connected to every other component, all components are connected to other components with which they need to communicate. The inter-chip bus connects the accelerator to other devices, such as off-chip memory or peripherals. For example, bus 414 provides high-speed communication across cores and can also connect core 402 to other units, such as off-chip memory or peripherals. Typically, if a peripheral interface 412 (e.g., an inter-chip bus) is present, bus 414 is only related to the on-chip bus, although in some implementations, bus 414 may still be related to dedicated inter-bus communication.

[0034] The accelerator architecture 400 can also communicate with the host unit 420. The host unit 420 can be one or more processing units (e.g., an x86 central processing unit). Figure 4 As shown, host unit 420 may be associated with host memory 421. In some embodiments, host memory 421 is integrated memory or external memory associated with host unit 420. In some embodiments, host memory 421 includes a host disk, which is external memory used to provide additional memory to host unit 420. Host memory 421 may be double data rate synchronous dynamic random-access memory (e.g., double data rate synchronous dynamic random-access memory, DDR-SDRAM), etc. Compared to on-chip memory integrated within the accelerator chip, host memory 421 is configured as a higher-level cache to store large amounts of data at slower access speeds. Data stored in host memory 421 may be transferred to accelerator architecture 400 for executing neural network models.

[0035] In some embodiments, a host system having a host unit 420 and a host memory 421 (e.g., Figure 3 The computing system 300 includes a compiler (not shown in the figure). A compiler is a program or computer software that translates computer code written in a programming language into instructions for the accelerator architecture 400 to create an executable program. In machine learning applications, a compiler can perform various operations, such as preprocessing, lexical analysis, parsing, semantic analysis, converting input programs into intermediate representations, neural network initialization, code optimization, and code generation, or combinations thereof. For example, a compiler compiles a neural network to generate static parameters, such as the connections between neurons and the weights of neurons.

[0036] In some embodiments, a host system including a compiler pushes one or more commands to the accelerator architecture 400. As described above, these commands can be further processed by the command processor 404 of the accelerator architecture 400, temporarily stored in the instruction buffer of the accelerator architecture 400, and allocated to one or more corresponding cores (e.g., Figure 4 (Core 402 in the DMA unit) or processing element. Some commands can instruct DMA units (e.g., Figure 4 The DMA unit 408) transfers instructions and data from host memory (e.g., Figure 4 The instructions are loaded into the accelerator architecture 400 from the host memory 421. These loaded instructions are then assigned to each core (e.g., ...) that has been assigned a corresponding task. Figure 4 The instructions are processed by one or more cores (core 402).

[0037] It is understood that the first few instructions received by core 402 may instruct core 402 to load / store data from host memory 421 into one or more local memories of the core. Then, each core 402 initiates an instruction pipeline that involves (e.g., via a sequencer) fetching instructions from the instruction buffer, (e.g., via...) Figure 4 The DMA unit 408 decodes instructions, generates (e.g., a local memory address corresponding to the operand), reads the source data, performs a load / store operation, and then writes back the result.

[0038] According to some embodiments, the accelerator architecture 400 also includes a global memory (not shown) having memory blocks (e.g., four 8GB blocks of second-generation high-bandwidth memory (HBM2)) used as main memory. In some embodiments, the global memory stores instructions and data fetched from host memory 421 via DMA unit 408. The instructions are then assigned to instruction buffers of each core, which are assigned corresponding tasks, and the cores can process these instructions accordingly.

[0039] In some embodiments, accelerator architecture 400 further includes a memory controller (not shown) configured to manage data reads and writes to specific memory blocks (e.g., HBM2) within global memory. For example, the memory controller manages data reads and writes from a core of another accelerator (e.g., from DMA unit 408 or a DMA unit corresponding to another accelerator) or from core 402 (e.g., from local memory within core 402). It is understood that more than one memory controller may be provided in accelerator architecture 400. For example, each memory block (e.g., HBM2) in global memory may have one memory controller.

[0040] The memory controller generates memory addresses and initiates memory read or write cycles. The memory controller may contain several hardware registers that can be written to and read by one or more processors. These registers may include memory address registers, byte count registers, one or more control registers, and other types of registers. These registers can specify a combination of source, destination, transfer direction (reading from or writing to an input / output (I / O) device), transfer unit size, number of bytes transferred in a burst, and other typical characteristics of the memory controller.

[0041] Although in some embodiments of this disclosure, Figure 4 The accelerator architecture 400 can be used for convolutional neural networks (CNNs), but it should be understood that... Figure 4 The accelerator architecture 400 can be used for various neural networks, such as deep neural networks (DNNs), recurrent neural networks (RNNs), etc. Furthermore, in some embodiments, various processing architectures can be configured, such as neural network processing units (NPUs), graphics processing units (GPUs), field-programmable gate arrays (FPGAs), tensor processing units (TPUs), application-specific integrated circuits (ASICs), any other type of heterogeneous accelerator processing unit (HAPU), etc.

[0042] Continue to refer to Figure 3 The computing system 300 can provide a storage space with a series of storage addresses for accessing (e.g., writing / reading) data in the computing system 300. The storage space includes DRAM 304 and cache 308. Therefore, the series of storage addresses includes a first set of addresses pointing to DRAM 304 and a second set of addresses pointing to cache 308. Thus, according to embodiments of this disclosure, in the computing system 300, cache 308 can also store partial data without storing copies of the data stored in DRAM 304. In other words, DRAM 304 and cache 308 together provide the storage functionality of the computing system 300.

[0043] Management unit 306 can determine whether a memory request (e.g., a memory read request or a memory write request) is directed to DRAM 304 or cache 308. Figure 3 In some embodiments, management unit 306 is shown as part of processing device 302. However, it will be understood that management unit 306 may also be implemented as a software component. Details of an exemplary management unit 306 will be described further below.

[0044] Cache 308 is an on-chip high-speed memory used for storing computations, data, and other work within a process. Cache 308 can be the next nearest memory after the processor registers of the ALU of processing device 302. Cache 308 can be relatively small in size and is therefore also referred to as scratchpad memory. Because cache 308 has a corresponding memory address in computing system 300 and also provides storage functionality to computing system 300 along with DRAM 304, cache 308 typically does not contain a copy of the data stored in DRAM 304.

[0045] As required by the processing device 302, the bus 310 can interconnect all internal components. While not all components are connected to every other component, all components are connected to other components with which they need to communicate.

[0046] Figure 5A A schematic diagram of an exemplary management unit 306 according to some embodiments of the present disclosure is shown.

[0047] like Figure 5A As shown, the management unit 306 includes a request processing subunit 502, a threshold generation subunit 504, and a data allocation subunit 506. These subunits can be further connected to other components of the computing system 300 via an interface or bus (e.g., bus 310). In some embodiments, the management unit 306 is implemented using, for example, an application-specific integrated circuit (ASIC) employing a hardware description language. In some embodiments, the management unit 306 is implemented by executing instructions on, for example, a processing device 302.

[0048] In some embodiments, the management unit 306 receives instructions from the processing device 302 to process the graph (e.g., Figure 1The graph (Figure 100) is loaded into the storage space of the computing system 300. The graph may include multiple nodes. Before being loaded, the graph may be stored in an external storage device (e.g., a hard disk). In some embodiments, the instructions include requests to allocate nodes to the storage space of the computing system 300. These instructions are generated by compiling a computing program related to graph processing.

[0049] The request processing subunit 502 can receive a request to allocate a node to storage space. As described above, the storage space includes DRAM 304 and cache 308. The request may also include the node's address in an external storage device. Based on the node's address in the external storage device, the node can be retrieved and preprocessed.

[0050] In some embodiments, request processing subunit 502 determines the degree of a node. For example, request processing subunit 502 traverses a graph (e.g., Figure 100 or 210) to determine the degree of a node. More specifically, request processing subunit 502 traverses the structural data of a node to determine the number of one or more neighboring nodes associated with that node.

[0051] Continue to refer to Figure 2B By traversing graph 210, request processing subunit 502 can determine, for example, that node 2 has pointers to three edges, therefore node 2 has three adjacent nodes. It should be understood that... Figure 2B The pointer may not be presented as a "pointer". In some embodiments, when the graph (e.g., Figure 210) is presented in Compressed Sparse Lines (CSR) format, Figure 2B The pointer is in the form of an offset within an array (e.g., array []), indicating the address of one or more adjacent nodes. For example, the offset P0 of node 0 could be '0', indicating that the address of the adjacent node is stored in array [0]. In another example, offsets P2 and P3 could be '3' and '6', respectively, indicating that the addresses of the adjacent nodes are stored in a series of arrays [3]-[6]. In other words, the number of adjacent nodes of node 2 could be the difference between offsets P3 and P2 (i.e., 6-3=3).

[0052] Therefore, the request processing subunit 502 can determine the number of one or more neighboring nodes associated with a node (e.g., node 2) as the node degree (e.g., 3).

[0053] The threshold generation subunit 504 can determine the conditions for node allocation. These conditions may include a node degree greater than a given threshold. In some embodiments, the threshold is determined by an administrator of the computing system 300. In some embodiments, the threshold is determined by instructions for loading the graph. In some embodiments, the threshold generation subunit 504 determines the available capacity of the cache 308 and adjusts the threshold based on the available capacity. For example, the threshold can be calculated based on the available capacity using a linear or nonlinear function, or it can be determined by adjusting a given threshold based on the available capacity. For example, the cache 308 may have only available capacity for storing three nodes, and the graph (e.g., FIG. 210) includes five nodes; therefore, the threshold is adjusted to reflect the limited available space in the cache 308. It is understood that the cache 308 may pass availability information to the threshold generation subunit 504 via, for example, bus 310.

[0054] Data allocation subunit 506 can allocate nodes (e.g., node 2 in FIG. 210) to storage space based on requests and conditions from request processing subunit 502 and threshold generation subunit 504. In some embodiments, data allocation subunit 506 determines whether a node meets a given condition (e.g., node degree is greater than a given threshold). When a node's node degree meets the given condition, data allocation subunit 506 allocates the node to cache 308.

[0055] In some embodiments, the data allocation subunit 506 allocates the node's attribute data and structure data to the cache 308, thereby improving the speed of accessing the node.

[0056] However, by allocating the node's attribute data and structure data to cache 308, the node data occupies a considerable amount of available space in cache 308. Therefore, in some embodiments, data allocation subunit 506 allocates the node's attribute data to cache 308 and allocates the node's structure data to DRAM 304. Figure 5B A schematic diagram of an exemplary node allocation 510 according to some embodiments of the present disclosure is shown. Figure 5B As shown, the attribute data of node 0 is allocated to a buffer (e.g., cache 308), and the structure data of node 0 is allocated to external memory (e.g., DRAM 304).

[0057] To allocate attribute data and structure data to cache 308 and DRAM 304 respectively, data allocation subunit 506 can also generate a mapping relationship between the node's attribute data and structure data. In some embodiments, the mapping relationship is stored as a part of the node's attribute data. Therefore, by allocating only attribute data in cache 308, the storage space of cache 308 can be utilized effectively.

[0058] When a node's degree fails to meet a given condition, the data allocation subunit 506 can allocate the node to DRAM 304. A node failing to meet the given condition means that the node is not frequently accessed by the computing program. Therefore, although the node is allocated to DRAM 304, which has a relatively slow access speed, the overall performance of the computing system is not significantly affected.

[0059] For example, refer to Figure 5B When the given condition is that the node degree is greater than 2, nodes 2 and 4, with a node degree of 3, satisfy the given condition. Therefore, the attribute data of nodes 2 and 4 are allocated to cache 308 to accelerate the access speed of Figure 210, and the structure data of nodes 2 and 4 are allocated to DRAM 304 to save storage space in cache 308. Since the given condition is not met, nodes 0, 1, and 3, with node degrees of 1, 2, and 2 respectively, are allocated to DRAM 304.

[0060] As described above, the series of memory addresses in the storage space of the computing system 300 may include a first set of addresses pointing to DRAM 304 and a second set of addresses pointing to cache 308. Therefore, after a node (e.g., node 2 in FIG. 210) is allocated to cache 308, the node's address falls within the second set of addresses. It is understood that in some embodiments, the node's structure data may be allocated separately in DRAM 304, and the address of the node's structure data falls within the first set of addresses. Furthermore, the address of the node's structure data can be determined based on a pointer associated with the address of the structure data in DRAM 304. Therefore, although the node's structure data may be allocated separately from the node's attribute data, the structure data can be accessed based on the node's address in cache 308.

[0061] Figure 6 A flowchart of a method 600 for performing memory management in graph processing according to some embodiments of the present disclosure is shown. Method 600 may be provided by, for example... Figure 3 The computing system 300 executes the method. The method 600 may include the following steps.

[0062] In step 602, the computing system may receive a request to allocate target node data to storage space. The storage space may include buffers (e.g., Figure 3 Cache 308) and external memory ( Figure 3 DRAM304). The target node data can represent a graph that includes multiple nodes and edges between the nodes (e.g., Figures 1-2BThe target node (Figure 100, 200, or 210). Target node data may include attribute data and structural data. For example, attribute data may also include at least one of the following: the target node's identifier, the target node's attributes, and a pointer to the structural data. Structural data may include the target node's edges.

[0063] In some embodiments, the computing system may receive instructions for graph processing. For example, instructions can be generated by compiling a computation program to determine relationships between nodes in a graph. Compilation instructions for graph processing may include a request to allocate target node data to storage space. It is understood that the target node represented by the target node data can be any one of multiple nodes in the graph.

[0064] In step 604, the computation system can determine the node degree associated with the target node data. The node degree associated with a node can be the number of edges connected to that node. In other words, the node degree is the number of neighboring nodes connected to that node. For example, in Figure 1 In Figure 100, node 0 has a degree of 1 because only node 1 is connected to node 0, while node 1 has a degree of 3 because nodes 0, 2, and 4 are connected to node 1. To determine the degree associated with target node data, the computation system can traverse the structured data of the target node data to determine the number of one or more nodes connected to the target node via corresponding edges, and determine the number of one or more nodes as the degree. In some embodiments, each node in the graph includes degree information. For example, a given field of a node can be used to contain degree information, and the computation system 300 can determine the degree of the target node based on such information.

[0065] In some embodiments, the target node is formatted as a Compressed Sparse Row (CSR). In a CSR, neighboring nodes of the target node can be determined based on offsets. Therefore, to determine the node degree of the target node, the computation system can determine the node degree of the target node based on a first offset and a second offset associated with the target node. For example, the first offset could be an offset indicating an edge to the target node, and the second offset could be an offset indicating an edge to a node stored next to the target node in the CSR. Therefore, the difference between a first number of edges indicated by the first offset and a second number of edges indicated by the second offset is the node degree of the target node.

[0066] In step 606, the computing system (e.g., data allocation subunit 506 of FIG. 5) may allocate a target node in the storage space based on the determined node degree. In some embodiments, the computing system may determine whether the node degree satisfies a given condition. In response to determining that the node degree satisfies the given condition, the computing system may partially allocate the target node data to the storage space. In some embodiments, the computing system may allocate attribute data of the target node data to a buffer and allocate structure data of the target node data to external memory. The attribute data of the target node data allocated in the buffer may also include a mapping of addresses of structure data in external memory. For example, a pointer to the target node data allocated in the buffer may be associated with an address of structure data in external memory. It is understood that the computing system may also allocate both the attribute data and structure data of the target node to the buffer.

[0067] In response to the determination that the node degree does not meet the given conditions, the computing system (e.g., the data allocation subunit 506 in Figure 5) can allocate the target node data to external memory.

[0068] The given condition can be determined, for example, by the threshold generation subunit 504 of Figure 5. In some embodiments, the given condition may include a node degree greater than a given threshold. The given threshold may be predetermined or calculated by a computing system. For example, the computing system (e.g., threshold generation subunit 504) may determine the available capacity of the buffer and adjust the given condition based on the available capacity. Thus, when there is less space available for nodes in the graph from the buffer, the threshold may be increased. Only nodes with higher node degrees can be assigned to the buffer.

[0069] According to various embodiments of this disclosure, the flowcharts and diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of devices, methods, and computer program products. In this regard, blocks in flowcharts or diagrams may represent software programs, segments, or portions of code, which include one or more executable instructions for implementing a specific function. It should also be noted that in some alternative implementations, the functions marked in the blocks may differ in order from those marked in the drawings. For example, two blocks shown consecutively may actually be executed substantially simultaneously, or sometimes in reverse order, depending on the functions involved. It will also be noted that each block in a diagram or flowchart, as well as combinations of blocks in diagrams and flowcharts, can be implemented by a system based on dedicated hardware that performs a specified function, action, or combination of dedicated hardware and computer instructions.

[0070] Embodiments of this disclosure are further illustrated by the following claims, which include:

[0071] 1. A storage management method, comprising:

[0072] Receive a request to allocate target node data to storage space, wherein the storage space includes a buffer and external memory, and the target node data includes attribute data and structure data, and represents the target node of a graph with multiple nodes and edges;

[0073] Determine the node degree associated with the target node data;

[0074] The target node data is allocated to the storage space based on the determined node degree.

[0075] 2. The storage management method according to claim 1, wherein allocating the target node data to the storage space based on the determined node degree comprises:

[0076] Determine whether the node degree satisfies the given condition; and

[0077] In response to determining that the node degree satisfies the given condition, the target node data is partially allocated to the buffer.

[0078] 3. The storage management method according to claim 2, wherein partially allocating the target node data to the buffer comprises:

[0079] Assign the attribute data to the buffer; and

[0080] The structure data is allocated to the external memory.

[0081] 4. The storage management method according to claim 3, wherein the attribute data of the target node includes at least one of the target node's identifier, the target node's attributes, and a pointer; and

[0082] The structural data of the target node includes the edges of the target node.

[0083] 5. The storage management method of claim 4, wherein the pointer of the target node allocated in the buffer is associated with the address of structure data in the external memory.

[0084] 6. The storage management method according to any one of claims 2-5, further comprising:

[0085] In response to determining that the node degree does not meet the given condition, the target node data is allocated to the external memory.

[0086] 7. The storage management method according to any one of claims 2-6, further comprising:

[0087] Determine the available capacity of the buffer; and

[0088] Adjust the given conditions based on the available capacity.

[0089] 8. The storage management method according to claim 7, wherein the given condition includes the node degree being greater than a given threshold.

[0090] 9. The storage management method according to any one of claims 1-8, wherein determining the node degree associated with the target node data includes:

[0091] Traverse the structure data of the target node to determine the number of one or more nodes connected to the target node via corresponding edges; and

[0092] The number of one or more nodes connected to the target node is defined as the node degree.

[0093] 10. The storage management method according to any one of claims 1-9, wherein the target node data is in a compressed sparse row format, and determining the node degree associated with the target node data further includes:

[0094] The node degree of the target node is determined based on a first offset and a second offset associated with the target node data.

[0095] 11. A computing system, comprising:

[0096] External memory is used to store a set of instructions;

[0097] The processor includes a buffer and circuitry configured to execute the set of instructions to cause the computing system to perform the following operations:

[0098] A request is received to allocate target node data to storage space, wherein the storage space includes the buffer and the external memory, and the target node data includes attribute data and structure data, and represents the target node of a graph with multiple nodes and edges;

[0099] Determine the node degree associated with the target node data;

[0100] The target node data is allocated to the storage space based on the determined node degree.

[0101] 12. The computing system of claim 11, wherein, in allocating the target node data to the storage space based on the determined node degree, the processor is configured to execute the set of instructions to cause the computing system to perform:

[0102] Determine whether the node degree satisfies the given condition; and

[0103] In response to determining that the node degree satisfies the given condition, the target node data is partially allocated to the buffer.

[0104] 13. The computing system of claim 12, wherein, when partially allocating the target node data to the buffer, the processor is configured to execute the set of instructions to cause the computing system to perform:

[0105] Assign the attribute data to the buffer; and

[0106] The structure data is allocated to the external memory.

[0107] 14. The computing system of claim 13, wherein the attribute data of the target node includes at least one of the identifier of the target node, the attributes of the target node, and a pointer; and

[0108] The structural data of the target node includes the edges of the target node.

[0109] 15. The computing system of claim 14, wherein the pointer to the target node allocated in the buffer is associated with the address of structure data in the external memory.

[0110] 16. The computing system according to any one of claims 12-15, wherein the processor is configured to execute the set of instructions to cause the computing system to perform:

[0111] In response to determining that the node degree does not meet the given condition, the target node data is allocated to the external memory.

[0112] 17. The computing system of any one of claims 12-16, wherein the processor is configured to execute the set of instructions to cause the computing system to perform:

[0113] Determine the available capacity of the buffer; and

[0114] Adjust the given conditions based on the available capacity.

[0115] 18. The computing system of claim 17, wherein the given condition includes the node degree being greater than a given threshold.

[0116] 19. The computing system according to any one of claims 11-18, wherein, in determining the node degree associated with the target node data, the processor is configured to execute the set of instructions to cause the computing system to perform:

[0117] Traverse the structure data of the target node to determine the number of one or more nodes connected to the target node via corresponding edges; and

[0118] The number of one or more nodes connected to the target node is defined as the node degree.

[0119] 20. The computing system according to any one of claims 11-19, wherein the target node data is in a compressed sparse line format, and in determining the node degree associated with the target node data, the processor is configured to execute the set of instructions to cause the computing system to perform:

[0120] The node degree of the target node is determined based on a first offset and a second offset associated with the target node data.

[0121] As used herein, the terms “comprising,” “including,” or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, composition, article, or apparatus that includes a list of elements may include not only those elements but also other elements not expressly listed or inherent to such a process, method, composition, article, or apparatus. The term “exemplary” is used in the sense of “example” rather than “ideal.”

[0122] As used herein, unless otherwise specified, the term "or" includes all possible combinations unless impractical. For example, if a database is stated to include A or B, then unless otherwise expressly stated or impractical, the database may include A, B, or A and B. As a second example, if a database is stated to include A, B, or C, then unless otherwise expressly stated or impractical, the database may include A, B, or C, or A and B, or A and C, or B and C, or A and B and C.

[0123] It should be understood that, for clarity, certain features of this disclosure described in the context of different embodiments may also be provided in combination in a single embodiment. Conversely, for brevity, various features of this disclosure described in the context of a single embodiment may also be provided separately, or in any suitable sub-combination, or in any other described embodiment of the appropriate disclosure. Certain features described in the context of various embodiments should not be considered as essential features of those embodiments unless the embodiment cannot be practiced without those elements.

Claims

1. A storage management method, comprising: Receive a request to allocate target node data stored in an external storage device to a storage space, wherein the storage space includes a buffer and an external random access memory, and the target node data includes attribute data and structure data, and represents the target node of a graph with multiple nodes and edges; Determine the node degree associated with the target node data; Based on the determined node degree, the target node data is allocated from the external storage device to the location in the memory space between the buffer and the external random access memory; Based on the determined allocation location of the target node data, the target node data is allocated to the buffer or the external random access memory, including: The attribute data of the target node is allocated to the buffer, and the structural data of the same target node is allocated to the external random access memory. The attribute data of the target node allocated in the buffer includes a pointer associated with the structure data address of the target node in the external random access memory.

2. The storage management method according to claim 1, wherein, The process of allocating the target node data to the storage space based on the determined node degree includes: Determine whether the node degree satisfies the given condition; and In response to determining that the node degree satisfies the given condition, the target node data is partially allocated to the buffer.

3. The storage management method according to claim 2, wherein, Allocating the target node data partially to the buffer includes: Assign the attribute data to the buffer; and The structure data is allocated to the external memory.

4. The storage management method according to claim 3, wherein, The attribute data of the target node includes at least one of the following: the identifier of the target node, the attributes of the target node, and a pointer; and The structural data of the target node includes the edges of the target node.

5. The storage management method according to claim 2, wherein, Also includes: In response to determining that the node degree does not meet the given condition, the target node data is allocated to the external memory.

6. The storage management method according to claim 2, wherein, Also includes: Determine the available capacity of the buffer; as well as Adjust the given conditions based on the available capacity.

7. The storage management method according to claim 6, wherein, The given condition includes the node degree being greater than a given threshold.

8. The storage management method according to claim 1, wherein, The determination of the node degree associated with the target node data includes: Traverse the structure data of the target node to determine the number of one or more nodes connected to the target node via corresponding edges; and The number of one or more nodes connected to the target node is defined as the node degree.

9. The storage management method according to claim 1, wherein, The target node data is in a compressed sparse row format, and determining the node degree associated with the target node data includes: The node degree of the target node is determined based on a first offset and a second offset associated with the target node data.

10. A computing system, comprising: External memory is used to store a set of instructions; The processor includes a buffer and circuitry configured to execute the set of instructions to cause the computing system to perform the following operations: A request is received to allocate target node data stored in an external storage device to a storage space, wherein the storage space includes the buffer and the external random access memory, and the target node data includes attribute data and structure data, and represents the target node of a graph with multiple nodes and edges; Determine the node degree associated with the target node data; Based on the determined node degree, the target node data is allocated from the external storage device to the location in the memory space between the buffer and the external random access memory; Based on the determined allocation location of the target node data, the target node data is allocated to the buffer or the external random access memory, including: The attribute data of the target node is allocated to the buffer, and the structural data of the same target node is allocated to the external random access memory. The attribute data of the target node allocated in the buffer includes a pointer associated with the structure data address of the target node in the external random access memory.

11. The computing system according to claim 10, wherein, In allocating the target node data to the storage space based on the determined node degree, the processor is configured to execute the set of instructions to cause the computing system to perform: Determine whether the node degree satisfies the given conditions; as well as In response to determining that the node degree satisfies the given condition, the target node data is partially allocated to the buffer.

12. The computing system according to claim 11, wherein, In allocating the target node data partially to the buffer, the processor is configured to execute the set of instructions to cause the computing system to perform: Assign the attribute data to the buffer; as well as The structure data is allocated to the external memory.

13. The computing system according to claim 12, wherein, The attribute data of the target node includes at least one of the following: the identifier of the target node, the attributes of the target node, and a pointer; and The structural data of the target node includes the edges of the target node.

14. The computing system according to claim 11, wherein, The processor is configured to execute the set of instructions to cause the computing system to perform: In response to determining that the node degree does not meet the given condition, the target node data is allocated to the external memory.

15. The computing system according to claim 11, wherein, The processor is configured to execute the set of instructions to cause the computing system to perform: Determine the available capacity of the buffer; as well as Adjust the given conditions based on the available capacity.

16. The computing system according to claim 15, wherein, The given condition includes the node degree being greater than a given threshold.

17. The computing system according to claim 10, wherein, In determining the node degree associated with the target node data, the processor is configured to execute the set of instructions to cause the computing system to perform: Traverse the structure data of the target node to determine the number of one or more nodes connected to the target node through corresponding edges; as well as The number of one or more nodes connected to the target node is defined as the node degree.

18. The computing system according to claim 10, wherein, The target node data is in a compressed sparse line format. In determining the node degree associated with the target node data, the processor is configured to execute the set of instructions to cause the computing system to perform: The node degree of the target node is determined based on a first offset and a second offset associated with the target node data.

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