A four-bit tree-type advance carry adder based on unipolar transistor and chip

Abstract

The application discloses a four-bit tree type advance carry adder based on unipolar transistor and a chip, wherein the adder is composed of differential logic gates, the differential logic gates are composed of multiple unipolar oxide thin film transistors, and the carry link of the four-bit tree type advance carry adder is optimized by using Koggle-Stone parallel algorithm. The adder is only composed of unipolar transistors and is suitable for flexible electronic technology which can be prepared in a large area. In addition, the carry link is optimized by using Koggle-Stone parallel algorithm, so that the wiring can be optimized, the intermediate link is increased and the wiring stability is improved without changing the advance carry characteristic. The application can be widely applied in the field of semiconductor integrated circuits.

Description

Technical Field

[0001] This invention relates to the field of semiconductor integrated circuits, and more particularly to a four-bit tree-structured carry-lookahead adder and chip based on unipolar transistors. Background Technology

[0002] Oxide thin-film transistors (TFTs) possess advantages such as simple fabrication process, low manufacturing cost, flexibility, stretchability, and large-area fabrication, making them a strong candidate for next-generation electronic devices. Currently, many characteristics of oxide TFTs perfectly meet the manufacturing requirements of new electronic devices, showing promising application prospects in future wireless radio frequency identification, wearable technology, and sensor electronic system design. While oxide TFT technology boasts numerous advantages, the lack of high-performance complementary devices poses a significant challenge to circuit design. Therefore, under normal circumstances, TFT circuit design can only utilize unipolar transistors and cannot employ traditional silicon-based CMOS technology.

[0003] An adder is a device that performs numerical addition, typically using binary operations. From the rules of binary addition, subtraction, multiplication, and division, we know that in digital circuits, multipliers, subtractors, and integrators can all be converted into adders. Therefore, the adder is the core and foundation of digital arithmetic circuits. Adders are also an important component of arithmetic logic units (ALUs) and microprocessors (CPU circuits). Currently, TFT circuits can implement 8-bit microprocessors; however, with the development of TFT circuits, achieving higher bit-count and faster processor circuits in the future requires further optimization of adder circuits. Summary of the Invention

[0004] In order to at least partially solve one of the technical problems existing in the prior art, the present invention aims to provide a four-bit tree-structured carry-lookahead adder and chip based on a unipolar transistor.

[0005] The technical solution adopted in this invention is:

[0006] A four-bit tree-structured carry-lookahead adder based on unipolar transistors is constructed using differential logic gates, each consisting of multiple unipolar oxide thin-film transistors. The carry path of the four-bit tree-structured carry-lookahead adder is optimized using the Koggle-Stone parallel algorithm.

[0007] Furthermore, the carry logic expression of the four-bit tree-structured carry-lookahead adder is as follows:

[0008] C0 = G0 (1)

[0009] C1=G1+P1C0=G1+P1G0 (2)

[0010] C2=G2+P2C1=G2+P2G1+P2P1G0 (3)

[0011] C3=G3+P3C2=G3+P3G2+P3P2G1+P3P2P1G0 (4)

[0012] In the formula, C i This is the carry input signal. G = AB, where A and B are the input signals of the full adder;

[0013] The formula for the Koggle-Stone parallel algorithm is as follows:

[0014]

[0015] in,

[0016] From formulas (1)-(4), we know that the formula for the adder carry chain is: C i =G i +P i C i-1 ;Optimize the carry path of the adder using the Koggle-Stone parallel algorithm, and obtain:

[0017] Q[1,1]=C1=P1C0+G1 (6)

[0018] Q[2,1]=C2=P2C1+G2=P2Q[1,1]+G2 (7)

[0019] Q[3,1]=C3=P3C2+G3=P3P2Q[1,1]+Q[3,2] (8)

[0020] Q[4,1]=C4=P4C3+G4=P4P3Q[2,1]+Q[4,3] (9)

[0021] Based on formulas (5)-(9), the logical expressions for Q[2,1], Q[3,2], and Q[4,3] are obtained;

[0022] After optimization using the Koggle-Stone parallel algorithm, the carry chain expression will consist of two parallel operations, as shown below:

[0023]

[0024] Furthermore, the carry path of the tree-shaped adder optimized using the Koggle-Stone parallel algorithm includes AB+C logic gates and ABC+D logic gates. ACRL logic is used to implement the AB+C logic gates and ABC+D logic gates to further optimize the adder.

[0025] Furthermore, the logic gate of the AB+C includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a first inverter, and a second inverter;

[0026] The first transistor has a gate input signal A, the second transistor has a gate input signal C, and the third transistor has a gate input signal B; the source of the first transistor is connected to the drain of the third transistor, the drain of the first transistor is connected to the drain of the second transistor, and the source of the second transistor and the source of the third transistor are both grounded.

[0027] The gate input signal A of the fourth transistor, the gate input signal C of the fifth transistor, and the gate input signal B of the sixth transistor; the source of the fourth transistor is connected to the drain of the sixth transistor, the drain of the fourth transistor is connected to the drain of the fifth transistor, and the source of the fifth transistor and the source of the sixth transistor are both grounded.

[0028] The source of the seventh transistor is connected to the drain of the first transistor, and the gate and drain of the seventh transistor are both connected to the power supply voltage; the gate of the eighth transistor is connected to the drain of the first transistor, the drain of the eighth transistor is connected to the power supply voltage, and the source of the eighth transistor is connected to the drain of the fourth transistor.

[0029] The input terminal of the first inverter is connected to the source of the eighth transistor, the output terminal of the first inverter is connected to the input terminal of the second inverter, and the output terminal of the first inverter serves as the output terminal of the AB+C logic gate.

[0030] Furthermore, the logic gates of ABC+D include the ninth transistor, the tenth transistor, the eleventh transistor, the twelfth transistor, the thirteenth transistor, the fourteenth transistor, the fifteenth transistor, the sixteenth transistor, the seventeenth transistor, the eighteenth transistor, the third inverter, and the fourth inverter;

[0031] The gate input signal A of the ninth transistor, the gate input signal B of the tenth transistor, the gate input signal C of the eleventh transistor, and the gate input signal D of the twelfth transistor; the drain of the ninth transistor is connected to the drain of the twelfth transistor, the source of the ninth transistor is connected to the drain of the tenth transistor, the source of the tenth transistor is connected to the drain of the eleventh transistor, and the source of the eleventh transistor and the source of the twelfth transistor are both grounded;

[0032] The gate input signal A of the thirteenth transistor, the gate input signal B of the fourteenth transistor, the gate input signal C of the fifteenth transistor, and the gate input signal D of the sixteenth transistor; the drain of the thirteenth transistor is connected to the drain of the sixteenth transistor, the source of the thirteenth transistor is connected to the drain of the fourteenth transistor, the source of the fourteenth transistor is connected to the drain of the fifteenth transistor, and the sources of the fifteenth transistor and the sixteenth transistor are both grounded;

[0033] The source of the seventeenth transistor is connected to the drain of the first transistor, and the gate and drain of the seventeenth transistor are both connected to the power supply voltage; the gate of the eighteenth transistor is connected to the drain of the ninth transistor, the drain of the eighteenth transistor is connected to the power supply voltage, and the source of the eighteenth transistor is connected to the drain of the thirteenth transistor.

[0034] The input terminal of the third inverter is connected to the source of the eighteenth transistor, the output terminal of the third inverter is connected to the input terminal of the fourth inverter, and the output terminal of the fourth inverter serves as the output terminal of the logic gate ABC+D.

[0035] Furthermore, the differential logic gates include differential AND gates and differential OR gates.

[0036] Furthermore, the differential logic gate includes an XOR gate for transmission transistor logic.

[0037] Another technical solution adopted in this invention is:

[0038] A chip comprising a four-bit tree-structured carry-lookahead adder based on a unipolar transistor as described above.

[0039] The beneficial effects of this invention are: the adder of this invention is composed of only unipolar transistors, which is suitable for flexible electronics technology that can be fabricated on a large area; in addition, by using the Koggle-Stone parallel algorithm to optimize the carry link, the wiring can be optimized without changing the carry-lookahead characteristics, and intermediate links can be added to optimize the wiring and improve stability. Attached Figure Description

[0040] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following description is provided with accompanying drawings of the relevant technical solutions in the embodiments of the present invention or the prior art. It should be understood that the accompanying drawings described below are only for the purpose of clearly illustrating some embodiments of the technical solutions of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0041] Figure 1 This is a structural diagram of a four-bit logarithmic carry-lookahead adder in an embodiment of the present invention;

[0042] Figure 2 This is a structural diagram of the differential logic AND gate in an embodiment of the present invention;

[0043] Figure 3 This is a structural diagram of the differential logic OR gate in an embodiment of the present invention;

[0044] Figure 4 This is a structural diagram of the XOR gate of the transmission tube logic in an embodiment of the present invention;

[0045] Figure 5 This is a structural diagram of the AB+C logic gate in an embodiment of the present invention;

[0046] Figure 6 This is a structural diagram of the ABC+D logic gates in an embodiment of the present invention;

[0047] Figure 7 This is a structural diagram of a four-bit tree adder using ACRL logic gates in an embodiment of the present invention;

[0048] Figure 8 This is a schematic diagram of the simulation waveform of the adder function in an embodiment of the present invention. Detailed Implementation

[0049] The embodiments of the present invention are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention. The step numbers in the following embodiments are set only for ease of explanation, and there is no limitation on the order between the steps. The execution order of each step in the embodiments can be adaptively adjusted according to the understanding of those skilled in the art.

[0050] In the description of this invention, it should be understood that the orientation descriptions, such as up, down, front, back, left, right, etc., are based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limiting this invention.

[0051] In the description of this invention, "several" means one or more, "more than" means two or more, "greater than," "less than," and "exceeding" are understood to exclude the stated number, while "above," "below," and "within" are understood to include the stated number. The use of "first" and "second" in the description is merely for distinguishing technical features and should not be construed as indicating or implying relative importance, or implicitly indicating the number of indicated technical features, or implicitly indicating the order of the indicated technical features.

[0052] In the description of this invention, unless otherwise explicitly defined, terms such as "set up," "install," and "connect" should be interpreted broadly, and those skilled in the art can reasonably determine the specific meaning of the above terms in this invention in conjunction with the specific content of the technical solution.

[0053] The design of an existing four-bit logarithmic carry-lookahead adder is as follows:

[0054] A full adder can be represented by the following logical expression:

[0055] C0(G, P) = G + PC i

[0056]

[0057] Where G = AB, In the formula, A and B are the input signals of the full adder to be summed, and C... i S is the carry input signal, S is the sum of the results, and C0 is the carry output of the results.

[0058] A typical traveling wave adder consists of four 1-bit full adders connected in parallel. This means that each carry can only be calculated after the carry output of the previous stage, which increases the delay time of the adder circuit.

[0059] Therefore, this embodiment proposes a novel four-bit adder that employs gates with differential logic, transport complementary logic, and ACRL logic gates. Furthermore, it utilizes the Koggle-Stone parallel algorithm to optimize the carry link structure, achieving low power consumption and low latency while performing normal four-bit addition operations. A detailed explanation follows.

[0060] This embodiment optimizes the logic expression of the carry-out terminal, and then designs the circuit based on this logic expression. First, the carry logic expression of the adder is optimized to make it a carry-lookahead adder. Therefore:

[0061] C0 = G0 (1)

[0062] C1=G1+P1C0=G1+P1G0 (2)

[0063] C2=G2+P2C1=G2+P2G1+P2P1G0 (3)

[0064] C3=G3+P3C2=G3+P3G2+P3P2G1+P3P2P1G0 (4)

[0065] As can be seen from expressions (1)-(4), the carry-out of each stage is now only related to the inputs A and B of that stage. Therefore, the calculation time of the carry-out will be greatly reduced, and a four-bit carry-lookahead adder can be designed accordingly. However, as the number of bits increases, the number of logic gates that the input circuit needs to pass through will also increase significantly. This will lead to an increase in the accumulation of parasitic resistance and parasitic capacitance of the carry-out circuit, making it impossible to optimize the output delay when the number of bits is large. Moreover, the carry-lookahead adder needs to use multi-fan-in AND-OR gates to ensure its own delay, and the overly complex combinational logic itself greatly reduces the stability of the circuit, making it extremely easy to generate race conditions and hazards, which will lead to the continuous propagation of some metastable states.

[0066] Therefore, in this embodiment, the Koggle-Stone parallel algorithm can be used to further optimize the carry logic expression.

[0067] The Koggle-Stone parallel algorithm proposes a new operator, as shown in equation (5):

[0068]

[0069] in,

[0070]

[0071] From formulas (1)-(4), we know that the formula for the adder carry chain is: C i =G i +P i C i-1 Using the Koggle-Stone parallel algorithm, the carry path of the adder can be further optimized. This results in:

[0072] Q[1,1]=C1=P1C0+G1 (6)

[0073] Q[2,1]=C2=P2C1+G2=P2Q[1,1]+G2 (7)

[0074] Q[3,1]=C3=P3C2+G3=P3P2Q[1,1]+Q[3,2] (8)

[0075] Q[4,1]=C4=P4C3+G4=P4P3Q[2,1]+Q[4,3] (9)

[0076] Based on formulas (5)-(9), the logical expressions for Q[2,1], Q[3,2], and Q[4,3] are obtained; thus, a four-bit logarithmic carry-lookahead adder is designed, such as... Figure 1 As shown. After optimization using this algorithm, the carry chain expression will consist of two parts of parallel computation, as shown below:

[0077]

[0078] When i is not an integer, it is rounded down. For example, if i = 1.5, 0.5 is removed and the result is rounded down to 1.

[0079] In this way, the carry output of each stage is not only related to the input of that stage, but can also be obtained by combining two parallel circuits, thereby further improving the operation speed of the carry link based on the carry-lookahead adder. Furthermore, the larger the number of bits K, the more significant the improvement in adder calculation speed will be, allowing the adder to be used even with high bit counts. Moreover, the tree-structured adder designed using the Koggle-Stone parallel algorithm has a low number of logic levels and low fan-in / fan-out, and it can optimize routing and add intermediate links without changing the carry-lookahead characteristics, thereby improving routing stability.

[0080] like Figure 1 As shown, this embodiment provides a four-bit tree-structured carry-lookahead adder based on unipolar transistors, which is constructed using differential logic gates. The differential logic gates are composed of multiple unipolar oxide thin-film transistors, and the carry path of the four-bit tree-structured carry-lookahead adder is optimized using the Koggle-Stone parallel algorithm.

[0081] Because the adder in this embodiment uses a unipolar oxide thin-film transistor process, traditional complementary CMOS logic gates cannot be used. Unlike traditional CMOS designs, Figure 1 The circuit structure uses a series of gate circuits employing differential logic and transmission transistor logic, and consists only of n-type transistors. Figure 2 The circuit structure of differential logic gates, including differential AND gates, is given. Figure 3The circuit structure of the differential logic OR gate is given; Figure 4 The circuit structure of the XOR gate in the transmission transistor logic is presented. Compared to pseudo-CMOS logic, differential logic units have lower static power consumption, thus optimizing adder power consumption. Differential logic units also provide complementary output signal pairs, directly implementing logic gates such as "OR" and "AND," thereby reducing the stacking of inverters on the link and optimizing both delay and power consumption.

[0082] In order to better cascade with differential input AND-OR gates and NAND gates without introducing additional inverters, the XOR gate in the adder also uses differential inputs. Therefore, we give priority to using XOR gates with transmission transistor logic.

[0083] For the three-input AND gate, since differential logic can only have two inputs, we use a traditional pseudo-CMOS three-input AND gate. By using gates with differential logic and transmission transistor logic, the number of gate layers in the carry path of the entire adder will be reduced compared to an adder that directly uses a pseudo-CMOS structure, thereby further optimizing the adder's speed and power consumption.

[0084] As an optional implementation, the underlying logic gates of the four-bit logarithmic carry-lookahead adder are further optimized.

[0085] As shown in equations (5)-(10), the carry path of the tree adder designed using the Koggle-Stone parallel algorithm will use the AB+C and ABC+D logic gates multiple times. Therefore, we can use ACRL logic to implement the AB+C and ABC+D logic gates to further optimize the speed of the adder.

[0086] like Figure 5 As shown, the logic gates of AB+C include the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, the eighth transistor M8, the first inverter, and the second inverter.

[0087] The gate input signal of the first transistor M1 is A, the gate input signal of the second transistor M2 is C, and the gate input signal of the third transistor M3 is B; the source of the first transistor M1 is connected to the drain of the third transistor M3, the drain of the first transistor M1 is connected to the drain of the second transistor M2, and the source of the second transistor M2 and the source of the third transistor M3 are both grounded.

[0088] The gate input signal of the fourth transistor M4 is A, the gate input signal of the fifth transistor M5 is C, and the gate input signal of the sixth transistor M6 is B; the source of the fourth transistor M4 is connected to the drain of the sixth transistor M6, the drain of the fourth transistor M4 is connected to the drain of the fifth transistor M5, and the source of the fifth transistor M5 and the source of the sixth transistor M6 are both grounded.

[0089] The source of the seventh transistor M7 is connected to the drain of the first transistor M1, and the gate and drain of the seventh transistor M7 are both connected to the power supply voltage; the gate of the eighth transistor M8 is connected to the drain of the first transistor M1, the drain of the eighth transistor M8 is connected to the power supply voltage, and the source of the eighth transistor M8 is connected to the drain of the fourth transistor M4.

[0090] The input of the first inverter is connected to the source of the eighth transistor M8, and the output of the first inverter is connected to the input of the second inverter. The output of the first inverter serves as the output of the AB+C logic gate.

[0091] The ACRL logic gate AB+C has a pre-drive stage and an output stage. When the pull-down network (transistors M1-M3) of the pre-drive stage is ON, the voltage at the gate of transistor M8 can drop rapidly, thus greatly reducing the current flowing up to the output stage transistor M8. Transistor M7 is an N-type load used to achieve a balanced voltage level at the gate of transistor M8 and can be held high when there is no path for transistors M1-M6 to conduct. To simplify the circuit complexity, the gate of transistor M7 is connected to VDD. Since both transistors M1-M3 and M4-M6 use a connection method where input A is in series with input B and then in parallel with input C, it implements the AB+C logic gate. The logic gate contains two inverters; after the first inverter, AB+C is achieved; the second inverter is added for integration with differential logic.

[0092] like Figure 6 As shown, the logic gates of ABC+D include the ninth transistor M9, the tenth transistor M10, the eleventh transistor M11, the twelfth transistor M12, the thirteenth transistor M13, the fourteenth transistor M14, the fifteenth transistor M15, the sixteenth transistor M16, the seventeenth transistor M17, the eighteenth transistor M18, the third inverter, and the fourth inverter.

[0093] The gate input signal A of the ninth transistor M9, the gate input signal B of the tenth transistor M10, the gate input signal C of the eleventh transistor M11, and the gate input signal D of the twelfth transistor M12; the drain of the ninth transistor M9 is connected to the drain of the twelfth transistor M12, the source of the ninth transistor M9 is connected to the drain of the tenth transistor M10, the source of the tenth transistor M10 is connected to the drain of the eleventh transistor M11, and the source of the eleventh transistor M11 and the source of the twelfth transistor M12 are both grounded;

[0094] The gate input signal of the thirteenth transistor M13 is A, the gate input signal of the fourteenth transistor M14 is B, the gate input signal of the fifteenth transistor M15 is C, and the gate input signal of the sixteenth transistor M16 is D; the drain of the thirteenth transistor M13 is connected to the drain of the sixteenth transistor M16, the source of the thirteenth transistor M13 is connected to the drain of the fourteenth transistor M14, the source of the fourteenth transistor M14 is connected to the drain of the fifteenth transistor M15, and the sources of the fifteenth transistor M15 and the sixteenth transistor M16 are both grounded;

[0095] The source of the seventeenth transistor M17 is connected to the drain of the first transistor, and the gate and drain of the seventeenth transistor M17 are both connected to the power supply voltage; the gate of the eighteenth transistor M18 is connected to the drain of the ninth transistor M9, the drain of the eighteenth transistor M18 is connected to the power supply voltage, and the source of the eighteenth transistor M18 is connected to the drain of the thirteenth transistor M13.

[0096] The input of the third inverter is connected to the source of the eighteenth transistor M18, and the output of the third inverter is connected to the input of the fourth inverter. The output of the fourth inverter serves as the output of the ABC+D logic gate.

[0097] The principle of the ABC+D logic gate is... Figure 5 The principle of the AB+C logic gate is the same. Since both (transistor M9-M12) and (transistor M13-M16) use the connection method of series connection of input A, input B, and input C, and then parallel connection of input D, they implement the ABC+D logic gate.

[0098] The circuit diagram of the four-bit tree adder after using ACRL logic gates is as follows: Figure 7 As shown, by using ACRL logic gates to implement AB+C and ABC+D, the number of gate circuits in the adder will be reduced, which further reduces the adder's delay. Furthermore, since AB+C and ABC+D are used multiple times in the carry path of the tree-structured adder designed using the Koggle-Stone parallel algorithm, this will reduce the congestion of the adder's placement and routing.

[0099] Experimental simulation

[0100] See Figure 8 We simulated a four-bit tree-structured carry-lookahead adder with inputs [B4, B3, B2, B1] of 1111 and [A4, A3, A2, A1] changing from 0000 to 0001. In this case, the highest carry C4 propagates from C1, resulting in the longest delay; therefore, this critical path is called the worst-case delay path. We will conduct simulation tests on this path. The output waveform is shown below. Figure 4 As shown, [S1,S2,S3,S4] changes from 1111 to 0000, and C4 changes from 0 to 1. The four-bit adder correctly obtained the calculation result.

[0101] Table 1 presents the simulation results of the adder, which has a carry propagation delay of 2.27 μs, a rise time of 4.0 μs, a fall time of 0.6 μs, and a carry link current consumption of 215 μA. This verifies that the adder achieves correct computational functionality while simultaneously maintaining low power consumption and low latency.

[0102] Table 1 Simulation results of the adder

[0103] Transmission delay (μs) 2.27 Carry link current consumption (μA) 215 Rise time (μs) 4.0 Fall time (μs) 0.6

[0104] In summary, the adder of this embodiment has the following advantages and beneficial effects compared to the prior art:

[0105] (1) The adder in this embodiment is composed of only unipolar transistors, which is suitable for flexible electronic technologies that can be fabricated on a large area (such as thin film transistors, carbon nanotubes, etc.).

[0106] (2) The carry link is optimized by using the koggle_stone parallel algorithm. A four-bit tree structure adder is designed with low logic level and low fan-in and fan-out. Furthermore, it can optimize the routing and increase intermediate links without changing the carry-lookahead characteristics, thereby optimizing the routing and improving stability.

[0107] (3) Applying transmission tube logic and differential logic gates to the bottom layer module of the adder reduces the number of gate circuits in the adder, speeds up the response speed of the adder, and reduces the power consumption of the adder.

[0108] (4) Since ACRL logic gates are used to implement AB+C and ABC+D, the number of gate circuits in the adder will be reduced, which further reduces the delay of the adder and further reduces the congestion of the tree adder layout and routing.

[0109] This embodiment also provides a chip, the chip comprising as follows: Figure 1 or Figure 7The diagram shows a four-bit tree-structured carry-lookahead adder based on a unipolar transistor.

[0110] The chip in this embodiment has the same structure as the four-bit tree-shaped carry-lookahead adder based on unipolar transistors in the above embodiment, and therefore has the same function and beneficial effects.

[0111] In the foregoing description of this specification, references to terms such as "one embodiment," "another embodiment," or "some embodiments" indicate that a specific feature, structure, material, or characteristic described in connection with an embodiment or example is included in at least one embodiment or example of the present invention. In this specification, illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0112] Although embodiments of the invention have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the claims and their equivalents.

[0113] The above is a detailed description of the preferred embodiments of the present invention. However, the present invention is not limited to the above embodiments. Those skilled in the art can make various equivalent modifications or substitutions without departing from the spirit of the present invention. All such equivalent modifications or substitutions are included within the scope defined by the claims of this application.

Claims

1. A four-bit tree-structured carry-lookahead adder based on a unipolar transistor, characterized in that, It is constructed using differential logic gates, which are composed of multiple unipolar oxide thin-film transistors. The carry link of the four-bit tree-shaped carry-lookahead adder is optimized using the Koggle-Stone parallel algorithm. The carry logic expression for the four-bit tree-structured carry-lookahead adder is as follows: （1） （2） （3） （4） In the formula, This is the carry input signal. , A and B are the input signals of the full adder; The formula for the Koggle-Stone parallel algorithm is as follows: （5） in, ; From formulas (1)-(4), we can see that the formula for the carry chain of the adder is: ;Optimize the carry path of the adder using the Koggle-Stone parallel algorithm, and obtain: （6） （7） （8） （9） According to formulas (5)-(9), we can obtain , , The logical expression; After optimization using the Koggle-Stone parallel algorithm, the carry chain expression will consist of two parallel operations, as shown below: 。 2. A four-bit tree-structured carry-lookahead adder based on a unipolar transistor according to claim 1, characterized in that, The carry path of the tree-shaped adder optimized using the Koggle-Stone parallel algorithm includes logic gates for AB+C and ABC+D. ACRL logic is used to implement the logic gates for AB+C and ABC+D to further optimize the adder.

3. A four-bit tree-structured carry-lookahead adder based on a unipolar transistor according to claim 2, characterized in that, The AB+C logic gates include a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a first inverter, and a second inverter; The first transistor has a gate input signal A, the second transistor has a gate input signal C, and the third transistor has a gate input signal B; the source of the first transistor is connected to the drain of the third transistor, the drain of the first transistor is connected to the drain of the second transistor, and the source of the second transistor and the source of the third transistor are both grounded. The gate input signal A of the fourth transistor, the gate input signal C of the fifth transistor, and the gate input signal B of the sixth transistor; the source of the fourth transistor is connected to the drain of the sixth transistor, the drain of the fourth transistor is connected to the drain of the fifth transistor, and the source of the fifth transistor and the source of the sixth transistor are both grounded. The source of the seventh transistor is connected to the drain of the first transistor, and the gate and drain of the seventh transistor are both connected to the power supply voltage; the gate of the eighth transistor is connected to the drain of the first transistor, the drain of the eighth transistor is connected to the power supply voltage, and the source of the eighth transistor is connected to the drain of the fourth transistor. The input terminal of the first inverter is connected to the source of the eighth transistor, the output terminal of the first inverter is connected to the input terminal of the second inverter, and the output terminal of the first inverter serves as the output terminal of the AB+C logic gate.

4. A four-bit tree-structured carry-lookahead adder based on a unipolar transistor according to claim 3, characterized in that, The logic gates of ABC+D include the ninth transistor, the tenth transistor, the eleventh transistor, the twelfth transistor, the thirteenth transistor, the fourteenth transistor, the fifteenth transistor, the sixteenth transistor, the seventeenth transistor, the eighteenth transistor, the third inverter, and the fourth inverter; The gate input signal A of the ninth transistor, the gate input signal B of the tenth transistor, the gate input signal C of the eleventh transistor, and the gate input signal D of the twelfth transistor; the drain of the ninth transistor is connected to the drain of the twelfth transistor, the source of the ninth transistor is connected to the drain of the tenth transistor, the source of the tenth transistor is connected to the drain of the eleventh transistor, and the source of the eleventh transistor and the source of the twelfth transistor are both grounded; The gate input signal A of the thirteenth transistor, the gate input signal B of the fourteenth transistor, the gate input signal C of the fifteenth transistor, and the gate input signal D of the sixteenth transistor; the drain of the thirteenth transistor is connected to the drain of the sixteenth transistor, the source of the thirteenth transistor is connected to the drain of the fourteenth transistor, the source of the fourteenth transistor is connected to the drain of the fifteenth transistor, and the sources of the fifteenth transistor and the sixteenth transistor are both grounded; The source of the seventeenth transistor is connected to the drain of the first transistor, and the gate and drain of the seventeenth transistor are both connected to the power supply voltage; the gate of the eighteenth transistor is connected to the drain of the ninth transistor, the drain of the eighteenth transistor is connected to the power supply voltage, and the source of the eighteenth transistor is connected to the drain of the thirteenth transistor. The input terminal of the third inverter is connected to the source of the eighteenth transistor, the output terminal of the third inverter is connected to the input terminal of the fourth inverter, and the output terminal of the fourth inverter serves as the output terminal of the logic gate ABC+D.

5. A four-bit tree-structured carry-lookahead adder based on a unipolar transistor according to claim 1, characterized in that, The differential logic gates include differential AND gates and differential OR gates.

6. A four-bit tree-structured carry-lookahead adder based on a unipolar transistor according to claim 1, characterized in that, The differential logic gates include XOR gates of transmission transistor logic.

7. A chip, characterized in that, Including a four-bit tree-structured carry-lookahead adder based on a unipolar transistor as described in any one of claims 1-6.

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