一种用于VHDL可编程逻辑设计的跨时钟域静态分析系统
By generating an abstract syntax tree using VHDL parsing units and combining it with clock tree data, cross-clock domain paths can be identified, solving the problem of identifying cross-clock domain issues in FPGA and integrated circuit design, and improving inspection efficiency and automation.
CN115185528BActive Publication Date: 2026-07-17BEIJING XUANYU INFORMATION TECH CO LTD
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- BEIJING XUANYU INFORMATION TECH CO LTD
- Filing Date
- 2022-06-10
- Publication Date
- 2026-07-17
AI Technical Summary
Technical Problem
In existing technologies for FPGA and integrated circuit design, cross-clock domain issues are difficult to identify and handle effectively, leading to design failures and making them difficult to troubleshoot in engineering practice.
Method used
A cross-clock domain static analysis system for VHDL programmable logic design is provided. It generates an abstract syntax tree through a VHDL parsing unit, combines the clock tree and signal clock domain data, identifies cross-clock domain paths, and determines the synchronizer type.
Benefits of technology
It improves the efficiency and automation of cross-clock domain problem checking, and significantly reduces working time, especially in large-scale complex designs.
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Abstract
本发明涉及硬件描述语言VHDL的跨时钟域分析，使用静态分析的方法识别可编程逻辑设计中的跨时钟域路径。本发明属于硬件描述语言静态分析技术领域。本发明能够对使用VHDL硬件描述语言编写的可编程逻辑设计，进行解析生成抽象语法树，分析并遍历抽象语法树，生成时钟树、推断信号时钟域、并判断跨时钟域路径及识别同步化器类型。
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