A method and apparatus for resolving pipeline computation conflicts

Abstract

The application is suitable for the field of computer technology, and relates to a method and device for solving pipeline calculation conflict. The method comprises the following steps: continuously acquiring data flow to perform pipeline calculation; when the pipeline current calculation in the pipeline calculation needs to read the written data of the pipeline history calculation to perform operation, monitoring whether the time when the pipeline current calculation reads the written data of the pipeline history calculation is before the time when the pipeline history calculation writes the data; if the time when the pipeline current calculation reads the written data of the pipeline history calculation is before the time when the pipeline history calculation writes the data, it is determined that there is conflict between the pipeline current calculation and the pipeline history calculation, and the conflict is solved by scheduling data and / or suspending calculation. The embodiment of the application solves the problem of pipeline address conflict.

Description

Technical Field

[0001] This application belongs to the field of computer technology, and in particular relates to a method and apparatus for resolving pipelined computing conflicts. Background Technology

[0002] A pipeline breaks down a complex processing procedure into several sub-processes. Each pipeline computation is implemented by a specialized functional unit. By staggering the time of multiple sub-processes, a continuous data stream can pass through each functional unit in sequence, thereby enabling each sub-process to run in parallel with other sub-processes and achieving time parallelism in data processing.

[0003] The basic computational principle of a convolutional neural network (CNN) is to multiply and accumulate data from multiple input channels with the convolution kernel to obtain the data for the output channel. Generally, when implementing accumulation calculations in a pipelined CNN chip, data from multiple input channels is read in batches for pipelined multiplication and accumulation operations. That is, after obtaining the convolution result, the current pipeline calculation needs to read the results from previous pipeline calculations for accumulation to obtain the current pipeline calculation result. Furthermore, if the current pipeline calculation result and the previous pipeline calculation result correspond to the same output channel, their write addresses are the same. Therefore, if the current pipeline calculation reads the result from a previous pipeline calculation before the previous pipeline calculation writes the result, an address conflict occurs between the current and previous pipeline calculations. This results in the current pipeline calculation reading a different result than the previous pipeline calculation writing the result, leading to an error in the output channel's calculation result. Summary of the Invention

[0004] In view of this, embodiments of this application provide a method and apparatus for resolving pipeline computing conflicts, which can solve one or more technical problems in the related art.

[0005] In a first aspect, one embodiment of this application provides a method for resolving pipelined computation conflicts, comprising: continuously acquiring data streams to perform pipelined computation, wherein, when the current pipeline computation requires reading written data from a previous pipeline computation for operation, monitoring whether the time when the current pipeline computation reads the written data from the previous pipeline computation is before the time when the previous pipeline computation wrote the data; if the time when the current pipeline computation reads the written data from the previous pipeline computation is before the time when the previous pipeline computation wrote the data, then determining that there is a conflict between the current pipeline computation and the previous pipeline computation, and resolving the conflict by scheduling data and / or pausing computation.

[0006] Secondly, one embodiment of this application provides an apparatus for resolving pipelined computation conflicts, comprising: a register for acquiring and buffering input data streams; an arithmetic module including at least one pipeline for performing pipelined computations to obtain computation results, wherein the current computation of the pipeline needs to read the written data from the previous computation of the pipeline for computation; a conflict monitoring module for monitoring whether the time when the current computation of the pipeline reads the written data from the previous computation of the pipeline is before the time when the previous computation of the pipeline wrote the data; if the time when the current computation of the pipeline reads the written data from the previous computation of the pipeline is before the time when the previous computation of the pipeline wrote the data, it is determined that there is a conflict between the current computation of the pipeline and the previous computation, and a signal is sent to the arithmetic module to cause the arithmetic module to resolve the conflict by scheduling data or pausing computation; and an on-chip memory for storing computation results.

[0007] Thirdly, one embodiment of this application provides a convolutional neural network chip, comprising: a register for acquiring and caching input feature data of N input channels, wherein N is a positive integer greater than 1; a first on-chip memory for acquiring and caching convolution kernel data corresponding to each output channel; an inner scheduling module for sending control signals and scheduling input feature data and convolution kernel data to the computation module to control the computation module to perform pipelined computation; and a computation module for performing pipelined computation using the input feature data and convolution kernel data of the N input channels to achieve convolution operation and obtain the computation results of each output channel; wherein the current pipelined computation is performed using the input feature data of the current input channel and the convolution kernel data. The kernel data is convolved to obtain the corresponding convolution result, and the historical input channel calculation results obtained from the previous pipeline calculation are accumulated to obtain the current pipeline calculation result. The conflict monitoring module is used to monitor whether the time when the current pipeline calculation reads the calculation result of the previous pipeline calculation is before the time when the previous pipeline calculation writes the calculation result. If so, the module sends a backpressure signal and / or a scheduling signal to the computing module to schedule the computing module to execute the data obtained before the previous pipeline calculation writes the calculation result for accumulation calculation or to pause the current calculation. The second on-chip memory is used to store the calculation results to be output by each output channel.

[0008] Fourthly, one embodiment of this application provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the method for resolving pipelined computing conflicts as described in any embodiment of the first aspect.

[0009] Fifthly, one embodiment of this application provides a computer storage medium storing a computer program that, when executed by a processor, implements the method for resolving pipelined computation conflicts as described in any embodiment of the first aspect.

[0010] In a sixth aspect, one embodiment of this application provides a computer program product that, when run on an electronic device, enables the electronic device to implement the method for resolving pipelined computing conflicts as described in any embodiment of the first aspect.

[0011] The embodiments of this application can resolve the address conflict problem in pipelines and convolutional neural network chips. Attached Figure Description

[0012] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0013] Figure 1 This is a schematic diagram illustrating the implementation process of a method for resolving pipeline computing conflicts according to an embodiment of this application;

[0014] Figure 2 This is a schematic diagram of a five-stage production line provided in one embodiment of this application;

[0015] Figure 3 This is a schematic diagram of the structure of a chip for resolving pipelined computing conflicts according to an embodiment of this application;

[0016] Figure 4 This is a schematic diagram illustrating the implementation process of a method for resolving pipeline computing conflicts according to an embodiment of this application;

[0017] Figure 5 This is a schematic diagram of the structure of a convolutional neural network chip provided in one embodiment of this application;

[0018] Figure 6 This is a schematic diagram of a multi-stage pipeline inside a convolutional neural network chip according to an embodiment of this application;

[0019] Figure 7 This is a schematic diagram of an assembly line provided in one embodiment of this application;

[0020] Figure 8 This is a schematic diagram of an assembly line provided in one embodiment of this application;

[0021] Figure 9This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0022] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application may also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods have been omitted so as not to obscure the description of this application with unnecessary detail.

[0023] The term “and / or” as used in this application specification and the appended claims means any combination of one or more of the associated listed items, as well as all possible combinations, and includes such combinations.

[0024] The terms "one embodiment" or "some embodiments" described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0025] Furthermore, in the description of this application, "a plurality of" means two or more. The terms "first" and "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0026] It should also be understood that, unless otherwise expressly specified or limited, the term "connection" should be interpreted broadly. For example, it can refer to a fixed connection, a detachable connection, or an integral part; it can refer to a direct connection or an indirect connection through an intermediate medium; it can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0027] To better illustrate the technical solution of this application, the following embodiments, in conjunction with some specific parameters, provide a detailed description of the technical solution of this application. It should be understood that these parameters are merely preferred parameters for ease of explanation and should not be construed as specific limitations on this application.

[0028] Figure 1This is a schematic diagram illustrating the implementation process of a method for resolving pipeline computation conflicts according to this application. The method includes:

[0029] S110: Continuously acquire data streams to perform pipelined computation. If the current computation of the pipeline needs to read the written data of the previous computation of the pipeline for operation, then monitor whether the time when the current computation of the pipeline reads the written data of the previous computation of the pipeline is before the time when the previous computation of the pipeline writes the data.

[0030] The current calculation in the pipeline and the previous calculations in the pipeline perform the same calculations, only the start time of execution differs.

[0031] More specifically, with Figure 2 The five-stage pipeline illustrated here demonstrates that input data is calculated starting from stage 1, progressing through each stage until the last stage writes data, which is considered a completed calculation. Therefore, the current calculation in the pipeline does not need to wait for previous calculations to finish before starting; instead, it is staggered from the start time of data reading in previous calculations. When the current calculation is reading data from stage 1, previous calculations have already completed stage 1 operations and have begun executing any of the stages 2-5 (writing, memory access, computation, or decoding), and so on. This high degree of parallelism, achieved when all pipelines are full, enables efficient computation.

[0032] Furthermore, when the current computation of the pipeline needs to read the written data from the previous computation of the pipeline for operation, it is necessary to determine the order in which the current computation reads the written data from the previous computation and the previous computation writes the data. If the current computation reads the written data from the previous computation after the previous computation writes the data, it means that the previous computation has completed the data writing step, and the current computation can directly read the data already written by the previous computation for operation.

[0033] S120: If the time when the current pipeline reads the data written by the previous pipeline calculation is before the time when the previous pipeline calculation writes the data, the current pipeline calculation needs to retrieve the data obtained before the previous pipeline calculation executes the data writing step for calculation or pause the current calculation until the current pipeline calculation can schedule the data of the previous pipeline calculation before it can proceed with the calculation, thereby obtaining and storing the calculation result of the current pipeline calculation.

[0034] In one embodiment, if the time when the current pipeline computation reads the data written by the previous pipeline computation is before the time when the previous pipeline computation wrote the data, it indicates that the previous pipeline computation has not yet completed the data writing step, and it can be determined that there is a conflict between the current pipeline computation and the previous pipeline computation. To resolve the above conflict, the current pipeline computation can selectively retrieve the data obtained before the previous pipeline computation executed the data writing step to continue computation or pause computation.

[0035] More specifically, the data retrieved by the current pipeline computation before the historical pipeline computation executes the write data step includes: if the historical pipeline computation has not completed the write data step, the current pipeline computation cannot directly read the data written by the historical pipeline computation, and needs to schedule and read the data obtained by the historical pipeline computation before executing the write data step; or, the current pipeline computation pauses operation until the current pipeline computation can resolve the conflict by scheduling the data of the historical pipeline computation before it can continue to move forward.

[0036] Figure 3 According to this application, a chip for resolving pipelined computation conflicts is provided. The chip includes a register 10, an arithmetic module 11, a conflict monitoring module 12, and an on-chip memory 13. The register 10 is used to acquire and buffer input data streams. The arithmetic module 11 includes at least one pipeline for performing pipelined computations to obtain computation results. The current computation of the pipeline needs to read data written from previous pipeline computations for computation. The conflict monitoring module 12 is used to monitor whether the time when the current computation reads data written from previous pipeline computations is before the time when previous pipeline computations wrote data. If the time when the current computation reads data written from previous pipeline computations is before the time when previous pipeline computations wrote data, a signal is sent to the arithmetic module 11 so that the current computation needs to retrieve data obtained before the write data step of previous pipeline computations for computation, or the current computation is paused until the current computation can schedule data from previous pipeline computations before proceeding. The on-chip memory 13 is used to store computation results.

[0037] In some embodiments, the arithmetic module 11 includes at least one pipeline, which may perform operations such as accumulation and iteration. It requires the calculation results of previous operations to perform the current operation in order to obtain the result of the current operation. Preferably, each pipeline may include multiple pipeline stages, and each pipeline stage consists of multiple arithmetic circuits to enable each pipeline stage to perform multiple operations.

[0038] It should be noted that register 10 includes a three-level register or static random access memory (SRAM); on-chip memory includes random access memory (RAM) with two read / write ports, which is not limited here.

[0039] Figure 4 This is a schematic diagram illustrating the implementation flow of a method for resolving pipeline computation conflicts based on the above principles of this application. The method is applied to a convolutional neural network chip and includes:

[0040] S210: Continuously acquire feature data from N input channels and convolutional kernel data corresponding to each output channel; where N is a positive integer greater than 1.

[0041] S220: Perform pipelined computation using feature data and convolution kernel data from N input channels; wherein, the current pipeline computation is to perform convolution operation using the feature data of the current input channel and the convolution kernel data to obtain the corresponding convolution result, and to read the historical input channel corresponding computation results obtained from the previous pipeline computations and accumulate them to obtain the computation result of the current pipeline computation.

[0042] More specifically, according to the principle of convolution operation, the output of a pipeline in a complete calculation process is the sum of the convolution result corresponding to the current input channel and the convolution result corresponding to the historical input channel. That is, the current calculation of the pipeline needs to read the calculation result written by the previous calculation of the pipeline and perform the calculation to obtain the calculation result of the current calculation of the pipeline.

[0043] S230: Monitor whether the time when the current calculation reads the calculation result of the previous calculation in the pipeline is before the time when the previous calculation writes the calculation result. If so, schedule the previous convolution calculation in the pipeline to perform the cumulative calculation on the data obtained before writing the calculation result, or pause the current calculation.

[0044] In one embodiment, there is a time difference between the start of computation using the feature data of each input channel during pipelined computation. Therefore, it is necessary to monitor whether the time when the current pipeline reads the computation result from the previous pipeline computation is before the time when the previous pipeline computation writes the computation result. If the time when the current pipeline reads the computation result from the previous pipeline computation is before the time when the previous pipeline computation writes the computation result, it is determined that there is a conflict between the current pipeline computation and the previous pipeline computation. In this case, the current pipeline computation needs to schedule the data obtained before the previous pipeline computation executed the step of writing the computation result to continue completing the current computation; or, the current pipeline computation can pause until it can continue by scheduling data from the previous pipeline computation.

[0045] Figure 5 To provide a convolutional neural network chip applying the above method according to this application, the hardware architecture includes a register 21, a first on-chip memory 22, an inner scheduling module 23, a computation module 24, a conflict detection module 25, and a second on-chip memory 26, wherein:

[0046] Register 21 is used to acquire and buffer the feature data of N input channels, i.e., the input feature data;

[0047] The first on-chip memory 22 is used to acquire and cache the convolution kernel data corresponding to each output channel;

[0048] Inner scheduling module 23 is used to send control signals and schedule input feature data and convolution kernel data to the computing module to control the computing module to perform pipelined computation;

[0049] The computation module 24 is used to perform pipeline computation to realize convolution operation by using the feature data and convolution kernel data of N input channels; wherein, the current pipeline computation is to perform convolution operation by using the feature data and convolution kernel data of the current input channel to obtain the corresponding convolution result, and to read the historical input channel corresponding computation results obtained from the previous pipeline computation and accumulate them to obtain the computation result of the current pipeline computation.

[0050] The conflict monitoring module 25 is used to monitor whether the time when the current calculation reads the calculation result of the previous calculation is before the time when the previous calculation writes the calculation result during the pipeline calculation process of the computing module. If so, it sends a back pressure signal and / or a scheduling signal to the computing module to make the computing module schedule the data obtained before the previous calculation is written to the calculation result for accumulation calculation or pause the current calculation.

[0051] The second on-chip memory 26 is used to store the calculation results to be output by each output channel.

[0052] It should be noted that the computation module 24 also includes a register unit, which is used to store the convolution obtained in the current calculation of the pipeline and the calculation result of the pipeline.

[0053] More specifically, Figure 6 This is a schematic diagram of a multi-stage pipeline inside a convolutional neural network chip according to the present invention. The numbers within the blocks represent different pipeline stages, characterizing each step in the pipeline computation. In one embodiment, based on... Figure 5 and Figure 6 As shown, level 0 indicates reading the feature data of the current input channel and the weight data in the convolution kernel; level 1 indicates obtaining the write address of the accumulated calculation result in the second on-chip memory 26, that is, the address where the calculation results of the current pipeline calculation and the pipeline history calculation need to be written; level 2 indicates sending a read request to the second on-chip memory 26 to read the calculation results obtained from the pipeline history calculation. When reading the calculation result from the second on-chip memory 26, arbitration is required to determine whether the data can be read. Therefore, the calculation results of the pipeline history calculation are read out in level 4; level 3 indicates using the current input data and the corresponding convolution kernel data to perform multiplication operations in convolution calculation to obtain multiple multiplication results; level 4 indicates adding the multiple multiplication results to obtain the convolution result corresponding to the current input data and storing it in the register unit in the operation module 24, and reading the calculation results obtained from the pipeline history calculation in the second on-chip memory 26; and from the second on-chip memory 26... Data read from memory 26 must be written to a register before it can be used. Therefore, level 5 indicates that the calculation result obtained from the pipeline's previous calculations read from the second on-chip memory is written to the register unit in the arithmetic module 24, and the convolution result obtained from the current pipeline calculation is accumulated in the arithmetic module 24 to obtain the calculation result to be output by the current pipeline calculation. Level 6 indicates that the data type of the calculation result of the current pipeline calculation is transformed so that the output data meets the preset requirements. Level 7 indicates that the arithmetic module 24 sends an enable signal to the second on-chip memory 26, preparing to write the calculation result obtained from the current pipeline calculation to the second on-chip memory 26. Since writing data to the second on-chip memory 26 requires arbitration to determine whether it is allowed to be written, level 8 indicates that the enable signal sent by the arithmetic module 24 is transmitted to the second on-chip memory 26. Level 9 indicates that the calculation result obtained from the current pipeline calculation is written to the second on-chip memory 26.

[0054] It should be noted that the pipeline depth described above is 10 levels. This depth can be adjusted according to the type of input data or the actual situation such as chip architecture, and this application does not impose any restrictions.

[0055] In one embodiment, when computation is performed using the pipeline in the computation module of a convolutional neural network chip, if the computation result of the current pipeline computation corresponds to the same output channel, then the addresses of the two computation results written to the second on-chip memory 26 are the same. Therefore, during the current pipeline computation, if the time when the computation result of a previous pipeline computation is read from the second on-chip memory 26 is before the time when the computation result of the previous pipeline computation is written to the second on-chip memory 26, it can be considered an address conflict, meaning that the computation result read by the current pipeline computation is not the computation result obtained from the previous pipeline computation, thus leading to an error in the computation result of the current pipeline computation.

[0056] More specifically, in Figure 7 In the pipeline shown, if the data read from stage 0 of the current computation is aligned with any stage from stage 1 to stage 5 of the previous computation and performed in parallel, the data read from stage 0 of the current computation will not have reached stage 4, or will have just reached stage 9. The computation result of the previous computation will not have been written to the second on-chip memory 26. This results in the current computation reading from the second on-chip memory 26 at stage 4 not being the computation result written by the previous computation, but rather the result of the previous computation. This causes a conflict between the current computation and the previous computation, leading to an error in the current computation result.

[0057] In view of this, in one embodiment, by means of... Figure 5 The conflict monitoring module 25 in the chip shows the time when the pipeline calculation of the arithmetic module 24 causes the aforementioned conflict, and selectively sends a back pressure signal and / or a scheduling signal to the arithmetic module according to the time of the conflict, so that the arithmetic module schedules the pipeline to perform the cumulative calculation of the data obtained before writing the calculation result in the previous calculation, or pauses the current calculation, so as to avoid the situation where the calculation result of the current pipeline calculation is incorrect.

[0058] More specifically, such as Figure 7 As shown, when the data read from stage 0 of the current pipeline calculation is aligned with any stage from stage 1 to stage 5 of the previous pipeline calculation for computation, a conflict exists between the current pipeline calculation and the previous pipeline calculation. In this case, the conflict monitoring module 25 can send a scheduling signal to the computation module 24 so that the computation module 24 can retrieve the computation results of the previous pipeline calculation that have been obtained but not written to the second on-chip memory 26 when performing the current pipeline calculation. This result is then used as equivalent data read from the second on-chip memory 26 for the current calculation to resolve the conflict and obtain the computation result of the current pipeline calculation.

[0059] It should be noted that the timing of the scheduling signal sent by the conflict monitoring module 25 to the computation module 24 varies depending on the time of the conflict. For example, when the current computation's level 0 aligns with any level from level 2 to level 5 of the previous computation, data is retrieved from levels 6 to 9 of the previous computation, respectively. Figure 7 As shown.

[0060] Figure 8 This is another pipelined computation diagram provided in this application. When the current pipeline computation executes at stage 0 and aligns with stage 1 of a previous pipeline computation, since the current pipeline computation has reached stage 4 while the previous pipeline computation has not yet reached stage 6, there is no retrievable data for the previous computation. The second on-chip memory 26 stores the previous computation result of the previous pipeline computation. Therefore, the conflict monitoring module 25 cannot resolve the conflict by sending a scheduling signal to the arithmetic module 24 to retrieve the data. In another embodiment, the conflict monitoring module 25 can send a backpressure signal to the arithmetic module 24 to cause the arithmetic module 24 to pause the current pipeline computation and wait for the previous pipeline computation to run. When the conflict monitoring module 25 detects that the conflict between the previous and current pipeline computations can be resolved through a scheduling signal, the conflict monitoring module 25 sends a scheduling signal to the arithmetic module 24 to release the backpressure signal and retrieve the computation result obtained from stage 6 of the previous pipeline computation to continue the current computation.

[0061] More specifically, such as Figure 8 As shown, when the pipeline's current calculation runs from stage 0 to stage 2, the current calculation is paused by a backpressure signal, causing the pipeline to remain at stage 2. At the same time, the pipeline's previous calculation runs to stage 3 and proceeds normally step by step until the previous calculation runs to stage 4. This means the current calculation remains at stage 1, which is equivalent to the current calculation's stage 0 aligning with the previous calculation's stage 2. When the current calculation reaches stage 5 and reads the previous calculation's result, the previous calculation has already reached stage 6 and obtained the corresponding result. At this point, the conflict monitoring module 25 can send a scheduling signal to the operation module 24 to release the backpressure signal, allowing the current calculation to run to stage 3. When it reaches stage 5, it retrieves the previous calculation's result from stage 6 to obtain the current calculation result.

[0062] Figure 9 This is a schematic diagram of an electronic device structure according to an embodiment of this application. The electronic device may include one or more such devices. Figure 2 or Figure 5 The processor 100 shown Figure 9 (Only one is shown in the image), memory 101, and a computer program 102 stored in memory 101 and executable on one or more processors 100, such as a program for resolving pipelined computation conflicts. When one or more processors 100 execute computer program 102, they can implement the various steps in the method embodiment for resolving pipelined computation conflicts. Alternatively, when one or more processors 100 execute computer program 102, they can implement the functions of various modules / units in the apparatus embodiment for resolving pipelined computation conflicts, which is not limited here.

[0063] Those skilled in the art will understand that Figure 9 This is merely an example of an electronic device and does not constitute a limitation on electronic devices. Electronic devices may include more or fewer components than illustrated, or combinations of certain components, or different components. For example, electronic devices may also include input / output devices, network access devices, buses, etc.

[0064] In one embodiment, the processor 100 may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or any conventional processor.

[0065] In one embodiment, memory 101 may be an internal storage unit of an electronic device, such as a hard drive or RAM. Memory 101 may also be an external storage device of the electronic device, such as a plug-in hard drive, smart media card (SMC), secure digital (SD) card, flash card, etc. Furthermore, memory 101 may include both internal and external storage units. Memory 101 is used to store computer programs and other programs and data required by the electronic device. Memory 101 can also be used to temporarily store data that has been output or will be output.

[0066] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is merely an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiments can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit. Furthermore, the specific names of the functional units and modules are only for easy differentiation and are not intended to limit the scope of protection of this application. The specific working process of the units and modules in the above system can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0067] An embodiment of this application also provides a computer-readable storage medium storing a computer program that, when executed by a processor, can implement the steps in the aforementioned method embodiment for resolving pipelined computation conflicts.

[0068] One embodiment of this application provides a computer program product that, when run on an electronic device, enables the electronic device to perform the steps described in the above-described method embodiment for resolving pipeline computing conflicts.

[0069] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0070] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0071] In the embodiments provided in this application, it should be understood that the disclosed devices / electronic devices and methods can be implemented in other ways. For example, the device / electronic device embodiments described above are merely illustrative. For instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0072] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0073] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0074] If integrated modules / units are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, all or part of the processes in the methods of the above embodiments can also be implemented by a computer program instructing related hardware. The computer program can be stored in a computer-readable storage medium, and when executed by a processor, it can implement the steps of the various method embodiments described above. The computer program includes computer program code, which can be in the form of source code, object code, executable files, or certain intermediate forms. Computer-readable media can include: any entity or device capable of carrying computer program code, recording media, USB flash drives, portable hard drives, magnetic disks, optical disks, computer memory, read-only memory (ROM), RAM, electrical carrier signals, telecommunication signals, and software distribution media, etc. It should be noted that the content included in a computer-readable medium can be appropriately added to or subtracted according to the requirements of legislation and patent practice in the jurisdiction. For example, in some jurisdictions, according to legislation and patent practice, computer-readable media do not include electrical carrier signals and telecommunication signals.

[0075] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A method for resolving pipeline computing conflicts, characterized in that, Applications in convolutional neural network chips include: The feature data of N input channels and the convolution kernel data of the corresponding output channels are continuously acquired; where N is a positive integer greater than 1. Pipeline computation is performed using the feature data of the N input channels and the convolution kernel data to obtain the computation result of the output channel; wherein, the computation result of the current pipeline computation is obtained by performing a convolution operation on the feature data of the current input channel and the convolution kernel data, and then accumulating the historical computation results of the input channels obtained from the previous pipeline computations. The current calculation in the pipeline and the previous calculation in the pipeline perform the same calculation, only the start time of execution is different; If the time when the current calculation of the pipeline reads the calculation result of the previous calculation is before the time when the previous calculation writes the calculation result, it is determined that there is a conflict between the current calculation and the previous calculation, and the conflict is resolved by scheduling data and / or pausing the calculation.

2. The method as described in claim 1, characterized in that, The method of resolving the conflict by scheduling data and / or pausing computation includes: the current computation of the pipeline needs to retrieve data obtained before the write data step of the previous computation of the pipeline for computation, or pausing the current computation until the current computation of the pipeline can schedule data of the previous computation of the pipeline before proceeding with the computation, thereby obtaining and storing the computation result of the current computation of the pipeline.

3. The method as described in claim 1 or 2, characterized in that, If the time when the current pipeline calculation reads the data written by the previous pipeline calculation is after the time when the previous pipeline calculation wrote the data, the current pipeline calculation can read the data already written by the previous pipeline calculation for computation.

4. A device for resolving computational conflicts in pipelines, characterized in that, include: Registers are used to acquire and buffer the input data stream; The computation module includes at least one pipeline for performing pipelined computation to obtain computation results. The current computation of the pipeline requires reading data written from previous computations of the pipeline for processing. This includes: continuously acquiring feature data from N input channels and convolution kernel data corresponding to the output channels; where N is a positive integer greater than 1; performing pipelined computation using the feature data from the N input channels and the convolution kernel data to obtain the computation result for the output channels; wherein the computation result of the current computation in the pipeline is obtained by performing a convolution operation using the feature data of the current input channel and the convolution kernel data to obtain the convolution result, and then accumulating the computation results corresponding to the historical input channels obtained from previous computations of the pipeline. The current calculation in the pipeline and the previous calculation in the pipeline perform the same calculation, only the start time of execution is different; The conflict monitoring module is used to monitor whether the time when the current calculation of the pipeline reads the data written by the previous calculation of the pipeline is earlier than the time when the previous calculation of the pipeline wrote the data. If the time when the current calculation of the pipeline reads the data written by the previous calculation is earlier than the time when the previous calculation of the pipeline wrote the data, it is determined that there is a conflict between the current calculation of the pipeline and the previous calculation, and a signal is sent to the computing module so that the computing module can resolve the conflict by scheduling data or pausing the calculation. On-chip memory for storing the calculation results.

5. The apparatus as described in claim 4, characterized in that, The computation module, based on the signal sent by the conflict monitoring module, enables the current pipeline calculation to retrieve data obtained before the data writing step in the previous pipeline calculation for calculation, or to pause the current calculation until the conflict can be resolved by scheduling the data from the previous pipeline calculation before proceeding to the next calculation, thereby obtaining and storing the calculation result of the current pipeline calculation.

6. A convolutional neural network chip, characterized in that, include: The register is used to acquire and buffer the input feature data of N input channels, where N is a positive integer greater than 1; The first on-chip memory is used to acquire and cache the convolution kernel data corresponding to each output channel; The inner scheduling module is used to send control signals and schedule the input feature data and the convolution kernel data to the computing module to control the computing module to perform pipelined computation. The computation module is used to continuously acquire feature data from N input channels and convolution kernel data corresponding to the output channels; where N is a positive integer greater than 1; and to perform pipelined computation using the feature data from the N input channels and the convolution kernel data to obtain the computation result of the output channel; wherein, the computation result of the current pipeline computation is obtained by performing convolution operation on the feature data of the current input channel and the convolution kernel data to obtain the convolution result, and by accumulating the historical computation results corresponding to the input channels obtained from the previous pipeline computations; the current pipeline computation and the previous pipeline computations perform the same computation, only the start time of execution differs; The conflict monitoring module is used to monitor whether the time when the current pipeline calculation reads the calculation result of the previous pipeline calculation is before the time when the previous pipeline calculation writes the calculation result. If so, the module transmits a back pressure signal and / or a scheduling signal to the computing module so that the computing module schedules the data obtained before the previous pipeline calculation writes the calculation result for cumulative calculation or suspends the current calculation. The second on-chip memory is used to store the calculation results to be output by each output channel.

7. The convolutional neural network chip as described in claim 6, characterized in that, If the conflict monitoring module detects that the time when the current pipeline calculation reads the calculation result of the previous pipeline calculation is before the time when the previous pipeline calculation writes the calculation result, and determines that the calculation result of the previous pipeline calculation has been obtained but not written to the second on-chip memory, then the conflict monitoring module sends a scheduling signal to the arithmetic module so that the arithmetic module, when executing the current pipeline calculation, retrieves the calculation result of the previous pipeline calculation that has been obtained but not written to the second on-chip memory for the current calculation, and obtains the calculation result of the current pipeline calculation; or, If the conflict monitoring module detects that the time when the current pipeline calculation reads the calculation result of the previous pipeline calculation is before the time when the previous pipeline calculation writes the calculation result, and determines that the calculation result of the previous pipeline calculation has not been obtained, then it sends a backpressure signal to the arithmetic module so that the arithmetic module controls the current pipeline calculation to pause and wait for the previous pipeline calculation to run. When the conflict monitoring module detects that the conflict between the previous pipeline calculation and the current pipeline calculation can be resolved by a scheduling signal, it sends the scheduling signal to the arithmetic module to release the backpressure signal and retrieve the calculation result of the previous pipeline calculation to continue the current calculation and obtain the calculation result of the current pipeline calculation.

8. An electronic device, characterized in that, The system includes a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that the processor, when executing the computer program, implements the method for resolving pipelined computation conflicts as described in any one of claims 1 to 3.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, characterized in that, when the computer program is executed by a processor, it implements the method for resolving pipelined computation conflicts as described in any one of claims 1 to 3.

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