A system-on-chip for packet processing and a processing method

Abstract

This invention discloses a system-on-a-chip (SoC) for packet processing, comprising a processor core and memory. The memory includes packet data on-chip memory, system program on-chip memory, and peripheral data on-chip memory. The processor core is connected to the packet data on-chip memory, system program on-chip memory, and peripheral data on-chip memory, respectively. The system has a simple structure, is secure, efficient, reliable, and easy to operate. The processing method has clear logic and concise steps. Both the system and the method effectively reduce bus contention and processor core control I / O overhead, achieving high-performance and low-latency packet processing.

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