Semiconductor device and method of forming the same

Abstract

A semiconductor structure and a forming method thereof, the forming method comprising: providing a substrate, forming a plurality of word line structures extending along a second direction on the substrate, each of the word line structures surrounding sidewalls of a plurality of columnar active regions arranged along the second direction and separated by a second trench between adjacent word line structures; sequentially forming a first sidewall material layer, a sacrificial layer and a second sidewall material layer on sidewall surfaces of the word line structures on both sides of the second trench; etching back to remove part of the second sidewall material layer to expose a top surface of the sacrificial layer; removing the sacrificial layer to form a double air gap between the adjacent word line structures; forming a second isolation layer on the first sidewall material layer and the remaining second sidewall material layer, the second isolation layer enclosing an opening of the double air gap. The method of the present application reduces the size of the parasitic capacitance and avoids the capacitive coupling effect between the word line structure and the adjacent word line structure.

Description

Technical Field

[0001] This application relates to the field of memory, and more particularly to a memory device and a method of forming the same. Background Technology

[0002] Dynamic Random Access Memory (DRAM) is a commonly used semiconductor memory device in computers, consisting of many repeating memory cells. Each memory cell typically includes a capacitor and a transistor. The gate of the transistor is connected to the word line, and its source and drain are connected to the bit line and the capacitor, respectively. The voltage signal on the word line can control the transistor to turn on or off, thereby reading data information stored in the capacitor through the bit line, or writing data information into the capacitor for storage through the bit line.

[0003] To improve the integration of memory structures, current DRAM manufacturing processes typically employ vertical channel transistor structures. However, when adjacent vertical transistors are spaced close together, they generate large parasitic capacitances, resulting in capacitive coupling between word lines and adjacent word lines. Summary of the Invention

[0004] Some embodiments of this application provide methods for forming semiconductor devices, including:

[0005] A substrate is provided on which a plurality of word line structures extending along a second direction are formed, each word line structure surrounding the sidewall of a plurality of columnar active regions arranged along the second direction, and adjacent word line structures are separated by a second trench.

[0006] A first sidewall material layer, a sacrificial layer, and a second sidewall material layer are sequentially formed on the sidewall surfaces of the word line structure on both sides of the second trench, and the second sidewall material layer fills the remaining second trench.

[0007] Etching back removes part of the second sidewall material layer, exposing the top surface of the sacrificial layer;

[0008] Remove the sacrificial layer to form a double air gap between the adjacent word line structures;

[0009] A second isolation layer is formed on the first sidewall material layer and the remaining second sidewall material layer, the second isolation layer sealing the opening of the double air gap.

[0010] In some embodiments, the first sidewall material layer and the second sidewall material layer are made of the same material, and the first sidewall material layer is made of a different material than the sacrificial layer.

[0011] In some embodiments, the materials of the first sidewall material layer and the second sidewall material layer are one of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonate, and silicon carbonitride.

[0012] In some embodiments, the material of the sacrificial layer is one of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonate, silicon carbonitride, amorphous carbon, amorphous silicon, or polycrystalline silicon.

[0013] In some embodiments, the thickness of the first sidewall material layer is 20-100 angstroms, the thickness of the second sidewall material layer is 50-200 angstroms, and the thickness of the sacrificial layer is 2-50 angstroms.

[0014] In some embodiments, the sacrificial layer is removed using an isotropic wet etching process, and when removing the sacrificial layer, the etching selectivity ratio of the sacrificial layer relative to the first sidewall material layer and the second sidewall material layer is greater than 2:1.

[0015] In some embodiments, the word line structure formation process includes: filling the second trench with a first isolation layer; forming a plurality of hard mask patterns extending in a second direction on the surface of the first isolation layer and the top surface of the columnar active regions, each hard mask pattern being located above a plurality of columnar active regions arranged in the second direction, and adjacent hard mask patterns having a first opening, each first opening being located above a corresponding second trench; etching back along the second opening, using the hard mask pattern as a mask, removing a portion of the thickness of the first isolation layer, exposing a portion of the sidewall surface of the top of the columnar active regions; and exposing the sidewalls of the hard mask pattern and the top of the columnar active regions. A sidewall is formed on the surface; continuing along the second opening, using the hard mask pattern and the sidewall as a mask, a portion of the thickness of the first isolation layer is etched away to expose the sidewall surface of the middle portion of the columnar active region, with the remaining surface of the first isolation layer higher than the bottom surface of the second trench; the exposed sidewall of the middle portion of the columnar active region, having a portion of its thickness etched away, forms a word line region, located in the middle of the columnar active region, with the top of the word line region above it and the bottom of the word line region below it, and the diameter of the word line region is smaller than the diameters of the top and bottom of the columnar active region; a word line structure is formed on the sidewall surface of the word line region.

[0016] In some embodiments, the word line structure includes an isolation medium layer located on the sidewall surface of the word line area and a metal layer located on the surface of the isolation medium layer.

[0017] In some embodiments, the process of forming the isolation dielectric layer and the metal layer includes: forming an isolation dielectric layer on the sidewall surface of the word line area by an oxidation process; filling the second trench with a metal material layer; and removing a portion of the metal material layer along the second opening, using the hard mask pattern and the sidewall as a mask, to form a metal layer on the surface of the isolation dielectric layer.

[0018] In some embodiments, the first sidewall material layer also covers the surface of the sidewall.

[0019] In some embodiments, it further includes: forming a capacitor connected to the top of the columnar active region.

[0020] Some embodiments of this application also provide a semiconductor device, including:

[0021] Substrate;

[0022] A word line structure is located on the substrate. There are several word line structures extending along a second direction. Each word line structure surrounds the sidewall of a plurality of columnar active regions arranged along the second direction, and adjacent word line structures are separated by a second trench.

[0023] The sidewall surface of the character line structure is provided with a first sidewall material layer and a second sidewall material layer in sequence, and there is an air gap between the first sidewall material layer and the second sidewall material layer;

[0024] A second isolation layer is located on the first sidewall material layer and the second sidewall material, and the second isolation layer closes the opening of the air gap.

[0025] In some embodiments, the materials of the first sidewall material layer and the second sidewall material layer are one of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonate, and silicon carbonitride.

[0026] In some embodiments, the columnar active region includes, from top to bottom, a top portion, a word line region, and a bottom portion. The diameter of the word line region is smaller than the diameters of the top portion and the bottom portion of the columnar active region. The word line structure is located on the sidewall surface of the word line region.

[0027] In some embodiments, the word line structure includes an isolation medium layer located on the sidewall surface of the word line area and a metal layer located on the surface of the isolation medium layer.

[0028] In some embodiments, the sidewall surface of the top portion of the columnar active region has a sidewall, and the letter line structure is located below the sidewall.

[0029] In some embodiments, the first sidewall material layer also covers the surface of the sidewall.

[0030] In some embodiments, it further includes a capacitor connected to the top of the columnar active region.

[0031] The semiconductor structure formation method in some of the foregoing embodiments of this application involves providing a substrate, forming a plurality of word line structures extending along a second direction on the substrate, each word line structure surrounding the sidewalls of a plurality of columnar active regions arranged along the second direction, and adjacent word line structures being separated by a second trench. A first sidewall material layer, a sacrificial layer, and a second sidewall material layer are sequentially formed on the sidewall surfaces of the word line structures on both sides of the second trench, with the second sidewall material layer filling the remaining second trench. A portion of the second sidewall material layer is etched back to expose the top surface of the sacrificial layer. The sacrificial layer is then removed, forming a double air gap between the adjacent word line structures. A second isolation layer is formed on the first sidewall material layer and the remaining second sidewall material layer, sealing the opening of the double air gap. Through the aforementioned steps, this application can easily form a double air gap between adjacent word line structures (i.e., two air gaps between two adjacent word line structures), thereby reducing the parasitic capacitance of adjacent vertical transistors when the spacing is short, and avoiding capacitive coupling effects between word line structures and adjacent word line structures. Attached Figure Description

[0032] Figures 1-36 This is a schematic diagram of the formation process of a semiconductor device in some embodiments of this application. Detailed Implementation

[0033] The specific embodiments of this application will be described in detail below with reference to the accompanying drawings. In describing the embodiments of this application in detail, for ease of explanation, the schematic diagrams may be partially enlarged without adhering to the general scale, and the schematic diagrams are merely examples and should not limit the scope of protection of this application. Furthermore, in actual manufacturing, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0034] refer to Figures 16-20 ,in Figure 17 for Figure 16 A schematic diagram of the cross-sectional structure along the cutting line AA1. Figure 18 for Figure 16 A schematic diagram of the cross-sectional structure along the cutting line BB1. Figure 19 for Figure 16 A schematic diagram of the cross-sectional structure along the cutting line CC1. Figure 20 for Figure 16A cross-sectional view along the cutting line DD1 shows a substrate 200 on which a plurality of word line structures (212, 213) extending in a second direction are formed. Each word line structure (212, 213) surrounds the sidewall of a plurality of columnar active regions 203 arranged in the second direction, and adjacent word line structures 203 are separated by a second trench 202.

[0035] The substrate 200 can be made of silicon (Si), germanium (Ge), or silicon-germanium (GeSi), silicon carbide (SiC); it can also be silicon-on-insulator (SOI), germanium-on-insulator (GOI); or other materials, such as gallium arsenide or other III-V compounds. In this embodiment, the substrate 200 is made of silicon. Depending on the type of vertical transistor subsequently formed, the substrate 200 needs to be doped with certain impurity ions. For example, the substrate can be doped in the channel region and the source / drain region. The impurity ions doped in the channel region can be N-type or P-type impurity ions. The P-type impurity ions are one or more of boron ions, gallium ions, or indium ions, and the N-type impurity ions are one or more of phosphorus ions, arsenic ions, or antimony ions. The type of impurity ions doped in the source / drain region can be the same as or different from the type of impurity ions doped in the channel region. The source / drain region doping is used to form the source / drain region of the vertical transistor, and the impurity ions doped in the source / drain region can be N-type or P-type impurity ions.

[0036] In this embodiment, the columnar active region 203 is formed by etching the substrate 200. In other embodiments, the columnar active region 203 can be formed by epitaxial processing.

[0037] The columnar active region 203 generally includes a central portion, a top portion above the central portion, and a bottom portion below the central portion. The central portion is subsequently used to form the channel region or word line region of a vertical transistor, the top portion is subsequently used to form the source region or drain region of a vertical transistor, and the bottom portion is subsequently used to form the drain region or source region of a vertical transistor. The columnar active regions 203 are discrete, and adjacent columnar active regions 203 are separated by a plurality of first trenches 201 extending along a first direction and a plurality of first trenches 202 extending along a second direction. In this embodiment, the plurality of columnar active regions 203 are arranged in rows and columns. In other embodiments, the columnar active regions 203 may also be arranged in other ways.

[0038] In some embodiments, the detailed formation process of the columnar active region 203 and the word line structure (212, 213) can be found in the following references. Figures 1-20 .

[0039] Please refer to the following first. Figures 1-5 ,in Figure 2 for Figure 1 A schematic diagram of the cross-sectional structure along the cutting line AA1. Figure 3 for Figure 1 A schematic diagram of the cross-sectional structure along the cutting line BB1. Figure 4 for Figure 1 A schematic diagram of the cross-sectional structure along the cutting line CC1. Figure 5 for Figure 1 A schematic diagram of the cross-sectional structure along the cutting line DD1 (it should be noted that, for ease of illustration, ...) Figure 1 Some structures are not shown, while... Figures 2-5 It is shown in the text, for example Figures 2-5 Substrate 200 in Figure 1 Not shown in the image. Figure 2 The sidewall protective layer 204 in Figure 1 (Not shown in the figure, similar situations exist in subsequent figures of this application, and will not be described in detail hereafter) A substrate 200 is provided, on which a plurality of columnar active regions 203 are formed. The plurality of columnar active regions 203 are separated by a plurality of first trenches 201 extending along a first direction and a plurality of second trenches 202 extending along a second direction. The first trenches 201 and the second trenches 202 are connected, and the depth of the first trenches 201 is greater than the depth of the second trenches 202.

[0040] In some embodiments, the first direction and the second direction are perpendicular to each other, and the angle between them is 90 degrees. In other embodiments, the first direction and the second direction may not be perpendicular; for example, the angle between the first direction and the second direction may be an acute angle.

[0041] In this embodiment, the plurality of columnar active regions 203 are formed by an etching process. In one specific embodiment, a first etching is performed on the substrate 200 to form a plurality of first trenches 201 extending along a first direction in the substrate 200, and the plurality of first trenches 201 are parallel to each other; then a second etching is performed on the substrate to form a plurality of second trenches 202 extending along a second direction in the substrate 200. The second trenches 202 intersect with the corresponding first trenches 201, and the depth of the second trenches 202 is less than the depth of the first trenches 201. Between the plurality of first trenches 201 and second trenches 202 are a plurality of discrete columnar active regions 203. In another embodiment, the substrate 200 can be etched first to form a plurality of first trenches 202 extending along the second direction, and then the substrate 200 can be etched to form a plurality of first trenches 201 extending along the first direction and spaced apart, and the depth of the formed first trenches 201 is greater than the depth of the second trenches 202. In another embodiment, the substrate 200 can be etched first to simultaneously form a first initial trench and a second trench in the substrate, and then the first initial trench can be etched to form a first trench 201, the depth of the first trench 201 being greater than the depth of the second trench 202. In some embodiments, before etching the substrate 200, a corresponding mask layer is formed on the substrate 200, and the substrate 200 is etched using the mask layer as a mask to form the first trench and / or the second trench in the substrate 200. In other embodiments, the columnar active region 203 can be formed by other formation processes.

[0042] In one embodiment, the columnar active region 203 is a rectangular or cylindrical columnar active region, wherein the cylindrical shape includes an elliptical columnar shape to improve the integration density of the device. The formation process of the cylindrical active region 203 includes: forming a plurality of rectangular columnar active regions on the substrate 200; and rounding the sidewalls of the columnar active regions to form cylindrical active regions. In some embodiments, the rounding process includes: oxidizing the sidewalls of the rectangular columnar active regions to form a silicon oxide layer; and removing the silicon oxide layer using a wet etching process. In other embodiments, after forming the rectangular columnar active regions, no rounding is performed, and subsequent processes are directly carried out.

[0043] In one embodiment, after forming the plurality of discrete columnar active regions 203, a sidewall protection layer 204 is formed on the sidewalls of the plurality of first trenches 202, and the bottom of the second trenches 202 is not covered by the sidewall protection layer material; using the sidewall protection layer 204 as a mask, the substrate 200 at the bottom of the plurality of second trenches 202 is etched, and a plurality of third trenches 206 are correspondingly formed in the substrate 200 at the bottom of the plurality of second trenches 202; metal is deposited on the substrate 200 at the bottom of the plurality of third trenches 206 to form a first bit line metal layer; the first bit line metal layer is diffused into the substrate 200 at the bottom of the columnar active regions 203 by a heat treatment process, and reacts with the substrate 200 to form metal silicide, and a plurality of bit lines 207 containing metal silicide extending along the first direction are formed at the bottom of the columnar active regions 203, and each bit line 207 electrically connects the bottom of the plurality of columnar active regions 203 arranged along the first direction.

[0044] In another embodiment, the bit line 207 containing metal silicide can also be formed in the following manner;

[0045] After the metal silicide is formed, to prevent the remaining first bit line metal layers from interconnecting and to reduce the contact resistance of the formed bit lines, the remaining first bit line metal layers need to be removed. A second bit line metal layer 208 is then deposited in the third trench 206. The second bit line metal layer and the metal silicide together form the bit line 207. The first bit line metal layer and the second bit line metal layer 208 can be made of the same or different materials, and the metals they contain can be nickel, tantalum, titanium, tungsten, cobalt, etc.

[0046] When forming the sidewall protective layer 204, the sidewalls and bottom of the first trench 201 and the top surface of the columnar active region 203 are also covered by the sidewall protective layer to prevent silicon material in other locations from reacting with the metal layer when forming the metal silicide-containing bit line 207. In some embodiments, the material of the sidewall protective layer 204 is silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, or silicon carbonitride.

[0047] The third trench 206 is recessed towards the bottom of the columnar active region 203, reducing the diffusion distance of the metal layer on the surface of the third trench 206. Metal silicide-containing bit lines 207 can be easily formed in the bottom of several columnar active regions 203 and several third trenches 206 in a certain row in the first direction, creating interconnected metal silicide-containing bit lines 207. The third trench 206 can be formed using an isotropic wet etching process.

[0048] The formed plurality of metal silicide-containing bit lines 207 are discrete. In some embodiments, the plurality of metal silicide-containing bit lines 207 are parallel to each other. Each metal silicide-containing bit line 207 is located at the bottom of a plurality of columnar active regions 203 and a plurality of third trenches 206 in a row in a first direction, connecting the source and drain doped regions formed at the bottom of the plurality of columnar active regions 203 in that row together. That is, the metal silicide-containing bit lines 207 formed in this application are defined in a plurality of third trenches 206 and at the bottom of the columnar active regions 203 between the third trenches 206, thus improving the positional accuracy of the formed metal silicide 207, reducing open circuits and short circuits between adjacent metal silicide-containing bit lines, and improving the electrical performance of the bit lines.

[0049] In some embodiments, the material of the metal silicide-containing bit line 207 is one or a combination of nickel silicide, tungsten silicide, cobalt silicide, tantalum silicide, and titanium silicide.

[0050] After forming bit line 207 containing metal silicide, refer to Figures 6-10 ,in Figure 7 for Figure 6 A schematic diagram of the cross-sectional structure along the cutting line AA1. Figure 8 for Figure 6 A schematic diagram of the cross-sectional structure along the cutting line BB1. Figure 9 for Figure 6 A schematic diagram of the cross-sectional structure along the cutting line CC1. Figure 10 for Figure 6 A cross-sectional view along the cutting line DD1 shows the sidewall protective layer 204 removed, and the first isolation layer 210 filled into the first trench 201 and the second trench 202. The surface of the first isolation layer 210 is flush with the top surface of the columnar active region 203. A plurality of hard mask patterns 209 extending along a second direction are formed on the surface of the first isolation layer 210 and the top surface of the columnar active region 203. Each hard mask pattern 209 is correspondingly located within a plurality of columnar active regions arranged along the second direction. Above the source region 203, there is a first opening (not shown in the figure) between adjacent hard mask patterns 209, each of the first openings being located above the corresponding second trench 202; along the second opening, using the hard mask pattern 209 as a mask, a portion of the thickness of the first isolation layer 210 is etched back to expose a portion of the sidewall surface of the top of the columnar active region 203; sidewalls 211 are formed on the sidewalls of the hard mask pattern 209 and the exposed sidewall surfaces at the top of the columnar active region 203.

[0051] In some embodiments, the first insulating layer 210 may be a single-layer structure formed by one of the following materials: silicon oxide, silicon nitride, silicon oxynitride, FSG (fluorine-doped silicon dioxide), BSG (boron-doped silicon dioxide), PSG (phosphorus-doped silicon dioxide), or BPSG (boron-phosphorus-doped silicon dioxide), or a low dielectric constant material, or a stacked structure formed by two or more materials from the group consisting of the above materials.

[0052] The sidewall 211 serves two purposes: firstly, it protects the top of the columnar active region 203 from etching when forming the word line region on the sidewall of the middle portion (middle part) of the columnar active region 203; secondly, it defines the position of the subsequently formed word line structure (including the upper end position and width of the word line structure); and thirdly, it can directly serve as a mask when breaking the metal layer during the subsequent formation of the word line structure, eliminating the need for an additional mask layer and saving process steps and manufacturing costs. The material of the sidewall 211 is different from that of the first isolation layer 210, so that the first isolation layer 210 has a high etching selectivity (greater than 2:1) relative to the sidewall 211 during subsequent etching of the first isolation layer 210. In one embodiment, the material of the sidewall 211 is one of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, or silicon carbonitride. In this embodiment, the material of the sidewall 211 is silicon nitride.

[0053] In some embodiments, the first isolation layer 210 is etched back at the lower edge of the top end of the columnar active region 203, and the sidewall 211 covers the sidewall surface of the top end of the columnar active region 203.

[0054] In one embodiment, the first isolation layer 210, which has a portion of its thickness, is etched back using a wet etching process or anisotropic dry etching process.

[0055] After the sidewall 211 is formed, refer to Figures 11-15 ,in Figure 12 for Figure 11 A schematic diagram of the cross-sectional structure along the cutting line AA1. Figure 13 for Figure 11 A schematic diagram of the cross-sectional structure along the cutting line BB1. Figure 14 for Figure 11 A schematic diagram of the cross-sectional structure along the cutting line CC1. Figure 15 for Figure 11A cross-sectional view along the cutting line DD1 shows that, continuing along the second opening, using the hard mask pattern 209 and the sidewall 202 as masks, a portion of the thickness of the first isolation layer 210 is etched away, exposing the sidewall surface of the middle portion of the columnar active region 203. The remaining surface of the first isolation layer 210 is higher than the bottom surface of the second trench 202. The exposed middle portion (or middle part) sidewall of the columnar active region 203, having had a portion of its thickness etched away, forms a word line region 11. The word line region 11 is located in the middle of the columnar active region 203. Above the word line region 11 is the top end portion 12 of the columnar active region 203, and below the word line region 11 is the bottom end portion 13 of the columnar active region 203. The diameter of the word line region 11 is smaller than the diameters of the top end portion 12 and the bottom end portion 13 of the columnar active region 203. The sidewall of the word line area 11 is subsequently used to form a word line structure. Since the diameter of the word line area 11 is smaller than the diameter of the top end 12 and bottom end 13 of the columnar active area 203, when forming the word line structure surrounding the word line area 11, the outermost part of the word line structure can be confined to the space below the sidewall 211. This reduces the space occupied by the word line structure in the second groove 202, allowing more space to be exposed in the second groove for subsequent double air gap formation. This reduces the difficulty of forming the double air gap and improves the accuracy of the position and size of the double air gap.

[0056] In some embodiments, the thickness of the sidewall removed from the middle portion (or middle part) of the columnar active region 203 is 1 / 2 to 1 / 4 of the radius of the columnar active region 203, ensuring sufficient space for forming the word line structure while maintaining the stability of the columnar active region structure. The etching process used to remove the thickness of the sidewall portion of the middle portion (or middle part) of the columnar active region 203 is an isotropic dry or wet etching process.

[0057] After forming the character line area 11, refer to Figures 16-20 ,in Figure 17 for Figure 16 A schematic diagram of the cross-sectional structure along the cutting line AA1. Figure 18 for Figure 16 A schematic diagram of the cross-sectional structure along the cutting line BB1. Figure 19 for Figure 16 A schematic diagram of the cross-sectional structure along the cutting line CC1. Figure 20 for Figure 16 A cross-sectional view along the cutting line DD1 shows that a character line structure (212, 213) is formed on the sidewall surface of the character line area.

[0058] The word line structure includes an isolation dielectric layer 212 located on the sidewall surface of the word line region 11 and a metal layer 213 located on the surface of the isolation dielectric layer 212. The material of the isolation dielectric layer 212 can be silicon oxide or a high-k (K greater than 2.5) dielectric material, and the material of the metal layer 213 can be one or more of Al, Cu, Ag, Au, Pt, Ni, Ti, TiN, TaN, Ta, TaC, TaSiN, W, WN, and Wsi.

[0059] In some embodiments, the process of forming the isolation dielectric layer and the metal layer includes: forming an isolation dielectric layer on the sidewall surface of the word line area by an oxidation process; filling the second trench 202 with a metal material layer; and removing part of the metal material layer along the second opening 202, using the hard mask pattern 209 and the sidewall 211 as a mask, to form a metal layer 213 on the surface of the isolation dielectric layer 212.

[0060] This application forms several parallel word line structures extending along the second direction, each word line structure covering the word line area of ​​multiple columnar active areas 203 arranged along the second direction.

[0061] After forming the character line structure, refer to Figures 21-24 , Figures 21-24 In respectively Figures 16-20 Based on this, a first sidewall material layer 214, a sacrificial layer 215, and a second sidewall material layer 216 are sequentially formed on the sidewall surfaces of the word line structures (212, 213) on both sides of the second trench, and the second sidewall material layer 216 fills the remaining second trench.

[0062] The first sidewall material layer 214 is used to protect the formed word line structure, the sacrificial layer 215 is removed subsequently to form an air gap, and the second sidewall material layer 216 is used to define the position of the formed air gap.

[0063] The materials of the first sidewall material layer 214 and the second sidewall material layer 216 are different from the material of the sacrificial layer 215. This results in the sacrificial layer 215 having a high etching selectivity (greater than 2:1) relative to the first sidewall material layer 214 and the second sidewall material layer 216 when the sacrificial layer 215 is subsequently removed to form a double air gap. This allows the sacrificial layer 215 to be removed to form an air gap, while the first sidewall material layer 214 and the second sidewall material layer 216 are retained.

[0064] In some embodiments, the materials of the first sidewall material layer 214 and the second sidewall material layer 216 are one of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, and silicon carbonitride, and the material of the sacrificial layer 215 is one of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, amorphous carbon, amorphous silicon, or polycrystalline silicon. In this embodiment, the materials of the first sidewall material layer 214 and the second sidewall material layer 216 are silicon nitride, and the material of the sacrificial layer 215 is silicon oxide.

[0065] In some embodiments, the thickness of the first sidewall material layer 214 is 20-100 angstroms, the thickness of the second sidewall material layer 216 is 50-200 angstroms, and the thickness of the sacrificial layer 215 is 2-50 angstroms. The first sidewall material layer 214, the sacrificial layer 215, and the second sidewall material layer 216 are formed by a deposition process, including atomic layer deposition. The first sidewall material layer 214 also covers the surface of the sidewall 211.

[0066] In some embodiments, the first sidewall material layer 214 may be formed on the sidewalls and bottom of the second trench using atomic layer deposition (ALD) and the bottom film layer may be removed by dry etching while the sidewall film layer is retained; or the film layer may be formed on the sidewalls and bottom of the second trench using reversed topology selectivity and the bottom film layer may be removed by wet etching while the sidewall film layer is retained.

[0067] refer to Figures 25-28 , Figures 25-28 In respectively Figures 21-24 Based on this, a portion of the second sidewall material layer 216 is etched back to expose the top surface of the sacrificial layer 215.

[0068] The re-etching removal of a portion of the second sidewall material layer 216 can be performed using an isotropic dry or wet etching process. During this re-etching removal, the second sidewall material layer 216 has a high etch selectivity (greater than 2:1) relative to the sacrificial layer 215. In some embodiments, during the re-etching removal of a portion of the second sidewall material layer 216, the sidewall 211 and the first sidewall material layer 214 are also partially removed simultaneously.

[0069] In some embodiments, the etch-back removal of a portion of the second sidewall material layer 216 may be performed using a hot phosphoric acid solution.

[0070] refer to Figures 29-32 , Figures 29-32 In respectively Figures 25-28 Based on this, the sacrificial layer 215 (reference) is removed. Figure 25 A double air gap 217 is formed between the adjacent word line structures (212, 213).

[0071] In this application, the aforementioned scheme allows for the simple formation of a double air gap 217 between adjacent word line structures (212, 213) (i.e., two air gaps between two adjacent word line structures). This reduces the parasitic capacitance of adjacent vertical transistors when the spacing is short, thus avoiding capacitive coupling between word line structures and adjacent word line structures.

[0072] The sacrificial layer is removed using an isotropic wet etching process. In one embodiment, the etching solution used in the isotropic wet etching process can be a diluted hydrofluoric acid solution.

[0073] In other embodiments, when the material of the sidewall 211 is the same as that of the sacrificial layer 215, the sidewall 211 may also be removed simultaneously to form a third air gap above the word line structure (212, 213) to further reduce the parasitic capacitance between adjacent transistors.

[0074] refer to Figures 33-35 , Figures 33-35 In respectively Figures 29-32 Based on this, a second isolation layer 218 is formed on the sidewall 211, the first sidewall material layer 214 and the remaining second sidewall material layer 216, and the second isolation layer 218 closes the opening of the double air gap.

[0075] In some embodiments, the material of the second insulating layer 218 may be a single-layer structure formed by one of the following materials: silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, silicon carbonitride, FSG (fluorine-doped silicon dioxide), BSG (boron-doped silicon dioxide), PSG (phosphorus-doped silicon dioxide), or BPSG (boron-phosphorus-doped silicon dioxide), or a low dielectric constant (K less than 2.5), or a stacked structure formed by two or more materials from the group consisting of the above materials.

[0076] In some embodiments, it further includes: forming a capacitor connected to the top of the columnar active region 203.

[0077] Some embodiments of this application also provide a semiconductor device, characterized in that, in conjunction with reference to... Figures 16-20 as well as Figures 33-36 ,include:

[0078] Substrate 200;

[0079] Word line structures (212, 213) are located on the substrate 200. There are a plurality of word line structures (212, 213) extending along the second direction. Each word line structure (212, 213) surrounds the sidewall of a plurality of columnar active regions arranged along the second direction, and adjacent word line structures (212, 213) are separated by a second trench 202.

[0080] The sidewall surfaces of the character line structure (212, 213) are sequentially provided with a first sidewall material layer 214 and a second sidewall material layer 216, and there is an air gap 217 between the first sidewall material layer 214 and the second sidewall material layer 216.

[0081] The second isolation layer 218 is located on the first sidewall material layer 214 and the second sidewall material layer 216, and the second isolation layer 218 closes the opening of the air gap 217.

[0082] In some embodiments, the substrate 200 has a plurality of columnar active regions 203, which are separated by a plurality of first trenches extending along a first direction and a plurality of second trenches extending along a second direction. The first trenches and the second trenches are connected, and the depth of the first trenches is greater than the depth of the second trenches. A first isolation layer 210 is located in the first trenches and the second trenches, and the surface of the first isolation layer 210 is higher than the bottom surface of the second trench and lower than the surface of the columnar active regions.

[0083] In some embodiments, the materials of the first sidewall material layer and the second sidewall material layer are one of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonate, and silicon carbonitride.

[0084] In some embodiments, the method further includes: forming a plurality of metal silicide-containing bit lines 207 extending along the first direction in the substrate located at the bottom of the second trench and the bottom of the columnar active region (see reference). Figure 33 Each of the metal silicide-containing bit lines 207 electrically connects the bottom of the plurality of columnar active regions 203 arranged along the first direction.

[0085] In some embodiments, the columnar active region 203 includes, from top to bottom, a top end portion 12, a word line region 11, and a bottom end portion 12 (see reference). Figure 33 The diameter of the word line area 11 is smaller than the diameter of the top end 12 and the bottom end 13 of the columnar active area, and the word line structure (212, 213) is located on the side wall surface of the word line area 11.

[0086] In some embodiments, the word line structure (212, 213) includes an isolation medium layer 212 located on the sidewall surface of the word line area 11 and a metal layer 213 located on the surface of the isolation medium layer 212.

[0087] In some embodiments, the top (or top portion 12) of the columnar active region 203 has a sidewall 211 on its sidewall surface, and the letter line structure is located below the sidewall 211.

[0088] In some embodiments, the first sidewall material layer 214 also covers the surface of the sidewall 211.

[0089] In some embodiments, it further includes a capacitor connected to the top of the columnar active region 203.

[0090] It should be noted that the limitations or descriptions of the same or similar structures in this embodiment (semiconductor device) and the foregoing embodiment (formation process of semiconductor device) will not be repeated in this embodiment. Please refer to the limitations or descriptions of the corresponding parts in the foregoing embodiments for details.

[0091] Although this application has been disclosed above with reference to preferred embodiments, it is not intended to limit this application. Any person skilled in the art can make possible changes and modifications to the technical solutions of this application by utilizing the methods and techniques disclosed above without departing from the spirit and scope of this application. Therefore, any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of this application without departing from the content of the technical solutions of this application shall fall within the protection scope of the technical solutions of this application.

Claims

1. A method for forming a semiconductor device, characterized in that, include: A substrate is provided on which a plurality of word line structures extending along a second direction are formed, each word line structure surrounding the sidewall of a plurality of columnar active regions arranged along the second direction, and adjacent word line structures are separated by a second trench. A first sidewall material layer, a sacrificial layer, and a second sidewall material layer are sequentially formed on the sidewall surfaces of the word line structure on both sides of the second trench, and the second sidewall material layer fills the remaining second trench. Etching back removes part of the second sidewall material layer, exposing the top surface of the sacrificial layer; Remove the sacrificial layer to form a double air gap between the adjacent word line structures; A second isolation layer is formed on the first sidewall material layer and the remaining second sidewall material layer, the second isolation layer sealing the opening of the double air gap.

2. The method for forming a semiconductor device as described in claim 1, characterized in that, The first sidewall material layer and the second sidewall material layer are made of the same material, and the first sidewall material layer is made of a different material than the sacrificial layer.

3. The method for forming a semiconductor device as described in claim 2, characterized in that, The materials of the first sidewall material layer and the second sidewall material layer are one of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonate, and silicon carbonitride.

4. The method for forming a semiconductor device as described in claim 2, characterized in that, The material of the sacrificial layer is one of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonate, silicon carbonitride, amorphous carbon, amorphous silicon, or polycrystalline silicon.

5. The method for forming a semiconductor device as described in claim 2, characterized in that, The thickness of the first sidewall material layer is 20-100 angstroms, the thickness of the second sidewall material layer is 50-200 angstroms, and the thickness of the sacrificial layer is 2-50 angstroms.

6. The method for forming a semiconductor device as described in claim 1, characterized in that, The sacrificial layer is removed using an isotropic wet etching process, and the etching selectivity ratio of the sacrificial layer relative to the first sidewall material layer and the second sidewall material layer is greater than 2:1 during the removal of the sacrificial layer.

7. The method for forming a semiconductor device as described in claim 1, characterized in that, The formation process of the word line structure includes: filling the second trench with a first isolation layer; forming a plurality of hard mask patterns extending along a second direction on the surface of the first isolation layer and the top surface of the columnar active regions, each hard mask pattern being located above a plurality of columnar active regions arranged along the second direction, with a first opening between adjacent hard mask patterns, each first opening being located above a corresponding second trench; etching back along the first opening, using the hard mask pattern as a mask, removing a portion of the thickness of the first isolation layer, exposing a portion of the sidewall surface of the top of the columnar active regions; forming a shape on the sidewall of the hard mask pattern and the exposed sidewall surface of the top of the columnar active regions. Form a sidewall; continue etching along the first opening, using the hard mask pattern and the sidewall as a mask, to remove a portion of the thickness of the first isolation layer, exposing the sidewall surface of the middle portion of the columnar active region, with the remaining surface of the first isolation layer higher than the bottom surface of the second trench; etch away a portion of the thickness of the exposed middle portion of the columnar active region to form a word line region, the word line region being located in the middle of the columnar active region, with the top of the word line region above it and the bottom of the word line region below it, and the diameter of the word line region being smaller than the diameter of the top and bottom of the columnar active region; form a word line structure on the sidewall surface of the word line region.

8. The method for forming a semiconductor device as described in claim 7, characterized in that, The word line structure includes an isolation medium layer located on the sidewall surface of the word line area and a metal layer located on the surface of the isolation medium layer.

9. The method for forming a semiconductor device as described in claim 8, characterized in that, The process of forming the isolation dielectric layer and the metal layer includes: forming an isolation dielectric layer on the sidewall surface of the word line area through an oxidation process; filling the second trench with a metal material layer; and removing part of the metal material layer along the first opening, using the hard mask pattern and the sidewall as a mask, to form a metal layer on the surface of the isolation dielectric layer.

10. The method for forming a semiconductor device as described in claim 7, characterized in that, The first sidewall material layer also covers the surface of the sidewall.

11. The method for forming a semiconductor device as claimed in claim 1, characterized in that, Also includes: A capacitor is formed that is connected to the top of the columnar active region.

12. A semiconductor device, characterized in that, The semiconductor device, manufactured according to the forming method according to any one of claims 1-11, comprises: Substrate; A word line structure is located on the substrate. There are several word line structures extending along a second direction. Each word line structure surrounds the sidewall of a plurality of columnar active regions arranged along the second direction, and adjacent word line structures are separated by a second trench. The sidewall surface of the character line structure is provided with a first sidewall material layer and a second sidewall material layer in sequence, and there is an air gap between the first sidewall material layer and the second sidewall material layer; A second isolation layer is located on the first sidewall material layer and the second sidewall material, and the second isolation layer closes the opening of the air gap.

13. The semiconductor device as claimed in claim 12, characterized in that, The materials of the first sidewall material layer and the second sidewall material layer are one of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonate, and silicon carbonitride.

14. The semiconductor device as claimed in claim 12, characterized in that, The columnar active area includes, from top to bottom, a top portion, a word line area, and a bottom portion. The diameter of the word line area is smaller than the diameter of the top portion and the bottom portion of the columnar active area. The word line structure is located on the side wall surface of the word line area.

15. The semiconductor device as claimed in claim 14, characterized in that, The word line structure includes an isolation medium layer located on the sidewall surface of the word line area and a metal layer located on the surface of the isolation medium layer.

16. The semiconductor device as claimed in claim 15, characterized in that, The top end of the columnar active region has a sidewall surface, and the letter line structure is located below the sidewall.

17. The semiconductor device as claimed in claim 16, characterized in that, The first sidewall material layer also covers the surface of the sidewall.

18. The semiconductor device as claimed in claim 15, characterized in that, Also includes: A capacitor connected to the top of the columnar active region.

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