Method for manufacturing a semiconductor structure and semiconductor structure

Abstract

The present disclosure provides a semiconductor structure manufacturing method and a semiconductor structure, and relates to the technical field of semiconductors. The manufacturing method comprises the following steps: forming a stack structure by alternately stacking a sacrificial layer and a support layer on a substrate; forming a plurality of active steps at positions corresponding to the sacrificial layer, wherein each active step comprises a plurality of active layers, a first end of each active step forms a plurality of active terraces, and the active steps are arranged in a second direction; forming a capacitor structure at a second end of each active step; forming a gate oxide layer covering a gate of each active layer; forming a plurality of word lines, each of which intersects with a corresponding active step at a preset angle, covers a part of a sidewall of each active layer corresponding to the word line, and corresponds to the gate of each active layer; and forming a plurality of bit lines, each of which is connected to each active terrace perpendicularly. In the present disclosure, the number of stacked layers of the memory in the semiconductor structure formed can be controlled by adjusting the number of stacked layers of the stack structure, so that the semiconductor structure has an increasing storage density.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a method for fabricating a semiconductor structure and the semiconductor structure itself. Background Technology

[0002] In the field of semiconductor chips, according to Moore's Law, the performance of a semiconductor chip doubles for every doubling of the number of semiconductor devices. To improve the performance of semiconductor chips, their feature sizes are continuously shrinking and their integration density is continuously increasing. However, due to the limitations of photolithography processes, there are limits to the size reduction of semiconductor chips. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail in this disclosure. This overview is not intended to limit the scope of the claims.

[0004] This disclosure provides a method for fabricating a semiconductor structure and the semiconductor structure itself.

[0005] The first aspect of this disclosure provides a method for fabricating a semiconductor structure, the method comprising:

[0006] A stacked structure is provided, the stacked structure being disposed on a substrate, the stacked structure comprising alternately stacked sacrificial layers and support layers;

[0007] Remove the sacrificial layer and form multiple sets of active steps at the corresponding locations of the sacrificial layer. Each active step includes multiple active layers spaced apart along a direction away from the substrate. Each active layer extends along a first direction and includes a gate. The width of the multiple active layers gradually decreases along the direction away from the substrate. Multiple active steps are formed at the first end of the active steps. The active steps are arranged in an array in a second direction.

[0008] A capacitor structure is formed at the second end of the active step, and the capacitor structure is connected to each active layer of each active step.

[0009] A gate oxide layer is formed to cover the gate of each of the active layers;

[0010] Multiple word lines are formed, each word line corresponds to each group of active steps, each word line intersects its corresponding active step at a preset angle, covers part of the sidewall of each active layer of its corresponding active step, and the part of each active layer covered by the word line corresponds to the gate of each active layer, and the word line is separated from the gate by the gate oxide layer;

[0011] Multiple bit lines are formed, and each bit line is vertically connected to each active step.

[0012] The stacked structure includes a central region and a stepped region, and the manufacturing method further includes:

[0013] The stepped area is etched to form a stepped groove that runs through the stacked structure. The stepped groove divides the stacked structure into at least one stepped structure. The stepped structure includes multiple stepped layers. Each stepped layer includes a portion of the sacrificial layer and a portion of the support layer.

[0014] Multiple first grooves are formed, each first groove penetrating the stepped area and the central area along the first direction. The first grooves are arranged at intervals in the second direction, and the multiple first grooves divide the stepped structure into multiple independently set sub-step units.

[0015] Removing the sacrificial layer includes:

[0016] A second trench is formed, which extends along the second direction and penetrates multiple sets of the sub-step units, and the sidewalls of the second trench expose a portion of the sacrificial layer of each of the sub-step units;

[0017] The sacrificial layer is etched based on the second trench to remove all of the sacrificial layer, and a first opening is formed at the position corresponding to the sacrificial layer, the first opening extending along the first direction.

[0018] In the process of etching the sacrificial layer based on the second trench, the sacrificial layer has a high etching selectivity relative to the support layer.

[0019] Wherein, in the first direction, the stepped structure includes a first region close to the stepped groove and a second region away from the stepped groove;

[0020] Multiple sets of active staircases are formed at certain locations corresponding to the sacrificial layer, including:

[0021] A conductive material is filled into the first opening located in the first region, and an active layer is formed in each of the first openings. A plurality of the active layers arranged in a direction away from the substrate form a set of active steps.

[0022] The process of filling the first opening located in the first region with conductive material includes:

[0023] The conductive material is filled into the first opening;

[0024] Based on the second trench, the conductive material is etched along the first direction to expose the first opening located in the second region, while retaining the conductive material located in the first region to form the active layer.

[0025] The capacitor structure includes multiple horizontal portions, each of which is located in each of the first openings in the second region, and each of the horizontal portions is in contact with each of the active layers.

[0026] The formation of the capacitor structure includes:

[0027] A lower electrode layer is formed, covering the trench wall of the second trench and the sidewall of the first opening located in the second region;

[0028] A high-k dielectric layer is formed to cover the lower electrode layer;

[0029] An upper electrode layer is formed to cover the high-k dielectric layer and fill the unfilled areas of the second trench and the first opening.

[0030] The method for fabricating the semiconductor structure further includes:

[0031] A dielectric layer is formed, which fills the first trench and the stepped groove.

[0032] The formation of the gate oxide layer includes:

[0033] A portion of the dielectric layer and a portion of the support layer are removed to form a plurality of word line slots in the central region, the word line slots being perpendicular to the top surface of the substrate, and each word line slot exposing the gate of each of the active layers of a set of active steps;

[0034] The gate oxide layer is formed, which covers the slot wall of each word slot and the gate exposed by the word slot.

[0035] This forms multiple character lines, including:

[0036] The word line is formed in each of the word line slots, and the word line covers the gate oxide layer located in the word line slot and fills the unfilled area of ​​the word line slot.

[0037] This forms multiple bit lines, including:

[0038] A portion of the dielectric layer and a portion of the support layer are removed, and a plurality of bit line grooves are formed in the step region. The bit line grooves are perpendicular to the top surface of the substrate. Each bit line groove is provided in correspondence with each active step in each group of active steps. Each bit line groove exposes a portion of the top surface of the active step corresponding to it.

[0039] A barrier layer is formed, which covers the groove wall of the bit line slot and the top surface of the active step exposed by the bit line slot;

[0040] A bit line conductive layer is formed, which covers the barrier layer and fills the unfilled areas in the bit line groove;

[0041] The blocking layer and the bit line conductive layer located in the same bit line groove form the bit line.

[0042] The method for fabricating the semiconductor structure further includes:

[0043] Multiple word line contact plugs are formed, and each of the multiple word line contact plugs is connected to a corresponding word line. The word line contact plugs are disposed on the top surface of the word line to which they correspond.

[0044] The method for fabricating the semiconductor structure further includes:

[0045] A bottom support layer is formed between the substrate and the stacked structure, the material of the bottom support layer including an insulating material.

[0046] The second aspect of this disclosure provides a semiconductor structure fabricated according to the method for fabricating the semiconductor structure described in the first aspect.

[0047] The semiconductor structure fabrication method and semiconductor structure disclosed herein can control the number of stacked layers of memory in the formed semiconductor structure by adjusting the number of stacked layers of the stacked structure in the fabrication method, so that the semiconductor structure has a continuously increasing storage density, overcoming the problem that the storage density of semiconductor chips is difficult to continue to increase due to the miniaturization of the chip size, and providing a new direction for the development of semiconductor chips.

[0048] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0049] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of these embodiments. In these drawings, similar reference numerals are used to denote similar elements. The drawings described below are some embodiments of the present disclosure, but not all embodiments. Other drawings will be readily available to those skilled in the art based on these drawings without inventive effort.

[0050] Figure 1 This is a flowchart illustrating a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0051] Figure 2 This is a schematic diagram of a stacked structure according to an exemplary embodiment.

[0052] Figure 3 yes Figure 2A cross-sectional view of surface AA.

[0053] Figure 4 Based on the cross-sectional view of the AA surface of the first sub-mask etching stack structure.

[0054] Figure 5 A cross-sectional view of the AA surface of the second mask etching stack structure.

[0055] Figure 6 A cross-sectional view of the AA surface that forms the stepped groove.

[0056] Figure 7 A schematic diagram illustrating the formation of stepped grooves according to an exemplary embodiment.

[0057] Figure 8 A schematic diagram illustrating the filling of a medium material in a stepped groove according to an exemplary embodiment.

[0058] Figure 9 A schematic diagram illustrating the formation of a first trench according to an exemplary embodiment.

[0059] Figure 10 A schematic diagram illustrating the filling of a medium material in a first trench according to an exemplary embodiment.

[0060] Figure 11 yes Figure 10 A cross-sectional view of the BB side.

[0061] Figure 12 yes Figure 10 A cross-sectional view of the C-plane.

[0062] Figure 13 A cross-sectional view of the CC surface forming the second trench, as shown in an exemplary embodiment.

[0063] Figure 14 A cross-sectional view of the CC surface forming the first opening, as shown in an exemplary embodiment.

[0064] Figure 15 A cross-sectional view of the C-plane of a first opening filled with conductive material, according to an exemplary embodiment.

[0065] Figure 16 A cross-sectional view of the CC plane in which an active layer is formed in a first opening, according to an exemplary embodiment.

[0066] Figure 17 A schematic diagram showing a first opening filled with conductive material is shown according to an exemplary embodiment.

[0067] Figure 18 yes Figure 17 A cross-sectional view of the DD plane.

[0068] Figure 19 This is a cross-sectional view of the DD plane in which an active layer is formed in a first opening, according to an exemplary embodiment.

[0069] Figure 20 This is a cross-sectional view of the DD plane forming a capacitor structure according to an exemplary embodiment.

[0070] Figure 21 This is a cross-sectional view of the DD surface forming the word line groove, according to an exemplary embodiment.

[0071] Figure 22 This is a cross-sectional view of the DD plane forming a word line, according to an exemplary embodiment.

[0072] Figure 23 This is a cross-sectional view of the DD surface forming a bit groove, according to an exemplary embodiment.

[0073] Figure 24 This is a cross-sectional view of the DD surface forming a word line contact structure according to an exemplary embodiment.

[0074] Figure 25 yes Figure 24 A cross-sectional view of the EE surface.

[0075] Figure 26 yes Figure 25 A magnified view of a portion of area A.

[0076] Figure 27 yes Figure 25 A magnified view of a portion of area B.

[0077] Figure label:

[0078] 100. Substrate; 110. Bottom support layer; 121. First sub-mask; 122. Second sub-mask; 200. Stacked structure; 201. Central region; 202. Stepped region; 210. Sacrificial layer; 220. Support layer; 230. Stepped trench; 231-1. First sub-trench; 231-2. Second sub-trench; 231-N. Nth sub-trench; 240. Stepped structure; 241. Stepped layer; 241-1. First stepped layer; 241-2. Second stepped layer; 241-N-1. N-1th stepped layer; 241-N. Nth stepped layer; 250. First trench; 260. Sub Stepped cell; 270, dielectric layer; 280, second trench; 290, isolation layer; 291, first isolation layer; 292, second isolation layer; 300, active step; 310, active layer; 311, source region; 312, gate; 313, drain region; 3101, active step; 400, capacitor structure; 410, lower electrode layer; 420, high-k dielectric layer; 430, upper electrode layer; 440, horizontal portion; 501, word line slot; 510, gate oxide layer; 520, word line; 530, word line contact plug; 601, bit line slot; 610, bit line; 611, barrier layer; 612, bit line conductive layer;

[0079] D1, First Direction; D2, Second Direction; D3, Third Direction. Detailed Implementation

[0080] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions in the disclosed embodiments will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without creative effort are within the scope of protection of this disclosure. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0081] Currently, Dynamic Random Access Memory (DRAM) chips are typically planar in structure. The size of planar DRAM has been reduced to its limit, making it difficult to continue miniaturizing and maintaining the effectiveness of Moore's Law. As a result, DRAM is beginning to evolve from planar to three-dimensional structures.

[0082] The exemplary embodiments disclosed herein provide a method for fabricating a semiconductor structure and a semiconductor structure. The number of stacked layers of memory in the formed semiconductor structure can be controlled by adjusting the number of stacked layers of the stacked structure in the fabrication method, so that the semiconductor structure has a continuously increasing storage density. This overcomes the problem that the storage density of semiconductor chips is difficult to continue to increase due to the miniaturization of the chip size, and provides a new direction for the development of semiconductor chips.

[0083] This disclosure provides a method for fabricating a semiconductor structure in exemplary embodiments, such as... Figure 1 As shown, Figure 1 A flowchart illustrating a method for fabricating a semiconductor structure according to an exemplary embodiment of the present disclosure is shown. Figures 2-27 The diagram below illustrates the various stages of semiconductor structure fabrication. Figures 2-27 The methods for fabricating semiconductor structures are introduced.

[0084] This embodiment does not limit the semiconductor structure. The following description will take dynamic random access memory (DRAM) as an example, but this embodiment is not limited to this. Other semiconductor structures are also possible in this embodiment.

[0085] like Figure 1 As shown, an exemplary embodiment of this disclosure provides a method for fabricating a semiconductor structure, comprising the following steps:

[0086] Step S110: Provide a stacked structure disposed on a substrate, the stacked structure comprising alternately stacked sacrificial layers and support layers.

[0087] In this embodiment, a stacked structure 200 is provided, including the following steps:

[0088] Reference Figure 2 , Figure 3 A substrate 100 is provided. The substrate 100 can be a semiconductor substrate, which may include a silicon substrate, a germanium (Ge) substrate, a silicon germanide (SiGe) substrate, an SOI (Silicon-on-Insulator) substrate, or a GOI (Germanium-on-Insulator) substrate, etc. The semiconductor substrate may be doped with ions; for example, it can be a P-type doped substrate or an N-type doped substrate. In this embodiment, the substrate 100 is a silicon substrate.

[0089] Reference Figure 2 , Figure 3The insulating material can be deposited using any of the following deposition processes: Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), or sputtering. The insulating material covers the top surface of the substrate 100 to form a bottom support layer 110. In this embodiment, the material of the bottom support layer 110 includes silicon nitride.

[0090] Then, refer to Figure 2 , Figure 3 A sacrificial layer 210 is deposited using any of the above-described deposition processes, covering the top surface of the bottom support layer 110. Then, a support layer 220 is deposited using any of the above-described deposition processes, covering the top surface of the sacrificial layer 210. The steps of forming the sacrificial layer 210 and the support layer 220 are repeated to form a stacked structure 200 on the bottom support layer 110. The stacked structure 200 includes alternately stacked sacrificial layers 210 and support layers 220. The stacked structure 200 and the substrate 100 are electrically isolated through the bottom support layer 110.

[0091] like Figure 2 , Figure 3 As shown, the sacrificial layer 210 and the support layer 220 of the stacked structure 200 can be stacked alternately in 2 to 1024 or more layers. For example, the sacrificial layer 210 and the support layer 220 can be stacked alternately in 48, 64, 128, 256, or 512 layers, etc., wherein the top layer of the stacked structure 200 is the support layer 220. In this embodiment, the material of the sacrificial layer 210 may include oxides, and the material of the support layer 220 may include nitrides. For example, the material of the sacrificial layer 210 may include silicon oxide, and the material of the support layer 220 may include silicon nitride.

[0092] like Figure 2 , Figure 3 As shown, each sacrificial layer 210 extends along a first direction D1 and a second direction D2, respectively. The first direction D1 and the second direction D2 are parallel to the top surface of the substrate 100 and perpendicular to the second direction D2. The stacking direction of the stacked structure 200 is a third direction D3, which is perpendicular to the top surface of the substrate 100 and perpendicular to both the first direction D1 and the second direction D2. In this embodiment, the stacked structure 200 includes a central region 201 and a stepped region 202 alternately arranged along the first direction D1.

[0093] Step S120: Etch the step area to form a stepped groove that runs through the stacked structure. The stepped groove divides the stacked structure into at least one stepped structure. The stepped structure includes multiple stepped layers, and each stepped layer includes a portion of the sacrificial layer and a portion of the support layer.

[0094] like Figure 7 As shown, refer to Figure 2 In this embodiment, the step area 202 is etched along the second direction D2 to form a stepped groove 230 in the step area 202. The stepped groove 230 penetrates the stacked structure 200 in the second direction D2 and also penetrates the stacked structure 200 in the third direction D3.

[0095] like Figure 6 , Figure 7 As shown, the stepped groove 230 includes multiple sub-grooves arranged along a third direction D3, and the width of the multiple sub-grooves increases in a stepped manner. For example, the stepped groove 230 includes a first sub-groove 231-1, a second sub-groove 231-2, ..., an Nth sub-groove 231-N arranged sequentially along the third direction D3. The stepped groove 230 divides the retained stacked structure 200 into independently arranged stepped structures 240. Part of the stepped structure 240 is located in the central region 201, and another part of the stepped structure 240 extends to the step area 202 and partially overlaps with the stepped groove 230.

[0096] like Figure 6 As shown, in the first direction D1, stepped structures 240 and stepped grooves 230 are alternately arranged, and the stepped structures 240 located on both sides of the stepped grooves 230 are arranged opposite to each other. The stepped structure 240 includes multiple stepped layers 241 stacked along the third direction D3. Each stepped layer 241 includes a portion of the structure of a sacrificial layer 210 and a portion of the structure of a support layer 220. The top surface of the sacrificial layer 210 of each stepped layer 241 is covered by the support layer 220 of the stepped layer 241.

[0097] Step S130: Multiple first grooves are formed, each first groove runs through the step area and the central area along the first direction, and the first grooves are arranged at intervals in the second direction. The multiple first grooves divide the stepped structure into multiple independently set sub-step units.

[0098] In this embodiment, the formation of multiple first trenches 250 can be achieved through the following implementation:

[0099] like Figure 8 As shown, reference Figure 7 The deposition medium material fills the stepped groove 230. For example, any one of the deposition processes selected from chemical vapor deposition, physical vapor deposition, atomic layer deposition, or sputtering can be used to deposit the medium material. In this embodiment, the medium material may include nitrides, such as silicon nitride.

[0100] Then, as Figure 9 As shown, reference Figure 6 , Figure 8 The dielectric material in the stepped structure 240 and stepped groove 230 is etched along the first direction D1 to remove part of the stepped structure 240 and part of the dielectric material, forming multiple first grooves 250. Each first groove 250 penetrates the stepped area 202 and the central area 201 along the first direction D1, and the first grooves 250 are spaced apart on the second direction D2.

[0101] like Figure 9 As shown, multiple first grooves 250 divide the retained portion of each step structure 240 into multiple independently set sub-step units 260, which are arrayed along the second direction D2.

[0102] Step S140: Remove the sacrificial layer and form multiple sets of active steps at the corresponding part of the sacrificial layer. The active steps include multiple active layers spaced apart along the direction away from the substrate. Each active layer extends along a first direction and includes a gate. The width of the multiple active layers gradually decreases along the direction away from the substrate. Multiple active steps are formed at the first end of the active steps. The active steps are arrayed in the second direction.

[0103] First, such as Figure 10 , Figure 11 , Figure 12 As shown, reference Figure 9 The first trench 250 is filled with a deposition medium material. For example, any one of the deposition processes, namely chemical vapor deposition, physical vapor deposition, atomic layer deposition, or sputtering, can be used to deposit the medium material. The medium material in the first trench 250 and the medium material in the stepped trench 230 together form the medium layer 270.

[0104] Then, as Figure 13 , Figure 17 As shown, refer to Figure 12 The process involves etching away a portion of the structure of each sub-step unit 260 and a portion of the dielectric layer 270 located in the first trench 250. A second trench 280 is formed at the locations where the sub-step units 260 and the dielectric layer 270 are removed. The second trench 280 extends along a second direction D2, and each second trench 280 penetrates multiple sub-step units 260. Multiple sub-step units 260 penetrated by the same second trench 280 are formed by etching the same step structure 240. The sidewalls of the second trench 280 expose a portion of the structure of each sacrificial layer 210 of each sub-step unit 260 penetrated by it.

[0105] Next, as Figure 14 As shown, refer to Figure 13Based on the second trench 280, the sacrificial layer 210 is etched to remove all of the sacrificial layer 210, forming a first opening 211 at the position corresponding to the sacrificial layer 210. The first opening 211 extends along the first direction D1. During the etching of the sacrificial layer 210 based on the second trench 280, the sacrificial layer 210 has a high etching selectivity relative to the support layer 220 and the dielectric layer 270, so that the sacrificial layer 210 is completely removed, while the support layer 220 and the dielectric layer 270 are retained. The first opening 211 extending along the first direction D1 is formed at the position of the sacrificial layer 210 in the sub-step unit 260. In this embodiment, the method of etching the sacrificial layer 210 based on the second trench 280 is as follows: an etching solution is injected into the second trench 280, the material of the sacrificial layer 210 dissolves in the etching solution, while the materials of the support layer 220 and the dielectric layer 270 are insoluble in the etching solution. After the material of the sacrificial layer 210 is completely dissolved in the etching solution, the etching solution is removed, and a first opening 211 is formed at the location of the sacrificial layer 210. In this embodiment, hot phosphoric acid can be used as the etching solution.

[0106] Next, as Figure 17 , Figure 18 As shown, refer to Figure 14 Conductive material is deposited into the second trench 280 using any one of the following deposition processes: chemical vapor deposition, physical vapor deposition, atomic layer deposition, or sputtering. The conductive material fills the first opening 211 through the second trench 280, and then the conductive material in the second trench 280 is removed by etching back. The conductive material in each first opening 211 forms an active layer 310. In this embodiment, the material of the active layer 310 includes a semiconductor material, which can be silicon (Si), germanium (Ge), or silicon-germanium (GeSi), silicon carbide (SiC); the semiconductor material can also be silicon-on-insulator (SOI), germanium-on-insulator (GOI); or it can be other materials, such as gallium arsenide or other group III-V compounds.

[0107] like Figure 18 As shown, a plurality of active layers 310 arranged along a direction away from the substrate 100 (i.e., the third direction D3) form a set of active steps 300. In each set of active steps 300, the lengths of the plurality of active layers 310 along the direction away from the substrate 100 decrease sequentially in the first direction D1, and the length difference between adjacent active layers 310 forms an active step 3101 at the first end of the active step 300, wherein the first end of the active step 300 is the end where the active step 300 is connected to the step groove 230.

[0108] Reference Figure 16 or Figure 25In the first direction D1, each active layer 310 includes a drain region 313 or a source region 311, a gate 312, and a source region 311 or a drain region 313 arranged sequentially. Active layers 310 belonging to the same group of active ladders 300 have their gates 312 arranged in a row in the third direction D3.

[0109] Step S150: Form a capacitor structure at the second end of the active ladder, and connect the capacitor structure to each active layer of each active ladder.

[0110] In this embodiment, a capacitor structure 400 is formed, comprising:

[0111] First, such as Figure 20 , Figure 25 and Figure 26 As shown, refer to Figure 19 The lower electrode layer 410 can be deposited using any of the following deposition processes: chemical vapor deposition, physical vapor deposition, atomic layer deposition, or sputtering. The lower electrode layer 410 covers the trench wall of the second trench 280 and the active layer 310 exposed on the trench wall of the second trench 280. The material of the lower electrode layer 410 includes compounds formed from one or two of metal nitrides and metal silicides, such as titanium nitride (Ti2N2), titanium silicide (TiSi2), nickel silicide (Ni2Si), and titanium silicon nitride (TiSixNy).

[0112] Then, refer to Figure 20 , Figure 25 and Figure 26 A high-k dielectric layer 420 is deposited using any of the above-described deposition processes, and the high-k dielectric layer 420 covers the lower electrode layer 410. The material of the high-k dielectric layer 420 may include metal silicates or metal oxides. For example, the material of the high-k dielectric layer 420 may include at least one of tantalum oxide (Ta2O5), titanium oxide (TiO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), hafnium silicon oxide (HfSiO2), or hafnium oxide (HfO2).

[0113] Next, refer to Figure 20 , Figure 25 and Figure 26 The upper electrode layer 430 is deposited using any of the above-described deposition processes. The upper electrode layer 430 covers the high-k dielectric layer 420 and fills the unfilled areas of the second trench 280. The material of the upper electrode layer 430 may include at least one of titanium or its alloys, tantalum or its alloys, and tungsten or its alloys.

[0114] like Figure 20 As shown, refer to Figure 25 and Figure 26The lower electrode layer 410, the high-K dielectric layer 420, and the upper electrode layer 430 together form a capacitor structure 400. In this embodiment, the capacitor structure 400 is located in the second trench 280. The capacitor structure 400 is disposed at the second end of the active step 300 away from the active step 3101. Furthermore, the capacitor structure 400 is in contact with the drain region 313 or the source region 311 of each active layer 310.

[0115] Step S160: Form a gate oxide layer to cover the gate of each active layer.

[0116] In this embodiment, forming the gate oxide layer 510 includes the following steps:

[0117] First, such as Figure 21 , Figure 25 As shown, refer to Figure 20 A portion of the dielectric layer 270 and a portion of the support layer 220 are removed, and a plurality of word slots 501 are formed in the central region 201. The word slots 501 are perpendicular to the top surface of the substrate 100, and each word slot 501 exposes the gate 312 of each active layer 310 of a set of active steps 300.

[0118] Then, as Figure 22 , Figure 25 As shown, refer to Figure 21 A gate oxide layer 510 is formed, which covers the trench walls of each word trench 501 and the gate 312 exposed by the word trench 501. The gate oxide layer 510 can be formed by any of the following deposition processes: chemical vapor deposition, physical vapor deposition, atomic layer deposition, or sputtering. The material of the gate oxide layer 510 includes silicon oxide or silicon oxynitride.

[0119] Step S170: Form multiple word lines, each word line corresponding to each group of active steps. Each word line intersects its corresponding active step at a preset angle, covering part of the sidewall of each active layer of its corresponding active step. The part of each active layer covered by the word line corresponds to the gate of each active layer. The word lines are separated from the gate by the gate oxide layer.

[0120] like Figure 22 , Figure 25 As shown, refer to Figure 21 A word line 520 is formed in each word slot 501, and the word line 520 covers the gate oxide layer 510 located in the word slot 501 and fills the unfilled area of ​​the word slot 501. In this embodiment, any one of the deposition processes selected from chemical vapor deposition, physical vapor deposition, atomic layer deposition, or sputtering can be used to form the word line 520. The material of the word line 520 may include at least one of titanium or its alloy, tantalum or its alloy, and tungsten or its alloy.

[0121] Step S180: Form multiple bit lines, each bit line being vertically connected to each active step.

[0122] In this embodiment, multiple bit lines 610 can be formed using the following implementation method:

[0123] like Figure 23 , Figure 25 , Figure 27 As shown, refer to Figure 22 A portion of the dielectric layer 270 and a portion of the support layer 220 are removed, and a plurality of bit line grooves 601 are formed in the step region 202. The bit line grooves 601 are perpendicular to the top surface of the substrate 100. Each bit line groove 601 is configured in a one-to-one correspondence with each active step 3101 in each group of active steps 300, and each bit line groove 601 exposes a portion of the top surface of its corresponding active step 3101.

[0124] Then, as Figure 23 , Figure 25 , Figure 27 As shown, refer to Figure 22 A conductive material can be deposited using any of the following deposition processes: chemical vapor deposition, physical vapor deposition, atomic layer deposition, or sputtering, to form a barrier layer 611. The barrier layer 611 covers the trench wall of the bit line trench 601 and the top surface of the active step 3101 exposed by the bit line trench 601. In this embodiment, the material of the barrier layer may include at least one of silicon oxide or silicon oxynitride.

[0125] Then, as Figure 23 , Figure 25 , Figure 27 As shown, any of the above deposition processes can be used to deposit conductive material to form a bit line conductive layer 612. The bit line conductive layer 612 covers the barrier layer 611 and fills the unfilled areas in the bit line groove 601. The barrier layer 611 and the bit line conductive layer 612 located in the same bit line groove 601 form a bit line 610. Figure 25 As shown, each bit line 610 is connected to the source region 311 or drain region 313 of each active layer 310. A barrier layer 611 is disposed between the bit line 610 and the active layer 310 to prevent the material of the bit line 610 from diffusing into the active layer 310 and avoid contamination of other devices in the semiconductor structure.

[0126] The fabrication method of this embodiment forms a memory stacked vertically on a substrate. The semiconductor structure memory has an increaseable number of stacked layers, which can form a larger number of memories on the same area of ​​deposition, thus meeting the development needs of the semiconductor field for high-capacity memories.

[0127] According to an exemplary embodiment, this embodiment is a further description of the above embodiments. The method for fabricating the semiconductor structure in this embodiment includes all the steps in the above embodiments. In addition, the method for fabricating the semiconductor structure in this embodiment further includes the following steps:

[0128] An isolation layer 290 is formed, which covers the top surface of word line 520 and bit line 610.

[0129] In this embodiment, the isolation layer 290 can be formed in the following ways:

[0130] First, such as Figure 21 As shown, after the capacitor structure 400 is formed, a first isolation layer 291 can be deposited using any of the following deposition processes: chemical vapor deposition, physical vapor deposition, atomic layer deposition, or sputtering. The first isolation layer 291 covers the top surface of the capacitor structure 400 to prevent the material of the capacitor structure 400 from being exposed to the process environment and contaminated. The material of the first isolation layer 291 may include silicon oxide or silicon oxynitride.

[0131] Then, as Figure 23 As shown, after forming the word line 520, a second isolation layer 292 is formed by depositing an isolation material using any of the above-described deposition processes. The second isolation layer 292 covers the top surface of the word line 520 to prevent the material of the word line 520 from being exposed to the process environment and becoming contaminated. The material of the second isolation layer 292 may include silicon oxide or silicon oxynitride. The first isolation layer 291 and the second isolation layer 292 together form the isolation layer 290.

[0132] Then, multiple word line contact plugs 530 are formed, and the multiple word line contact plugs 530 are connected to multiple word lines 520 respectively. The word line contact plugs 530 are disposed on the top surface of the corresponding word line 520.

[0133] In this embodiment, the word line contact plug 530 is formed after the bit line 610 is formed, and can be implemented in the following way:

[0134] like Figure 24 , Figure 25 As shown, a portion of the isolation layer 290 is etched away, forming multiple word line contact holes (not shown in the figure) corresponding to the positions of multiple word lines 520. Each word line contact hole exposes the top surface of its corresponding word line 520. Conductive material is deposited to fill the word line contact holes 502 using any of the above deposition processes, and the conductive material in the word line contact holes forms word line contact plugs 530. In this embodiment, after forming the bit lines, word line contact plugs are formed to allow the word lines to be led out and connected to other electronic devices or circuits.

[0135] According to an exemplary embodiment, this embodiment is a further description of the above embodiment, and this embodiment is a description of step S120 in the above embodiment. In this embodiment, etching the step area to form a stepped groove through the stacked structure can be implemented in the following way:

[0136] like Figure 3 As shown, along the third direction D3, each sacrificial layer 210 and the support layer 220 on its top surface are used as a step layer 241. The stacked structure 200 includes a first step layer 241-1, a second step layer 241-2, ... the Nth step layer 241-N.

[0137] like Figure 4 As shown, a first sub-mask 121 is formed on the top surface of the stacked structure 200. The first sub-mask 121 exposes part of the top surface of the stacked structure 200 of the step region 202. The stacked structure 200 is etched according to the first sub-mask layer 121 to form a trench with a width of L1 in the Nth step layer 241-N.

[0138] like Figure 5 As shown, a second sub-mask 122 is formed, and the stacked structure 200 is etched using the second sub-mask layer 122 and the Nth step layer 241-N as masks. A trench with a width of L2 is formed in the Nth step layer 241-N, and a trench with a width of L1 is formed in the (N-1)th step layer 241-N-1, where L2 is greater than L1.

[0139] Then, repeat the above steps, as follows: Figure 6 , Figure 7 As shown, until a trench of width L1 is formed in the first stepped layer 241-1, along the direction away from the substrate 100, the trench in the first stepped layer 241-1 is the first sub-trench 231-1, the trench in the second stepped layer 241-2 is the second sub-trench 231-2, and so on, the trench in the Nth stepped layer 241-N is the Nth sub-trench 231-N. The first sub-trench 231-1, the second sub-trench 231-2, and so on, together form the stepped trench 230, and along the third direction D3, the trench widths of the first sub-trench 231-1, the second sub-trench 231-2, and so on, increase in the same stepwise manner.

[0140] In this embodiment, the stacked structure is divided into multiple stepped layers, and the stacked structure is etched multiple times. Sub-trenches are formed in each stepped layer, and the trench width of the sub-trenches in the multiple stepped layers increases stepwise along the direction away from the substrate to form stepped grooves in the stepped area. In the first direction, the stacked structure to be retained is divided into stepped structures that are relatively set on both sides of the stepped grooves. The stepped shape of the stepped structure is more accurate so that the sub-stepped units formed based on the stepped structure can retain the stepped contour of the stepped structure.

[0141] According to an exemplary embodiment, this embodiment is a further description of the above embodiment, and the embodiment is a description of step S140 in the above embodiment. In this embodiment, multiple sets of active stairs are formed at a portion of the location corresponding to the sacrificial layer, including the following steps:

[0142] First, such as Figure 15 As shown, refer to Figure 14 Conductive material is filled into the first opening 211. In this embodiment, in the first direction D1, the stepped structure 240 includes a first region 240-1 near the stepped groove 230 and a second region 240-2 away from the stepped groove 230.

[0143] Then, based on the second trench 280, conductive material is etched along the first direction D1 to expose the first opening 211 located in the second region 240-2, while retaining the conductive material 240-1 located in the first region to form the active layer 310. Figure 16 As shown, after the deposited material fills the first opening 211, the conductive material in the second trench 280 is etched away, and based on the second trench 280, the conductive material located in the second region 240-2 is removed by etching in the first direction D1, while the conductive material located in the first region 240-1 is retained to form the active layer 310.

[0144] In this embodiment, as Figure 20 , Figure 25 , Figure 26 As shown, during the formation of the capacitor structure 400, a lower electrode layer 410 is first deposited, covering the trench walls of the second trench 280 and the sidewalls of the first opening 211 in the second region 240-2. Then, a high-k dielectric layer 420 is deposited on the lower electrode layer 410. Next, an upper electrode layer 430 is deposited, covering the high-k dielectric layer 420 and filling the unfilled areas of the second trench 280 and the first opening 211. The lower electrode layer 410, the high-k dielectric layer 420, and the upper electrode layer 430 together form the capacitor structure 400. The lower electrode layer 410, the high-k dielectric layer 420, and the upper electrode layer 430 in each first opening 211 of the second region 240-2 constitute the horizontal portion 440 of the capacitor structure 400. Each horizontal portion 440 is in contact with the drain 313 or source 311 of each active layer 310.

[0145] The fabrication method of this embodiment removes the conductive material in the second region and forms a horizontal portion of the capacitor structure in the second region, thereby increasing the proportion of the capacitor structure in the semiconductor structure and improving the storage capacity of the semiconductor structure.

[0146] This disclosure provides a semiconductor structure in exemplary embodiments, which is fabricated using the method described in the previous embodiments. The semiconductor structure of this embodiment can be a memory chip, which can be used in Dynamic Random Access Memory (DRAM). However, it can also be applied to Static Random-Access Memory (SRAM), flash EPROM, ferroelectric Random-Access Memory (FRAM), magnetic Random-Access Memory (MRAM), phase-change Random-Access Memory (PRAM), etc. The semiconductor structure of this embodiment has an continuously increasing storage density, overcoming the problem that storage density is difficult to increase further due to chip size miniaturization.

[0147] The various embodiments or implementation methods described in this specification are presented in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referred to each other.

[0148] In the description of this specification, references to the terms "embodiment," "exemplary embodiment," "some implementation," "illustrated implementation," "example," etc., refer to specific features, structures, materials, or characteristics described in connection with an implementation or example that are included in at least one implementation or example of this disclosure.

[0149] In this specification, the illustrative expressions of the terms used do not necessarily refer to the same implementation or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more implementations or examples.

[0150] In the description of this disclosure, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this disclosure.

[0151] It is understood that the terms "first," "second," etc., as used in this disclosure may be used to describe various structures, but these structures are not limited by these terms. These terms are only used to distinguish one structure from another.

[0152] In one or more accompanying drawings, the same elements are represented by similar reference numerals. For clarity, many parts in the drawings are not drawn to scale. Furthermore, certain well-known parts may not be shown. For simplicity, a structure obtained after several steps may be depicted in a single drawing. Many specific details of this disclosure, such as the structure, materials, dimensions, processing methods, and techniques of the devices, are described below to provide a clearer understanding of the disclosure. However, as those skilled in the art will understand, this disclosure may be implemented without adhering to these specific details.

[0153] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this disclosure, and are not intended to limit them. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this disclosure.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, The method for fabricating the semiconductor structure includes: A stacked structure is provided, the stacked structure being disposed on a substrate, the stacked structure comprising alternately stacked sacrificial layers and support layers; Remove the sacrificial layer and form multiple sets of active steps at the corresponding locations of the sacrificial layer. Each active step includes multiple active layers spaced apart along a direction away from the substrate. Each active layer extends along a first direction and includes a gate. The width of the multiple active layers gradually decreases along the direction away from the substrate. Multiple active steps are formed at the first end of the active steps. The active steps are arranged in an array in a second direction. A capacitor structure is formed at the second end of the active step, and the capacitor structure is connected to each active layer of each active step. A gate oxide layer is formed to cover the gate of each of the active layers; Multiple word lines are formed, each word line corresponds to each group of active steps, each word line intersects its corresponding active step at a preset angle, covers part of the sidewall of each active layer of its corresponding active step, and the part of each active layer covered by the word line corresponds to the gate of each active layer, and the word line is separated from the gate by the gate oxide layer; Multiple bit lines are formed, and each bit line is vertically connected to each active step; The stacked structure includes a central region and a stepped region, and the manufacturing method further includes: The stepped area is etched to form a stepped groove that runs through the stacked structure. The stepped groove divides the stacked structure into at least one stepped structure. The stepped structure includes multiple stepped layers. Each stepped layer includes a portion of the sacrificial layer and a portion of the support layer. Multiple first grooves are formed, each first groove penetrating the stepped area and the central area along the first direction. The first grooves are arranged at intervals in the second direction, and the multiple first grooves divide the stepped structure into multiple independently set sub-step units.

2. The method for fabricating a semiconductor structure according to claim 1, characterized in that, Removing the sacrificial layer includes: A second trench is formed, which extends along the second direction and penetrates multiple sets of the sub-step units, and the sidewalls of the second trench expose a portion of the sacrificial layer of each of the sub-step units; The sacrificial layer is etched based on the second trench to remove all of the sacrificial layer, and a first opening is formed at the position corresponding to the sacrificial layer, the first opening extending along the first direction.

3. The method for fabricating a semiconductor structure according to claim 2, characterized in that, During the etching of the sacrificial layer based on the second trench, the sacrificial layer has a high etching selectivity relative to the support layer.

4. The method for fabricating a semiconductor structure according to claim 2, characterized in that, In the first direction, the stepped structure includes a first region close to the stepped groove and a second region away from the stepped groove; Multiple sets of active staircases are formed at certain locations corresponding to the sacrificial layer, including: A conductive material is filled into the first opening located in the first region, and an active layer is formed in each of the first openings. A plurality of the active layers arranged in a direction away from the substrate form a set of active steps.

5. The method for fabricating a semiconductor structure according to claim 4, characterized in that, Filling the first opening located in the first region with a conductive material includes: The conductive material is filled into the first opening; Based on the second trench, the conductive material is etched along the first direction to expose the first opening located in the second region, while retaining the conductive material located in the first region to form the active layer.

6. The method for fabricating a semiconductor structure according to claim 5, characterized in that, The capacitor structure includes a plurality of horizontal portions, each of which is located in each of the first openings in the second region, and each of the horizontal portions is in contact with each of the active layers.

7. The method for fabricating a semiconductor structure according to claim 6, characterized in that, Forming a capacitor structure includes: A lower electrode layer is formed, covering the trench wall of the second trench and the sidewall of the first opening located in the second region; A high-k dielectric layer is formed to cover the lower electrode layer; An upper electrode layer is formed to cover the high-k dielectric layer and fill the unfilled areas of the second trench and the first opening.

8. The method for fabricating a semiconductor structure according to claim 1, characterized in that, The method for fabricating the semiconductor structure further includes: A dielectric layer is formed, which fills the first trench and the stepped groove.

9. The method for fabricating a semiconductor structure according to claim 8, characterized in that, Forming a gate oxide layer includes: A portion of the dielectric layer and a portion of the support layer are removed to form a plurality of word line slots in the central region, the word line slots being perpendicular to the top surface of the substrate, and each word line slot exposing the gate of each of the active layers of a set of active steps; The gate oxide layer is formed, which covers the slot wall of each word slot and the gate exposed by the word slot.

10. The method for fabricating a semiconductor structure according to claim 9, characterized in that, This forms multiple character lines, including: The word line is formed in each of the word line slots, and the word line covers the gate oxide layer located in the word line slot and fills the unfilled area of ​​the word line slot.

11. The method for fabricating a semiconductor structure according to claim 10, characterized in that, Multiple bit lines are formed, including: A portion of the dielectric layer and a portion of the support layer are removed, and a plurality of bit line grooves are formed in the step region. The bit line grooves are perpendicular to the top surface of the substrate. Each bit line groove is provided in correspondence with each active step in each group of active steps. Each bit line groove exposes a portion of the top surface of the active step corresponding to it. A barrier layer is formed, which covers the groove wall of the bit line slot and the top surface of the active step exposed by the bit line slot; A bit line conductive layer is formed, which covers the barrier layer and fills the unfilled areas in the bit line groove; The blocking layer and the bit line conductive layer located in the same bit line groove form the bit line.

12. The method for fabricating a semiconductor structure according to claim 11, characterized in that, The method for fabricating the semiconductor structure further includes: Multiple word line contact plugs are formed, and each of the multiple word line contact plugs is connected to a corresponding word line. The word line contact plugs are disposed on the top surface of the word line to which they correspond.

13. The method for fabricating a semiconductor structure according to claim 1, characterized in that, The method for fabricating the semiconductor structure further includes: A bottom support layer is formed between the substrate and the stacked structure, the material of the bottom support layer including an insulating material.

14. A semiconductor structure, characterized in that, The semiconductor structure is fabricated according to the semiconductor structure fabrication method according to any one of claims 1 to 13.

Images