Metallized stack and method of manufacturing the same and electronic device comprising the metallized stack

Abstract

A metallization stack is disclosed. According to embodiments, the metallization stack can include at least one interconnect line layer and at least one via layer alternatingly disposed on a substrate. At least one pair of adjacent interconnect line layer and via layer in the metallization stack includes an interconnect line in the interconnect line layer and a via in the via layer. The via layer is closer to the substrate than the interconnect line layer. At least a portion of the interconnect line extends longitudinally along a first direction, a sidewall of the at least a portion of the interconnect line along the first direction is substantially coplanar with at least an upper portion of a corresponding sidewall of the via under the at least a portion of the interconnect line.

Description

[0001] This application is a divisional application of invention patent application 201911254611.8 entitled “Metallized Stack and Manufacturing Method Thereof and Electronic Device Including Metallized Stack”, filed on December 6, 2019. Technical Field

[0002] This disclosure relates to the semiconductor field, and more specifically, to metallized stacks, methods of manufacturing the same, and electronic devices including such metallized stacks. Background Technology

[0003] As semiconductor devices continue to miniaturize, it becomes increasingly difficult to manufacture high-density interconnect structures because it requires extremely fine metal lines (meaning small die size, excessive barrier layer thickness, and consequently high resistance) and extremely small line spacing (meaning misalignment and difficulty in filling contact vias). Furthermore, the difficulty in aligning metal lines with vias can lead to short circuits or open circuits in integrated circuits (ICs), thus increasing IC manufacturing costs. Summary of the Invention

[0004] In view of this, the purpose of this disclosure is at least in part to provide a metallized stack, a method of manufacturing the same, and an electronic device including such a metallized stack.

[0005] According to one aspect of this disclosure, a metallization stack is provided, comprising at least one interconnect layer and at least one via layer alternately disposed on a substrate. At least one pair of adjacent interconnect layers and via layers in the metallization stack includes interconnects in the interconnect layers and vias in the via layers. The interconnect layers are closer to the substrate than the via layers. The outer peripheral sidewalls of the vias on at least a portion of the interconnects do not extend beyond the outer peripheral sidewalls of said at least a portion of the interconnects.

[0006] According to another aspect of this disclosure, a method for manufacturing a metallized stack is provided. The metallized stack includes at least one interconnect layer and at least one via layer arranged alternately. The method includes forming at least one pair of adjacent interconnect layers and via layers in the metallized stack by: forming a first metal layer on a lower layer; forming a second metal layer on the first metal layer; patterning the first metal layer and the second metal layer into an interconnect pattern; and patterning the second metal layer into a separated portion to form the via.

[0007] According to another aspect of this disclosure, an electronic device is provided, including the aforementioned metallized stack.

[0008] According to embodiments of this disclosure, interconnect patterns can be formed by photolithography. Therefore, the linewidth and spacing of interconnects, as well as the critical dimension (CD) and spacing of vias, can be determined by the photolithographic linewidth or CD and spacing, thereby reducing the linewidth or CD and spacing and thus increasing integration density. Furthermore, the difficulties of metal filling in conventional processes are avoided. Moreover, since no filling process is used, metal materials such as ruthenium (Ru), molybdenum (Mo), rhodium (Rh), platinum (Pt), iridium (Ir), nickel (Ni), cobalt (Co), or chromium (Cr) can be used, thus eliminating the need for a diffusion barrier layer. Attached Figure Description

[0009] The above and other objects, features, and advantages of this disclosure will become clearer from the following description of embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0010] Figures 1 to 16 The illustration schematically shows some stages in the process of manufacturing a metallized stack according to embodiments of the present disclosure;

[0011] Figures 17 to 24(d) The illustration schematically shows some stages in the process of manufacturing a metallized stack according to another embodiment of the present disclosure.

[0012] in, Figure 3(a) , 7 , 8(a), 9, 10(a), 11(a), 14(a), 18(a), 21, 22(a), 23, 24(a) are top views, Figure 1 , 2 Figures 10(b), 11(b), 12(a), 14(b), 15(a), 15(b), 16, 17, and 24(b) are cross-sectional views along line AA′. Figure 3(b) , 4(a) Figures 5(a), 8(b), 10(c), 11(c), 12(b), 13(a), 14(c), 18(b), 19(a), 20(a), 22(b), and 24(c) are cross-sectional views along line BB′. Figure 3(c) , 4(b) Figures 5(b), 8(c), 10(d), 11(d), 12(c), 13(b), 14(d), 18(c), 19(b), 20(b), 22(c), and 24(d) are cross-sectional views along line CC′. Figures 6(a) to 6(c) It is an enlarged view of the area near the metal wire in the cross section along the BB′ or CC′ line.

[0013] Throughout the accompanying drawings, the same or similar reference numerals denote the same or similar parts. Detailed Implementation

[0014] Embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.

[0015] The accompanying drawings illustrate various structural schematics according to embodiments of the present disclosure. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0016] In the context of this disclosure, when a layer / element is referred to as being "above" another layer / element, the layer / element may be directly above the other layer / element, or there may be an intermediate layer / element between them. Additionally, if a layer / element is "above" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element.

[0017] Embodiments of this disclosure provide a method for manufacturing a metallization stack. Unlike conventional techniques that first form an interlayer dielectric layer, then form trenches or holes in the interlayer dielectric layer, and fill the trenches or holes with a conductive material to form interconnects or vias, embodiments of this disclosure allow for the formation of a metal pattern on a lower layer (e.g., a substrate on which devices are formed or the next layer in a metallization stack), followed by filling the gaps between the metal patterns with a dielectric material to form the interlayer dielectric layer. The metal pattern can be formed by photolithography. Thus, the linewidth and spacing of interconnects, as well as the critical dimension (CD) and spacing of vias, can be determined by the photolithographic linewidth or CD and spacing, thereby reducing the linewidth or CD and spacing and thus increasing integration density. Furthermore, the challenges of metal filling in conventional processes are avoided. Moreover, since no filling process is used, metals such as ruthenium (Ru), molybdenum (Mo), rhodium (Rh), platinum (Pt), iridium (Ir), nickel (Ni), cobalt (Co), or chromium (Cr) can be used, eliminating the need for a diffusion barrier layer.

[0018] Furthermore, in conventional processes, trenches or vias formed by etching have a tapering shape from top to bottom, and thus the interconnects or vias formed therein have a corresponding shape. In contrast, according to embodiments of this disclosure, interconnects or vias can be directly obtained by photolithography, and thus can have a tapering shape from bottom to top.

[0019] According to embodiments of this disclosure, a pair of adjacent interconnect layers and via layers can be formed together. For example, a first metal layer for interconnect layers and a second metal layer for via layers can be formed on a lower layer. The first and second metal layers can be sequentially formed over the entire area where a metallization stack is to be formed, for example, covering substantially the entire surface of the lower layer. The first and second metal layers can be patterned, for example, by photolithography, into interconnect patterns, which may correspond to or correspond to the layout of interconnects in the interconnect layers. The second metal layer with interconnect patterns can be patterned into separate portions to form vias. Additionally, interconnects can be formed from the first metal layer with interconnect patterns (possibly cut in certain areas). Thus, the interconnects and the vias thereon can be self-aligned with each other.

[0020] A spacer layer may be disposed between the first metal layer and the second metal layer. For example, such a spacer layer may be used as an etch stop layer (to optimize the manufacturing process, particularly the etching process therein) and / or a diffusion barrier layer (which improves interconnect performance). The spacer layer may be patterned together with the first and second metal layers into an interconnect pattern.

[0021] The metallization stack may include multiple such interconnect layers and via layers, wherein at least some or all of the interconnect layers and via layers may be fabricated in this manner.

[0022] According to embodiments of this disclosure, the interconnect pattern may include a series of metal lines. These metal lines may have the same pattern as the layout of the interconnects in the interconnect layer. That is, the metal layer may be patterned according to the layout of the interconnects. Alternatively, the interconnect pattern may have a pattern in which the metal lines extend according to the layout of the interconnects, but the metal lines corresponding to the separated interconnects opposite each other may extend continuously. In this case, forming metal lines extending in the same direction is advantageous for patterning. This layout, combined with metal lines extending in another direction intersecting (e.g., orthogonal) to this direction in another interconnect layer, can realize various interconnect routes. For example, in a metallization stack, interconnect layers with interconnects extending in a first direction and interconnect layers with interconnects extending in a second direction orthogonal to the first direction may be alternately arranged in the vertical direction. After the second metal layer is patterned as a via, the metal lines formed in the first metal layer may be cut at a predetermined area according to the layout of the interconnects to achieve separation between different interconnects.

[0023] In the above fabrication process, after the metal lines are formed, dielectric material can be filled into the gaps between the metal lines and in the voids created by the removal of the second metal layer after the patterned vias, to form an interlayer dielectric layer. Because the gaps between the metal lines or the aforementioned voids are small, air gaps or pores can be formed in the filled dielectric material. These air gaps or pores can help reduce capacitance. As described below, the position of the air gaps or pores can be adjusted using a deposition-etching-deposition method. Furthermore, the dielectric material used for each filling step can be the same or different.

[0024] According to the above method, a metallized stack according to embodiments of the present disclosure can be obtained. As described above, at least a portion of the interconnect and the vias thereon can be obtained from the first metal layer and the second metal layer respectively through the same photolithography process (followed by further cutting processes to form the interconnect and the vias), thus allowing them to be self-aligned with each other, so that the sidewalls of the vias do not exceed the sidewalls of the underlying interconnects. For example, the sidewalls of the at least portion of the interconnect along its longitudinal extension direction are substantially coplanar with at least the lower portion of the corresponding sidewall of the via.

[0025] This disclosure may be presented in various forms, some of which will be described below. In the following description, the selection of various materials is discussed. The selection of materials takes into account not only their function (e.g., semiconductor materials for forming active regions, dielectric materials for forming electrical isolation, and conductive materials for forming interconnects and vias) but also etch selectivity. In the following description, the desired etch selectivity may or may not be indicated. Those skilled in the art will understand that when the following references to etching a material layer, unless it is mentioned that other layers are electrically etched or not shown in the figures, then such etching may be selective, and the material layer may possess etch selectivity relative to other layers exposed to the same etch formulation.

[0026] Figures 1 to 16 The illustrations schematically depict some stages in the process of manufacturing a metallization stack according to embodiments of the present disclosure.

[0027] like Figure 1 As shown, a substrate 1001 is provided. The substrate 1001 can be of various forms, including but not limited to bulk semiconductor material substrates such as bulk Si substrates, semiconductor-on-insulator (SOI) substrates, and compound semiconductor substrates such as SiGe substrates. The following description uses a bulk Si substrate as an example.

[0028] In substrate 1001, active regions can be defined by isolation portions 1003, such as shallow trench isolation (STI). For example, isolation portions 1003 can surround each active region. On each active region, a semiconductor device T, such as a metal-oxide-semiconductor field-effect transistor (MOSFET), a fin field-effect transistor (FinFET), a nanowire field-effect transistor, etc., can be formed. The semiconductor device T can have a gate stack including a gate dielectric layer 1005 and a gate electrode layer 1007, and source / drain regions S / D formed on both sides of the gate stack in the active region. On the sidewalls of the gate stack, a gate spacer 1009 can be formed. The semiconductor device T can be a planar device such as a MOSFET or a three-dimensional device such as a FinFET. In the case of a FinFET, the active region can be formed in the form of fins protruding relative to the substrate surface.

[0029] An interlayer dielectric layer 1011, such as an oxide (e.g., silicon oxide), can be formed on the substrate 1001 to cover each semiconductor device T formed on the substrate 1001. Additionally, contact portions 1013 to each semiconductor device T can be formed in the interlayer dielectric layer 1011. Figure 1 The diagram only shows the contact portion to the source / drain region S / D, but it may also include the contact portion to the gate electrode layer 1007 (for example, see FIG3(b)).

[0030] Afterwards, interconnect structures or metallization stacks can be fabricated on substrate 1001.

[0031] like Figure 2 As shown, a first metal layer 1015 for a first interconnect layer and a second metal layer 1115 for a first via layer in a metallization stack can be formed on the interlayer dielectric layer 1011 by deposition, for example, physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), etc. For example, the first metal layer 1015 and the second metal layer 1115 may include conductive metals such as ruthenium (Ru), molybdenum (Mo), rhodium (Rh), platinum (Pt), iridium (Ir), nickel (Ni), cobalt (Co), or chromium (Cr). According to an embodiment, the first metal layer 1015 and the second metal layer 1115 may have a certain etching selectivity relative to each other, for example, by using different materials. In one example, the first metal layer 1015 is a Ru layer, and the second metal layer 1115 is a Mo layer. The first metal layer 1015 may have a thickness for the first interconnect layer, for example, about 5nm-100nm; the second metal layer 1115 may have a thickness for the first via layer, for example, about 5nm-100nm.

[0032] According to embodiments of this disclosure, a Ru source can be purified to obtain high-purity Ru metal. An ozone (O3) gas stream can be introduced into one or more reaction chambers to contact the Ru source, thereby forming gaseous ruthenium tetroxide (RuO4) under reaction conditions. The ruthenium tetroxide, along with unreacted ozone and gas stream residue, can be fed into a collection chamber where the gaseous ruthenium tetroxide can be reduced to a ruthenium dioxide (RuO2) layer on a semiconductor substrate. The deposited ruthenium dioxide can then be reduced using, for example, hydrogen, to produce high-purity Ru metal. Alternatively, ozone can be used as an etching gas to etch and pattern the deposited Ru metal layer.

[0033] like Figures 3(a) to 3(c) As shown, the first metal layer 1015 and the second metal layer 1115 can be patterned into a series of metal lines. Patterning can be performed using photolithography, such as barrier pattern transfer lithography or extreme ultraviolet (EUV) lithography. In photolithography, reactive ion etching (RIE) can be used, and the RIE can stop at the interlayer dielectric layer 1011 (or its contact portion 1013) below the first metal layer 1015. The spacing between the metal lines can define the spacing between interconnects in the first interconnect layer, for example, approximately 5 nm to 150 nm. Furthermore, to avoid excessive fluctuations in pattern density between different regions within the same layer, dummy metal lines can be formed, thereby arranging the metal lines, for example, at approximately uniform spacing. The linewidth of the metal lines can define the linewidth of the interconnects in the first interconnect layer, for example, approximately 5 nm to 100 nm. Additionally, at least a portion of the metal lines can contact and be electrically connected to the underlying contact portion 1013.

[0034] In this example, the formed metal wire extends substantially parallel to a first direction (the horizontal direction on the paper in FIG. 3(a)) and can be coupled with a subsequently formed metal wire extending in a second direction that intersects (e.g., is perpendicular to) the first direction to achieve various interconnect routes. However, this disclosure is not limited thereto. For example, different metal wires may extend in different directions, and the same metal wire may extend in a zigzag pattern.

[0035] like Figure 4(a) and 4(b) As shown, another interlayer dielectric layer can be formed on the interlayer dielectric layer 1011 to fill the gap between the metal lines 1015 and 1115. This other interlayer dielectric layer may include a dielectric material such as silicon oxide, silicon carbide, or other low-k dielectric materials. Here, this other interlayer dielectric layer and the previous interlayer dielectric layer 1011 may include the same material and can therefore be integrally shown as 1011, with the possible boundaries between them schematically shown by dashed lines. Of course, they may also include different materials.

[0036] This additional interlayer dielectric layer can be formed by depositing (e.g., CVD or ALD) a dielectric material to cover metal lines 1015 and 1115, followed by etching back or planarizing (e.g., chemical mechanical polishing (CMP)) the deposited dielectric material and stopping at the top surface of metal line 1115. The etching back can be performed using atomic layer etching (ALE) to achieve good process control.

[0037] exist Figure 4(a) and 4(b) In the example shown, the deposited dielectric material completely fills the gap between metal lines 1015 and 1115. However, this disclosure is not limited thereto. Figure 5(a) and 5(b) As shown, due to the small gaps between the metal lines 1015, air gaps or holes 1017 can be formed between the metal lines 1015 during the deposition of dielectric materials, for example, when using a CVD process. These air gaps or holes 1017 help reduce the capacitance between the metal lines.

[0038] According to embodiments of this disclosure, the position of the air gap or pore 1017 in the vertical direction can be adjusted by modifying the deposition process.

[0039] For example, as shown in Figure 6(a), a dielectric material can be deposited into the gap between metal lines 1015 and 1115 until the dielectric material closes the top of the gap. During the deposition process, multiple layers (of the same or different materials) can be used. In this case, the resulting air gap or pore 1017a can be located approximately at the center of the gap in the vertical direction.

[0040] Alternatively, as shown in Figure 6(b), dielectric material can be deposited into the gap between metal lines 1015 and 1115 without closing the top of the gap. Then, the deposited dielectric material can be selectively etched, such as by re-etching (RIE), leaving a portion at the bottom of the gap, thereby increasing the opening in the dielectric material. Next, dielectric material deposition can continue until the dielectric material closes the top of the gap. The dielectric materials deposited in the two depositions can be the same or different. Of course, this deposition-etching-deposition process can be repeated multiple times. In this case, the resulting air gap or hole 1017b can be located in the lower part of the gap in the vertical direction.

[0041] Alternatively, as shown in Figure 6(c), dielectric material can be deposited into the gaps between the metal lines 1015 until the dielectric material completely fills the gaps. Then, the deposited dielectric material can be selectively etched, such as with RIE, leaving a portion at the bottom of the gap. Next, dielectric material deposition can continue until the dielectric material closes the top of the gap. The dielectric materials deposited in the two depositions can be the same or different. Of course, this deposition-etching-deposition process can be repeated multiple times. In this case, the resulting air gap or hole 1017c can be located at the upper part of the gap in the vertical direction.

[0042] As described above, by alternating between deposition and etching, the position of the air gap or hole between the metal lines can be adjusted up and down.

[0043] Currently, the pattern of the second metal layer used for the first via layer is the same as the pattern of the first metal layer used for the first interconnect layer (i.e., the metal line pattern described above). The second metal layer used for the first via layer (currently in the form of metal lines) can be further patterned to form a via pattern.

[0044] like Figure 7 As shown, photoresist 1019 can be formed on the interlayer dielectric layer 1011 and the metal line 1115, and the photoresist 1019 can be patterned (e.g., by exposure and development) to cover the area where the via will be formed, while exposing the remaining area.

[0045] Here, the width W1 of the photoresist 1019 (thus defining the width of the via in the first via layer) (a scale in the longitudinal extension direction of the metal line, in this example, ...) Figure 7 The horizontal dimension within the paper can be relatively large so that the interconnects in the second interconnect layer formed on top of it can better land on the vias and thus make better contact with them.

[0046] like Figures 8(a) to 8(c) As shown, photoresist 1019 can be used as an etching mask to selectively etch metal lines 1115, such as through-etches (RIEs), to form vias. According to an embodiment, the etching of metal lines 1115 can be selective relative to metal lines 1015, thus stopping at the top surface of metal lines 1015. Of course, this disclosure is not limited to this; endpoint detection can also be used to determine whether etching has reached the top surface of metal lines 1015. In this way, metal lines 1115 can be formed into some discrete patterns (vias in the first via layer can be formed, see the top view of FIG8(a)). Afterwards, photoresist 1019 can be removed.

[0047] Since vias are obtained from lines formed by photolithography, the minimum spacing between vias can be limited by (e.g., equal to) the minimum line spacing achievable by the photolithography process. However, typically, the minimum spacing between vias formed by photolithography is greater than the minimum line spacing.

[0048] Additionally, the metal lines 1015 used for the first interconnect layer currently extend continuously. They can be separated into multiple sections depending on the design layout.

[0049] like Figure 9 As shown, photoresist 1021 can be formed on the interlayer dielectric layer 1011 and metal lines 1015, 1115, and the photoresist 1021 can be patterned to cover the areas where interconnects exist in the pattern of the first interconnect layer, while exposing the areas where interconnects do not exist in the pattern of the first interconnect layer.

[0050] like Figures 10(a) to 10(d) As shown, photoresist 1021 can be used as an etching mask to selectively etch metal lines 1015, such as through re-etching (RIE). Here, the etching of metal lines 1015 can stop at the underlying interlayer dielectric layer 1011 to cut the metal lines 1015. Thus, in the first interconnect layer, metal lines 1015 can form several separate metal segments, resulting in corresponding interconnects. Afterwards, photoresist 1021 can be removed.

[0051] In the example above, the vias in the first via layer are patterned first (etching of metal line 1115), and then the interconnects in the first interconnect layer are patterned (etching of metal line 1015). This is advantageous because the etching depth of each etching process is reduced. However, this disclosure is not limited thereto. For example, the order of these two patterning processes can be interchanged.

[0052] As shown in Figure 10(b), metal lines 1015 extend on the interlayer dielectric layer 1011 to form interconnects; metal lines 1115 are patterned as localized patterns on the interconnects to form vias. Since metal lines 1015 and 1115 can be formed using the same photolithography process (and then undergo further cutting processes to form interconnects and vias respectively), interconnects 1015 and vias 1115 can be self-aligned with each other.

[0053] Furthermore, as shown by the dashed line in via 1115 on the far right of Figure 10(b), the metal trace thickness between adjacent vias on the same interconnect does not need to be reduced, provided it does not cause incorrect electrical connections between upper-layer interconnects. That is, the width of adjacent vias is increased to connect them as a single unit. This reduces connection resistance.

[0054] Additionally, as shown in Figure 10(b), in the longitudinal extension direction of interconnect 1015 (the horizontal direction within the plane of the paper in Figure 10(b)), via 1115 can be located within a local region of the interconnect, for example, the sidewall of the via is recessed relative to the corresponding sidewall of the interconnect. Furthermore, as... Figure 10(c) and 10(d) As shown, in a cross-section perpendicular to the longitudinal extension direction of interconnect 1015, the sidewall of via 1115 and the corresponding sidewall of interconnect can be substantially coplanar.

[0055] Due to the etching of metal lines 1015 and 1115, voids were formed in the interlayer dielectric layer 1011. For example... Figures 11(a) to 11(d) As shown, these gaps can be filled using a dielectric material. This can be done by deposition followed by etching back or planarization as described above. The deposited dielectric material can be the same as or different from the preceding interlayer dielectric layer 1011. Here, the deposited dielectric material and the preceding interlayer dielectric layer are still shown integrally as 1011, and the possible boundaries between them are schematically shown by dashed lines. According to other embodiments, a thin layer can be formed, for example, by deposition, before depositing the dielectric material for purposes such as diffusion barrier, protection, or etching stop.

[0056] Similarly, as mentioned above, due to the small gaps to be filled, air gaps or pores 1023 may be formed during the deposition of dielectric materials, such as... Figures 12(a) to 12(c) As shown. The air gap or hole 1023 can vary depending on the shape of the corresponding gap. In addition, as mentioned above, the position of the air gap or hole 1023 in the vertical direction can be adjusted by adjusting the deposition process.

[0057] in addition, Figure 13(a) and 13(b) This illustrates the case where air gaps or voids are formed when the gap in the interlayer dielectric layer is filled twice. That is, in... Figure 13(a) and 13(b) The example shown combines the air gap or hole 1017 and air gap or hole 1023 described above.

[0058] The above process forms the first interconnect layer and the first via layer. Next, the upper interconnect layers and via layers in the metallization stack can be formed in the same manner.

[0059] However, this disclosure is not limited thereto. Hereinafter, a manufacturing method according to another embodiment of this disclosure will be described in conjunction with the second interconnect layer and the second via layer. The methods described below can be used alone or in combination with the methods described above.

[0060] like Figures 14(a) to 14(d) As shown in the above combination Figure 2The aforementioned method can form a third metal layer 1025 for the second interconnect layer in the metallization stack and a fourth metal layer 1125 for the second via layer in the metallization stack. The third metal layer 1025 and the fourth metal layer 1125 may comprise the same or different metallic materials as the first metal layer 1015 and the second metal layer 1115. For example, the third metal layer 1025 may comprise the same material as the first metal layer 1015, such as Ru, and the fourth metal layer 1125 may comprise the same material as the second metal layer 1115, such as Mo. Similarly, the third metal layer 1025 may have a thickness for the second interconnect layer, for example, about 5 nm to 100 nm; and the fourth metal layer 1125 may have a thickness for the second via layer, for example, about 5 nm to 100 nm.

[0061] Then, as described above... Figures 3(a) to 3(c) The third metal layer 1025 and the fourth metal layer 1125 can be patterned as a series of metal lines. In this example, instead of patterning the third metal layer 1025 and the fourth metal layer 1125 as continuously extending metal lines, the third metal layer 1025 and the fourth metal layer 1125 can be directly patterned according to the pattern of the second interconnect layer. Thus, the third metal layer 1025 and the fourth metal layer 1125 can be patterned as a series of metal line segments. That is, here, the above is combined... Figure 9 and Figures 10(a) to 10(d) The aforementioned metal wire cutting process is integrated with the metal layer structure. Figure 1 This process can be performed simultaneously, eliminating the need for a separate photolithography cutoff process. Furthermore, due to this patterning method, the metal segments are not limited to straight lines but can include zigzag segments. Thus, the metal segments 1025 form the interconnects in the second interconnect layer.

[0062] Furthermore, during the etching of the third metal layer 1025 and the fourth metal layer 1125, over-etching of the underlying via 1115 can occur. Thus, as shown in FIG14(b), the upper width of the via 1115 in the first via layer can be reduced, and is approximately the same as the linewidth of the metal segment 1025 formed above. Additionally, as shown in FIG14(b), the linewidth W2 of the metal segment 1025 (the horizontal dimension in the plane of the paper in FIG14(b)) can be relatively small, smaller than the width W1 (the horizontal dimension in the plane of the paper in FIG14(b)) of the via in the first via layer (ignoring its upper portion, whose width may be reduced due to the aforementioned over-etching). This allows the metal segment 1025 (which subsequently forms the interconnect in the second interconnect layer) to better land on the via and thus make better contact with it.

[0063] Another interlayer dielectric layer can be formed on the interlayer dielectric layer 1011 to fill the gap between the metal segments 1025 and 1125. The other interlayer dielectric layer may include a dielectric material such as silicon oxide, silicon carbide, or other low-k dielectric materials.

[0064] The other interlayer dielectric layer is formed as described below.

[0065] As shown in Figure 15(a), dielectric material can be deposited (e.g., CVD or ALD) to cover metal segments 1025, 1125. Here, the deposited dielectric material and the preceding interlayer dielectric layer 1011 may include the same material and can therefore be integrally shown as 1011, with the possible boundaries between them schematically shown by dashed lines. Of course, they may also include different materials.

[0066] Alternatively, as described above and shown in Figure 15(b), during the deposition of the dielectric material, air gaps or voids 1027 can be formed between the metal segments 1025 and 1125. In this example, because the metal segments have a pattern of a second interconnect layer, the density of the metal segments can be lower in some regions, or the gaps between the metal segments may be larger. In these regions, it is difficult to form air gaps or voids.

[0067] Then, as Figure 16 As shown, the dielectric material deposited by CMP can be etched back or planarized and stopped at the top surface of metal segment 1125. ALE (Alternating Layer Etching) can be used for good process control.

[0068] Then, you can combine the above steps. Figure 7 and 8(a) The process described in 8(c) involves forming vias in the second via layer using metal segment 1125. Then, the process can be performed according to the above combination. Figures 11(a) to 11(d) The described process utilizes a dielectric material to fill the voids in the interlayer dielectric layer 1011. This forms a second interconnect layer and a second via layer.

[0069] Figures 17 to 24(d) The illustration schematically shows some stages in the process of manufacturing a metallized stack according to another embodiment of the present disclosure. Hereinafter, the description will primarily focus on the stages in conjunction with the above. Figures 1 to 16 The differences between the described embodiments.

[0070] like Figure 17 As shown, a first metal layer 1015 for a first interconnect layer in a metallization stack and a second metal layer 1215 for a first via layer in a metallization stack can be formed on the interlayer dielectric layer 1011, as referenced above. Figure 2The first metal layer 1015 and the second metal layer 1215 may include the same material, such as Ru, or they may include different materials as in the above embodiments. The difference from the above embodiments is that a spacer layer 1201 may be additionally deposited between the first metal layer 1015 and the second metal layer 1215, for example. For example, the spacer layer 1201 may serve as a diffusion barrier layer or an etching stop layer between the first metal layer 1015 and the second metal layer 1215. For example, the spacer layer 1201 may include conductive metal silicides such as NiSi, NiPtSi, CoSi, etc., or conductive metal nitrides such as TiN, TaN, etc., or metals such as Ti, Pt, etc., with a thickness of approximately 1 nm to 10 nm.

[0071] like Figures 18(a) to 18(c) As shown, the first metal layer 1015, the spacer layer 1201, and the second metal layer 1215 can be patterned into a series of linear patterns, as referenced above. Figures 3(a) to 3(c) As stated above.

[0072] like Figure 19(a) and 19(b) As shown, another interlayer dielectric layer can be formed on the interlayer dielectric layer 1011 to fill the gaps between the linear patterns, as referenced above. Figure 4(a) and 4(b) As described above. Similarly, air gaps or pores 1017 may be formed, such as... Figure 20(a) and 20(b) As shown.

[0073] like Figure 21 as well as Figures 22(a) to 22(c) As shown, photoresist 1019 can be formed, and the second metal layer 1215 can be selectively etched, such as RIE, to pattern it as vias, as referenced above. Figure 7 as well as Figures 8(a) to 8(c) The etching can be stopped at spacer layer 1201.

[0074] like Figure 23 as well as Figures 24(a) to 24(d) As shown, photoresist 1021 can be formed, and selective etching, such as RIE, can be performed on the spacer layer 1201 and the first metal layer 1015 to form interconnects, as referenced above. Figure 9 as well as Figures 10(a) to 10(d) As described. Figures 24(a) to 24(d) As shown, the spacer layer 1201 (e.g., used as a diffusion barrier layer) may extend only on the bottom surface of the via 1215 or the bottom surface of the interconnect 1015, without extending to the sidewall of the via 1215, which is different from the diffusion barrier layer formed by conventional processes.

[0075] In addition, in the above references Figures 14(a) to 16In the described process, a spacer layer may also be incorporated between the third and fourth metal layers. Regarding the spacer layer, it can be used as an etching stop layer when patterning the fourth metal layer, and the spacer layer itself can be patterned together with the third metal layer. Other aspects are the same as in the embodiments described above.

[0076] The metallized stack according to embodiments of this disclosure can be applied to various electronic devices. Therefore, this disclosure also provides an electronic device including the aforementioned metallized stack. The electronic device may further include components such as a display screen and a wireless transceiver. Examples of such electronic devices include smartphones, computers, tablet computers (PCs), wearable smart devices, and power banks.

[0077] According to embodiments of this disclosure, a method for manufacturing a system-on-a-chip (SoC) is also provided. This method may include the methods described above. Specifically, multiple devices may be integrated on the chip, at least some of which are manufactured according to the methods of this disclosure.

[0078] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.

[0079] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

1. A metallization stack comprising at least one interconnect layer and at least one via layer alternately disposed on a substrate, wherein at least one pair of adjacent interconnect layers and via layers in the metallization stack comprises: The interconnects in the interconnect layer; as well as The vias in the via layer The via layer is closer to the substrate than the interconnect layer. In this embodiment, at least a portion of the interconnect extends longitudinally along a first direction, and the sidewall of the at least portion of the interconnect along the first direction is substantially coplanar with at least the upper portion of the corresponding sidewall of the via below the at least portion. The metallization stack further includes: Another interconnect layer closer to the substrate and adjacent to the via layer, wherein at least a portion of another interconnect in the other interconnect layer extends longitudinally along a second direction intersecting the first direction below the via, and the portion of the other interconnect along the second direction is substantially coplanar with the lower portion of the corresponding sidewall of the via. Wherein, the width of the upper part of the via in the second direction is smaller than the width of the lower part of the via in the second direction.

2. The metallization stack according to claim 1, further comprising: A first dielectric layer is filled between the vias in the via layer, and a portion of the sidewalls of the first dielectric layer is self-aligned with the sidewalls of the corresponding interconnects in the other interconnect layer.

3. The metallization stack according to claim 2, further comprising: A second dielectric layer is filled between interconnects in the other interconnect layer, the second dielectric layer further extending into a portion of the space between vias in the via layer, the first dielectric layer filling the remaining space between vias in the via layer, and the portion of the sidewall of the first dielectric layer being the interface between the first dielectric layer and the second dielectric layer.

4. The metallization stack according to claim 1, wherein, The interconnects and the vias are made of different materials.

5. The metallization stack according to claim 1, wherein, The interconnects and vias comprise metal and are in direct contact with the surrounding dielectric layer.

6. The metallization stack according to claim 5, wherein, The metals include ruthenium (Ru), molybdenum (Mo), rhodium (Rh), platinum (Pt), iridium (Ir), nickel (Ni), cobalt (Co), or chromium (Cr).

7. The metallization stack according to claim 1, wherein, In a cross-section perpendicular to the first direction, at least a portion of the interconnect and the upper portion of the via have a tapering shape from bottom to top, and the lower portion of the via has a tapering shape from bottom to top.

8. The metallization stack according to claim 1, wherein, The minimum spacing between vias is limited by the minimum line spacing achievable by the photolithography process.

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