Semiconductor structure and method of manufacturing the same

Abstract

The application relates to a semiconductor structure and a preparation method thereof. The semiconductor structure comprises a substrate, a semiconductor substrate, a first groove extending along a first direction on the semiconductor substrate, a second groove extending along a second direction on the semiconductor substrate, the first groove and the second groove intersecting to form a plurality of semiconductor columns on the semiconductor substrate, the second groove being filled with a first dielectric layer, the semiconductor column top being provided with a second dielectric layer, and the first groove sidewall being provided with a third dielectric layer; an isolation layer being located in the semiconductor substrate below the first groove and extending along the second direction; and a bit line being located on the isolation layer and extending along the second direction, the bit line being connected to the semiconductor column bottom. The application can effectively reduce the leakage between the bit line and the substrate.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor structure and its fabrication method. Background Technology

[0002] With the development of semiconductor technology, Gate-All-Around (GAA) technology has emerged. This technology is characterized by the gate completely surrounding the channel on all four sides, thus enabling stronger control over the channel. Gate-All-Around transistors include Vertical Gate-All-Around (VGAA) transistors, where the channel is perpendicular to the substrate.

[0003] Traditional VGAA has its bit lines fabricated directly on the substrate surface, which can easily lead to leakage between the bit lines and the substrate. Summary of the Invention

[0004] This application provides a semiconductor structure and its fabrication method to reduce leakage current between bit lines and the substrate.

[0005] A semiconductor structure, comprising:

[0006] The substrate includes a semiconductor substrate having a first trench extending in a first direction and a second trench extending in a second direction, the first trench and the second trench intersecting to form a plurality of semiconductor pillars on the semiconductor substrate, the second trench being filled with a first dielectric layer, the top of the semiconductor pillar having a second dielectric layer, and the sidewalls of the first trench having a third dielectric layer.

[0007] An isolation layer is located within the semiconductor substrate below the first trench and extends along the second direction;

[0008] Bit lines are located on the isolation layer and extend along a second direction, the bit lines being connected to the bottom of the semiconductor pillars.

[0009] In one embodiment, the isolation layer is beak-shaped in the portion opposite to the semiconductor pillar.

[0010] In one embodiment, the isolation layer is continuous in the second direction.

[0011] In one embodiment, a metal silicide is present between the semiconductor pillar and the bit line, and the first trench is filled with an insulating layer.

[0012] A method for fabricating a semiconductor structure, comprising:

[0013] A substrate is provided, the substrate including a semiconductor substrate having a first trench extending in a first direction and a second trench extending in a second direction, the first trench and the second trench intersecting to form a plurality of semiconductor pillars on the semiconductor substrate, the second trench being filled with a first dielectric layer, the top of the semiconductor pillar having a second dielectric layer, and the sidewalls of the first trench having a third dielectric layer.

[0014] An isolation layer extending along the second direction is formed within the semiconductor substrate below the first trench;

[0015] A bit line extending in a second direction is formed on the isolation layer, and the bit line is connected to the bottom of the semiconductor pillar.

[0016] In one embodiment, before forming an isolation layer extending in the second direction within the semiconductor substrate below the first trench, the process includes:

[0017] The semiconductor substrate beneath the first trench is etched to isolate the semiconductor pillar.

[0018] In one embodiment, etching the semiconductor substrate beneath the first trench to isolate the semiconductor pillar includes:

[0019] An etch barrier layer extending in a second direction is formed below the first trench. The etch barrier layer is located inside the semiconductor substrate and is spaced apart from the first trench.

[0020] The semiconductor substrate beneath the first trench is etched using the etch barrier layer to isolate the semiconductor pillar.

[0021] In one embodiment, an etch barrier layer extending in a second direction is formed below the first trench, comprising:

[0022] Ion implantation is performed on the semiconductor substrate to form the etching barrier layer.

[0023] In one embodiment, an isolation layer extending along the second direction is formed within the semiconductor substrate below the first trench, comprising:

[0024] A sacrificial layer is formed on the bottom surface of the semiconductor pillar and on the opposite surface of the etch barrier layer and / or a portion of the surface of the semiconductor substrate;

[0025] Thermal oxidation is performed on the etch barrier layer and / or the semiconductor substrate exposed by the sacrificial layer to form the isolation layer, wherein the isolation layer is beak-shaped at the portion opposite to the semiconductor pillar;

[0026] Before forming a bit line extending in the second direction on the surface of the isolation layer, the method further includes:

[0027] Remove the sacrificial layer.

[0028] In one embodiment, an isolation layer extending along the second direction is formed within the semiconductor substrate below the first trench, comprising:

[0029] An isolation material layer is filled in the first trench and the region between the semiconductor pillar and the semiconductor substrate;

[0030] The isolation material layer is etched back to the bottom of the semiconductor pillar;

[0031] A supplementary medium layer is formed again on the sidewall of the first trench;

[0032] Continue etching back the isolation material layer to form the isolation layer on the etch barrier layer and / or the semiconductor substrate.

[0033] In one embodiment, an isolation layer extending along the second direction is formed within the semiconductor substrate below the first trench, comprising:

[0034] An isolation material layer is filled in the first trench and the region between the semiconductor pillar and the semiconductor substrate;

[0035] The isolation material layer is etched back to form the isolation layer on the etch barrier layer and / or the semiconductor substrate.

[0036] In one embodiment, etching the semiconductor substrate beneath the first trench to isolate the semiconductor pillar includes:

[0037] An etching barrier layer extending in a second direction is formed below the first trench, and the etching barrier layer is spaced apart from the first trench.

[0038] The semiconductor substrate at the bottom of the first trench is etched to form a third trench, wherein the third trench is spaced apart from the etch barrier layer;

[0039] A fourth dielectric layer is formed on the sidewalls of the first trench and the third trench;

[0040] The semiconductor substrate below the third trench is etched based on the etch barrier layer to isolate the semiconductor pillar;

[0041] The formation of an isolation layer extending along the second direction within the semiconductor substrate below the first trench includes:

[0042] The isolation layer is formed between the semiconductor substrate and the semiconductor pillar below the third trench.

[0043] In one embodiment, after forming the isolation layer between the semiconductor substrate and the semiconductor pillar below the third trench, and before forming a bit line extending in the second direction on the surface of the isolation layer, the process includes:

[0044] Remove the fourth dielectric layer;

[0045] The semiconductor substrate beneath the first trench is etched to further isolate the semiconductor pillar.

[0046] In one embodiment, before etching the semiconductor substrate below the first trench to separate the semiconductor pillars, the process includes:

[0047] The semiconductor substrate below the first trench is doped to form an ion-doped layer extending along a second direction, the ion-doped layer being connected to the semiconductor pillar.

[0048] In one embodiment, after forming a bit line extending in the second direction on the surface of the isolation layer, the method further includes:

[0049] The bit line is heat-treated to form a metal silicide between the bit line and the semiconductor pillar;

[0050] An insulating layer is filled into the first trench.

[0051] In one embodiment, before forming a bit line extending in the second direction on the surface of the isolation layer, the method further includes:

[0052] A metal material layer is formed between the surface of the isolation layer and the bottom of the semiconductor pillar;

[0053] The metal material layer is heat-treated to form a metal silicide at the bottom of the semiconductor pillar;

[0054] Remove the layer of metal material that did not participate in the reaction.

[0055] In one embodiment, after filling the first trench with an insulating layer, the method further includes:

[0056] Forming a transistor structure,

[0057] The aforementioned semiconductor structure and its fabrication method form an isolation layer extending along a second direction within the semiconductor substrate below the first trench. Bit lines are formed on the isolation layer, thereby blocking the current path between the bit lines and the bottom of the semiconductor substrate, effectively reducing leakage current between the bit lines and the semiconductor substrate. Attached Figure Description

[0058] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0059] Figure 1 This is a flowchart of a method for fabricating a semiconductor structure provided in one embodiment;

[0060] Figures 2-16 This is a schematic diagram of the fabrication process of the semiconductor structure provided in one embodiment, wherein, Figure 6 The first image is a top-view structural diagram; the others are cross-sectional structural diagrams taken along the directions aa', bb', cc', and dd', respectively.

[0061] Figures 17-21 This is a cross-sectional structural diagram of the semiconductor structure fabrication process provided in another embodiment;

[0062] Figures 22-28 This is a schematic cross-sectional view of the semiconductor structure fabrication process provided in another embodiment;

[0063] Figure 29 This is a schematic diagram of the cross-sectional structure after the formation of an ion-doped layer during the fabrication process of the semiconductor structure provided in another embodiment.

[0064] Explanation of reference numerals in the attached figures: 100-substrate, 110-semiconductor substrate, 110a-first trench, 110b-second trench, 111-semiconductor pillar, 120-second dielectric layer, 130-third dielectric layer, 140-first dielectric layer, 200-isolation layer, 300-bit line, 301-bit line material layer, 401-mask material layer, 500-etch stop layer, 600-sacrificial layer, 700-supplementary dielectric layer, 800-fourth dielectric layer, 900-ion doped layer, 10-metal silicide, 20-insulating layer. Detailed Implementation

[0065] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0066] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0067] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, parts, regions, layers, doping types, and / or portions, these elements, parts, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, part, region, layer, doping type, or portion from another element, part, region, layer, doping type, or portion. Therefore, without departing from the teachings of this application, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0068] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0069] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, in this specification, the term “and / or” includes any and all combinations of the associated listed items.

[0070] In one embodiment, see Figure 1 This application provides a method for fabricating a semiconductor structure, comprising the following steps:

[0071] For step S200, please refer to... Figure 6 as well as Figure 7 A substrate 100 is provided, the substrate 100 including a semiconductor substrate 110, the semiconductor substrate 110 having a first trench 110a extending in a first direction and a second trench 110b extending in a second direction, the first trench 110a and the second trench 110b intersecting to form a plurality of semiconductor pillars 111 on the semiconductor substrate 110, the second trench 110b being filled with a first dielectric layer 140, the top of the semiconductor pillars 111 having a second dielectric layer 120, and the sidewalls of the first trench having a third dielectric layer 130;

[0072] For step S400, please refer to... Figure 11 An isolation layer 200 extending in the second direction is formed in the semiconductor substrate 110 below the first trench 110a.

[0073] For step S600, please refer to... Figure 15 A bit line 300 extending in a second direction is formed on the isolation layer 200, and the bit line 300 is connected to the bottom of the semiconductor pillar 111.

[0074] In step S200, the formation process of substrate 100 may include:

[0075] Step S210: Provide a semiconductor substrate 110. The material of the semiconductor substrate 110 may include silicon, germanium, germanium-silicon, etc.

[0076] For step S220, please refer to... Figure 2 The semiconductor substrate 110 is etched to form a plurality of second trenches 110b extending along a second direction. As an example, the plurality of second trenches 110b can be arranged in a row in parallel and at equal intervals, and bit lines BL on both sides of the second trenches 110b are used to form transistor structures.

[0077] For step S230, please refer to... Figure 3The first dielectric layer 140 is filled within the second communication 110b. The material of the first dielectric layer 140 may be, but is not limited to, any one or more of silicon dioxide, silicon nitride, and silicon oxynitride.

[0078] For step S240, please refer to... Figure 4 A mask material layer 401 is formed on the surface of the semiconductor substrate 110 after the second trench 110b is formed, and on the surface of the first dielectric layer 140. The mask material layer 401 may include a single-layer material film or a multi-layer material film. As an example, when the mask material layer 401 includes a multi-layer film, it may include an oxide material layer, an amorphous carbon material layer, a first silicon oxynitride (SIOH) material layer, a spin-on hard mask (SOH) material layer, and a second silicon oxynitride (SIOH) material layer formed in sequence.

[0079] Step S250: The mask material layer 401 is patterned to form a mask layer (not shown).

[0080] For step S260, please refer to... Figure 5 Based on the mask layer, the semiconductor substrate 110 is etched to form a plurality of first trenches 110a extending along a first direction. As an example, the plurality of first trenches 110a can be arranged in a row in parallel and at equal intervals. The trench depth of the first trenches 110a can be less than the trench depth of the second trenches 110b. Word lines WL for forming transistor structures are formed on both sides of the first trenches 110a.

[0081] Here, when the mask material layer 401 comprises multiple material film layers, the resulting mask layer also comprises multiple film layers after patterning each material film layer. At this time, after forming the first trench 110a, the bottommost patterned material film layer (such as a patterned oxide material layer) can be retained as the second dielectric layer 120. Simultaneously, the other film layers of the mask layer can be removed. Of course, the formation method of the second dielectric layer 120 is not limited to this. For example, in step S230, filling the second trench 110b with the first dielectric layer 140 can include forming an insulating material layer on the second trench 110b and the surface of the semiconductor substrate 110. Then, the first dielectric layer 140 is planarized. The remaining surface of the first dielectric layer 140 is higher than the surface of the semiconductor substrate 110. The insulating material layer located within the second trench 110b constitutes the first dielectric layer 140, while the portion higher than the surface of the semiconductor substrate 110 can be etched in step S260 to form the second dielectric layer 120. The material of the second dielectric layer 120 may include, but is not limited to, any one or more of silicon dioxide, silicon nitride, and silicon oxynitride.

[0082] For step S270, please refer to... Figure 7 A third dielectric layer 130 is formed on the sidewall of the first trench 110a. The material of the third dielectric layer 130 may be, but is not limited to, any one or more of silicon dioxide, silicon nitride, and silicon oxynitride.

[0083] The first trench 110a and the second trench 110b intersect to form a plurality of semiconductor pillars 111 on the semiconductor substrate 110. The top and bottom of the semiconductor pillars 111 are heavily doped to form source and drain regions, respectively. The portion between the source and drain regions can be completely surrounded by the gate in subsequent portions, thereby forming a conductive channel.

[0084] In step S400, please refer to Figure 12 An isolation layer 200 is formed within the semiconductor substrate 110. Specifically, multiple parallel isolation layers 200 can be formed within the semiconductor substrate 110. Furthermore, both the isolation layer 200 and the second trench 110b extend along the second direction, and they are arranged alternately.

[0085] The material of the isolation layer 200 may be, but is not limited to, any one or more of silicon dioxide, silicon nitride, silicon oxynitride, etc.

[0086] In step S600, please refer to Figure 15 Bit line 300 is connected to the bottom of semiconductor pillar 111, thereby providing voltage to the source or drain region formed at the bottom of semiconductor pillar 111. It is understood that bit line 300 is connected to semiconductor pillar 111, which can be a direct connection or a connection through an intermediate layer (such as metal silicide 10), and there is no limitation in this regard.

[0087] Bit lines 300 are formed on isolation layers 200. Multiple bit lines are formed on multiple isolation layers 200, and thus the bit lines are also arranged alternately with the second trench 110b.

[0088] The material of bit line 300 may include, but is not limited to, metals such as Mo, Co, W, and Ti.

[0089] In this embodiment, bit line 300 is formed on isolation layer 200, thereby blocking the current path between bit line 300 and bottom of semiconductor substrate 110, thereby effectively reducing leakage current between bit line 300 and semiconductor substrate 110.

[0090] In one embodiment, the method further includes the following steps prior to step S400:

[0091] For step S300, please refer to... Figure 9 The semiconductor substrate 110 below the first trench 110a is etched to isolate the semiconductor pillar 111.

[0092] By isolating the semiconductor pillar 111, a gap is formed between the semiconductor pillar 111 and the semiconductor substrate 110 below it. This facilitates the subsequent formation of the isolation layer 200 and the bit line 300 between the semiconductor pillar 111 and the semiconductor substrate 110 below it.

[0093] In one embodiment, step S300 includes:

[0094] Step S311, please refer to Figure 8 An etch barrier layer 500 extending in a second direction is formed below the first trench 100a. The etch barrier layer 500 is located inside the semiconductor substrate 110 and is spaced apart from the first trench 110a.

[0095] For step S312, please refer to... Figure 9 The semiconductor substrate 110 below the first trench 110a is etched based on the etch barrier layer 500 to isolate the semiconductor pillar 111.

[0096] In step S311, please refer to Figure 8 The bottom of the etching barrier layer 500 can be higher than the bottom of the second trench 110b, so that the etching barrier layer 500 will not be formed at the location of the second trench 110b. Therefore, the etching barrier layer 500 can also extend along the second direction and be alternated with the second trench 110b.

[0097] The etch barrier layer 500 is spaced from the first trench 110a, thereby allowing etching of the semiconductor substrate 110 between them.

[0098] In step S312, please refer to Figure 9 When etching is performed based on the etch barrier layer 500, the vertical etching stops on the etch barrier layer 500, while the horizontal etching will isolate the semiconductor pillar 111.

[0099] As an example, an etching solution or etching gas can be introduced into the first trench 110a. At this time, since the second trench 110b has a first dielectric layer 140, the top of the semiconductor pillar 111 has a second dielectric layer 120, and the sidewalls of the first trench 110a have a third dielectric layer 130, etching begins from the semiconductor substrate 110a leaking from the bottom of the first trench 110a and proceeds outwards. The semiconductor pillar 111 is etched below the first trench 110a.

[0100] Figure 9 The five figures in the dashed box are schematic diagrams of five different structures formed under different etching conditions when the semiconductor pillar 111 is etched below the first trench 110a and cross-sectioned along the aa' direction.

[0101] In this embodiment, the etching barrier layer 500 effectively isolates the semiconductor pillar 111. Of course, in some embodiments, the etching barrier layer 500 may not be provided, and there is no limitation on this.

[0102] In this embodiment, the isolation layer 200 formed in step S400 and the bit line 300 formed in step S600 can jointly fill the portion below the first trench 110a that has been etched away. After the isolation layer 200 is formed in step S400, there is still a gap between the isolation layer 200 and the semiconductor pillar 111, and the bit line 300 can fill the gap.

[0103] In one embodiment, in step S311, an etch barrier layer 500 can be formed inside the semiconductor substrate 110 by ion implantation. Specifically, the etch barrier layer 500 can be formed by implanting B ions, Be ions, Li ions, Mg ions, Ca ions, etc.

[0104] Here, after the first trench 110a is formed, ion implantation is performed on the semiconductor substrate 110 to form an etch barrier layer 500.

[0105] In other embodiments, this is not a limitation. For example, the semiconductor substrate 110 may be ion implanted to form the etch barrier layer 500 after the second trench 110 is formed and the first dielectric layer 140 is filled in the second communication 110b, but before the first trench 110a is formed. Alternatively, the semiconductor substrate 110 may be ion implanted to form the etch barrier layer 500 before any other processing is performed on it.

[0106] In one embodiment, after step S312, step S400 includes:

[0107] For step S411, please refer to... Figure 10 A sacrificial layer 600 is formed on the bottom surface of the semiconductor pillar 111 and on the opposite etch barrier layer 500 and / or a portion of the surface of the semiconductor substrate 110.

[0108] For step S412, please refer to... Figure 11 Thermal oxidation is performed on the etch barrier layer 500 and / or semiconductor substrate 110 exposed by the sacrificial layer 600 to form an isolation layer 200, wherein the isolation layer 200 is beak-shaped in the portion opposite to the semiconductor pillar 111.

[0109] Correspondingly, prior to step S600, the following steps are also included:

[0110] For step S511, please refer to... Figure 12 Remove the sacrificial layer 600.

[0111] In step S411, a sacrificial material layer (not shown) may first be formed on each surface of the structure after the semiconductor pillar 111. As an example, the sacrificial material layer may be deposited on each surface of the structure after the semiconductor pillar 111 by ALD deposition.

[0112] Then, the sacrificial material layer can be etched back. At this time, due to the shielding of the semiconductor pillar 111, the sacrificial material layer on the bottom surface of the semiconductor pillar 111, as well as the sacrificial material layer on a portion of the surface of the etch stop layer 500 and / or the semiconductor substrate 110 opposite to the semiconductor pillar 111, can be retained, thereby forming the sacrificial layer 600. The material of the sacrificial layer 600 can be, but is not limited to, any one or more of silicon dioxide, silicon nitride, silicon oxynitride, etc.

[0113] Here, it is understandable that in the actual process, during the etching of the semiconductor substrate 110 below the first trench 110a based on the etch barrier layer 500 to isolate the semiconductor pillar 111 (step S312), the etch barrier layer 500 may also be etched to a certain extent.

[0114] As an example, please refer to Figure 10 The etch barrier layer 500 can be partially etched, but it still blocks the semiconductor substrate 110 underneath. At this time, the sacrificial layer 600 is formed on the bottom surface of the semiconductor pillar 111, and also on a portion of the surface of the etch barrier layer 500 opposite to the semiconductor pillar 111.

[0115] As an example two, the etch barrier layer 500 can also be completely etched, thus fully exposing the semiconductor substrate 110 underneath. In this case, the sacrificial layer 600 is formed on the bottom surface of the semiconductor pillar 111, and also on a portion of the surface of the semiconductor substrate 110 opposite to the semiconductor pillar 111.

[0116] As an example three, if the etch barrier layer 500 is partially etched and broken, and the etch barrier layer 500 is etched away at the edge of the portion opposite to the semiconductor pillar 111, then the sacrificial layer 600 can be formed on the bottom surface of the semiconductor pillar 111, and can also be formed on the partial surface of the etch barrier layer 500 and the semiconductor substrate 110 opposite to the semiconductor pillar 111.

[0117] As an example four, the etch barrier layer 500 is partially etched and broken, but in the part of the area between the semiconductor pillars 111, the sacrificial layer 600 is formed on the bottom surface of the semiconductor pillars 111 and also on the part of the surface of the etch barrier layer 500 opposite to the semiconductor pillars 111.

[0118] In step S412, specifically, in the case of Example 1 above, the etch stop layer 500 exposed by the sacrificial layer 600 can be thermally oxidized. In the cases of Examples 2 and 3 above, the semiconductor substrate 110 exposed by the sacrificial layer 600 can be thermally oxidized. In the case of Example 4 above, both the semiconductor substrate 110 exposed by the sacrificial layer 600 and the etch stop layer 500 can be thermally oxidized simultaneously.

[0119] Simultaneously, during the thermal oxidation process, oxygen ions can diffuse within the film layer. Therefore, the isolation layer 200 can be formed not only between the semiconductor pillars 111 (i.e., where the sacrificial layer 600 is exposed), but also extended to the position opposite to the semiconductor pillars 111 (i.e., the area covered by the sacrificial layer 600). In this case, the portion of the isolation layer 200 opposite to the semiconductor pillars 111 has a beak-like shape. This facilitates the continuity of the isolation layer 200 in the second direction, thereby effectively preventing leakage current.

[0120] Of course, in some examples, the isolation layer 200 may also be discontinuous in the second direction (e.g., it may be nearly continuous but not continuous), and there is no restriction on this.

[0121] Specifically, after the isolation layer 200 is formed in step S400, there is still a gap between the isolation layer 200 and the semiconductor pillar 111.

[0122] At this time, please refer to Figure 13 or Figure 14 In step S600, the bit line material layer 301 can be filled first in the region between the first trench 110a and the isolation layer 200 and the semiconductor pillar 111. For example, the bit line material layer 301 can be filled using atomic layer deposition (ALD). The material of the bit line material layer 301 can be selected from Mo, Co, W, Ti, etc. The material filling effect of the bit line material layer 301 can vary depending on the actual process conditions. For some examples, please refer to [reference needed]. Figure 14 There are gaps in the middle of the bit line material layer 301. See other examples. Figure 13 The bit line material layer 301 can also be well filled without any intermediate gaps.

[0123] Then, please see Figure 15 The bit line material layer 301 can be etched back to form the bit line 300.

[0124] In one embodiment, step S312 (see [link]) Figure 9 After that, step S400 includes:

[0125] Step S421: Fill the first trench 110a and the region between the semiconductor pillar 111 and the semiconductor substrate 110 with an isolation material layer 201;

[0126] For step S422, please refer to... Figure 17 The isolation material layer 201 is etched back to the bottom of the semiconductor pillar 111;

[0127] For step S423, please refer to... Figure 18 A supplementary medium layer 700 is formed again on the sidewall of the first trench 110a;

[0128] For step S424, please refer to... Figure 19 Continue etching back the isolation material layer 201 to form the isolation layer 200 on the etch barrier layer 500 and / or the semiconductor substrate 110.

[0129] In step S421, the material of the isolation material layer may be, but is not limited to, any one or more of silicon dioxide, silicon nitride, silicon oxynitride, etc.

[0130] In step S422, when the material of the isolation material layer is the same as or has a smaller etching selectivity than the third dielectric layer 130 on the sidewall of the first trench 110a, the third dielectric layer 130 may also be removed while the isolation material layer is being etched back.

[0131] In step S423, the material of the supplementary dielectric layer 700 may be, but is not limited to, any one or more of silicon dioxide, silicon nitride, and silicon oxynitride. The material of the supplementary dielectric layer 700 may be selected to have a larger etching selectivity ratio than the isolation material layer. For example, when the isolation material layer is silicon nitride, the supplementary dielectric layer 700 may be selected to be silicon dioxide.

[0132] In step S424, the isolation material layer is etched back to form an isolation layer 200 spaced from the semiconductor pillar 111. The space between the two can be used to form a bit line 300.

[0133] Please see Figure 19 After the semiconductor pillar 111 is isolated, its bottom may have a sharp corner due to the manufacturing process. Sharp corners are prone to charge accumulation. This step, after etching back the isolation material layer, can also oxidize the sharp corners at the bottom of the semiconductor pillar 111 to remove them, and then remove the oxide layer formed at the sharp corners. This effectively reduces charge accumulation at the sharp corners.

[0134] As explained above, during step S312, the etch barrier layer 500 may also be etched to a certain extent. Specifically, the etch barrier layer 500 may be partially etched, but still shield the underlying semiconductor substrate 110. Alternatively, the etch barrier layer 500 may be completely etched, fully exposing the underlying semiconductor substrate 110. Or, the etch barrier layer 500 may be partially etched and broken, partially exposing the underlying semiconductor substrate 110.

[0135] Therefore, by continuing to etch back the isolation material layer, the isolation layer 200 can be formed on the etch barrier layer 500, or on the semiconductor substrate 110, or on both the etch barrier layer 500 and the semiconductor substrate 110.

[0136] In this embodiment, the isolation layer 200 is formed by etching back the isolation material layer, thereby facilitating the formation of an isolation layer 200 that is continuous along the second direction.

[0137] Meanwhile, in this embodiment, the etch-back of the isolation material layer is performed in two steps. After the first etch-back, a supplementary dielectric layer 700 is formed again on the sidewall of the first trench 110a, which effectively prevents damage to the semiconductor pillar 111 during the etch-back process of the isolation material layer.

[0138] Of course, in some embodiments, the etchback of the isolation material layer can also be performed in one step. Specifically, after step S312, step S400 includes:

[0139] Step S431: Fill the first trench 110a and the region between the semiconductor pillar 111 and the semiconductor substrate 110 with an isolation material layer (not shown);

[0140] Step S432: The isolation material layer is etched back to form an isolation layer 200 on the etch barrier layer 500 and / or the semiconductor substrate 110.

[0141] At this point, as an example, the material of the formed isolation material layer can be selected to have a larger etching selectivity ratio than the third dielectric layer 130 of the sidewall of the first trench 110a.

[0142] In one embodiment, when step S300 is included before step S400, step S300 includes:

[0143] For step S321, please refer to... Figure 22 An etching barrier layer 500 extending in the second direction is formed below the first trench 110a, and the etching barrier layer 500 is spaced apart from the first trench 110a.

[0144] Please refer to step S322. Figure 22The semiconductor substrate 110 at the bottom of the first trench 110a is etched to form a third trench 110c, and the third trench 110c is spaced apart from the etch barrier layer 500.

[0145] For step S323, please refer to [link / reference]. Figure 23 A fourth dielectric layer 800 is formed on the sidewall of the first trench 110a and the sidewall of the third trench 110c.

[0146] For step S324, please refer to [link / reference]. Figure 24 The semiconductor substrate 110 below the third trench 110c is etched based on the etch barrier layer 500 to isolate the semiconductor pillar 111.

[0147] Meanwhile, step S400 includes:

[0148] For step S441, please refer to... Figure 25 An isolation layer 200 is formed between the semiconductor substrate 110 and the semiconductor pillar 111 below the third trench.

[0149] In step S321, please refer to Figure 22 The bottom of the etching barrier layer 500 can be higher than the bottom of the second trench 110b, so that the etching barrier layer 500 will not be formed at the location of the second trench 110b. Therefore, the etching barrier layer 500 can also extend along the second direction and be alternated with the second trench 110b.

[0150] The etch barrier layer 500 can be formed by ion implantation. Here, after forming the first trench 110a, ion implantation is performed on the semiconductor substrate 110 to form the etch barrier layer 500.

[0151] In other embodiments, this is not a limitation. For example, the semiconductor substrate 110 may be ion implanted to form the etch barrier layer 500 after the second trench 110 is formed and the first dielectric layer 140 is filled in the second communication 110b, but before the first trench 110a is formed. Alternatively, the semiconductor substrate 110 may be ion implanted to form the etch barrier layer 500 before any other processing is performed on it.

[0152] In step S322, please continue reading. Figure 22 This forms a third trench 110c that connects with the first trench 110a.

[0153] In step S323, please refer to Figure 23 Since the first trench 110a has a third dielectric layer 130 on its sidewall, the fourth dielectric layer 800 is specifically located on the side surface of the third dielectric layer 130 and the sidewall of the third trench 110c.

[0154] In step S324, please refer to Figure 24 When etching is performed based on the etch barrier layer 500, the fourth dielectric layer 800 protects the semiconductor pillar 111. During etching, the vertical etching stops on the etch barrier layer 500, while the horizontal etching isolates the semiconductor pillar 111.

[0155] In step S441, please refer to Figure 25 First, an isolation material layer (not shown) can be filled into the first trench 110a, the third trench 110c, and the region between the semiconductor pillar 111 and the semiconductor substrate 110. Then, the isolation material layer is etched back to remove the isolation material layer in the first trench 110a and the third trench 110c, and the remaining isolation material layer constitutes the isolation layer 200.

[0156] In this embodiment, the isolation layer 200 fills the portion below the third trench 110c that has been etched away. This ensures the continuity of the isolation layer 200 more effectively, and eliminates the need for further etching, thus reducing the complexity of the process.

[0157] In one embodiment, after step S441 and before step S600, the method further includes:

[0158] Please refer to step S521. Figure 25 Remove the fourth dielectric layer 800;

[0159] For step S522, please refer to... Figure 26 The semiconductor substrate 110 below the first trench 110a is etched to isolate the semiconductor pillar 111 again.

[0160] In step S521, after the fourth dielectric layer 800 is removed, the semiconductor substrate 110 corresponding to the third trench is exposed.

[0161] In step S522, during etching, the third dielectric layer 130 on the sidewall of the first trench 110a protects the semiconductor pillar 111. Furthermore, during etching, longitudinal etching can stop on the isolation layer 200, while lateral etching will isolate the semiconductor pillar 111.

[0162] Figure 26 The five figures in the dashed box are schematic diagrams of five different structures formed under different etching conditions when the semiconductor pillar 111 is etched below the first trench 110a and cross-sectioned along the aa' direction.

[0163] At this time, please refer to Figure 27 The bit line 300 formed in step S600 can fill the portion below the first trench 110a that has been etched away.

[0164] In one embodiment, see Figure 29 Before step S300, the following are included:

[0165] The semiconductor substrate 110 below the first trench 110a is doped to form an ion-doped layer 900 extending along the second direction, and the ion-doped layer 900 is connected to the semiconductor pillar 111.

[0166] As an example, the ions doped in the ion-doped layer 900 can be As ions, P ions, N ions, etc. The formation of the ion-doped layer 900 can accelerate the etching rate of the semiconductor substrate 110 below the first trench 110a, thereby accelerating the separation of the semiconductor pillar 111.

[0167] Specifically, an ion-doped layer 900 can be formed below the first trench 110a by ion implantation. It is understood that the ions implanted when forming the ion-doped layer 900 are different from the ions implanted when forming the etch barrier layer 500, thereby forming films with different functions.

[0168] Of course, the formation of the ion-doped layer 900 is not limited to this. For example, it can also be formed by diffusion doping. Diffusion doping can include solid-state diffusion doping or gas diffusion doping. There are no restrictions on either method.

[0169] In one embodiment, after step S600, the method further includes:

[0170] For step S700, please refer to... Figure 15 or Figure 20 or Figure 27 The bit line 300 is heat-treated to form a metal silicide 10 between the bit line 300 and the semiconductor pillar 111.

[0171] For step S800, please refer to [link / reference]. Figure 16 or Figure 21 or Figure 28 An insulating layer 20 is filled into the first trench 110a.

[0172] In step S700, after the bit line 300 is heat-treated, it can react with the bottom of the contacting semiconductor pillar 111 to form a metal silicide. The formation of the metal silicide 10 can effectively reduce the contact resistance between the source or drain region at the bottom of the semiconductor pillar 111 and the bit line.

[0173] In step S800, the insulating layer 20 may be, but is not limited to, any one or more of silicon dioxide, silicon nitride, silicon oxynitride, etc.

[0174] In this embodiment, metal silicide 10 is formed by heat treatment of the alignment line 300, thereby simplifying the process.

[0175] Of course, the formation of metal silicide 10 is not limited to this. For example, in some embodiments, the following steps may also be performed before step S600:

[0176] Step S10: A metal material layer is formed between the surface of the isolation layer 200 and the bottom of the semiconductor pillar 111;

[0177] Step S20: Heat treatment is performed on the metal material layer to form metal silicide 10 at the bottom of semiconductor pillar 111;

[0178] Step S30: Remove the layer of metal material that did not participate in the reaction.

[0179] There are various metallic materials that can be used as bit lines, but relatively few of them can react with semiconductor pillars 111 to form metal silicides. Therefore, the metal silicide 10 and bit line 200 are formed separately, which allows for greater flexibility in the selection of bit line materials.

[0180] In one embodiment, after step 800, the method further includes:

[0181] Step S900: Forming a transistor structure.

[0182] Specifically, the third dielectric layer 130 on the sidewall of the first trench 110a can be partially removed up to the word line (gate) location. The remaining bottom third dielectric layer 130 isolates the bit line 300 from the word line. Then, gate metal filling, etch-back, etc., can be performed sequentially to form the word line. The top region of the semiconductor pillar 111 is exposed to serve as a drain region (or source region). Afterwards, a suitable material such as oxide can be filled between the drain regions (or source regions).

[0183] Of course, the specific way in which the transistor structure is formed is not limited to this. It can also be formed in other ways, as is known to those skilled in the art, and will not be elaborated on here.

[0184] It should be understood that, although Figure 1 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order in which these steps are executed, and they can be performed in other orders. Figure 1At least some of the steps in the process may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but may be executed at different times. The execution order of these steps or stages is not necessarily sequential, but may be executed in turn or alternately with other steps or at least some of the steps or stages in other steps.

[0185] In one embodiment, see Figure 16 or Figure 21 or Figure 28 The invention also provides a semiconductor structure including a substrate 100, an isolation layer 200, and a bit line 300.

[0186] The substrate 100 includes a semiconductor substrate 110. The semiconductor substrate 110 has a first trench 110a extending in a first direction and a second trench 110b extending in a second direction. The first trench 110a and the second trench 110b intersect to form a plurality of semiconductor pillars 111 on the semiconductor substrate 110. The second trench 100b is filled with a first dielectric layer 140, the top of the semiconductor pillars 111 has a second dielectric layer 120, and the sidewalls of the first trench 110a have a third dielectric layer 130.

[0187] The isolation layer 200 is located within the semiconductor substrate 110 below the first trench 110a and extends along the second direction.

[0188] Bit line 300 is located on isolation layer 200 and extends along the second direction, and bit line 200 is connected to the bottom of semiconductor pillar 111.

[0189] In one embodiment, the isolation layer 200 is beak-shaped in the portion opposite to the semiconductor pillar 111.

[0190] In one embodiment, the isolation layer 200 is continuous in the second direction.

[0191] In one embodiment, a metal silicide 10 is provided between the semiconductor pillar 111 and the bit line 300, and an insulating layer 20 is filled in the first trench 110a.

[0192] For specific limitations on semiconductor structures, please refer to the limitations on semiconductor structure fabrication methods mentioned above, which will not be elaborated further here.

[0193] In the description of this specification, the references to terms such as "one embodiment," "other embodiments," "some embodiments," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of this application. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0194] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0195] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: A substrate is provided, the substrate including a semiconductor substrate having a first trench extending in a first direction and a second trench extending in a second direction, the first trench and the second trench intersecting to form a plurality of semiconductor pillars on the semiconductor substrate, the second trench being filled with a first dielectric layer, the top of the semiconductor pillar having a second dielectric layer, and the sidewalls of the first trench having a third dielectric layer. An isolation layer extending along the second direction is formed within the semiconductor substrate below the first trench; A bit line extending in a second direction is formed on the isolation layer, and the bit line is connected to the bottom of the semiconductor pillar; Before forming an isolation layer extending in the second direction within the semiconductor substrate below the first trench, the method includes: The semiconductor substrate beneath the first trench is etched to isolate the semiconductor pillars; Etching the semiconductor substrate beneath the first trench to isolate the semiconductor pillars includes: An etch barrier layer extending in a second direction is formed below the first trench. The etch barrier layer is located inside the semiconductor substrate and is spaced apart from the first trench. The semiconductor substrate beneath the first trench is etched based on the etch barrier layer to isolate the semiconductor pillar; An isolation layer extending along the second direction is formed within the semiconductor substrate below the first trench, comprising: A sacrificial layer is formed on the bottom surface of the semiconductor pillar and on the opposite surface of the etch barrier layer and / or a portion of the surface of the semiconductor substrate; Thermal oxidation is performed on the etch barrier layer and / or the semiconductor substrate exposed by the sacrificial layer to form the isolation layer, wherein the isolation layer is beak-shaped at the portion opposite to the semiconductor pillar; Before forming a bit line extending in the second direction on the surface of the isolation layer, the method further includes: Remove the sacrificial layer.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that, An etching barrier layer extending in a second direction is formed below the first trench, comprising: Ion implantation is performed on the semiconductor substrate to form the etching barrier layer.

3. The method for preparing a semiconductor structure according to claim 1, characterized in that, Etching the semiconductor substrate beneath the first trench to isolate the semiconductor pillars includes: An etching barrier layer extending in a second direction is formed below the first trench, and the etching barrier layer is spaced apart from the first trench. The semiconductor substrate at the bottom of the first trench is etched to form a third trench, wherein the third trench is spaced apart from the etch barrier layer; A fourth dielectric layer is formed on the sidewalls of the first trench and the third trench; The semiconductor substrate below the third trench is etched based on the etch barrier layer to isolate the semiconductor pillar; The formation of an isolation layer extending along the second direction within the semiconductor substrate below the first trench includes: The isolation layer is formed between the semiconductor substrate and the semiconductor pillar below the third trench.

4. The method for preparing a semiconductor structure according to claim 3, characterized in that, After the isolation layer is formed between the semiconductor substrate and the semiconductor pillar below the third trench, and before a bit line extending in the second direction is formed on the surface of the isolation layer, the process includes: Remove the fourth dielectric layer; The semiconductor substrate beneath the first trench is etched to further isolate the semiconductor pillar.

5. The method for preparing a semiconductor structure according to any one of claims 1-4, characterized in that, Before etching the semiconductor substrate below the first trench to separate the semiconductor pillars, the process includes: The semiconductor substrate below the first trench is doped to form an ion-doped layer extending along a second direction, the ion-doped layer being connected to the semiconductor pillar.

6. The method for preparing a semiconductor structure according to claim 1, characterized in that, After forming bit lines extending in the second direction on the surface of the isolation layer, the method further includes: The bit line is heat-treated to form a metal silicide between the bit line and the semiconductor pillar; An insulating layer is filled into the first trench.

7. The method for preparing a semiconductor structure according to claim 1, characterized in that, Before forming a bit line extending in the second direction on the surface of the isolation layer, the method further includes: A metal material layer is formed between the surface of the isolation layer and the bottom of the semiconductor pillar; The metal material layer is heat-treated to form a metal silicide at the bottom of the semiconductor pillar; Remove the layer of metal material that did not participate in the reaction.

8. The method for preparing a semiconductor structure according to claim 6, characterized in that, After filling the first trench with an insulating layer, the method further includes: To form a transistor structure.

9. A semiconductor structure, said semiconductor structure being prepared by the preparation method according to any one of claims 1-8, characterized in that, include: The substrate includes a semiconductor substrate having a first trench extending in a first direction and a second trench extending in a second direction, the first trench and the second trench intersecting to form a plurality of semiconductor pillars on the semiconductor substrate, the second trench being filled with a first dielectric layer, the top of the semiconductor pillar having a second dielectric layer, and the sidewalls of the first trench having a third dielectric layer. An isolation layer is located within the semiconductor substrate below the first trench and extends along the second direction; Bit lines are located on the isolation layer and extend along a second direction, the bit lines being connected to the bottom of the semiconductor pillars.

10. The semiconductor structure according to claim 9, characterized in that, The isolation layer is beak-shaped in the portion opposite to the semiconductor pillar.

11. The semiconductor structure according to claim 9 or 10, characterized in that, The isolation layer is continuous in the second direction.

12. The semiconductor structure according to claim 9, characterized in that, There is a metal silicide between the semiconductor pillar and the bit line, and the first trench is filled with an insulating layer.

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