Layout structure of semiconductor devices

Abstract

The present invention provides a layout structure of a semiconductor device, comprising an active area and a gate area, wherein the gate area passes through the active area along a first direction, and the active area is divided into a source area and a drain area arranged on both sides of the gate area along a second direction. When a voltage is applied to the gate area, the direction of the electric field line is perpendicular to the outline of the gate area. Since the outline of the gate area and the two overlapping parts of the active area are both arc-shaped, the electric field can be dispersed, the electric field concentration can be prevented, and the risk of device breakdown is reduced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a layout structure of a semiconductor device. Background Art

[0002] The layout design of semiconductor devices is one of the most important steps in chip preparation. The layout is a combination of geometric figures corresponding to the device structure. These geometric figures are composed of different layers of figures combined with each other. Each layer of the layout corresponds to different process steps, and each layer of the layout is represented by a different pattern.

[0003] MOS tube is a type of field effect tube. Field effect tube is a voltage-controlled semiconductor device and a key component for providing stable power supply to the motherboard. Compared with ordinary MOS devices, high-voltage MOS devices are used in working environments with higher voltage (such as greater than or equal to 100V). Since the voltage of high-voltage MOS devices is high when they are working, the electric field inside the device is concentrated and it is easy to be broken down, causing device damage. Therefore, how to reduce the risk of device breakdown through layout design is a problem that needs to be solved urgently. Summary of the invention

[0004] The object of the present invention is to provide a layout structure of a semiconductor device to solve the problem that the existing MOS device is easily broken down, resulting in device damage.

[0005] In order to achieve the above-mentioned purpose, the present invention provides a layout structure of a semiconductor device, including an active area and a gate area, wherein the gate area passes through the active area along a first direction, and the active area is divided into a source area and a drain area arranged on both sides of the gate area along a second direction, and the outline of the gate area and the two overlapping parts of the active area are both arc-shaped.

[0006] Optionally, the overlapping portion is in an arc shape that is concave or convex relative to the center of the gate region.

[0007] Optionally, it further includes a plurality of source contact hole regions and a plurality of drain contact hole regions, wherein the source contact hole regions are all located in the source region and arranged along the first direction, and the drain contact hole regions are all located in the drain region and arranged along the first direction; and,

[0008] A virtual line connecting the centers of adjacent source contact hole regions is arc-shaped and has the same arc-shaped trend as the adjacent overlapping portions; a virtual line connecting the centers of adjacent drain contact hole regions is arc-shaped and has the same arc-shaped trend as the adjacent overlapping portions.

[0009] Optionally, the active area has a smooth profile.

[0010] Optionally, the active area is circular, elliptical or rounded polygonal.

[0011] Optionally, at least one body region is further included, wherein the body region is located outside the active region and the gate region and circumferentially surrounds at least a portion of the active region, and the contour of the body region is smooth.

[0012] Optionally, the body region is annular, and the body region is a complete ring or a 1 / n ring, where n is greater than 1.

[0013] Optionally, a partial outline of the body region overlaps with a partial outline of the active region.

[0014] Optionally, it further comprises a plurality of gate contact hole regions arranged along the second direction, wherein the gate contact hole regions are all located in the gate region and outside the active region, and a virtual line connecting the centers of adjacent gate contact hole regions is in an arc shape.

[0015] Optionally, the semiconductor device is a MOS tube with an operating voltage greater than or equal to 100V.

[0016] In the layout structure of the semiconductor device provided by the present invention, an active area and a gate area are included. The gate area passes through the active area along a first direction, and the active area is divided into a source area and a drain area arranged on both sides of the gate area along a second direction. When a voltage is applied to the gate area, the direction of the electric field line is perpendicular to the outline of the gate area. Since the outline of the gate area and the two overlapping parts of the active area are both arc-shaped, the electric field can be dispersed to prevent electric field concentration and reduce the risk of device breakdown. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 A schematic diagram of a layout structure of a semiconductor device provided in Embodiment 1 of the present invention;

[0018] Figure 2 A schematic diagram of the layout structure of a semiconductor device provided in the second embodiment of the present invention;

[0019] Figure 3 A schematic diagram of the layout structure of a semiconductor device provided in Embodiment 3 of the present invention;

[0020] Figure 4 A schematic diagram of the layout structure of a semiconductor device provided in Embodiment 4 of the present invention;

[0021] Wherein, the accompanying drawings are marked as follows:

[0022] AA-active area; S-source area; S1-first source area; S2-second source area; D-drain area; PG-gate area; PG1-first gate area; PG2-second gate area; L1-virtual line of the centers of all source contact hole areas; L2-virtual line of the centers of all drain contact hole areas; L3-virtual line of the centers of all gate contact hole areas at each end of the gate area along the first direction; B-body area; B1-first body area; B2-second body area; CT1-source contact hole area; CT11-first source contact hole area; CT12-second source contact hole area; CT2-drain contact hole area; CT21-first drain contact hole area; CT22-second drain contact hole area; CT3-gate contact hole area; CT31-first gate contact hole area; CT32-second gate contact hole area;

[0023] X-first direction; Y-second direction. DETAILED DESCRIPTION

[0024] The specific implementation of the present invention will be described in more detail below in conjunction with the schematic diagram. The advantages and features of the present invention will become clearer based on the following description. It should be noted that the drawings are all in a very simplified form and are not in exact proportions, and are only used to facilitate and clearly assist in explaining the purpose of the embodiments of the present invention.

[0025] Embodiment 1

[0026] This embodiment provides a layout structure of a semiconductor device, and the semiconductor device can be a high-voltage MOS tube with an operating voltage greater than or equal to 100V, such as a high-voltage NMOS tube, a high-voltage PMOS tube or a high-voltage CMOS tube, but should not be limited to this. The semiconductor device can also be a normal voltage or low voltage MOS tube with an operating voltage less than 100V.

[0027] Figure 1 FIG. 1 is a schematic diagram of the layout structure of the semiconductor device provided in this embodiment. Figure 1 As shown, the layout structure of the semiconductor device includes an active area AA and a gate area PG. The gate area PG passes through the active area AA along a first direction X, and divides the active area AA into a source area S and a drain area D arranged on both sides of the gate area PG along a second direction Y. It can be understood that the active area AA does not only include the source area S and the drain area D, but also includes a channel area located between the source area S and the drain area D, and the channel area is the overlapping area of ​​the active area AA and the gate area PG.

[0028] Please continue reading Figure 1The outline of the gate area PG has two overlapping parts with the active area AA. The two overlapping parts are actually the parts of the outline of the gate area PG located in the active area AA. For the convenience of description, the one of the two overlapping parts closer to the source area S is called the first overlapping part, and the one of the two overlapping parts closer to the drain area D is called the second overlapping part.

[0029] In this embodiment, when a voltage is applied to the gate region PG, the direction of the electric field lines is always perpendicular to the outline of the gate region PG. Since the first overlapping portion and the second overlapping portion are both arc-shaped, the electric field can be dispersed to prevent electric field concentration and reduce the risk of device breakdown. This is particularly suitable for high-voltage MOS tubes with higher operating voltages.

[0030] In this embodiment, the gate region PG is elliptical, so the first overlapping portion and the second overlapping portion are arcs that are convex relative to the center of the gate region PG, but the present invention is not limited to this. The first overlapping portion and the second overlapping portion may also be arcs that are concave relative to the center of the gate region PG, or one of the first overlapping portion and the second overlapping portion may be an arc that is concave relative to the center of the gate region PG, and the other may be an arc that is convex relative to the center of the gate region PG.

[0031] Similarly, the gate region PG in the present invention is not limited to being an ellipse, but may also be a circle, a circle with both ends flattened along the first direction X, or an ellipse with both ends flattened along the first direction X, etc., which will not be explained one by one here.

[0032] Furthermore, the layout structure of the semiconductor device also includes a plurality of source contact hole areas CT1 and a plurality of drain contact hole areas CT2, the source contact hole areas CT1 are all located in the source area S and arranged along the first direction X, and the drain contact hole areas CT2 are all located in the drain area D and arranged along the first direction X.

[0033] Optionally, the virtual line connecting the centers of the adjacent source contact hole regions CT1 is arc-shaped and has a consistent arc-shaped trend with the adjacent overlapping portions, and the virtual line connecting the centers of the adjacent drain contact hole regions CT2 is arc-shaped and has a consistent arc-shaped trend with the adjacent overlapping portions. Specifically, in this embodiment, the virtual line L1 connecting the centers of all the source contact hole regions CT1 is arc-shaped and has a consistent arc-shaped trend with the adjacent first overlapping portions, and the virtual line L2 connecting the centers of all the drain contact hole regions CT2 is arc-shaped and has a consistent arc-shaped trend with the adjacent second overlapping portions. The "consistent trend" described here means that the two arcs have approximately the same shape, for example, both are arcs that are concave relative to the center of the gate region PG or both are arcs that are concave relative to the center of the gate region PG, and it is not required that the curvature and shape of the two arcs must be strictly consistent.

[0034] It can be understood that the source contact hole area CT1 and the drain contact hole area CT2 can match the shapes of the first overlapping part and the second overlapping part respectively, so that the route of each current is roughly the same, which can reduce the parasitic resistance of the device; and, compared with the source contact hole area and the drain contact hole area arranged in a row along the first direction X, the arrangement of the source contact hole area CT1 and the drain contact hole area CT2 in this embodiment can increase the channel width (the width of the channel along the first direction X), and when the width of the active area AA (the width of the active area AA along the first direction X) is constant, more source contact hole areas CT1 and drain contact hole areas CT2 can be arranged, thereby reducing the parasitic resistance of the device and increasing the conduction performance of the device.

[0035] Similarly, the layout structure of the semiconductor device further includes a plurality of gate contact hole regions CT3 arranged along the second direction Y.

[0036] Optionally, the virtual connection line between the centers of adjacent gate contact hole regions CT3 is in an arc shape. Specifically, in this embodiment, the gate contact hole regions CT3 are all located in the gate region PG and outside the active area AA, and the virtual connection line L3 between the centers of all the gate contact hole regions CT3 at each end of the gate region PG along the first direction X is also in an arc shape. Therefore, when the width of the gate region PG (the width of the gate region PG along the second direction Y) is constant, more gate contact hole regions CT3 can be arranged to further reduce the parasitic resistance of the device and increase the conduction performance of the device.

[0037] As an optional embodiment, the source contact hole regions CT1 and / or the drain contact hole regions CT2 may actually be arranged in a row along the first direction X, and the gate contact hole regions CT3 may also be arranged in a row along the second direction Y.

[0038] Please continue reading Figure 1 In this embodiment, the active area AA is a rounded rectangle, so the active area AA has a smooth outline without sharp corners. When a voltage is applied to the source area S or the drain area D, electric field concentration at the sharp corners can be avoided, thereby reducing the risk of device breakdown.

[0039] As an optional embodiment, the active area AA is not limited to being a rounded rectangle, and may also be a circle, an ellipse, or other rounded polygons except a rounded rectangle, which will not be described one by one here.

[0040] Please continue reading Figure 1 In this embodiment, the layout structure of the semiconductor device also includes a body region B, which is annular and circumferentially surrounds the active area AA. The body region B is located outside the active area AA and the gate area PG, so the body region B has no overlapping area with the active area AA and the gate area PG.

[0041] In this embodiment, the body region B is a rounded rectangular ring and a complete ring, which can completely surround the active area AA and the gate area PG. The body region B has a smooth contour without sharp corners. When a voltage is applied to the body region B, electric field concentration at the sharp corners can be avoided, thereby reducing the risk of device breakdown.

[0042] As an optional embodiment, the shape of the body region B is not limited to a rounded rectangular ring, but can also be an elliptical ring, a circular ring, or a rounded polygonal ring other than a rounded rectangular ring, etc., which will not be illustrated one by one here; of course, the body region B is not a whole ring, but can also be a 1 / n ring, which is greater than 1, such as a half ring, a 1 / 4 ring or a 1 / 3 ring, etc., that is, the body region B can only surround part of the active area AA.

[0043] It can be understood that a plurality of body region contact hole regions ( Figure 1 (not shown) for leading out the body region B. Since the body region contact hole region is not the focus of the present invention, it will not be described in detail here.

[0044] Embodiment 2

[0045] Figure 2 FIG. 1 is a schematic diagram of the layout structure of the semiconductor device provided in this embodiment. Figure 2 As shown, the difference from the first embodiment is that in this embodiment, the number of the body regions is two, namely the first body region B1 and the second body region B2.

[0046] Please continue reading Figure 2The first body region B1 and the second body region B2 are both annular, but the first body region B1 and the second body region B2 are not a complete ring, but only a part of a complete ring. The first body region B1 and the second body region B2 both circumferentially surround a portion of the active area AA, and are symmetrically distributed relative to the center of the active area AA.

[0047] Of course, the number of the body regions is not limited to two, but may be more than two, and the distance between the center of each body region and the center of the active area AA may be equal or unequal, which is not limited by the present invention. Preferably, the size and shape of each body region may be the same, and the active area AA may be uniformly surrounded in the circumferential direction, so that the structure of the device is more symmetrical, beautiful, and easy to manufacture.

[0048] Optionally, there may be a gap between two adjacent body regions (the ends of the two adjacent body regions do not touch each other), but they do not overlap.

[0049] Embodiment 3

[0050] Figure 3 FIG. 1 is a schematic diagram of the layout structure of the semiconductor device provided in this embodiment. Figure 3 As shown, the difference from the second embodiment is that in this embodiment, the active area AA is circular, and the partial outlines of the first body area B1 and the second body area B2 coincide with the partial outline of the active area AA.

[0051] Specifically, the first body region B1 and the second body region B2 have an inner contour and an outer contour relative to the active area AA. Since the first body region B1 and the second body region B2 need to be located outside the active area AA, the partial contours of the first body region B1 and the second body region B2 coincide with the partial contour of the active area AA, which means that the inner contours of the first body region B1 and the second body region B2 coincide with the partial contour of the active area AA.

[0052] It can be understood that the first body region B1 and the second body region B2 in this embodiment are in close contact with the active area AA, and the distance between the first body region B1 and the second body region B2 and the active area AA can be shortened to a minimum, which can improve the de-biasing effect (De-Biasing, also known as the body effect); and since the gap between the first body region B1 and the second body region B2 and the active area AA is omitted, the area of ​​the layout can be saved.

[0053] It is understandable that in this embodiment, the active area AA is set to be circular only for the convenience of display. In other embodiments, the active area AA can be other shapes, and the first body area B1 and the second body area B2 can also change their shapes accordingly to fit the contour of the active area AA. Further, the number of body areas in this embodiment is not limited to two, and can also be any other possible number.

[0054] Embodiment 4

[0055] Figure 4 FIG. 1 is a schematic diagram of the layout structure of the semiconductor device provided in this embodiment. Figure 4 As shown, the difference from the first embodiment, the second embodiment and the third embodiment is that in this embodiment, the active area AA has two gate regions, namely the first gate region PG1 and the second gate region PG2.

[0056] Specifically, both the first gate region PG1 and the second gate region PG2 pass through the active area AA along the first direction X, the first gate region PG1 and the second gate region PG2 are arranged along the second direction Y, and there is a certain gap between the first gate region PG1 and the second gate region PG in the second direction Y. The first gate region PG1 and the second gate region PG2 divide the active area AA into two source regions and one drain region D, the two source regions are respectively referred to as the first source region S1 and the second source region S2, and the drain region D is located between the first source region S1 and the second source region S2.

[0057] Further, the first source region S1 and the drain region D are arranged on both sides of the first gate region PG1 along the second direction Y, the drain region D and the second source region S2 are arranged on both sides of the second gate region PG2 along the second direction Y, and the first gate region PG1 and the second gate region PG2 share the drain region D. The active area AA further includes a first channel region located between the first source region S1 and the drain region D and a second channel region located between the second source region S2 and the drain region D, the first channel region is an overlapping region of the active area AA and the first gate region PG1, and the second channel region is an overlapping region of the active area AA and the second gate region PG2.

[0058] It is worth noting that, in this embodiment, the first source region S1 has a plurality of first source contact hole regions CT11 arranged along the first direction X, and the second source region S2 has a plurality of second source contact hole regions CT12 arranged along the first direction X. The active region AA actually has two MOS transistors. Since the first gate region PG1 and the second gate region PG2 share the drain region D, the drain region D needs to have a plurality of first drain contact hole regions CT21 arranged along the first direction X and a plurality of second drain contact hole regions CT22 arranged along the first direction X. Similarly, the first gate region PG1 also has a plurality of first gate contact hole regions CT31 arranged along the second direction Y, and the second gate region PG2 also has a plurality of second gate contact hole regions CT32 arranged along the second direction Y.

[0059] It is worth reminding that the “several” described in this article refers to a quantity of at least two.

[0060] In summary, in the layout structure of the semiconductor device provided in an embodiment of the present invention, an active area and a gate area are included. The gate area passes through the active area along a first direction, and the active area is divided into a source area and a drain area arranged on both sides of the gate area along a second direction. When a voltage is applied to the gate area, the direction of the electric field line is perpendicular to the outline of the gate area. Since the outline of the gate area and the two overlapping parts of the active area are both arc-shaped, the electric field can be dispersed to prevent electric field concentration and reduce the risk of device breakdown.

[0061] It should be noted that the various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments, and the same or similar parts between the various embodiments can be referred to each other. For the system disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part description.

[0062] It should also be noted that, although the present invention has been disclosed as a preferred embodiment, the above embodiment is not intended to limit the present invention. For any technician familiar with the art, without departing from the scope of the technical solution of the present invention, the technical content disclosed above can be used to make many possible changes and modifications to the technical solution of the present invention, or modified into equivalent embodiments of equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention without departing from the content of the technical solution of the present invention still falls within the scope of protection of the technical solution of the present invention.

[0063] It should also be understood that, unless otherwise specified or indicated, the terms "first", "second", "third", etc. in the specification are merely used to distinguish between the various components, elements, steps, etc. in the specification, and are not used to indicate the logical relationship or sequential relationship between the various components, elements, steps, etc.

[0064] It should also be recognized that the terms described herein are only used to describe specific embodiments and are not intended to limit the scope of the invention. It should be noted that the singular forms "a" and "an" used herein and in the appended claims include plural references unless the context clearly indicates otherwise. For example, a reference to "a step" or "a device" means a reference to one or more steps or devices, and may include secondary steps and secondary devices. All conjunctions used should be understood in the broadest sense. And, the word "or" should be understood to have the definition of a logical "or", rather than a logical "exclusive or", unless the context clearly indicates otherwise. In addition, the implementation of the method and / or device in the embodiments of the present invention may include performing the selected task manually, automatically, or in combination.

Claims

1. A layout structure of a semiconductor device, characterized in that: The invention comprises an active region and a gate region, wherein the gate region passes through the active region along a first direction, and the active region is divided into a source region and a drain region arranged on both sides of the gate region along a second direction, and the outline of the gate region and two overlapping parts of the active region are both arc-shaped; It also includes a plurality of source contact hole regions and a plurality of drain contact hole regions, wherein the source contact hole regions are all located in the source region and arranged along the first direction, and the drain contact hole regions are all located in the drain region and arranged along the first direction; and A virtual line connecting the centers of adjacent source contact hole regions is arc-shaped and has the same arc-shaped trend as the adjacent overlapping portions; a virtual line connecting the centers of adjacent drain contact hole regions is arc-shaped and has the same arc-shaped trend as the adjacent overlapping portions.

2. The layout structure of the semiconductor device according to claim 1, characterized in that: The overlapping portion is in an arc shape that is concave or convex relative to the center of the gate region.

3. The layout structure of the semiconductor device according to claim 1, characterized in that: The active area has a smooth profile.

4. The layout structure of the semiconductor device according to claim 1 or 3, characterized in that: The active area is circular, elliptical or rounded polygonal.

5. The layout structure of the semiconductor device according to claim 1, characterized in that: The invention also includes at least one body region, which is located outside the active region and the gate region and circumferentially surrounds at least a portion of the active region, and the contour of the body region is smooth.

6. The layout structure of the semiconductor device according to claim 5, characterized in that: The body region is annular, and the body region is a complete ring or a 1 / n ring, where n is greater than 1.

7. The layout structure of the semiconductor device according to claim 5, characterized in that: A partial outline of the body region coincides with a partial outline of the active region.

8. The layout structure of the semiconductor device according to claim 1, characterized in that: It also includes a plurality of gate contact hole regions arranged along the second direction, wherein the gate contact hole regions are all located in the gate region and outside the active region, and a virtual line connecting the centers of adjacent gate contact hole regions is in an arc shape.

9. The layout structure of the semiconductor device according to claim 1, characterized in that: The semiconductor device is a MOS tube with an operating voltage greater than or equal to 100V.

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