Semiconductor memory device and method of forming the same

Abstract

A semiconductor memory device and a method of forming the same, wherein the semiconductor memory device includes a substrate, a nanowire structure suspended over the substrate, the nanowire structure including a channel region and a source region and a drain region respectively located at both ends of the channel region, the drain region having a size smaller than that of the source region, the source region, the drain region and the channel region having the same doping type, a word line structure surrounding the channel region, a bit line connected to the drain region, and a capacitor structure connected to the source region. The semiconductor memory device reduces a leakage current from the channel region to the drain region when a junctionless field effect transistor of a specific structure is in an off state.

Description

Technical Field

[0001] This invention relates to the field of memory, and more particularly to a semiconductor memory device and a method for forming the same. Background Technology

[0002] Dynamic Random Access Memory (DRAM) is a commonly used semiconductor memory device in computers, consisting of many repeating memory cells. Each memory cell typically includes a capacitor and a transistor. The gate of the transistor is connected to the word line, the drain is connected to the bit line, and the source is connected to the capacitor. The voltage signal on the word line can control the transistor to turn on or off, thereby reading data information stored in the capacitor through the bit line, or writing data information into the capacitor for storage through the bit line.

[0003] Transistors in existing dynamic random access memory (DRAM) still suffer from leakage current when they are off. Summary of the Invention

[0004] Some embodiments of this application provide a semiconductor memory device, including:

[0005] Substrate;

[0006] A nanowire structure suspended above the substrate, the nanowire structure including a channel region and source and drain regions located at opposite ends of the channel region, the size of the drain region being smaller than the size of the source region, and the source, drain and channel regions having the same doping type;

[0007] The word line structure surrounding the channel region;

[0008] Bit lines connected to the drain region and capacitor structures connected to the source region.

[0009] In some embodiments, the size of the drain region is smaller than the size of the channel region, and the size of the channel region is smaller than the size of the source region.

[0010] In some embodiments, the size of the nanowire structure gradually increases in a linear, arc-shaped, or step-like manner from the drain region to the source region.

[0011] In some embodiments, the channel region, source region, and drain region of the nanowire structure are cylindrical or elliptical sheet-like in shape of different sizes.

[0012] In some embodiments, the nanowire structure is "trumpet-shaped".

[0013] In some embodiments, the size of the source region is the diameter of the source region, the size of the drain region is the diameter of the drain region, and the difference between the diameter of the source region and the diameter of the drain region is at least greater than 10 nm.

[0014] In some embodiments, the diameter of the drain region is 4nm-20nm, and the diameter of the source region is 15nm-50nm.

[0015] In some embodiments, the material of the nanowire structure is Si or SiGe.

[0016] In some embodiments, the two ends of the nanowire structure are supported by a sacrificial layer located on the substrate surface, so that the nanowire structure is horizontally suspended on the substrate, and the nanowire structure is at least one layer.

[0017] In some embodiments, the capacitor structure is connected to the source region of the horizontally suspended nanowire structure.

[0018] In some embodiments, the nanowire structure is vertically suspended on the substrate, the source region is located at the upper end of the nanowire structure, the drain region is located at the lower end of the nanowire structure, the drain region is in contact with the substrate and supports the nanowire structure, so that the nanowire structure is vertically suspended on the substrate.

[0019] In some embodiments, the capacitor structure is connected to the source region of the vertically suspended nanowire structure.

[0020] In some embodiments, the word line structure includes a gate dielectric layer located on the surface of the channel region and surrounding the channel region, and a gate electrode located on the surface of the gate dielectric layer and surrounding the channel region.

[0021] Other embodiments of this application also provide a method for forming a semiconductor memory device, including:

[0022] Provide substrate;

[0023] A nanowire structure is formed on the substrate, the nanowire structure is suspended on the substrate, the nanowire structure includes a channel region and a source region and a drain region located at both ends of the channel region, the size of the drain region is smaller than the size of the source region, and the source region, drain region and channel region are doped with the same type;

[0024] A word line structure is formed around the channel region of the nanowire structure.

[0025] A bit line and a capacitor structure are fabricated, wherein the drain region is connected to the bit line and the source region is connected to the capacitor structure.

[0026] In some embodiments, the two ends of the nanowire structure are supported by a sacrificial layer located on the substrate surface, so that the nanowire structure is horizontally suspended on the substrate, and the nanowire structure is at least one layer.

[0027] In some embodiments, the formation process of the nanowire structure includes: forming a stacked structure of alternating sacrificial layers and semiconductor layers on the substrate; forming a plurality of parallel trenches penetrating the stacked structure, wherein the remaining plurality of semiconductor layers between adjacent trenches form a plurality of initial nanowire structures; removing a portion of the sacrificial layer between the plurality of initial nanowire structures, leaving the remaining sacrificial layer causing the initial nanowire structure to be suspended; and etching the initial nanowire structure to form the nanowire structure, wherein the nanowire structure includes a channel region and a source region and a drain region located at opposite ends of the channel region, wherein the size of the drain region is smaller than the size of the source region, and during the etching process, etching gas is input from above the substrate at an acute angle to the substrate, such that the etching gas flows from one end of the initial nanowire to which the drain region is to be formed to one end of the initial nanowire to which the source region is to be formed.

[0028] In some embodiments, the etching gas used in the etching process is hydrogen fluoride gas and ammonia gas, the acute angle between the input direction of the etching gas and the substrate is 30-50 degrees, the flow rate of the etching gas is 1slm-10slm, and the chamber temperature is 30-50 degrees Celsius.

[0029] In some embodiments, the formation process of the nanowire structure includes: forming a stacked structure of alternating sacrificial layers and semiconductor layers on the substrate, wherein the thickness of the semiconductor layers gradually increases from one end to the other; forming a plurality of parallel trenches penetrating the stacked structure, wherein the remaining plurality of semiconductor layers between adjacent trenches form a plurality of initial nanowire structures, wherein the thickness of the initial nanowire structures gradually increases from one end to the other; removing part of the sacrificial layer between the plurality of initial nanowire structures, wherein the remaining sacrificial layer causes the initial nanowire structures to be suspended; and performing an annealing process to round the surface of the initial nanowire structures, thereby forming the nanowire structure, wherein the nanowire structure includes a channel region and a source region and a drain region located at both ends of the channel region, wherein the size of the drain region is smaller than the size of the source region.

[0030] In some embodiments, a capacitor structure is formed that is connected to the source region of the horizontally suspended nanowire structure.

[0031] In some embodiments, the nanowire structure is vertically suspended on the substrate, the source region is located at the upper end of the nanowire structure, the drain region is located at the lower end of the nanowire structure, the drain region is in contact with the substrate and supports the nanowire structure, so that the nanowire structure is vertically suspended on the substrate.

[0032] In some embodiments, the formation process of the nanowire structure includes: forming a sacrificial layer on the substrate; etching the sacrificial layer to form at least one first via in the sacrificial layer, wherein the size of the lower end of the first via is smaller than the size of the upper end of the first via; filling the first via with semiconductor material to form a vertically suspended nanowire structure, wherein the size of the lower end of the nanowire structure is smaller than the size of the upper end of the nanowire structure; and removing the sacrificial layer.

[0033] In some embodiments, a capacitor structure is formed that is connected to the source region of the vertically suspended nanowire structure.

[0034] In some embodiments, the nanowire structure is "trumpet-shaped".

[0035] In some embodiments, the size of the source region is the diameter of the source region, the size of the drain region is the diameter of the drain region, and the difference between the diameter of the source region and the diameter of the drain region is at least greater than 10 nm.

[0036] In some embodiments, the diameter of the drain region is 4nm-20nm, and the diameter of the source region is 15nm-50nm.

[0037] In some embodiments, the channel region, source region, and drain region of the nanowire structure are cylindrical or elliptical sheet-like in shape of different sizes.

[0038] The semiconductor memory device in some of the foregoing embodiments of this application includes: a substrate; a nanowire structure suspended above the substrate, the nanowire structure including a channel region and a source region and a drain region located at opposite ends of the channel region, the drain region being smaller than the source region, and the source region, drain region, and channel region having the same doping type; a word line structure surrounding the channel region; a bit line connected to the drain region; and a capacitor structure connected to the source region. When the junctionless field-effect transistor of the aforementioned specific structure of the semiconductor memory device of this application is in the off state, the leakage current from the channel region to the drain region is reduced. Attached Figure Description

[0039] Figure 1 -8 is a schematic diagram of the semiconductor memory device formation process in some embodiments of the present invention;

[0040] Figure 9 -14 is a schematic diagram of the semiconductor memory device formation process in some other embodiments of the present invention. Detailed Implementation

[0041] As mentioned in the background section, transistors in existing dynamic random access memory (DRAM) still suffer from leakage current when the memory is off.

[0042] Research has found that transistors in existing DRAM devices often employ fully enclosed gate junctionless field-effect transistors (JFETs). A JFET typically includes: a columnar nanowire comprising a channel region and source and drain regions at either end of the channel region. The channel, source, and drain regions have the same doping type, such as N-type or P-type; and a gate structure surrounding the channel region. When a JFET operates, majority carriers in the channel travel from the source to the drain within the cylindrical channel rather than from the surface. By controlling the gate bias voltage to accumulate or deplete the majority carriers in the channel, channel conductivity can be modulated, thereby controlling the channel current. When the gate bias voltage is large enough to completely deplete the carriers at a certain cross-section near the drain of the columnar channel, the channel resistance becomes quasi-infinite, and the device is in an off state. Because a junctionless field-effect transistor is a majority carrier device, a high doping concentration of the columnar nanowire is required to increase the on-state current. However, the drain, channel, and source regions in highly doped columnar nanowires are the same size, which causes an overlap between the valence band and conduction band in the channel and drain of the highly doped columnar nanowires. This overlap causes electrons to tunnel from the valence band of the channel to the conduction band of the drain, resulting in interband tunneling. In the off state, this leads to a significant leakage current.

[0043] Therefore, the present invention provides a semiconductor memory device and a method for forming the same, which can prevent leakage current from occurring in the off state.

[0044] To make the above-mentioned objects, features, and advantages of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. In the detailed description of the embodiments of the present invention, for ease of explanation, the schematic diagrams may be partially enlarged without adhering to general proportions, and the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. Furthermore, in actual manufacturing, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0045] Some embodiments of this application first provide a semiconductor memory device, in conjunction with Reference 1 and... Figure 2 ,include:

[0046] Substrate 201;

[0047] A nanowire structure 204 is suspended above the substrate 201. The nanowire structure 204 includes a channel region 205 and a source region 207 and a drain region 206 located at opposite ends of the channel region 205 (see reference). Figure 1 The size of the drain region 206 is smaller than the size of the source region 207, and the source region 207, drain region 206 and channel region 205 have the same doping type;

[0048] Word line structure 208 surrounding the channel region (reference) Figure 1 );

[0049] Bit lines (not shown in the figure) connected to the drain region 206, and capacitor structures (not shown in the figure) connected to the source region 207.

[0050] Specifically, the substrate 201 can be made of single-crystal silicon (Si), single-crystal germanium (Ge), or silicon-germanium (GeSi), silicon carbide (SiC); it can also be silicon-on-insulator (SOI), germanium-on-insulator (GOI); or it can be other materials, such as gallium arsenide or other group III-V compounds.

[0051] The nanowire structure 204 is made of Si or SiGe. The nanowire structure 204 includes a channel region 205 and a source region 207 and a drain region 206 located at opposite ends of the channel region 205. The source region 207, drain region 206, and channel region 205 have the same doping type. A word line structure 208 surrounds the channel region. Therefore, the transistor in the semiconductor memory device of this application is a fully enclosed gate junctionless field-effect transistor. Furthermore, since the size of the drain region 206 is smaller than the size of the source region 207, the leakage current from the channel region 205 to the drain region 206 is reduced when the junctionless field-effect transistor of this application is in the off state.

[0052] The impurity ions doped in the source region 207, drain region 206, and channel region 205 are N-type or P-type impurity ions. In some embodiments, the P-type impurity ions are one or more of boron, gallium, and indium, and the N-type impurity ions include one or more of phosphorus, arsenic, and antimony.

[0053] The size of the drain region 206 being smaller than the size of the source region 207 means that the average size of the drain region 206 is smaller than the average size of the drain region, or that the size of the largest part of the drain region 206 is smaller than the size of the smallest part of the source region 207.

[0054] In one embodiment, the size of the drain region 206 is smaller than the size of the channel region 205, and the size of the channel region 205 is smaller than the size of the source region 207.

[0055] In some embodiments, the size of the nanowire structure 204 gradually increases in a linear, arc-shaped, or stepped manner from the drain region 206 towards the source region 207. Specifically, in the direction from the drain region 206 to the source region 207, the size of the drain region 206 gradually increases from one end in a linear, arc-shaped, or stepped manner to the end connected to the channel region 205; the size of the channel region 205 gradually increases from the end connected to the drain region 206 in a linear, arc-shaped, or stepped manner to the end connected to the source region 207; and the size of the source region 207 gradually increases from the end connected to the channel region 205 in a linear, arc-shaped, or stepped manner to the end.

[0056] In some embodiments, the channel region 205, source region 207, and drain region 206 of the nanowire structure 204 are cylindrical or elliptical sheet-like in different sizes.

[0057] In this embodiment, the nanowire structure 204 is trumpet-shaped. The size of the source region 207 is the diameter of the source region 207, and the size of the drain region 206 is the diameter of the drain region 206. The difference between the diameter of the source region 207 and the diameter of the drain region 206 is at least greater than 10 nm, so that when the junctionless field-effect transistor of this specific shape and size is in the off state, the leakage current from the channel region 205 to the drain region 206 is further reduced.

[0058] In one specific embodiment, the diameter of the drain region 206 is 4nm-20nm, and the diameter of the source region 207 is 15nm-50nm.

[0059] The word line structure 208 includes a gate dielectric layer located on the surface of the channel region 205 and surrounding the channel region 205, and metal word lines located on the surface of the gate dielectric layer and surrounding the channel region 205. In one embodiment, the material of the gate dielectric layer is silicon oxide, and the material of the metal word lines can be one or more of Al, Cu, Ag, Au, Pt, Ni, Ti, TiN, TaN, Ta, TaC, TaSiN, W, WN, and Wsi.

[0060] In this embodiment, the nanowire structure 204 is horizontally suspended on the substrate 201. The two ends of the nanowire structure 204 are supported by the sacrificial layer 202 located on the surface of the substrate 201, so that the nanowire structure 204 is horizontally suspended on the substrate 201. The capacitor structure is connected to the source region 207 of the horizontally suspended nanowire structure 204.

[0061] The material of the sacrificial layer 202 is different from the material of the nanowire structure 204. In some embodiments, the material of the sacrificial layer 202 is one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide nitride, amorphous silicon, amorphous carbon, polycrystalline silicon, and germanium silicon.

[0062] In this embodiment, the nanowire structure 204 is a single layer, which may include multiple parallel nanowire structures 204. In other embodiments, the nanowire structure 204 may be multi-layered (greater than or equal to two layers), with each layer including multiple parallel nanowire structures 204, and each nanowire structure layer supported by a sacrificial layer. Please refer to [reference needed] for details. Figure 4 and Figure 5The nanowire structure 204 has three layers, and the corresponding support layer 202 can also have three layers, with each support layer supporting one nanowire structure 204. There can be multiple word line structures 208, each word line structure 208 surrounding the channel region of multiple nanowire structures 204 arranged vertically. Correspondingly, there can be multiple bit lines, which can be horizontally arranged, with each bit line connecting the drain regions of multiple nanowire structures 204 in one layer. In other embodiments, the word line structures are horizontally arranged, each word line structure surrounding the channel region of multiple nanowire structures 204 in one layer, and the corresponding bit lines are vertically arranged, with each bit line connecting the drain regions of multiple nanowire structures 204 arranged vertically.

[0063] In other embodiments, please refer to Figure 11 and Figure 12 , Figure 12 for Figure 11 A three-dimensional schematic diagram of a nanowire structure is shown. The nanowire structure 204 is vertically suspended on the substrate 201. The source region 207 is located at the upper end of the nanowire structure 204, the drain region 206 is located at the lower end of the nanowire structure 204, and the channel region 205 is located in the middle of the nanowire structure 204. The drain region 206 is in contact with the substrate 201 and supports the nanowire structure 204, so that the nanowire structure 204 is vertically suspended on the substrate 201.

[0064] refer to Figure 13 The word line structure 208 surrounds the channel region 205 of the vertical nanowire structure 204 (see reference). Figure 12 An isolation dielectric layer (not shown) may be present between the word line structure 208 and the substrate 201.

[0065] The substrate 201 may have one or more vertical nanowire structures 204. In some embodiments, when there are multiple nanowire structures 204 on the substrate, adjacent nanowire structures 204 are isolated by an isolation dielectric layer.

[0066] refer to Figure 14 The capacitor structure 211 is connected to the source region 207 of the vertically suspended nanowire structure 204.

[0067] Other embodiments of this application also provide a method for forming a semiconductor memory device, the specific process of which is as follows:

[0068] Reference Figure 3 and Figure 4A substrate 201 is provided; a nanowire structure 204 is formed on the substrate 201, the nanowire structure 204 is suspended on the substrate 201, the nanowire structure 204 includes a channel region 205 and a source region 207 and a drain region 206 located at both ends of the channel region 205, the size of the drain region 206 is smaller than the size of the source region 207, and the source region 207, the drain region 206 and the channel region 205 have the same doping type.

[0069] The nanowire structure 204 is horizontally suspended on the substrate 201 by the two ends of a sacrificial layer 202 located on the surface of the substrate 201. The nanowire structure 204 is at least one layer. In a specific embodiment, the nanowire structure 204 can be one or more layers.

[0070] In one embodiment, the formation process of the nanowire structure 204 includes: forming a stacked structure of alternating sacrificial layers and semiconductor layers on the substrate; forming a plurality of parallel trenches penetrating the stacked structure, wherein the remaining plurality of semiconductor layers between adjacent trenches form a plurality of initial nanowire structures 203; removing a portion of the sacrificial layer between the plurality of initial nanowire structures 203, leaving the remaining sacrificial layer 202 such that the initial nanowire structures 203 are suspended (see reference). Figure 3 ); for the initial nanowire 203 (reference) Figure 3 The nanowire structure 204 (reference) is formed by etching. Figure 4 The nanowire structure 204 includes a channel region 205 and a source region 207 and a drain region 206 located at both ends of the channel region 205, respectively. The size of the drain region 206 is smaller than the size of the source region 207. During the etching process, the etching gas 21 is input from above the substrate 201 at an acute angle to the substrate 201, so that the etching gas 21 flows from one end of the initial nanowire 203 to form the drain region to one end of the initial nanowire 203 to form the source region.

[0071] The source region 207, drain region 206, and channel region 205 are all doped with the same type of impurity ions, which are either N-type or P-type impurity ions. In this embodiment, when forming the semiconductor layer, N-type or P-type impurity ions are doped into the semiconductor layer to save process steps.

[0072] During the etching process, the etching gas 21 is input from above the substrate 201 at an acute angle to the substrate 201, so that the etching gas 21 flows from one end of the initial nanowire 203 to form the drain region to one end of the initial nanowire 203 to form the source region. Therefore, the etching rate of the etching gas is faster at the end of the initial nanowire 203 to form the drain region and slower at the end of the initial nanowire 203 to form the source region, so that the size of the drain region 206 of the formed nanowire structure 204 is smaller than the size of the source region 207.

[0073] In one embodiment, the etching process uses hydrogen fluoride and ammonia as the etching gases. The acute angle between the input direction of the etching gas 21 and the substrate 201 is 30-50 degrees, and the flow rate of the etching gas is 1 slm (standard liters / minute) to 10 slm (standard liters / minute). The chamber temperature is 30-50 degrees Celsius. Under these specific etching parameters, it is relatively easy to make the size of the drain region 206 of the formed nanowire structure 204 smaller than the size of the source region 207, and the surface morphology of the formed nanowire structure 204 has good uniformity.

[0074] In other embodiments, the formation process of the nanowire structure 204 includes: forming a stacked structure of alternating sacrificial layers and semiconductor layers on the substrate 201, wherein the thickness of the semiconductor layers gradually increases from one end to the other; forming a plurality of parallel trenches penetrating the stacked structure, wherein the remaining plurality of semiconductor layers between adjacent trenches form a plurality of initial nanowire structures, wherein the thickness of the initial nanowire structures gradually increases from one end to the other; removing part of the sacrificial layer between the plurality of initial nanowire structures, wherein the remaining sacrificial layer makes the initial nanowire structures suspended; performing an annealing process to round the surface of the initial nanowire structures, thereby forming the nanowire structure 204, wherein the nanowire structure 204 includes a channel region 205 and a source region 207 and a drain region 206 located at both ends of the channel region 205, wherein the size of the drain region 206 is smaller than the size of the source region 207.

[0075] In some embodiments, when forming a semiconductor layer, the thickness of the semiconductor layer can be gradually increased from one end to the other through an etching process.

[0076] In some embodiments, the formed nanowire structure 204 is trumpet-shaped. The size of the source region 207 is the diameter of the source region, the size of the drain region 206 is the diameter of the drain region, and the difference between the diameter of the source region 207 and the diameter of the drain region 206 is at least greater than 10 nm. In some embodiments, the diameter of the drain region 206 is 4 nm–20 nm, and the diameter of the source region 207 is 15 nm–50 nm.

[0077] In some embodiments, the channel region 205, source region 207, and drain region 206 of the nanowire structure 204 are cylindrical or elliptical sheet-like in different sizes.

[0078] refer to Figure 5 This forms a word line structure 208 surrounding the channel region of the nanowire structure.

[0079] refer to Figure 6 An isolation dielectric layer 209 is formed covering the word line structure 208 and a portion of the nanowire structure.

[0080] In one embodiment, after forming the isolation dielectric layer 209, a portion of the sacrificial layer is removed to expose the drain region of the nanowire structure, and bit lines connected to the drain region are formed.

[0081] refer to Figure 7 and Figure 8 A portion of the sacrificial layer is removed to form a capacitor structure 211 connected to the source region 207.

[0082] In the aforementioned embodiment, when forming the nanowire structure 204, the formed nanowire structure 204 is horizontally suspended on the substrate 201. In other embodiments, when forming the nanowire structure, the formed nanowire structure is vertically suspended on the substrate, and the specific process includes: referencing... Figure 9 A sacrificial layer 215 is formed on the substrate 201; the sacrificial layer 215 is etched to form at least one first through-hole 216 in the sacrificial layer 215, wherein the size of the lower end of the first through-hole 216 is smaller than the size of the upper end of the first through-hole 216.

[0083] The sacrificial layer 215 can be made of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide nitride, or amorphous carbon. In this embodiment, the sacrificial layer 215 is made of silicon oxide.

[0084] The bottom of the formed first via 216 can expose a portion of the surface of the substrate 201. The size of the lower end of the first via 216 is smaller than the size of the upper end of the first via 216. A nanowire structure is subsequently formed in the first via 216, and the shape of the first via 216 defines the shape of the subsequently formed nanowire structure. In some embodiments, the size of the first via 216 gradually increases from bottom to top.

[0085] In some embodiments, the sacrificial layer 215 is etched using a plasma etching process. By controlling parameters such as gas flow rate and bias voltage during the etching process, the size of the lower end of the first through hole 216 is smaller than the size of the upper end of the first through hole 216.

[0086] refer to Figure 10The first through-hole is filled with semiconductor material to form a vertically suspended nanowire structure 204, wherein the lower end of the nanowire structure 204 is smaller than the upper end of the nanowire structure.

[0087] The upper end of the nanowire structure 204 serves as the source region 207, the lower end of the nanowire structure 204 serves as the drain region 206, and the middle of the nanowire structure 204 serves as the channel region 205. The size of the drain region 206 is smaller than the size of the source region 207.

[0088] The semiconductor material can be Si or GeSi. In one embodiment, the process of filling the first via with semiconductor material includes: forming a semiconductor material layer in the first via and on the surface of the sacrificial layer 215 by deposition or epitaxy, wherein the semiconductor material layer fills the first via; and removing the semiconductor material layer above the upper surface of the sacrificial layer by chemical mechanical polishing to form semiconductor material filling the first via.

[0089] refer to Figure 11 and Figure 12 , Figure 12 for Figure 11 A three-dimensional structural diagram of a nanowire structure, with the sacrificial layer removed.

[0090] The sacrificial layer may be completely or partially removed. In some embodiments, when the material of the sacrificial layer 215 is silicon oxide, a portion of the subsequent sacrificial layer 215 may be retained on the substrate 201 as an isolation layer.

[0091] refer to Figure 13 The word line structure 208 forms a channel region surrounding the vertically suspended nanowire structure 204.

[0092] Before forming the word line structure 208, a bit line (not shown) is formed to connect with the drain region of the suspended nanowire structure 204; after forming the bit line, a first isolation dielectric layer (not shown) is formed on the substrate 201, the surface of the first isolation dielectric layer being flush with the bottom of the channel region.

[0093] refer to Figure 14 A capacitor structure 211 is formed that is connected to the source region 207, which is a vertically suspended nanowire structure.

[0094] Before forming the capacitor structure 211, a second isolation dielectric layer (not shown in the figure) is formed covering the word line structure 208, the upper surface of the second isolation dielectric layer being flush with the upper surface of the source region 207; a capacitor structure 211 connected to the region 207 is formed on the second isolation dielectric layer.

[0095] It should be noted that the limitations or descriptions of the same or similar parts in some embodiments of the aforementioned semiconductor memory device formation method and some embodiments of the aforementioned semiconductor memory device will not be repeated here. For details, please refer to the limitations or descriptions of the corresponding parts in some embodiments of the aforementioned semiconductor memory device.

[0096] Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make possible changes and modifications to the technical solutions of the present invention by utilizing the methods and techniques disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solutions of the present invention shall fall within the protection scope of the technical solutions of the present invention.

Claims

1. A method for forming a semiconductor memory device, characterized in that, include: Provide substrate; A nanowire structure is formed on the substrate, the nanowire structure is suspended on the substrate, the nanowire structure includes a channel region and a source region and a drain region located at both ends of the channel region, the size of the drain region is smaller than the size of the source region, and the source region, drain region and channel region are doped with the same type; A word line structure is formed around the channel region of the nanowire structure. A bit line and a capacitor structure are fabricated, wherein the drain region is connected to the bit line and the source region is connected to the capacitor structure; The formation process of the nanowire structure includes: forming a stacked structure of alternating sacrificial layers and semiconductor layers on the substrate; forming several parallel trenches penetrating the stacked structure, with the remaining semiconductor layers between adjacent trenches forming several initial nanowire structures; removing part of the sacrificial layer between the initial nanowire structures, leaving the initial nanowire structure suspended by the remaining sacrificial layer; and etching the initial nanowire structure to form the nanowire structure, which includes a channel region and a source region and a drain region located at both ends of the channel region, respectively. The size of the drain region is smaller than the size of the source region. During the etching process, etching gas is input from above the substrate at an acute angle to the substrate, so that the etching gas flows from one end of the initial nanowire to form the drain region to one end of the initial nanowire to form the source region.

2. The method for forming a semiconductor memory device as claimed in claim 1, characterized in that, The nanowire structure is horizontally suspended on the substrate by sacrificial layers located on the substrate surface at both ends, and the nanowire structure consists of at least one layer.

3. The method for forming a semiconductor memory device as described in claim 1, characterized in that, The etching process uses hydrogen fluoride and ammonia as etching gases. The acute angle between the input direction of the etching gas and the substrate is 30-50 degrees. The flow rate of the etching gas is 1 slm-10 slm, and the chamber temperature is 30-50 degrees Celsius.

4. The method for forming a semiconductor memory device as described in claim 2, characterized in that, The formation process of the nanowire structure includes: forming a stacked structure of alternating sacrificial layers and semiconductor layers on the substrate, wherein the thickness of the semiconductor layers gradually increases from one end to the other; forming a plurality of parallel trenches penetrating the stacked structure, wherein the remaining plurality of semiconductor layers between adjacent trenches form a plurality of initial nanowire structures, wherein the thickness of the initial nanowire structures gradually increases from one end to the other; removing part of the sacrificial layer between the plurality of initial nanowire structures, leaving the remaining sacrificial layer to suspend the initial nanowire structures; performing an annealing process to round the surface of the initial nanowire structures, thereby forming the nanowire structure, wherein the nanowire structure includes a channel region and a source region and a drain region located at both ends of the channel region, wherein the size of the drain region is smaller than the size of the source region.

5. The method for forming a semiconductor memory device as described in claim 1 or 4, characterized in that, A capacitor structure is formed that is connected to the source region of the suspended nanowire structure.

6. The method for forming a semiconductor memory device as claimed in claim 2, characterized in that, The nanowire structure is trumpet-shaped.

7. The method for forming a semiconductor memory device as described in claim 5, characterized in that, The size of the source region is the diameter of the source region, the size of the drain region is the diameter of the drain region, and the difference between the diameter of the source region and the diameter of the drain region is at least greater than 10 nm.

8. The method for forming a semiconductor memory device as described in claim 7, characterized in that, The diameter of the drain region is 4nm-20nm, and the diameter of the source region is 15nm-50nm.

9. The method for forming a semiconductor memory device as claimed in claim 1, characterized in that, The channel, source, and drain regions of the nanowire structure are cylindrical or elliptical in shape of different sizes.

10. A semiconductor memory device, formed using the method for forming a semiconductor memory device according to any one of claims 1-9, characterized in that, include: Substrate; A nanowire structure suspended above the substrate, the nanowire structure including a channel region and source and drain regions located at opposite ends of the channel region, the size of the drain region being smaller than the size of the source region, and the source, drain and channel regions having the same doping type; The word line structure surrounding the channel region; Bit lines connected to the drain region and capacitor structures connected to the source region.

11. The semiconductor memory device as claimed in claim 10, characterized in that, The size of the leak region is smaller than the size of the channel region, and the size of the channel region is smaller than the size of the source region.

12. The semiconductor memory device as claimed in claim 10, characterized in that, The size of the nanowire structure gradually increases in a straight line, arc, or step shape from the drain region to the source region.

13. The semiconductor memory device as claimed in claim 10 or 11, characterized in that, The channel, source, and drain regions of the nanowire structure are cylindrical or elliptical in shape of different sizes.

14. The semiconductor memory device as claimed in claim 10 or 11, characterized in that, The nanowire structure is trumpet-shaped.

15. The semiconductor memory device as claimed in claim 14, characterized in that, The size of the source region is the diameter of the source region, the size of the drain region is the diameter of the drain region, and the difference between the diameter of the source region and the diameter of the drain region is at least greater than 10 nm.

16. The semiconductor memory device as claimed in claim 15, characterized in that, The diameter of the drain region is 4nm-20nm, and the diameter of the source region is 15nm-50nm.

17. The semiconductor memory device as claimed in claim 10, characterized in that, The nanowire structure is made of Si or SiGe.

18. The semiconductor memory device as claimed in claim 10, characterized in that, The nanowire structure is horizontally suspended on the substrate by sacrificial layers located on the substrate surface at both ends, and the nanowire structure consists of at least one layer.

19. The semiconductor memory device as claimed in claim 18, characterized in that, The capacitor structure is connected to the source region of the horizontally suspended nanowire structure.

20. The semiconductor memory device as claimed in claim 10, characterized in that, The word line structure includes a gate dielectric layer located on the surface of the channel region and surrounding the channel region, and a gate electrode located on the surface of the gate dielectric layer and surrounding the channel region.

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