半导体器件及其形成方法
By employing a dual-channel transistor design in semiconductor devices, the problems of size reduction and low yield have been solved, achieving high integration and simplified manufacturing processes.
CN115188807BActive Publication Date: 2026-07-17CHANGXIN MEMORY TECH INC
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CHANGXIN MEMORY TECH INC
- Filing Date
- 2022-06-28
- Publication Date
- 2026-07-17
AI Technical Summary
Technical Problem
In existing technologies, the size of semiconductor devices is difficult to shrink further, the manufacturing process is complex, the yield is low, and the integration is insufficient.
Method used
The transistor design employs a dual-channel structure, with the channel regions located on opposite sides of the gate electrode. The arrangement directions of the source, channel, and drain regions intersect with the extension direction of the word lines, and the gate electrode is formed by directly filling the second trench, simplifying the manufacturing process.
Benefits of technology
It increases the integration of semiconductor devices, reduces device size, improves yield, and reduces manufacturing difficulty.
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Smart Images
Figure CN115188807B_ABST
Abstract
本公开涉及一种半导体器件及其形成方法。所述半导体器件包括：衬底；存储阵列，位于所述衬底上，至少包括沿第一方向间隔排布的多个存储单元，所述存储单元包括晶体管，所述晶体管包括栅电极、沿第三方向分布于所述栅电极相对两侧的沟道区、以及沿第二方向分布于所述沟道区相对两侧的源极区和漏极区，所述第一方向和所述第三方向均为平行于所述衬底的顶面的方向，且所述第一方向与所述第三方向相交，所述第二方向为垂直于所述衬底的顶面的方向；字线，沿所述第一方向延伸，且连续电连接沿所述第一方向间隔排布的多个所述栅电极。本公开提高了半导体器件内部的集成度，缩小半导体器件的尺寸，并改善半导体器件的良率。
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