High power supply rejection ratio operational amplifiers and chips

Abstract

This invention discloses an operational amplifier and chip with high power supply rejection ratio (PSRR). The operational amplifier includes a first-stage amplifier circuit, a second-stage amplifier circuit, and an output stage circuit. The second-stage amplifier circuit includes an amplification unit, a capacitor unit, a fifteenth MOSFET, and a driving unit. The capacitor unit is connected to the amplification unit; the fifteenth MOSFET is connected to both the amplification unit and the capacitor unit; the driving unit is connected to the fifteenth MOSFET and is used to drive the fifteenth MOSFET to operate in the subthreshold region to improve the PSRR in conjunction with the capacitor unit. The operational amplifier of this invention drives the fifteenth MOSFET to operate in the subthreshold region through the driving unit, thereby providing a large on-resistance. Compared with traditional poly resistors, this significantly saves area, and together with the capacitor unit, forms an RC network to suppress high-frequency jitter and improve the high PSRR. This invention further improves the high PSRR through the output stage circuit.

Description

Technical Field

[0001] This invention relates to the field of integrated circuits, and in particular to an operational amplifier and chip with a high power supply rejection ratio. Background Technology

[0002] The design of high power supply rejection ratio (PSRR) circuits has always been a challenge in CMOS amplifiers. In communication system applications, there are usually high requirements for PSRR. Therefore, it is necessary to provide an operational amplifier to improve the PSRR, especially the performance in the corresponding high frequency band.

[0003] The information disclosed in this background section is intended only to enhance the understanding of the overall background of the invention and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Summary of the Invention

[0004] The purpose of this invention is to provide an operational amplifier with a high power supply rejection ratio, which can improve the power supply rejection ratio performance of the operational amplifier in the high-frequency range.

[0005] To achieve the above objectives, embodiments of the present invention provide an operational amplifier with a high power supply rejection ratio, comprising: a first-stage amplifier circuit and a second-stage amplifier circuit, wherein the second-stage amplifier circuit comprises: an amplification unit, a capacitor unit, a fifteenth MOS transistor, and a driving unit.

[0006] The amplification unit is used to amplify the signal output from the first-stage amplifier circuit; the capacitor unit is connected to the amplification unit; the fifteenth MOS transistor is connected to both the amplification unit and the capacitor unit; the driving unit is connected to the fifteenth MOS transistor, and the driving unit is used to drive the fifteenth MOS transistor to operate in the subthreshold region in order to cooperate with the capacitor unit to improve the power supply rejection ratio.

[0007] In one or more embodiments of the present invention, the driving unit includes a sixteenth MOS transistor, a seventeenth MOS transistor, and a first resistor. The source of the sixteenth MOS transistor is connected to a power supply voltage. The gate and drain of the sixteenth MOS transistor are connected and connected to the source of the fifteenth MOS transistor and the source of the seventeenth MOS transistor. The first terminal of the first resistor is connected to the drain of the seventeenth MOS transistor and the gate of the fifteenth MOS transistor. The second terminal of the first resistor is connected to the gate of the seventeenth MOS transistor and ground voltage.

[0008] In one or more embodiments of the present invention, the driving unit further includes a second current source, a first terminal of the second current source being connected to a second terminal of the first resistor, and a second terminal of the second current source being connected to ground voltage.

[0009] In one or more embodiments of the present invention, the capacitor unit includes a fourteenth MOS transistor, the source and drain of the fourteenth MOS transistor being connected to a power supply voltage, and the gate of the fourteenth MOS transistor being connected to the drain of a fifteenth MOS transistor and an amplification unit.

[0010] In one or more embodiments of the present invention, the capacitor unit is a MIM capacitor or a MOM capacitor.

[0011] In one or more embodiments of the present invention, the operational amplifier further includes an output stage circuit connected to the amplification unit, the output stage circuit being used to improve the power supply rejection ratio, the output stage circuit including an eighteenth MOS transistor, a nineteenth MOS transistor, a twentieth MOS transistor, a twenty-first MOS transistor, and a third current source;

[0012] The gates of the eighteenth and nineteenth MOS transistors are connected and simultaneously connected to the amplification unit. The drains of the eighteenth and nineteenth MOS transistors are connected and simultaneously connected to the power supply voltage. The source of the eighteenth MOS transistor is connected to the twentieth MOS transistor. The gate and drain of the twentieth MOS transistor are connected and simultaneously connected to the first terminal of the third current source. The second terminal of the third current source is connected to ground. The sources of the nineteenth and twenty-first MOS transistors are connected and connected to the output terminal. The gate of the twenty-first MOS transistor is connected to the gate of the twentieth MOS transistor, and the drain of the twenty-first MOS transistor is connected to ground; or

[0013] The gate and drain of the eighteenth MOS transistor are connected and simultaneously connected to the second terminal of the third current source. The first terminal of the third current source is connected to the power supply voltage. The gates of the eighteenth and nineteenth MOS transistors are connected. The drain of the nineteenth MOS transistor is connected to the power supply voltage. The source of the eighteenth MOS transistor is connected to the twentieth MOS transistor. The sources of the nineteenth and twenty-first MOS transistors are connected and connected to the output terminal. The gates of the twentieth and twenty-first MOS transistors are connected and simultaneously connected to the amplification unit. The drains of the twentieth and twenty-first MOS transistors are connected to the ground voltage.

[0014] In one or more embodiments of the present invention, the amplification unit includes an eleventh MOS transistor and a twelfth MOS transistor. The source of the eleventh MOS transistor is connected to the power supply voltage, the gate of the eleventh MOS transistor is connected to the capacitor unit and the drain of the fifteenth MOS transistor, the drain of the eleventh MOS transistor is connected to the output stage circuit and the drain of the twelfth MOS transistor, and the gate of the twelfth MOS transistor is connected to the first stage amplification circuit.

[0015] In one or more embodiments of the present invention, the amplification unit further includes a first capacitor, a first terminal of which is connected to the gate of the twelfth MOS transistor, and a second terminal of which is connected to the drain of the twelfth MOS transistor or to ground voltage.

[0016] In one or more embodiments of the present invention, a plurality of thirteenth MOS transistors are connected in series between the twelfth MOS transistor and the ground voltage. The gate of the thirteenth MOS transistor is connected to the gate of the twelfth MOS transistor, the drain of the thirteenth MOS transistor is connected to the source of the twelfth MOS transistor, and the source of the thirteenth MOS transistor is connected to the ground voltage.

[0017] The present invention also discloses a chip including the aforementioned high power supply rejection ratio operational amplifier.

[0018] Compared to existing technologies, the high power supply rejection ratio (PSRR) operational amplifier and chip according to this embodiment drive the fifteenth MOS transistor to operate in the subthreshold region through a driving unit, thereby providing a large on-resistance. Compared to traditional poly resistors, this significantly saves area, and together with the capacitor unit, forms an RC network to suppress high-frequency jitter and improve the high PSRR. This invention further improves the high PSRR through the output stage circuit. Attached Figure Description

[0019] Figure 1 This is a circuit schematic of an operational amplifier with high power supply rejection ratio according to an embodiment of the present invention.

[0020] Figure 2 This is a circuit schematic diagram of the output stage circuit according to another embodiment of the present invention. Detailed Implementation

[0021] The specific embodiments of the present invention will now be described in detail with reference to the accompanying drawings, but it should be understood that the scope of protection of the present invention is not limited to the specific embodiments.

[0022] Unless otherwise expressly stated, throughout the specification and claims, the term "comprising" or its variations such as "including" or "comprises" shall be understood to include the stated elements or components without excluding other elements or other components.

[0023] It should be understood that, in the following description, "circuit" may include single or combined hardware circuits, programmable circuits, state machine circuits, and / or elements capable of storing instructions executed by the programmable circuit. When an element or circuit is said to be "connected to" or "connected to" another element, or when an element / circuit is said to be "connected" between two nodes, it may be directly coupled to or connected to the other element, or there may be intermediate elements; the connection between elements may be physical, logical, or a combination thereof. Conversely, when an element is said to be "directly coupled to" or "directly connected to" another element, it means that there are no intermediate elements between them.

[0024] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0025] like Figure 1 As shown, an operational amplifier with high power supply rejection ratio includes: a first-stage amplifier circuit 10, a second-stage amplifier circuit 20, and an output stage circuit 30.

[0026] The first-stage amplifier circuit 10 includes a first MOSFET M1, a second MOSFET M2, and a first current source I1. The first terminal of the first current source I1 is connected to the source of the first MOSFET M1 and the second MOSFET M2, and the second terminal of the first current source I1 is connected to the power supply voltage VDD. The first MOSFET M1 and the second MOSFET M2 form a differential input pair, and the gates of the first MOSFET M1 and the second MOSFET M2 receive differential signals Vin and Vip.

[0027] Meanwhile, the first-stage amplifier circuit 10 also includes a common-source, common-gate amplifier circuit composed of the third MOSFET M3, the fourth MOSFET M4, the fifth MOSFET M5, the sixth MOSFET M6, the seventh MOSFET M7, the eighth MOSFET M8, the ninth MOSFET M9, and the tenth MOSFET M10.

[0028] Specifically, the sources of the third MOSFET M3 and the fourth MOSFET M4 are connected to the power supply voltage VDD, and the gates of the third MOSFET M3 and the fourth MOSFET M4 are connected. The gates of the fifth MOSFET M5 and the sixth MOSFET M6 are connected, the drain of the third MOSFET M3 is connected to the source of the fifth MOSFET M5, and the drain of the fourth MOSFET is connected to the source of the sixth MOSFET M6.

[0029] The drains of the fifth MOSFET M5 and the seventh MOSFET M7 are connected. The drains of the sixth MOSFET M6 and the eighth MOSFET M8 are connected, and both are connected to the second-stage amplifier circuit 20. The gates of the seventh MOSFET M7 and the eighth MOSFET M8 are connected. The gates of the ninth MOSFET M9 and the tenth MOSFET M10 are connected, and both are connected to the drain of the seventh MOSFET M7. The sources of the ninth MOSFET M9 and the tenth MOSFET M10 are connected to ground voltage VSS. The source of the seventh MOSFET M7 is connected to the drain of the ninth MOSFET M9, and both are connected to the drain of the first MOSFET M1. The source of the eighth MOSFET M8 is connected to the drain of the tenth MOSFET M10, and both are connected to the drain of the second MOSFET M2.

[0030] In other embodiments, the first-stage amplifier circuit 10 may also be a differential amplifier circuit with other structures.

[0031] like Figure 1 As shown, the second-stage amplifier circuit 20 includes: an amplifier unit 21, a capacitor unit 22, a fifteenth MOS transistor M15, and a driver unit 23.

[0032] The amplification unit 21 amplifies the signal output from the first-stage amplifier circuit 10. The capacitor unit 22 is connected to the amplification unit 21, the fifteenth MOSFET M15 is connected to both the amplification unit 21 and the capacitor unit 22, and the driving unit 23 is connected to the fifteenth MOSFET M15. The driving unit 23 drives the fifteenth MOSFET M15 to operate in the subthreshold region to cooperate with the capacitor unit 22 and improve the power supply rejection ratio.

[0033] Specifically, such as Figure 1 As shown, the amplification unit 21 includes a first capacitor C1, an eleventh MOSFET M11, and a twelfth MOSFET M12. In addition, several thirteenth MOSFETs M13 are connected in series between the twelfth MOSFET M12 and the ground voltage VSS.

[0034] The source of the eleventh MOSFET M11 is connected to the power supply voltage VDD. The gate of the eleventh MOSFET M11 is connected to capacitor unit 22 and the drain of the fifteenth MOSFET M15. The drain of the eleventh MOSFET M11 is connected to the output stage circuit 30 and the drain of the twelfth MOSFET M12, forming a connection node Vx with the output stage circuit 30. The gate of the twelfth MOSFET M12 is connected to the drain of the eighth MOSFET M8 in the first-stage amplifier circuit 10.

[0035] In this embodiment, the first terminal of the first capacitor C1 is connected to the gate of the twelfth MOSFET M12, and the second terminal of the first capacitor C1 is connected to the drain of the twelfth MOSFET M12. In other embodiments, the second terminal of the first capacitor C1 is connected to ground voltage VSS. The first capacitor C1 is used for circuit stabilization.

[0036] In this embodiment, one thirteenth MOSFET M13 is provided. The gate of the thirteenth MOSFET M13 is connected to the gate of the twelfth MOSFET M12, the drain of the thirteenth MOSFET M13 is connected to the source of the twelfth MOSFET M12, and the source of the thirteenth MOSFET M13 is connected to ground voltage VSS. In other embodiments, multiple thirteenth MOSFETs M13 are provided.

[0037] like Figure 1 As shown, capacitor unit 22 includes a fourteenth MOSFET M14. The source and drain of the fourteenth MOSFET M14 are connected to the power supply voltage VDD, and the gate of the fourteenth MOSFET M14 is connected to the drain of the fifteenth MOSFET M15 and the amplification unit 21. The fourteenth MOSFET M14 is a MOSFET capacitor.

[0038] In other embodiments, capacitor unit 22 may be a MIM capacitor or a MOM capacitor.

[0039] like Figure 1 As shown, the driving unit 23 includes a sixteenth MOS transistor M16, a seventeenth MOS transistor M17, a first resistor R1, and a second current source I2.

[0040] Specifically, the source of the sixteenth MOSFET M16 is connected to the power supply voltage VDD. The gate and drain of the sixteenth MOSFET M16 are connected and also connected to the sources of the fifteenth MOSFET M15 and the seventeenth MOSFET M17. The first terminal of the first resistor R1 is connected to the drain of the seventeenth MOSFET M17 and the gate of the fifteenth MOSFET M15. The second terminal of the first resistor R1 is connected to the gate of the seventeenth MOSFET M17 and the ground voltage VSS. The first terminal of the second current source I2 is connected to the second terminal of the first resistor R1, and the second terminal of the second current source I2 is connected to the ground voltage VSS.

[0041] In this embodiment, the gate voltage of the fifteenth MOSFET M15 is increased by the first resistor R1, so that the fifteenth MOSFET M15 operates in the subthreshold region. The fifteenth MOSFET M15 operating in the subthreshold region can provide a megaohm level on-resistance. At this time, the fifteenth MOSFET M15 and the fourteenth MOSFET M14 form an RC network to suppress high-frequency jitter.

[0042] like Figure 1 As shown, the output stage circuit 30 is a source follower output, which can further improve the power supply rejection ratio. The output stage circuit 30 includes the eighteenth MOSFET M18, the nineteenth MOSFET M19, the twentieth MOSFET M20, the twenty-first MOSFET M21, and the third current source I3.

[0043] The gates of the eighteenth MOSFET M18 and the nineteenth MOSFET M19 are connected and simultaneously connected to the connection node Vx of the amplifier unit 21. The drains of the eighteenth MOSFET M18 and the nineteenth MOSFET M19 are connected and simultaneously connected to the power supply voltage VDD. The eighteenth MOSFET M18 is connected to the source of the twentieth MOSFET M20. The gate and drain of the twentieth MOSFET M20 are connected and simultaneously connected to the first terminal of the third current source I3. The second terminal of the third current source I3 is connected to the ground voltage VSS. The sources of the nineteenth MOSFET M19 and the twenty-first MOSFET M21 are connected and connected to the output terminal Vout. The gate of the twenty-first MOSFET M21 is connected to the gate of the twentieth MOSFET M20. The drain of the twenty-first MOSFET M21 is connected to the ground voltage VSS.

[0044] In this embodiment, the first MOSFET M1, the second MOSFET M2, the third MOSFET M3, the fourth MOSFET M4, the fifth MOSFET M5, the sixth MOSFET M6, the eleventh MOSFET M11, the fourteenth MOSFET M14, the fifteenth MOSFET M15, the sixteenth MOSFET M16, the seventeenth MOSFET M17, the twentieth MOSFET M20, and the twenty-first MOSFET M21 are P-channel MOSFETs.

[0045] The seventh MOSFET M7, the eighth MOSFET M8, the ninth MOSFET M9, the tenth MOSFET M10, the twelfth MOSFET M12, the thirteenth MOSFET M13, the eighteenth MOSFET M18, and the nineteenth MOSFET M19 are N-channel MOSFETs.

[0046] In other embodiments, the P-channel MOSFET and the N-channel MOSFET can be interchanged.

[0047] like Figure 2As shown, in other embodiments, the output stage circuit 30 can be connected in a different manner. For example, the gate and drain of the eighteenth MOSFET M18 are connected and simultaneously connected to the second terminal of the third current source I3, and the first terminal of the third current source I3 is connected to the power supply voltage VDD. The gates of the eighteenth MOSFET M18 and the nineteenth MOSFET M19 are connected, and the drain of the nineteenth MOSFET M19 is connected to the power supply voltage VDD. The source of the eighteenth MOSFET M18 is connected to the twentieth MOSFET M20, and the sources of the nineteenth MOSFET M19 and the twenty-first MOSFET M21 are connected and connected to the output terminal. The gates of the twentieth MOSFET M20 and the twenty-first MOSFET M21 are connected and simultaneously connected to the amplification unit 21, and the drains of the twentieth MOSFET M20 and the twenty-first MOSFET M21 are connected to the ground voltage VSS. Of course, it should be noted that this connection method requires the 11th MOSFET M11, 12th MOSFET M12 and 13th MOSFET M13 in the amplifier unit 21 to also change the MOSFET type. For example, the 12th MOSFET M12 and 13th MOSFET M13 are P-channel MOSFETs and the 11th MOSFET M11 is an N-channel MOSFET.

[0048] The present invention also discloses a chip comprising the above-described high power supply rejection ratio operational amplifier.

[0049] The foregoing description of specific exemplary embodiments of the invention is for illustrative and explanatory purposes. These descriptions are not intended to limit the invention to the precise forms disclosed, and it will be apparent that many changes and variations can be made in accordance with the foregoing teachings. The exemplary embodiments were chosen and described in order to explain the specific principles of the invention and its practical application, thereby enabling those skilled in the art to implement and utilize various different exemplary embodiments of the invention, as well as various different choices and variations. The scope of the invention is intended to be defined by the claims and their equivalents.

Claims

1. An operational amplifier with high power supply rejection ratio, comprising: The first-stage amplifier circuit and the second-stage amplifier circuit are characterized in that the second-stage amplifier circuit includes: Amplification unit, used to amplify the signal output from the first-stage amplifier circuit; The capacitor unit is connected to the amplifier unit; The fifteenth MOSFET is connected to the amplifier unit and the capacitor unit; and A driving unit is connected to the fifteenth MOS transistor. The driving unit is used to drive the fifteenth MOS transistor to operate in the subthreshold region in order to cooperate with the capacitor unit to improve the power supply rejection ratio. The driving unit includes a sixteenth MOS transistor, a seventeenth MOS transistor, a first resistor, and a second current source. The source of the sixteenth MOS transistor is connected to the power supply voltage. The gate and drain of the sixteenth MOS transistor are connected and connected to the source of the fifteenth MOS transistor and the source of the seventeenth MOS transistor. The first terminal of the first resistor is connected to the drain of the seventeenth MOS transistor and the gate of the fifteenth MOS transistor. The second terminal of the first resistor is connected to the gate of the seventeenth MOS transistor and the first terminal of the second current source. The second terminal of the second current source is connected to ground voltage.

2. The operational amplifier with high power supply rejection ratio as described in claim 1, characterized in that, The capacitor unit includes a fourteenth MOS transistor, the source and drain of which are connected to the power supply voltage, and the gate of which is connected to the drain of the fifteenth MOS transistor and the amplification unit.

3. The operational amplifier with high power supply rejection ratio as described in claim 1, characterized in that, The capacitor unit is a MIM capacitor or a MOM capacitor.

4. The operational amplifier with high power supply rejection ratio as described in claim 1, characterized in that, The operational amplifier also includes an output stage circuit connected to the amplification unit. The output stage circuit is used to improve the power supply rejection ratio. The output stage circuit includes an eighteenth MOS transistor, a nineteenth MOS transistor, a twentieth MOS transistor, a twenty-first MOS transistor, and a third current source. The gates of the eighteenth and nineteenth MOS transistors are connected and simultaneously connected to the amplification unit. The drains of the eighteenth and nineteenth MOS transistors are connected and simultaneously connected to the power supply voltage. The source of the eighteenth MOS transistor is connected to the twentieth MOS transistor. The gate and drain of the twentieth MOS transistor are connected and simultaneously connected to the first terminal of the third current source. The second terminal of the third current source is connected to ground. The sources of the nineteenth and twenty-first MOS transistors are connected and connected to the output terminal. The gate of the twenty-first MOS transistor is connected to the gate of the twentieth MOS transistor, and the drain of the twenty-first MOS transistor is connected to ground; or The gate and drain of the eighteenth MOS transistor are connected and simultaneously connected to the second terminal of the third current source. The first terminal of the third current source is connected to the power supply voltage. The gates of the eighteenth and nineteenth MOS transistors are connected. The drain of the nineteenth MOS transistor is connected to the power supply voltage. The source of the eighteenth MOS transistor is connected to the twentieth MOS transistor. The sources of the nineteenth and twenty-first MOS transistors are connected and connected to the output terminal. The gates of the twentieth and twenty-first MOS transistors are connected and simultaneously connected to the amplification unit. The drains of the twentieth and twenty-first MOS transistors are connected to the ground voltage.

5. The operational amplifier with high power supply rejection ratio as described in claim 1, characterized in that, The amplification unit includes an eleventh MOS transistor and a twelfth MOS transistor. The source of the eleventh MOS transistor is connected to the power supply voltage. The gate of the eleventh MOS transistor is connected to the capacitor unit and the drain of the fifteenth MOS transistor. The drain of the eleventh MOS transistor is connected to the output stage circuit and the drain of the twelfth MOS transistor. The gate of the twelfth MOS transistor is connected to the first-stage amplification circuit.

6. The operational amplifier with high power supply rejection ratio as described in claim 5, characterized in that, The amplification unit further includes a first capacitor, the first terminal of which is connected to the gate of the twelfth MOS transistor, and the second terminal of which is connected to the drain of the twelfth MOS transistor or to ground voltage.

7. The operational amplifier with high power supply rejection ratio as described in claim 5, characterized in that, Several thirteenth MOS transistors are connected in series between the twelfth MOS transistor and the ground voltage. The gate of the thirteenth MOS transistor is connected to the gate of the twelfth MOS transistor, the drain of the thirteenth MOS transistor is connected to the source of the twelfth MOS transistor, and the source of the thirteenth MOS transistor is connected to the ground voltage.

8. A chip, characterized in that, The operational amplifier includes the high power supply rejection ratio as described in any one of claims 1 to 7.

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