Clock correction method and circuit, storage device

Abstract

The embodiment of the present disclosure discloses a clock correction method and circuit and a storage device. The clock correction circuit comprises at least one duty cycle correction sub-circuit. Each duty cycle correction sub-circuit comprises a duty cycle adjustment circuit. The duty cycle adjustment circuit comprises an adjustment unit and a first inverter unit. The output end of the adjustment unit is connected with the input end of the first inverter unit. The output end of the first inverter unit is connected with the input end of the adjustment unit. The duty cycle adjustment circuit is configured to delay or advance the falling edge of an input clock signal to increase or decrease the duty cycle of the input clock signal, and output a corrected clock signal.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a time correction method, circuit, and storage device. Background Technology

[0002] Delay-locked loops (PLLs) and duty cycle correction circuits are widely used in microprocessors, memory interfaces, chip-to-chip interfaces, and clock distribution networks for large-scale integrated circuits. A PLL synchronizes the phase of an externally input clock signal with the clock signal inside the memory device, ensuring error-free data transmission to or retrieval from the memory device and improving system timing. A duty cycle correction circuit adjusts the clock's duty cycle (typically 50%) to maximize clock level utilization, ensuring normal system operation and optimal performance. PLLs and duty cycle correction circuits are often used together in various application systems. Summary of the Invention

[0003] In view of this, the present disclosure provides a duty cycle correction method, circuit, and storage device to solve at least one problem existing in the prior art.

[0004] To achieve the above objectives, the technical solution of this disclosure embodiment is implemented as follows:

[0005] In a first aspect, embodiments of this disclosure provide a clock correction circuit, comprising: at least one duty cycle correction sub-circuit; each duty cycle correction sub-circuit includes a duty cycle adjustment circuit; the duty cycle adjustment circuit includes an adjustment unit and a first inverter unit; the output terminal of the adjustment unit is connected to the input terminal of the first inverter unit; the output terminal of the first inverter unit is connected to the input terminal of the adjustment unit.

[0006] The duty cycle adjustment circuit is configured to delay or advance the falling edge of the input clock signal to increase or decrease the duty cycle of the input clock signal and output a corrected clock signal.

[0007] In one alternative implementation, it further includes: a phase comparison circuit, a delay chain, and a replication circuit;

[0008] The replication circuit is configured to delay the output clock signal generated by the delay chain to generate a feedback clock signal;

[0009] The phase comparison circuit is configured to generate a delay control signal corresponding to the phase difference by detecting the phase difference between the input clock signal and the feedback clock signal;

[0010] The delay chain is configured to adjust the rising edge of the corrected clock signal according to the delay control signal to generate an output clock signal so that the feedback clock signal is phase-aligned with the input clock signal.

[0011] In one alternative implementation, each duty cycle corrector circuit further includes a step size control circuit;

[0012] The step size control circuit is configured to control the adjustment step size of the duty cycle based on the duty cycle correction code;

[0013] The duty cycle adjustment circuit is specifically configured to increase or decrease the duty cycle of the input clock signal by delaying or advancing the falling edge of the input clock signal based on the adjustment step size, and output the corrected clock signal.

[0014] In one alternative implementation, each duty cycle correction sub-circuit further includes a first node and a second node;

[0015] The step size control circuit includes a parallel multi-state inverter unit and a second inverter unit;

[0016] The input terminal of the second inverter unit is connected to the first node, and the output terminal of the second inverter unit is connected to the second node;

[0017] The input terminal of the first inverter unit is connected to the second node.

[0018] In one alternative implementation, the adjustment unit includes a pull-down adjustment unit;

[0019] The pull-down adjustment unit includes a first NMOS transistor and a first parallel NMOS transistor, wherein the first parallel NMOS transistor includes a plurality of NMOS transistors connected in parallel.

[0020] In one optional implementation, the duty cycle correction code includes a first pull-down code input to the pull-down adjustment unit;

[0021] The duty cycle adjustment circuit is specifically configured to control the on or off of each NMOS transistor in the first parallel NMOS transistor based on the first pull-down code, so as to delay or advance the falling edge of the input clock signal.

[0022] In one optional implementation, the multi-state inverter unit includes a pull-up control unit and a pull-down control unit;

[0023] The pull-up control unit includes a first PMOS transistor and parallel PMOS transistors, wherein the parallel PMOS transistors include multiple PMOS transistors connected in parallel.

[0024] The pull-down control unit includes a second NMOS transistor and a second parallel NMOS transistor, wherein the second parallel NMOS transistor includes multiple NMOS transistors connected in parallel.

[0025] In one optional implementation, the duty cycle correction code includes a second pull-up code input to the pull-up control unit and a second pull-down code input to the pull-down control unit;

[0026] The step size control circuit is specifically configured to control the on or off of each PMOS transistor in the parallel PMOS transistors based on the second pull-up code, and to control the on or off of each NMOS transistor in the second parallel NMOS transistors based on the second pull-down code, so as to achieve control of the duty cycle adjustment step size.

[0027] In one optional implementation, the duty cycle detection unit is configured to detect the duty cycle information of the initial input clock signal and the output clock signal of each duty cycle correction sub-circuit, and output the duty cycle information of the initial input clock signal and the corrected clock signal output by each duty cycle correction sub-circuit.

[0028] The correction code generation unit is configured to generate a duty cycle correction code for a first-stage duty cycle correction sub-circuit based on the duty cycle information of the initial input clock signal, and, in the case where the duty cycle correction circuit includes multiple duty cycle correction sub-circuits connected in stages, generate a duty cycle correction code for a subsequent-stage duty cycle correction sub-circuit based on the corrected duty cycle information output by the previous-stage duty cycle correction sub-circuit.

[0029] Secondly, embodiments of this disclosure provide a clock correction method, wherein the clock correction circuit includes at least one duty cycle correction sub-circuit; wherein each duty cycle correction sub-circuit includes a duty cycle adjustment circuit; the duty cycle adjustment circuit includes an adjustment unit and a first inverter unit; the method includes:

[0030] The duty cycle of the input clock signal is increased or decreased by delaying or advancing the falling edge of the input clock signal using a duty cycle adjustment circuit, and a corrected clock signal is output.

[0031] The first inverter unit in the duty cycle adjustment circuit outputs the corrected clock signal, and the corrected clock signal is fed back to the adjustment unit in the duty cycle adjustment circuit.

[0032] In one optional implementation, the clock correction circuit further includes a phase comparison circuit, a delay chain, and a replication circuit; the method further includes:

[0033] The replication circuit delays the output clock signal generated by the delay chain to generate a feedback clock signal.

[0034] The phase comparison circuit uses the phase difference detection between the input clock signal and the feedback clock signal to generate a delay control signal corresponding to the phase difference.

[0035] The delay chain is used to adjust the rising edge of the corrected clock signal according to the delay control signal to generate an output clock signal, so that the feedback clock signal is phase-aligned with the input clock signal.

[0036] In one optional implementation, each duty cycle correction subcircuit further includes a step size control circuit; the method further includes:

[0037] The step size control circuit is used to control the adjustment step size of the duty cycle based on the duty cycle correction code;

[0038] The method of using a duty cycle adjustment circuit to delay or advance the falling edge of the input clock signal to increase or decrease the duty cycle of the input clock signal and outputting a corrected clock signal includes:

[0039] The duty cycle adjustment circuit increases or decreases the duty cycle of the input clock signal by delaying or advancing the falling edge of the input clock signal based on the adjustment step size, and outputs the corrected clock signal.

[0040] In one optional implementation, each duty cycle correction sub-circuit further includes a first node and a second node; the first node is used to receive an input clock signal; the step size control circuit includes a parallel multi-state inverter unit and a second inverter unit; the input terminal of the second inverter unit is connected to the first node, and the output terminal of the second inverter unit is connected to the second node; the input terminal of the first inverter unit is connected to the second node.

[0041] The step of using the first inverter unit in the duty cycle adjustment circuit to output the corrected clock signal includes:

[0042] The second inverter unit inverts the input clock signal and outputs it to the second node. The duty cycle adjustment circuit generates the corrected clock signal of the duty cycle correction sub-circuit based on the signal output by the first inverter unit and the signal at the second node.

[0043] In one optional embodiment, the adjustment unit includes a pull-down adjustment unit; the pull-down adjustment unit includes a first NMOS transistor and a first parallel NMOS transistor, the first parallel NMOS transistor including a plurality of parallel NMOS transistors; the duty cycle correction code includes a first pull-down code input to the pull-down adjustment unit;

[0044] The method of using a duty cycle adjustment circuit to delay or advance the falling edge of the input clock signal to increase or decrease the duty cycle of the input clock signal includes:

[0045] The duty cycle adjustment circuit uses the first pull-down code to control the opening or closing of each NMOS transistor in the first parallel NMOS transistors, thereby delaying or advancing the falling edge of the input clock signal.

[0046] In one optional embodiment, the multi-state inverter unit includes a pull-up control unit and a pull-down control unit; the pull-up control unit includes a first PMOS transistor and parallel PMOS transistors, the parallel PMOS transistors including a plurality of PMOS transistors connected in parallel; the pull-down control unit includes a second NMOS transistor and a second parallel NMOS transistor, the second parallel NMOS transistor including a plurality of NMOS transistors connected in parallel; the duty cycle correction code includes a second pull-up code input to the pull-up control unit and a second pull-down code input to the pull-down control unit;

[0047] The method of using a step-size control circuit to control the adjustment step size of the duty cycle based on a duty cycle correction code includes:

[0048] The step size control circuit uses the second pull-up code to control the opening or closing of each PMOS transistor in the parallel PMOS transistors, and the second pull-down code to control the opening or closing of each NMOS transistor in the second parallel NMOS transistors, so as to achieve control of the duty cycle adjustment step size.

[0049] In one optional implementation, the clock correction circuit further includes a duty cycle detection unit and a correction code generation unit; the method further includes:

[0050] The duty cycle detection unit detects the duty cycle of the initial input clock signal and the output clock signal of each duty cycle correction sub-circuit, and outputs the duty cycle information of the initial input clock signal and the corrected clock signal output by each duty cycle correction sub-circuit.

[0051] The duty cycle correction code of the first-stage duty cycle correction sub-circuit is generated by the correction code generation unit based on the duty cycle information of the initial input clock signal. In the case that the duty cycle correction circuit includes multiple duty cycle correction sub-circuits connected in stages, the duty cycle correction code of the subsequent-stage duty cycle correction sub-circuit is generated based on the duty cycle information of the corrected clock signal output by the previous-stage duty cycle correction sub-circuit.

[0052] Thirdly, embodiments of this disclosure provide a storage device including a clock correction circuit as described in any of the first aspects.

[0053] This disclosure provides a clock correction circuit, which includes at least one duty cycle correction sub-circuit. Each duty cycle correction sub-circuit includes a duty cycle adjustment circuit. The duty cycle adjustment circuit can increase or decrease the duty cycle of the input clock signal by delaying or advancing only the falling edge of the input clock signal, and outputs a corrected clock signal. In this disclosure, the output terminal of the first inverter unit in the duty cycle adjustment circuit is connected to the input terminal of the adjustment unit in the duty cycle adjustment circuit to achieve positive feedback control of the corrected clock signal, thereby improving the accuracy and efficiency of duty cycle correction. Furthermore, the clock correction circuit provided in this disclosure can adjust the duty cycle only on the falling edge of the input clock signal, thereby avoiding adjustment conflicts with the delay chain and making it more advantageous to combine the delay chain to adjust the rising edge of the clock signal to achieve clock signal alignment. Attached Figure Description

[0054] Figure 1 This is a schematic diagram of the structure of a clock correction circuit provided in an embodiment of the present disclosure;

[0055] Figure 2 This is a schematic diagram of the structure of a duty cycle correction sub-circuit provided in an embodiment of the present disclosure;

[0056] Figure 3 This is a schematic diagram of the structure of a duty cycle adjustment circuit provided in an embodiment of the present disclosure;

[0057] Figure 4 This is a schematic diagram of a step size control circuit provided in an embodiment of the present disclosure;

[0058] Figure 5 A timing diagram of the clock signal provided in an embodiment of this disclosure;

[0059] Figure 6 This is a schematic flowchart of a clock correction method provided in an embodiment of the present disclosure. Detailed Implementation

[0060] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0061] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0062] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0063] It should be understood that spatial relation terms such as “below,” “under,” “below,” “below,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “below” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0064] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0065] The block diagrams shown in the accompanying drawings are merely functional entities and do not necessarily correspond to physically independent entities. That is, these functional entities can be implemented in software, or in one or more software-hardened modules, or in different network and / or processor devices and / or microcontroller devices.

[0066] The storage devices involved in the embodiments of this disclosure may include dynamic random access memory (DRAM), and are particularly suitable for double data rate synchronous dynamic random access memory using DDR4 memory specifications and DDR5 memory specifications, and low power double data rate synchronous dynamic random access memory using LPDDR4 memory specifications and LPDDR5 memory specifications. It should be noted that the embodiments of this disclosure are not limited to DRAM, but for clarity in the following description, only DRAM will be used as an example.

[0067] This disclosure provides a duty cycle correction circuit. Figure 1 This is a schematic diagram of a clock correction circuit provided in an embodiment of the present disclosure. Figure 2 This is a schematic diagram of the structure of a duty cycle correction sub-circuit provided in an embodiment of the present disclosure, combined with... Figure 1 and Figure 2 As shown, the clock correction circuit includes:

[0068] At least one duty cycle correction sub-circuit 10; each duty cycle correction sub-circuit 10 includes a duty cycle adjustment circuit 100; the duty cycle adjustment circuit 100 includes an adjustment unit 110 and a first inverter unit 120; the output terminal of the adjustment unit 110 is connected to the input terminal of the second inverter unit 120; the output terminal of the first inverter unit 120 is connected to the input terminal of the adjustment unit 110;

[0069] The duty cycle adjustment circuit 100 is configured to delay or advance the falling edge of the input clock signal to increase or decrease the duty cycle of the input clock signal, and output a corrected clock signal.

[0070] In this embodiment, the output of the first inverter unit in the duty cycle adjustment circuit is connected to the input of the adjustment unit in the duty cycle adjustment circuit to achieve positive feedback control of the corrected clock signal, thereby improving the accuracy and efficiency of duty cycle correction. Furthermore, the duty cycle correction circuit provided in this embodiment can adjust the duty cycle only on the falling edge of the input clock signal, thus avoiding conflicts with delay chain transmission adjustment and making it more advantageous to combine delay chain adjustment of the rising edge of the clock signal to achieve clock signal alignment.

[0071] In one specific example, the clock correction circuit provided in this disclosure embodiment can be a delay-locked loop (DLL) including a duty cycle correction (DCC) circuit; in another specific example, the clock correction circuit provided in this disclosure embodiment can be a clock correction circuit including a duty cycle correction circuit and a delay-locked loop.

[0072] In this embodiment, the duty cycle correction circuit includes multiple duty cycle correction sub-circuits connected in stages. The output of a preceding duty cycle correction sub-circuit is sequentially connected to the input of a subsequent duty cycle correction sub-circuit. This sequential connection of multiple duty cycle correction sub-circuits allows for further adjustment of the duty cycle by activating the next stage when one sub-circuit is insufficient to adjust the duty cycle to the desired range. This improves the correction capability of the duty cycle correction circuit and increases the adjustment range of the duty cycle. It should be noted that the corrected clock signal output from the preceding duty cycle correction sub-circuit serves as the input clock signal for the subsequent duty cycle correction sub-circuit.

[0073] In this embodiment of the disclosure, each duty cycle correction sub-circuit 10 further includes a step size control circuit 200;

[0074] The step size control circuit 200 is configured to control the adjustment step size of the duty cycle based on the duty cycle correction code;

[0075] The duty cycle adjustment circuit 100 is specifically configured to increase or decrease the duty cycle of the input clock signal by delaying or advancing the falling edge of the input clock signal based on the adjustment step size, and output the corrected clock signal.

[0076] Because current duty cycle correction circuits have a small duty cycle adjustment range and a single adjustment step size, this disclosure provides a clock correction circuit. This clock correction circuit includes at least one duty cycle correction sub-circuit, and each duty cycle correction sub-circuit includes a step size control circuit. This step size control circuit can control the adjustment step size of the duty cycle based on a duty cycle correction code. In other words, the clock correction circuit provided in this disclosure can adaptively adjust the adjustment step size of the duty cycle according to the clock frequency, thereby improving the adjustment range and efficiency of duty cycle correction.

[0077] This disclosure uses a delay phase-locked loop (DLL) including a duty cycle correction circuit (DCC) as an example for illustration. Furthermore, it describes an example where the DCC includes two duty cycle correction sub-circuits.

[0078] In this embodiment, the clock correction circuit further includes a phase comparison circuit 20, a delay chain 30, and a replica circuit 40. The replica circuit 40 is configured to replicate the actual delay of subsequent logic circuits, thereby incorporating the impact of subsequent logic circuits on the clock phase into the clock correction circuit and improving the reliability of clock correction. The replica circuit 40 delays the output clock signal generated by the delay chain 30 to generate a feedback clock signal. The phase comparison circuit 20 is configured to generate a delay control signal corresponding to the phase difference between the input clock signal and the feedback clock signal by detecting the phase difference between the input clock signal and the feedback clock signal. The delay chain 30 is configured to adjust the rising edge of the corrected clock signal generated by the duty cycle correction circuit after duty cycle correction according to the delay control signal, and generate an output clock signal to align the phase of the feedback clock signal with the phase of the input clock signal. In the clock correction circuit provided in this embodiment, the delay chain adjusts the rising edge of the clock signal to achieve phase alignment between the feedback clock signal and the input clock signal. In combination with the duty cycle correction circuit, the duty cycle can be adjusted only on the falling edge of the input clock signal, thereby avoiding the conflict between duty cycle adjustment and phase adjustment, which is more conducive to achieving clock signal alignment.

[0079] In some embodiments, the phase comparison circuit 20 includes a phase detector 21 and a delay chain control circuit 22. The input clock signal of the DLL is delayed by a delay chain to generate an output clock signal. The output clock signal is delayed by a replication circuit to generate a feedback clock signal. Both the feedback clock signal and the input clock signal are input to the phase detector. The phase detector compares the input clock and the feedback clock and outputs the comparison result (phase difference) to the delay chain control circuit. The delay chain control circuit generates a delay control signal corresponding to the phase difference based on the comparison result to adjust the delay of the delay chain, thereby aligning the phase of the feedback clock signal with the input clock signal and achieving an output clock signal with a specific delay requirement relative to the input clock signal.

[0080] In some embodiments, the delay chain 30 includes a coarse delay chain (CDL) 31 and a fine delay chain (FDL) 32, which are connected in series.

[0081] In this embodiment, each duty cycle correction sub-circuit 10 further includes a first node NO1 and a second node NO2; the step size control circuit 200 includes a parallel multi-state inverter unit 210 and a second inverter unit 220; the input terminal of the second inverter unit 220 is connected to the first node NO1, and the output terminal of the second inverter unit 220 is connected to the second node NO2; the input terminal of the first inverter unit 220 is connected to the second node NO2. Here, as... Figure 2As shown, the output terminal of the second inverter unit 220 is connected to the input terminal of the first inverter unit 120.

[0082] In this embodiment of the disclosure, in each duty cycle correction sub-circuit 10, the first node NO1 is used to receive the input clock signal, the second inverter unit 220 inverts the input clock signal and outputs it to the second node NO2, and the duty cycle adjustment circuit 100 generates the corrected clock signal of the duty cycle correction sub-circuit 10 based on the signal output by the first inverter unit and the signal at the second node NO2. It should be noted that the corrected clock signal of the duty cycle correction sub-circuit 10 is output by the duty cycle adjustment circuit.

[0083] Figure 3 This is a schematic diagram of a duty cycle adjustment circuit provided in an embodiment of the present disclosure, as shown below. Figure 3 As shown in this embodiment, the adjustment unit 110 includes a pull-up unit and a pull-down adjustment unit; the pull-up unit includes two PMOS transistors P2 and P3 connected in series; the pull-down adjustment unit includes a first NMOS transistor N1 and a first parallel NMOS transistor B. <m:0>The first parallel NMOS transistor B <m:0>This includes m+1 NMOS transistors connected in parallel. It should be noted that... Figure 3 The following explanation uses an example of a first parallel NMOS transistor configuration consisting of six NMOS transistors connected in parallel. Figure 3 As shown, the first parallel NMOS transistor B<6:0> includes 6 parallel NMOS transistors, namely NMOS transistor B<6:0>. <0> NMOS transistor B <1> NMOS transistor B <2> NMOS transistor B <3> NMOS transistor B <4> and NMOS transistor B <5> .

[0084] In this embodiment of the disclosure, the pull-up unit does not have the function of adjusting the duty cycle of the input clock signal.

[0085] Combination Figure 1 and Figure 3 As shown, the source terminals of two series-connected PMOS transistors P2 and P3 are configured to receive the power supply voltage VDD. Each NMOS transistor in the first parallel NMOS transistor B<6:0> has a gate terminal, a source terminal, and a drain terminal. The source terminal of each NMOS transistor in the first parallel NMOS transistor B<6:0> is configured to receive the ground voltage VSS, and the drain terminal is connected to the source terminal of the first NMOS transistor N1. The drain terminal of PMOS transistor P2 is connected to the drain terminal of the first NMOS transistor N1, and the drain terminals of PMOS transistor P2 and the drain terminals of the first NMOS transistor N1 are connected to the second node NO2. The gate terminals of PMOS transistor P2 and the first NMOS transistor N1 are connected to the output terminal of the first inverter unit 120.

[0086] In this embodiment of the disclosure, the duty cycle correction code further includes a first pull-down code input to the pull-down adjustment unit;

[0087] The duty cycle adjustment circuit 100 is specifically configured to control the first parallel NMOS transistor B based on the first pull-down code. <m:0>The duty cycle adjustment circuit 100 can be configured to control the on / off state of PMOS transistors P2 and P3 based on the first pull-up code.

[0088] In this embodiment of the disclosure, the first parallel NMOS transistor B can be controlled. <m:0>The number of NMOS transistors in the circuit is adjusted to delay or advance the falling edge of the input clock signal, thereby increasing or decreasing the duty cycle. Here, whether increasing or decreasing the duty cycle, the adjustment step size output by the step control circuit is used as the step size. The following examples, Example 1 and Example 2, illustrate the increase or decrease of the duty cycle.

[0089] Example 1: By reducing the number of parallel NMOS transistors B <m:0>The number of NMOS transistors turned on in the circuit shifts the rising edge of the clock signal at the second node NO2 forward, which in turn shifts the falling edge of the corrected clock signal output by the first-stage duty cycle correction circuit forward, thereby reducing the duty cycle of the clock signal.

[0090] Example 2: By adding a first parallel NMOS transistor B <m:0>The number of NMOS transistors turned on in the circuit delays the rising edge of the clock signal at the second node NO2, which in turn delays the falling edge of the corrected clock signal output by the first-stage duty cycle correction circuit, thereby increasing the duty cycle of the clock signal.

[0091] Figure 4 This is a schematic diagram of a step size control circuit provided in an embodiment of the present disclosure, as shown below. Figure 4 As shown in this embodiment, the multi-state inverter unit 210 includes a pull-up control unit and a pull-down control unit; the pull-up control unit includes a first PMOS transistor P1 and parallel PMOS transistors P <n:0>The parallel PMOS transistor P <n:0>It includes n+1 parallel PMOS transistors; the pull-down control unit includes a second NMOS transistor N2 and a second parallel NMOS transistor N <n:0>The second parallel NMOS transistor N <n:0>This includes n+1 NMOS transistors connected in parallel. It should be noted that... Figure 4 This explanation will take the example of a parallel PMOS transistor configuration consisting of five PMOS transistors connected in parallel, and a parallel NMOS transistor configuration consisting of five NMOS transistors connected in parallel. Figure 4 As shown, the parallel PMOS transistor P<4:0> configuration includes five PMOS transistors connected in parallel, namely PMOS transistor P<4:0>. <0> PMOS transistor P <1> PMOS transistor P <2> PMOS transistor P <3> and PMOS transistor P <4> The second parallel NMOS transistor N<4:0> includes five parallel NMOS transistors, namely NMOS transistor N<4:0>. <0> NMOS transistor <1> NMOS transistor <2> NMOS transistor <3> and NMOS transistor N <4> .

[0092] Combination Figure 2 and Figure 4 As shown, each PMOS transistor in the parallel PMOS transistor P<4:0> has a gate, a source, and a drain. The source of each PMOS transistor in the parallel PMOS transistor P<4:0> is configured to receive the power supply voltage VDD, and the drain is connected to the source of the first PMOS transistor P1. Each NMOS transistor in the second parallel NMOS transistor N<4:0> has a gate, a source, and a drain. The source of each NMOS transistor in the second parallel NMOS transistor N<4:0> is configured to receive the ground voltage VSS, and the drain is connected to the source of the second NMOS transistor N2. The drain of the first PMOS transistor P1 is connected to the drain of the second NMOS transistor N2. The gates of the first PMOS transistor P1 and the second NMOS transistor N2 serve as the input terminals of the multi-state inverter unit 210, connected to the first node NO1, for receiving the input clock signal.

[0093] In this embodiment of the disclosure, the duty cycle correction code includes a second pull-up code input to the pull-up control unit and a second pull-down code input to the pull-down control unit; the step size control circuit 200 is specifically configured to control the parallel PMOS transistor P based on the second pull-up code. <n:0>The switching on or off of each PMOS transistor, and the control of the second parallel NMOS transistor N based on the second pull-down code. <n:0>The duty cycle is controlled by turning each NMOS transistor on or off.

[0094] Here, the correction code generation unit is configured to generate a duty cycle correction code (DCC_code) based on the duty cycle information. In other words, the correction code generation unit can adjust the code value of the duty cycle correction code DCC_code in response to the duty cycle information. The duty cycle correction code DCC_code includes a second pull-up code input to the pull-up control unit and a second pull-down code input to the pull-down control unit. The second pull-up code and the second pull-down code are respectively used to control the parallel PMOS transistor P. <n:0>Second parallel NMOS transistor N <n:0>.

[0095] In this embodiment of the disclosure, the parallel PMOS transistor P <n:0>Second parallel NMOS transistor N <n:0>In this system, MOSFETs can be grouped together using one PMOS and one NMOS transistor, and controlled as a unit. For example, ... Figure 4 As shown, PMOS transistor P <0> and NMOS transistor N <0> A group of MOS transistors, PMOS transistor P <1> and NMOS transistor N <1> A group of MOS transistors, ..., PMOS transistor P <4> and NMOS transistor N <4> This refers to a group of MOSFETs. When controlling a group of MOSFETs, the switching states of this group of MOSFETs are consistent, i.e., PMOS transistor P... <0> and NMOS transistor N <0> When both are turned on or off simultaneously, the PMOS transistor P <1> and NMOS transistor N <1> Simultaneous on or off, ..., PMOS transistor P <4> and NMOS transistor N <4> They can be turned on or off simultaneously. It should be noted that although the parallel PMOS transistors P... <n:0>Second parallel NMOS transistor N <n:0>Control is performed on a group of MOSFETs, but the PMOS transistors are connected in parallel. <n:0>Second parallel NMOS transistor N <n:0>Control is achieved through the second pull-up code and the second pull-down code, respectively.

[0096] In this embodiment of the disclosure, the parallel PMOS transistor P can be controlled. <n:0>The number of switches for each PMOS transistor and the second parallel NMOS transistor N <n:0>The duty cycle adjustment step size is adjusted by changing the number of switches of each NMOS transistor. Examples 3 and 4 below illustrate the adjustment control of the duty cycle adjustment step size.

[0097] Example 3: By controlling the parallel PMOS transistor P <n:0>Second parallel NMOS transistor N <n:0>When all PMOS and NMOS transistors are turned on simultaneously, the second pull-up code is <0, 0, 0, 0, 0> and the second pull-down code is <1, 1, 1, 1, 1>. This speeds up the edge rate of the clock signal, i.e., reduces the rise and fall times of the clock signal, thereby reducing the duty cycle adjustment step size.

[0098] Example 4: By controlling the parallel PMOS transistor P <n:0>Second parallel NMOS transistor N <n:0>When all PMOS and NMOS transistors in the circuit are turned off simultaneously, the second pull-up code is <1, 1, 1, 1, 1> and the second pull-down code is <0, 0, 0, 0, 0>. This reduces the edge rate of the clock signal, i.e. increases the rise and fall times of the clock signal, thereby increasing the duty cycle adjustment step size.

[0099] In this embodiment of the present disclosure, the parallel PMOS transistor P can be controlled by the second pull-up code. <n:0>The number of switches for each PMOS transistor and the control of the second parallel NMOS transistor N via the second pull-down code. <n:0>The number of switches for each NMOS transistor changes the drive strength of the step size control circuit 200, which in turn changes the edge rate of the clock signal, thereby changing the adjustment step size and achieving multi-adjustable step size control. It should be noted that Example 3 describes... Figure 4 Example 4 describes the minimum adjustment step size of the step size control circuit 200 shown. Figure 4 The step size control circuit 200 shown is configured to adjust the step size to its maximum value. It should also be noted that this is achieved by controlling the parallel PMOS transistor P... <n:0>Second parallel NMOS transistor N <n:0>By simultaneously turning on some PMOS transistors and some NMOS transistors, an intermediate adjustment step size can be achieved between the minimum adjustment step size in Example 3 and the maximum adjustment step size in Example 4.

[0100] In some embodiments, parallel PMOS transistor P <n:0>The specifications of the individual PMOS transistors in the circuit can be different, and the second parallel NMOS transistor N... <n:0>The specifications of the individual NMOS transistors in the circuit can be different. Thus, by controlling the on / off state of various NMOS transistors with different specifications, various adjustment step sizes can be achieved. Figure 4 The step size control circuit 200 shown is used as an example for explanation. The parallel PMOS transistor P in the step size control circuit 200 <n:0>The specifications of each PMOS transistor in the circuit are different, and the second parallel NMOS transistor N... <n:0>When the specifications of each NMOS transistor are different, it is possible to achieve 2 5 The adjustment step size of the duty cycle.

[0101] With a fixed clock frequency, the duty cycle adjustment step size can be controlled by the step size control circuit 200, thereby changing the adjustment range of the duty cycle. For example, when the duty cycle of the input clock signal is 20%, a larger adjustment step size can be used for coarse adjustment, while when the duty cycle of the input clock signal is 44%, a smaller adjustment step size can be used for fine adjustment.

[0102] When the clock frequency is not fixed, the step size control circuit 200 can be used to control the adjustment step size of the duty cycle to ensure the correction accuracy of the duty cycle. For example, a smaller adjustment step size is used at high frequencies, while a larger adjustment step size is used at low frequencies.

[0103] The step size control circuit 200 provided in this embodiment can be applied to fine and coarse tuning when the clock frequency is fixed, and it can also be applied to fine and coarse tuning when the clock frequency is not fixed, so it has a wide range of applications.

[0104] Figure 5 The timing diagram of the clock signal provided in the embodiments of this disclosure should be noted as follows: Figure 5 Let's take increasing the duty cycle of the input clock signal as an example. Figure 5 As shown, clock-out is the corrected clock signal output by the first-stage duty cycle correction circuit provided in this embodiment, which delays the falling edge of the input clock signal by one adjustment step. clock-in is the input clock signal. At time TI, clock-in is high, and the clock signal at the second node NO2 is low. At this time, the clock signal output by the first-stage duty cycle correction circuit is high. The pull-down adjustment unit is then controlled by the first pull-down code, turning on the NMOS transistor in the first parallel NMOS transistor. At time T2, clock-in changes from high to low. Due to the hysteresis voltage characteristic, clock-out output by the first-stage duty cycle correction circuit is still high. Therefore, the NMOS transistor in the first parallel NMOS transistor in the pull-down adjustment unit is still on. As a result, under the influence of the pull-down adjustment unit, the clock signal at the second node NO2 will be delayed from low to high (rising edge delay). At time T3, the clock signal at the second node NO2 changes from low to high. The falling edge of clock-out output by the first-stage duty cycle correction circuit is delayed. Therefore, the duty cycle of the corrected clock signal output by the first-stage duty cycle correction circuit is increased relative to the input clock signal.

[0105] In this embodiment of the disclosure, the duty cycle correction circuit further includes: a duty cycle detection unit (not shown in the figure), configured to detect the duty cycle information of the initial input clock signal and the output clock signal of each duty cycle correction sub-circuit 10, and output the corrected duty cycle information output by the initial input clock signal and each duty cycle correction sub-circuit 10; and a correction code generation unit (not shown in the figure), configured to generate a duty cycle correction code for a first-stage duty cycle correction sub-circuit based on the duty cycle information of the initial input clock signal, and, in the case where the duty cycle correction circuit includes multiple duty cycle correction sub-circuits connected in stages, generate a duty cycle correction code for a subsequent-stage duty cycle correction sub-circuit based on the corrected duty cycle information output by the preceding-stage duty cycle correction sub-circuit.

[0106] In this embodiment of the disclosure, this method of connecting multiple duty cycle correction sub-circuits in stages allows for further adjustment of the duty cycle by activating the next stage duty cycle correction sub-circuit when one sub-circuit is insufficient to adjust the duty cycle to the desired range. Therefore, the correction code generation unit can generate the duty cycle correction code for the subsequent duty cycle correction sub-circuit based on the duty cycle information of the output clock signal of the preceding duty cycle correction sub-circuit. Here, the duty cycle information can be the duty cycle value of the clock signal. This improves the correction capability of the duty cycle correction circuit and increases the adjustment range of the duty cycle.

[0107] Here, the initial input clock signal is the clock signal for the first-stage duty cycle correction circuit.

[0108] In this embodiment of the present disclosure, the correction code generating unit is further configured to determine the duty cycle based on the duty cycle information output by the duty cycle detection unit; if the duty cycle is within a first preset range, a fine duty cycle correction code is output; if the duty cycle is outside the first preset range, a coarse duty cycle correction code is output.

[0109] In some embodiments, the first preset range is 40%-60%. In this embodiment, if the duty cycle is within the 40%-60% range, fine duty cycle correction is performed on the input clock signal; if the duty cycle is outside the 40%-60% range, coarse duty cycle correction is performed on the input clock signal. Here, fine duty cycle correction means performing duty cycle correction with a small adjustment step size, and coarse duty cycle correction means performing duty cycle correction with a large adjustment step size.

[0110] In this embodiment of the disclosure, the step size control circuit 200 is specifically configured to control the adjustment step size of the duty cycle based on the fine duty cycle correction code, and / or based on the coarse duty cycle correction code; wherein the adjustment step size corresponding to the fine duty cycle correction code is smaller than the adjustment step size corresponding to the coarse duty cycle correction code. For example, the second pull-up code <0,0,0,0,0> and the second pull-down code <1,1,1,1,1> described in Example 3 are fine duty cycle correction codes, and the second pull-up code <1,1,1,1,1> and the second pull-down code <0,0,0,0,0> described in Example 4 are coarse duty cycle correction codes, and the adjustment step size corresponding to the fine duty cycle correction code is smaller than the adjustment step size corresponding to the coarse duty cycle correction code.

[0111] This disclosure provides a clock correction circuit, which includes at least one duty cycle correction sub-circuit. Each duty cycle correction sub-circuit includes a duty cycle adjustment circuit. The duty cycle adjustment circuit can increase or decrease the duty cycle of the input clock signal by delaying or advancing only the falling edge of the input clock signal, and outputs a corrected clock signal. In this disclosure, the output terminal of the first inverter unit in the duty cycle adjustment circuit is connected to the input terminal of the adjustment unit in the duty cycle adjustment circuit to achieve positive feedback control of the corrected clock signal, thereby improving the accuracy and efficiency of duty cycle correction. Furthermore, the duty cycle correction circuit provided in this disclosure can adjust the duty cycle only on the falling edge of the input clock signal, thereby avoiding adjustment conflicts with the delay chain and making it more advantageous to combine the delay chain to adjust the rising edge of the clock signal to achieve clock signal alignment.

[0112] Based on the same technical concept as the aforementioned clock correction circuit, this disclosure provides a clock correction method. Figure 6 This is a flowchart illustrating a clock correction method provided in an embodiment of the present disclosure. It should be noted that... Figure 6 The following explanation uses a clock correction circuit, comprising two duty cycle correction sub-circuits connected in stages, as an example. Figure 6 As shown, the clock calibration method includes the following steps:

[0113] Step 601: Detect the duty cycle of the initial input clock signal using the duty cycle detection unit, and output the duty cycle information of the initial input clock signal;

[0114] Step 602: Use the correction code generation unit to generate the duty cycle correction code of the first-stage duty cycle correction sub-circuit based on the duty cycle information of the initial input clock signal;

[0115] Step 603: Use the step size control circuit of the first-stage duty cycle correction sub-circuit to control the adjustment step size of the duty cycle based on the duty cycle correction code;

[0116] Step 604: Using the duty cycle adjustment circuit of the first-stage duty cycle correction sub-circuit, based on the adjustment step size output by the step size control circuit of the first-stage duty cycle correction sub-circuit, the falling edge of the input clock signal is delayed or advanced to increase or decrease the duty cycle of the input clock signal, and the corrected clock signal is output; and the corrected clock signal is fed back to the adjustment unit in the duty cycle adjustment circuit.

[0117] Step 605: Adjust the rising edge of the corrected clock signal output by the first-stage duty cycle corrector circuit using a delay chain, and generate an output clock signal.

[0118] Step 606: Use the duty cycle detection unit to detect the duty cycle of the output clock signal of the delay chain, and output the duty cycle information of the output clock signal;

[0119] Step 607: Use the correction code generation unit to generate the duty cycle correction code for the second-stage duty cycle correction sub-circuit based on the duty cycle information of the output clock signal;

[0120] Step 608: Use the step size control circuit of the second-stage duty cycle correction sub-circuit to control the adjustment step size of the duty cycle based on the duty cycle correction code;

[0121] Step 609: Using the duty cycle adjustment circuit of the second-stage duty cycle correction sub-circuit, based on the adjustment step size output by the step size control circuit of the second-stage duty cycle correction sub-circuit, the falling edge of the input clock signal is delayed or advanced to increase or decrease the duty cycle of the input clock signal, and the corrected clock signal is output; and the corrected clock signal is fed back to the adjustment unit in the duty cycle adjustment circuit.

[0122] Here, when the clock correction circuit includes two duty cycle correction sub-circuits connected in stages, the corrected clock signal output by the second-stage duty cycle correction sub-circuit is the final corrected clock signal.

[0123] In some embodiments, each duty cycle correction sub-circuit further includes a first node and a second node; the first node is used to receive an input clock signal; the step size control circuit includes a parallel multi-state inverter unit and a second inverter unit; the input terminal of the second inverter unit is connected to the first node, and the output terminal of the second inverter unit is connected to the second node; the input terminal of the first inverter unit is connected to the second node.

[0124] Steps 604 and 609 include:

[0125] The second inverter unit inverts the input clock signal and outputs it to the second node. The duty cycle adjustment circuit generates the corrected clock signal of the duty cycle correction sub-circuit based on the signal output by the first inverter unit and the signal at the second node.

[0126] In some embodiments, the multi-state inverter unit includes a pull-up control unit and a pull-down control unit; the pull-up control unit includes a first PMOS transistor and a parallel PMOS transistor, the parallel PMOS transistor including a plurality of PMOS transistors connected in parallel; the pull-down control unit includes a second NMOS transistor and a second parallel NMOS transistor, the second parallel NMOS transistor including a plurality of NMOS transistors connected in parallel; the duty cycle correction code includes a second pull-up code input to the pull-up control unit and a second pull-down code input to the pull-down control unit;

[0127] Steps 603 and 608 include:

[0128] The step size control circuit uses the second pull-up code to control the opening or closing of each PMOS transistor in the parallel PMOS transistors, and the second pull-down code to control the opening or closing of each NMOS transistor in the second parallel NMOS transistors, so as to achieve control of the duty cycle adjustment step size.

[0129] In some embodiments, the adjustment unit includes a pull-down adjustment unit; the pull-down adjustment unit includes a first NMOS transistor and a first parallel NMOS transistor, the first parallel NMOS transistor including a plurality of parallel NMOS transistors; the duty cycle correction code includes a first pull-down code input to the pull-down adjustment unit;

[0130] Steps 604 and 609 include:

[0131] The duty cycle adjustment circuit uses the first pull-down code to control the opening or closing of each NMOS transistor in the first parallel NMOS transistors, thereby delaying or advancing the falling edge of the input clock signal.

[0132] In some embodiments, steps 602 and 607 include:

[0133] The duty cycle is determined by the correction code generation unit based on the duty cycle information output by the duty cycle detection unit; if the duty cycle is within a first preset range, a fine duty cycle correction code is output; if the duty cycle is outside the first preset range, a coarse duty cycle correction code is output.

[0134] In some embodiments, steps 603 and 608 include:

[0135] The step size control circuit uses the fine duty cycle correction code to control the adjustment step size of the duty cycle, and / or uses the coarse duty cycle correction code to control the adjustment step size of the duty cycle; wherein the adjustment step size corresponding to the fine duty cycle correction code is smaller than the adjustment step size corresponding to the coarse duty cycle correction code.

[0136] It should be noted that the description of the clock correction method above is similar to the description of the clock correction circuit embodiment above, and has similar beneficial effects as the clock correction circuit embodiment, therefore it will not be repeated. For technical details not disclosed in the duty cycle correction method of this disclosure embodiment, please refer to the description of the duty cycle correction circuit in this disclosure embodiment for understanding.

[0137] This disclosure also provides a storage device, including the clock correction circuit described above.

[0138] In some embodiments, the storage device is a dynamic random access memory.

[0139] In some embodiments, the dynamic random access memory conforms to the DDR2 memory specification.

[0140] In some embodiments, the dynamic random access memory conforms to the DDR3 memory specification.

[0141] In some embodiments, the dynamic random access memory conforms to the DDR4 memory specification.

[0142] In some embodiments, the dynamic random access memory conforms to the DDR5 memory specification.

[0143] In some embodiments, the dynamic random access memory conforms to the LPDDR4 memory specification.

[0144] In some embodiments, the dynamic random access memory conforms to the LPDDR5 memory specification.

[0145] This disclosure also provides a storage system, including: the storage device described above and a controller coupled to the storage device.

[0146] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0147] The features disclosed in the several device embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new device embodiments.

[0148] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A clock correction circuit, characterized in that, include: At least one duty cycle correction sub-circuit; each duty cycle correction sub-circuit includes a duty cycle adjustment circuit; The duty cycle adjustment circuit includes an adjustment unit and a first inverter unit; The output terminal of the adjustment unit is connected to the input terminal of the first inverter unit; the output terminal of the first inverter unit is connected to the input terminal of the adjustment unit. The duty cycle adjustment circuit is configured to delay or advance the falling edge of the input clock signal to increase or decrease the duty cycle of the input clock signal, and output a corrected clock signal. Each duty cycle correction sub-circuit also includes a step size control circuit; The step size control circuit is configured to control the adjustment step size of the duty cycle based on the duty cycle correction code; the duty cycle adjustment circuit is specifically configured to increase or decrease the duty cycle of the input clock signal by delaying or advancing the falling edge of the input clock signal based on the adjustment step size, and output the corrected clock signal. Each duty cycle correction sub-circuit also includes a first node and a second node; The step size control circuit includes a parallel multi-state inverter unit and a second inverter unit; the input terminal of the second inverter unit is connected to the first node, and the output terminal of the second inverter unit is connected to the second node; the input terminal of the first inverter unit is connected to the second node. The multi-state inverter unit includes a pull-up control unit and a pull-down control unit; The pull-up control unit includes a first PMOS transistor and a parallel PMOS transistor, wherein the parallel PMOS transistor includes multiple PMOS transistors connected in parallel; the pull-down control unit includes a second NMOS transistor and a second parallel NMOS transistor, wherein the second parallel NMOS transistor includes multiple NMOS transistors connected in parallel.

2. The clock correction circuit according to claim 1, characterized in that, Also includes: Phase comparator circuit, delay chain, and replication circuit; The replication circuit is configured to delay the output clock signal generated by the delay chain to generate a feedback clock signal; The phase comparison circuit is configured to generate a delay control signal corresponding to the phase difference by detecting the phase difference between the input clock signal and the feedback clock signal; The delay chain is configured to adjust the rising edge of the corrected clock signal according to the delay control signal to generate an output clock signal so that the feedback clock signal is phase-aligned with the input clock signal.

3. The clock correction circuit according to claim 1, characterized in that, The adjustment unit includes a pull-down adjustment unit; The pull-down adjustment unit includes a first NMOS transistor and a first parallel NMOS transistor, wherein the first parallel NMOS transistor includes a plurality of NMOS transistors connected in parallel.

4. The clock correction circuit according to claim 3, characterized in that, The duty cycle correction code includes a first pull-down code input to the pull-down adjustment unit; The duty cycle adjustment circuit is specifically configured to control the on or off of each NMOS transistor in the first parallel NMOS transistor based on the first pull-down code, so as to delay or advance the falling edge of the input clock signal.

5. The clock correction circuit according to claim 1, characterized in that, The duty cycle correction code includes a second pull-up code input to the pull-up control unit and a second pull-down code input to the pull-down control unit; The step size control circuit is specifically configured to control the on or off of each PMOS transistor in the parallel PMOS transistors based on the second pull-up code, and to control the on or off of each NMOS transistor in the second parallel NMOS transistors based on the second pull-down code, so as to achieve control of the duty cycle adjustment step size.

6. The clock correction circuit according to any one of claims 1-5, characterized in that, Also includes: The duty cycle detection unit is configured to detect the duty cycle information of the initial input clock signal and the output clock signal of each duty cycle correction sub-circuit, and output the duty cycle information of the initial input clock signal and the corrected clock signal output by each duty cycle correction sub-circuit. The correction code generation unit is configured to generate a duty cycle correction code for a first-stage duty cycle correction sub-circuit based on the duty cycle information of the initial input clock signal, and, in the case where the duty cycle correction circuit includes multiple duty cycle correction sub-circuits connected in stages, generate a duty cycle correction code for a subsequent-stage duty cycle correction sub-circuit based on the corrected duty cycle information output by the previous-stage duty cycle correction sub-circuit.

7. A clock calibration method, characterized in that, The clock correction circuit includes at least one duty cycle correction sub-circuit; wherein each duty cycle correction sub-circuit includes a duty cycle adjustment circuit; the duty cycle adjustment circuit includes an adjustment unit and a first inverter unit; the method includes: The duty cycle of the input clock signal is increased or decreased by delaying or advancing the falling edge of the input clock signal using a duty cycle adjustment circuit, and a corrected clock signal is output. The first inverter unit in the duty cycle adjustment circuit outputs the corrected clock signal, and the corrected clock signal is fed back to the adjustment unit in the duty cycle adjustment circuit. Each duty cycle correction sub-circuit also includes a step size control circuit; The step size control circuit is configured to control the adjustment step size of the duty cycle based on the duty cycle correction code; the duty cycle adjustment circuit is specifically configured to increase or decrease the duty cycle of the input clock signal by delaying or advancing the falling edge of the input clock signal based on the adjustment step size, and output the corrected clock signal. Each duty cycle correction sub-circuit also includes a first node and a second node; The step size control circuit includes a parallel multi-state inverter unit and a second inverter unit; the input terminal of the second inverter unit is connected to the first node, and the output terminal of the second inverter unit is connected to the second node; the input terminal of the first inverter unit is connected to the second node. The multi-state inverter unit includes a pull-up control unit and a pull-down control unit; The pull-up control unit includes a first PMOS transistor and a parallel PMOS transistor, wherein the parallel PMOS transistor includes multiple PMOS transistors connected in parallel; the pull-down control unit includes a second NMOS transistor and a second parallel NMOS transistor, wherein the second parallel NMOS transistor includes multiple NMOS transistors connected in parallel.

8. The clock correction method according to claim 7, characterized in that, The clock correction circuit further includes a phase comparison circuit, a delay chain, and a replication circuit; the method further includes: The replication circuit delays the output clock signal generated by the delay chain to generate a feedback clock signal. The phase comparison circuit uses the phase difference detection between the input clock signal and the feedback clock signal to generate a delay control signal corresponding to the phase difference. The delay chain is used to adjust the rising edge of the corrected clock signal according to the delay control signal to generate an output clock signal, so that the feedback clock signal is phase-aligned with the input clock signal.

9. The clock correction method according to claim 7, characterized in that, The method further includes: The step size control circuit is used to control the adjustment step size of the duty cycle based on the duty cycle correction code; The method of using a duty cycle adjustment circuit to delay or advance the falling edge of the input clock signal to increase or decrease the duty cycle of the input clock signal and outputting a corrected clock signal includes: The duty cycle adjustment circuit increases or decreases the duty cycle of the input clock signal by delaying or advancing the falling edge of the input clock signal based on the adjustment step size, and outputs the corrected clock signal.

10. The clock correction method according to claim 9, characterized in that, The step of using the first inverter unit in the duty cycle adjustment circuit to output the corrected clock signal includes: The second inverter unit inverts the input clock signal and outputs it to the second node. The duty cycle adjustment circuit generates the corrected clock signal of the duty cycle correction sub-circuit based on the signal output by the first inverter unit and the signal at the second node.

11. The clock correction method according to claim 10, characterized in that, The adjustment unit includes a pull-down adjustment unit; the pull-down adjustment unit includes a first NMOS transistor and a first parallel NMOS transistor, the first parallel NMOS transistor including a plurality of parallel NMOS transistors; the duty cycle correction code includes a first pull-down code input to the pull-down adjustment unit; The method of using a duty cycle adjustment circuit to delay or advance the falling edge of the input clock signal to increase or decrease the duty cycle of the input clock signal includes: The duty cycle adjustment circuit uses the first pull-down code to control the opening or closing of each NMOS transistor in the first parallel NMOS transistors, thereby delaying or advancing the falling edge of the input clock signal.

12. The clock correction method according to claim 10, characterized in that, The duty cycle correction code includes a second pull-up code input to the pull-up control unit and a second pull-down code input to the pull-down control unit; The method of using the step size control circuit to control the adjustment step size of the duty cycle based on the duty cycle correction code includes: The step size control circuit uses the second pull-up code to control the opening or closing of each PMOS transistor in the parallel PMOS transistors, and the second pull-down code to control the opening or closing of each NMOS transistor in the second parallel NMOS transistors, so as to achieve control of the duty cycle adjustment step size.

13. The clock correction method according to claim 7, characterized in that, The clock correction circuit further includes a duty cycle detection unit and a correction code generation unit; the method further includes: The duty cycle detection unit detects the duty cycle of the initial input clock signal and the output clock signal of each duty cycle correction sub-circuit, and outputs the duty cycle information of the initial input clock signal and the corrected clock signal output by each duty cycle correction sub-circuit. The duty cycle correction code of the first-stage duty cycle correction sub-circuit is generated by the correction code generation unit based on the duty cycle information of the initial input clock signal. In the case that the duty cycle correction circuit includes multiple duty cycle correction sub-circuits connected in stages, the duty cycle correction code of the subsequent-stage duty cycle correction sub-circuit is generated based on the duty cycle information of the corrected clock signal output by the previous-stage duty cycle correction sub-circuit.

14. A storage device, characterized in that, Includes the clock correction circuit as described in any one of claims 1 to 6.

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