Multi-bit level shifter and method of operation thereof

Abstract

The present disclosure relates to a multi-bit level shifter and a method of operating the same. A multi-bit level shifter (MBLS) includes two or more input circuits respectively configured to operate in a first voltage domain. The MBLS further includes two or more single-bit level shifters (SBLS) respectively electrically coupled with the two or more input circuits and respectively configured to operate in a second voltage domain. The MBLS further includes a control circuit configured to switch each of the two or more SBLS between a normal state and a standby state according to a switching control signal received from the control circuit.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more specifically, to multi-bit level shifters and methods of operating thereof. Background Technology

[0002] Integrated circuits (ICs) sometimes comprise multiple sections corresponding to multiple independently controlled power domains. In some cases, a first power domain includes a first power supply voltage level, and a second power domain includes a second power supply voltage level different from the first power supply voltage level. A level shifter is used to propagate signals between these sections, shifting logic levels between the first and second power supply voltage levels.

[0003] In digital electronics, level shifters (also known as logic level shifters or voltage level converters) are circuits used to convert signals from one logic level or voltage domain to another, thereby promoting compatibility between ICs with different voltage requirements (such as transistor-to-transistor logic (TTL) and complementary metal-oxide-semiconductor (CMOS)). Level shifters serve as a link between domains of processors, logic, sensors, and other circuits. Summary of the Invention

[0004] One aspect of this disclosure relates to a circuit for a semiconductor device, comprising: two or more input circuits configured to operate in a first voltage domain; two or more one-bit level shifters (SBLS) electrically coupled to the two or more input circuits and configured to operate in a second voltage domain; and a control circuit configured to cause each of the two or more SBLSs to switch between a normal state and a standby state upon receiving a control signal from the control circuit.

[0005] Another aspect of this disclosure relates to an integrated circuit (IC) comprising: a first N-well (NW) located at the intersection of a vertical axis and a horizontal axis; a second NW located on a first side of the vertical axis along the horizontal axis; a third NW located on a second side of the vertical axis along the horizontal axis; a first power node configured to have a first power supply voltage; a second power node configured to have a second power supply voltage; a third power node configured to have a third power supply voltage; and an input circuit configured to receive an input signal in a first voltage domain, the input circuit comprising: a first PMOS transistor located in the first NW, and the first PMOS transistor including a first source / drain (S / D) terminal coupled to the first power node; and a second PMOS transistor located in the first NW, and the second PMOS transistor including a second source / drain (S / D) terminal coupled to the first power node. The input / output (S / D) terminals; and at least two one-bit level shifters (SBLS), including: a first SBLS comprising a third PMOS transistor in the second NW, the third PMOS transistor comprising a third S / D terminal coupled to the second power node; and a second SBLS comprising a fourth PMOS transistor in the third NW, the fourth PMOS transistor comprising a fourth S / D terminal coupled to the second power node; wherein the first SBLS and the second SBLS are configured to receive corresponding input signals from the input circuit and to convert the corresponding input signals from the first voltage domain to the second voltage domain; and a control circuit electrically coupled to the first SBLS and the second SBLS, the control circuit being configured to switch the first SBLS and the second SBLS between a normal mode and a standby mode according to a switching control signal.

[0006] Another aspect of this disclosure relates to a method of operating a plurality of one-bit level shifters (SBLS), the method comprising: receiving a first power supply voltage and a second power supply voltage, the second power supply voltage being between the first power supply voltage and a third power supply voltage; receiving input from a first voltage domain operating under the first power supply voltage at two or more input circuits electrically connected to the first power supply voltage; outputting a version of the input from the first voltage domain from the two or more input circuits to two or more corresponding SBLS operating in a second voltage domain and electrically connected to the second power supply voltage; correspondingly converting the version of the input from the first voltage domain to the second voltage domain via the two or more SBLS; receiving a switching control signal from a control circuit at each of the two or more corresponding SBLS; and switching the two or more corresponding SBLS between a normal mode and a standby mode based on the switching control signal. Attached Figure Description

[0007] The various aspects of this disclosure can be best understood by reading the following detailed description in conjunction with the accompanying drawings. According to industry standard practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features can be arbitrarily increased or decreased.

[0008] Figure 1 This is a block diagram of an integrated circuit according to some embodiments.

[0009] Figure 2 It is a block diagram of a region that couples two voltage domains according to some embodiments.

[0010] Figure 3 This is a block diagram of a multi-bit level shifter (MBLS) having two one-bit level shifters (SBLS) according to some embodiments.

[0011] Figure 4 This is a block diagram of an MBLS with four SBLSs according to some embodiments.

[0012] Figure 5 This is a block diagram of an MBLS with eight SBLS according to some embodiments.

[0013] Figure 6 This is a block diagram of the first voltage domain NWELL (FNW) according to some embodiments.

[0014] Figure 7 These are block diagrams of two SBLS according to some embodiments.

[0015] Figure 8 This is a layout diagram of an MBLS circuit structure based on some embodiments.

[0016] Figure 9A , Figure 9B , Figure 9C and Figure 9D This is a layout diagram of the SBLS circuit structure according to some embodiments.

[0017] Figure 10 This is a table based on some embodiments.

[0018] Figure 11 This is a flowchart of a method for converting data between voltage domains according to some embodiments.

[0019] Figure 12 This is a flowchart of a method for manufacturing a semiconductor device according to some embodiments.

[0020] Figure 13 This is a block diagram of an electronic design automation (EDA) system according to some embodiments.

[0021] Figure 14 This is a block diagram of an integrated circuit (IC) manufacturing system and its associated IC manufacturing process according to some embodiments. Detailed Implementation

[0022] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components, values, operations, materials, arrangements, etc., are described below to simplify this disclosure. Of course, these are merely examples and not intended to be limiting. Other components, values, operations, materials, arrangements, etc., can be considered. For example, in the following description, forming a first feature on or over a second feature can include embodiments where the first and second features are formed in direct contact, and can also include embodiments where an additional feature can be formed between the first and second features such that the first and second features do not need to be in direct contact. Additionally, reference numerals and / or letters may be repeated in various examples throughout this disclosure. Such repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0023] Furthermore, spatially related terms (e.g., "below," "under," "down," "above," "up," etc.) may be used herein to readily describe the relationship of one element or feature shown in the figure relative to another element(s) or feature(s). These spatially related terms are intended to cover different orientations of the device in use or operation other than those shown in the figure. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially related descriptors used herein shall be interpreted accordingly.

[0024] In some embodiments, a multi-bit level shifter (MBLS) is a circuit that includes a plurality of single-bit level shifters (SBLS) (each SBLS being a corresponding circuit) and a plurality of corresponding input circuits, wherein the plurality of SBLSs share a common control circuit, each of the plurality of SBLSs has a corresponding second voltage domain N-well (SNW), and the plurality of input circuits share a first voltage domain N-well (FNW). In some embodiments, the MBLS serves as a voltage domain interface in a semiconductor device having multiple voltage domains (e.g., power supplies). In some embodiments, the MBLS is used for parallel data / address signal transmission. In some embodiments, a single control circuit is used to switch the operation of the MBLS between, for example, a normal state and a standby state. Therefore, all SBLSs in the MBLS share a single control circuit. In some embodiments, the normal state is described as a response mode, and the standby state is described as a non-response mode. In some embodiments, in the response mode, the single control circuit controls the MBLS to generate an output signal having values ​​corresponding to the values ​​of the input signals to the MBLS. In some embodiments, in a no-response mode, a single control circuit controls the MBLS to generate output signals with static values, such that all output signals of the MBLS have either a high logic level or a low logic level regardless of the value of the input signal to the MBLS, making the MBLS unresponsive to changes in the value of the input signal to the MBLS. In some embodiments, one of the SBLS has a shared SNW with the control circuit. According to another approach, multiple SBLS and multiple control circuits are provided in a one-to-one (1:1) ratio, i.e., each SBLS has a corresponding control circuit. Furthermore, according to another approach, each SBLS includes three NWs: a first NW for the SBLS, a second NW for the input circuit, and a third NW that is (actually) a pseudo-NW. In some embodiments, the advantage of having a single control circuit for multiple SBLS share an NW and / or having multiple SBLS share an NW compared to the other approach is reduced power consumption and area usage. In some embodiments, a power saving of 17% or greater is achieved for two SBLS compared to the other approach. In some embodiments, an area saving of 39% or greater is achieved by having two SBLS share a single control circuit compared to the other approach. In some embodiments, in MBLS, power and area savings continue to be achieved as the number of bits increases from 2 bits to 4 bits, 8 bits, or more.

[0025] In some embodiments, each input circuit in an input circuit that receives data to be converted from one voltage domain to another shares a common field number (FNW) within an MBLS, and a field number (SNW) is located around this centralized FNW. In some embodiments, the SNWs are arranged symmetrically with respect to the FNW. In some embodiments, SBLSs that output data that has been converted from one voltage domain to another share the SNW located around the centralized FNW. Additionally or alternatively, each additional SNW supports one or more SBLSs.

[0026] Figure 1 This is a block diagram of an integrated circuit according to some embodiments.

[0027] exist Figure 1 In some embodiments, IC 100 includes: a region 102 operating in a first voltage domain, a region 104 operating in a second voltage domain, and a region including one or more circuits (e.g., MBLS). Figure 2 Area 106 of the circuitry is used to adjust the data level from one voltage domain to another.

[0028] In some embodiments, IC 100 is also referred to as a chip or microchip. Alternatively or additionally, IC 100 is a set of electronic circuits on a flat piece of semiconductor material, typically silicon. In some embodiments, IC 100 integrates a large number of tiny metal-oxide-semiconductor (MOS) transistors into a chiplet, thereby producing circuits that are orders of magnitude smaller, faster, and cheaper than circuits made of discrete electronic components.

[0029] In some embodiments, IC 100 includes a group of electronic circuits correspondingly configured to operate in a region 102 including a first voltage domain. Figure 2 Alternatively or concurrently, IC 100 also includes a group of electronic circuits configured to operate in region 104, which includes a second voltage domain. Figure 2 In some embodiments, the first voltage domain operates at a voltage higher or lower than that of the second voltage domain. In some embodiments, the difference between the voltage domains may be large or small. In some embodiments, the electronic circuit ( Figure 2 This includes individual electronic components such as resistors, transistors, capacitors, inductors, and diodes, which are connected by conductive lines or traces through which current flows. Alternatively or additionally, the combination of components and wires performs a variety of simple and / or complex operations, such as amplifying signals, performing calculations, performing logic operations, moving data from one location to another, etc.

[0030] In some embodiments, region 106 is configured to convert data having a level corresponding to a first voltage domain to data having a level corresponding to a second voltage domain. Additionally or alternatively, region 106 includes one or more MBLSs, which include a single control circuitry as follows (see...). Figure 2 This single control circuit is configured to switch the operation of the MBLS between a normal state (or mode) (discussed below) and a standby state (or mode) (discussed below). Alternatively or additionally, the control circuit selectively switches the transistors of each MBLS, the cells of each MBLS, or even the entire circuitry of each MBLS.

[0031] In some embodiments, the normal state is described as a responsive mode, and the standby state is described as a non-responsive mode. In some embodiments, the normal state is described as a responsive mode because the value of the MBLS output signal responds accordingly to changes in the value of the input signal to the MBLS. In some embodiments, the standby state is described as a non-responsive mode because the value of the MBLS output signal is static; for example, all output signals of the MBLS are either at a high logic level or all are at a low logic level, therefore, the value of the MBLS output signal does not respond accordingly to changes in the value of the input signal to the MBLS. In some embodiments, the normal mode and the non-responsive mode are respectively described as an enabled mode and a disabled mode. In some embodiments, the normal mode and the non-responsive mode are respectively described as an ON mode and an OFF mode.

[0032] In some embodiments, sleep mode is a low-power mode for electronic devices such as ICs, computers, and semiconductor devices. Additionally or alternatively, low-power modes significantly reduce power consumption compared to keeping the device fully powered. In some embodiments, for ICs, entering sleep mode is roughly equivalent to pausing the IC at a given point. Additionally or alternatively, upon resumption, operation continues from the given point. In some embodiments, for ICs, sleep mode is synonymous with standby and idle. In some embodiments, control circuitry disconnects the power supply to the SBLS (i.e., the SBLS) and places the SBLS in a minimum power state.

[0033] In some embodiments, IC 100 includes region 106 for coupling region 102 to region 104 or region 104 to region 102. Additionally or alternatively, region 106 includes two or more input circuits correspondingly configured to operate in a first voltage domain (see [link to relevant documentation]). Figure 2 Each data input circuit handles a data signal representing a single bit. Therefore, since region 106 includes multiple data input circuits, region 106 is described as the multi-bit (MB) portion of IC 100. In some embodiments, region 106 also includes two or more SBLS (Multi-Bit Subsystems). Figure 2 These SBLSs are electrically coupled to two or more input circuits respectively and are accordingly configured to operate in a second voltage domain. Additionally or alternatively, region 106 also includes a single control circuit for each SBLS. Figure 2 The control circuit is configured to perform switching. In some embodiments, region 106 includes one or more MBLS.

[0034] Figure 2 This is a block diagram of region 206, which couples two voltage domains according to some embodiments.

[0035] In some embodiments, region 206 is configured to convert data from a first voltage domain 202 into data that operates in a second voltage domain 204. In some embodiments, region 206 is similar to region 106, the first voltage domain 102 is similar to the first voltage domain 202, and the second voltage domain 104 is similar to the second voltage domain 204. Alternatively or additionally, region 206 includes one or more MBLS 200s, each including a single control circuit 280 configured to switch SBLS 222A and 222B between a normal state and a standby state based on a control signal TOGL signal 207 received by the control circuit 280. In some embodiments, another circuit in the second voltage domain 204 (not shown, e.g., a power management circuit) generates the TOGL signal 207.

[0036] In some embodiments, the first voltage domain 202 includes one or more general-purpose circuits 203, which are configured to operate in the region including the first voltage. Alternatively, the second voltage domain 204 also includes one or more general-purpose circuits 205, which are configured to operate in the region including the second voltage. In some embodiments, the one or more general-purpose circuits 203 and 205 include individual electronic components, such as resistors, transistors, capacitors, inductors, and diodes, which are connected by conductive lines or traces through which current flows. Alternatively, the combination of components and wires performs various simple and / or complex operations, such as amplifying signals, performing calculations, performing logical operations, moving data from one location to another, etc. Regardless of the specific function performed by the one or more general-purpose circuits 203, the one or more general-purpose circuits 203 output a data signal to the second voltage domain 204. After level shifting (discussed below), the output signal of the one or more general-purpose circuits 203 is provided as a corresponding input signal to the one or more general-purpose circuits 205.

[0037] In some embodiments, MBLS 200 is configured to level-adjust data received from one or more general-purpose circuits 203 (which have a level corresponding to a first voltage domain 202) such that the data, after being leveled, has a level corresponding to a second voltage domain 204, and then provide the data to one or more general-purpose circuits 205. In some embodiments, the first voltage domain 202 is approximately 0.6V, and the second voltage domain 204 is approximately 0.9V. Alternatively or additionally, MBLS 200 is configured to include common FNW 250, SNW 208, 212, control circuitry 280, SBLS 222A and 222B, and input circuitry 216, 218.

[0038] In some embodiments, input circuits 216 and 218 receive data bits from one or more general-purpose circuits 203 in the first voltage domain 202 to be converted to another voltage domain, such as the second voltage domain 204. In some embodiments, each input circuit 216 and 218 accepts one data bit (e.g., whose corresponding value represents logic zero (0) or logic one (1)). Additionally or alternatively, MBLS 200 supports two voltage levels (e.g., 0.6V and 0.9V). In some embodiments, MBLS 200 is sufficiently robust to operate using two voltage levels (e.g., 0.6V and 0.9V). In some embodiments, MBLS 200 is compatible with two voltage levels (e.g., 0.6V and 0.9V). In some embodiments, FNW 250 includes a voltage input for the first voltage domain, and SNW 208 and 212 include a voltage input for the second voltage domain. In some embodiments, the output of each of SBLS 222A and 222B is a corresponding data bit input at input circuits 216 and 218, but converted to another voltage domain. A TOGL signal 207 is received by control circuitry 280. In some embodiments, control circuitry 280 generates a delayed version of TOGL signal 207 (i.e., signal TOGLd 782) and distributes it to each of SBLS 222A and 222B. Signal TOGLd 782 causes each of SBLS 222A and 222B to switch between a normal mode and a standby mode. In some embodiments, using one control circuitry 280 for multiple SBLS 222 saves power and area within MBLS 200.

[0039] In some embodiments, NWs (e.g., FNWs and SNWs) are N-type semiconductor regions produced by doping an intrinsic semiconductor with an electron donor element during manufacturing. Additionally or alternatively, the N-type originates from the negative charge of electrons. In some embodiments, electrons are the majority carriers and holes are the minority carriers in the N-type semiconductor. Additionally or alternatively, the dopant used for N-type silicon is phosphorus or arsenic. In some embodiments, depending on the respective NW and / or the respective voltage domain, the substrate is P-type and connected (body biased) to Vss, and the N-type NW is connected (body biased) to Vss. DD or V DDL .

[0040] Figure 3 This is a block diagram of an MBLS 300 having two SBLS 322A and 322B according to some embodiments.

[0041] MBLS 300 includes two instances of SBLS (discussed below), namely, MBLS 300 is multi-bit and therefore similar to MBLS 200. In some embodiments, MBLS 300 is used in region 106 of IC 100. In some embodiments, MBLS 300 includes an FNW 350 located at the intersection of vertical axis 304 and horizontal axis 306. In some embodiments, vertical axis 304 is positioned anywhere along horizontal boundary 301A, and in some embodiments, horizontal axis 306 is positioned anywhere along vertical boundary 301B. In some embodiments, MBLS 300 also includes an SNW 308 located on a first side 310 of vertical axis 304 along horizontal axis 306 and an SNW 312 located on a second side 314 of vertical axis 304 along horizontal axis 306. In some embodiments, horizontal axis 306 bisects each of SNW 308 and SNW 312. In some embodiments, horizontal axis 306 bisects FNW 350. In some embodiments, SNW 308 and SNW 312 are positioned along the vertical axis 304. In some embodiments, the vertical axis 304 and the horizontal axis 306 are shown as bisecting MBLS 300.

[0042] Alternatively or concurrently, the MBLS 300 also includes components configured to have a first supply voltage (e.g., V). DDL The first power node (see) Figure 6 (670). In some embodiments, the first power node is at a first voltage domain voltage (V DDL And it is located within the common FNW 350. In some embodiments, the MBLS 300 also includes a second voltage domain voltage (e.g., V). DD The second power node (see) Figure 7(770). Alternatively or concurrently, a second power supply is located within SNW 308 and / or SNW 312. In some embodiments, MBLS 300 further includes input circuitry 316, which includes a first PMOS transistor (see 770). Figure 6 The first PMOS transistor (P1) is located in FNW 350 and on the first side 310 of the vertical axis 304, and the first PMOS transistor includes a first source / drain (S / D) terminal coupled to the first power node. Figure 6 Furthermore, the MBLS 300 also includes an input circuit 318, which includes a second PMOS transistor (see...). Figure 6 The second PMOS transistor (P12) is located in FNW 350 and on the second side 314 of the vertical axis 304, and the second PMOS transistor includes a second S / D terminal coupled to the first power node. Figure 6 ), wherein input circuits 316 and 318 are configured to receive input signals having voltage levels corresponding to a first voltage domain (see Figure 6 Data-1, Data-2).

[0043] Alternatively or concurrently, the MBLS 300 also includes the SBLS 322A, which includes a third PMOS transistor (see...). Figure 7 The third PMOS transistor is located in SNW 308 (P5), and the third PMOS transistor includes coupling to the second power node (see P5). Figure 7 The third S / D terminal of the 770) Figure 7 ); and the fourth PMOS transistor (see Figure 7 The fourth PMOS transistor is located in SNW 308, and the fourth PMOS transistor includes a fourth S / D terminal coupled to the second power node. Figure 7 ), wherein SBLS 322A receives a data output signal from input circuit 316 and converts the data output signal from a level having a first voltage domain to a level having a second voltage domain.

[0044] Alternatively or concurrently, the MBLS 300 also includes the SBLS 322B, which includes a fifth PMOS transistor (see...). Figure 7 The fifth PMOS transistor (P16) is located in SNW 312, and the fifth PMOS transistor includes coupling to the second power node (see P16). Figure 7 The fifth S / D terminal of the 770) Figure 7 ); and the sixth PMOS transistor (see Figure 7The sixth PMOS transistor (P17) is located in SNW 312, and the sixth PMOS transistor includes a sixth S / D terminal coupled to the second power node. Figure 7 ), wherein SBLS 322B receives a data output signal from input circuit 318 and converts the data output signal from a level having a first voltage domain to a level having a second voltage domain.

[0045] In some embodiments, the MBLS 300 further includes a control circuit 380 electrically coupled to the SBLS 322A and 322B, and the control circuit 380 is configured to generate a TOGLd signal based on the TOGL signal 307. Figure 7 The 782) outputs to each of the SBLS322A and 322B, which allows the SBLS 322A and 322B to switch between normal and standby states. Figure 3 In this embodiment, control circuitry 380 is partially located within SNW 308. Alternatively, control circuitry 380 is partially located within SNW 312. In some embodiments, control circuitry 380 is electrically coupled to a second power node (see [link to SNW 308]). Figure 7 770). In some embodiments, the control circuit 380 includes the SNW 308 ( Figure 7 This can be a PMOS transistor within SNW 312. Alternatively, control circuitry 380 outputs a TOGLd signal, which, when sent to SBLS 322A and 322B, causes each SBLS 322 to switch between normal and standby states. SBLS 322A is located at SNW 308, and another SBLS 322B is located at SNW 312.

[0046] In some embodiments, each input (e.g., data-1, data-2) arrives at a level corresponding to a first voltage domain (e.g., V). DDL The input circuits 316 and 318. Alternatively, the input circuits 316 and 318 then output at V in a manner corresponding to SBLS 322A and 322B. DDL The data signals (e.g., ib1, ibb1, ib2, ibb2). In some embodiments, SBLS 322A and 322B acquire the data signals (e.g., ib1, ibb1, ib2, ibb2) received from input circuits 316 and 318, and convert them to a state at V DDL The output data signals (e.g., Z1, Z2). Alternatively or alternatively, Z1 (i.e., at V) DD ) represents data -1 (i.e., in V) DDL Z2 (i.e., at V) DD ) represents data -2 (i.e., at V)DDL V DD (That is, Z1 and Z2) are the level shift representations of the corresponding data-1 and data-2.

[0047] Figure 4 This is a block diagram of an MBLS 400 having four SBLS 422A, 422B, 422C and 422D according to some embodiments.

[0048] MBLS 400 includes four instances of SBLS (discussed below), meaning MBLS 400 is multi-bit and therefore similar to MBLS 200 and 300. In some embodiments, MBLS 400 is used in region 106 of IC 100. In some embodiments, MBLS 400 is similar to MBLS 200 and 300, except that MBLS 400 is configured to convert four inputs from a first voltage domain to a second voltage domain, while MBLS 200 and 300 are configured to convert two inputs from the first voltage domain to the second voltage domain.

[0049] In some embodiments, MBLS 400 includes an FNW 450 located at the intersection of a vertical axis 404 and a horizontal axis 406. Alternatively or additionally, MBLS 400 also includes an SNW 408 located on a first side 410 of the vertical axis 404 along the horizontal axis 406 and an SNW 412 located on a second side 414 of the vertical axis 404 along the horizontal axis 406. In some embodiments, the horizontal axis 406 bisects each of SNW 408 and SNW 412. In some embodiments, the horizontal axis 406 bisects the FNW 450. In some embodiments, SNW 408 and SNW 412 are positioned along the vertical axis 404. In some embodiments, the vertical axis 404 and the horizontal axis 406 are shown as bisecting MBLS 400.

[0050] Alternatively or concurrently, the MBLS 400 also includes components configured to have a first supply voltage (e.g., V). DDL The first power node (see) Figure 6 (670). In some embodiments, the first power node is at a first voltage domain voltage (V DDL And it is located within the common FNW 450. In some embodiments, the MBLS 400 also includes a configuration having a second voltage domain voltage (e.g., V). DD The second power node (see) Figure 7 (770). Alternatively or concurrently, a second power supply is located within SNW 408 and / or SNW412. In some embodiments, MBLS 400 further includes input circuitry 416, which includes a PMOS transistor (see 770). Figure 6The first PMOS transistor (P1) is located in FNW 450 and on the first side 410 of the vertical axis 404, and includes a first source / drain (S / D) terminal coupled to the first power node. Figure 6 The MBLS 400 also includes an input circuit 418, which includes a second PMOS transistor located in the FNW 450 on the second side 414 of the vertical axis 404 (see [link to relevant documentation]). Figure 6 The second PMOS transistor includes a second S / D terminal coupled to the first power node (P12), and the second PMOS transistor includes a second S / D terminal coupled to the first power node. Figure 6 The input circuits 416 and 418 are configured to receive input signals having voltage levels corresponding to the first voltage domain (see Data-1 and Data-4).

[0051] Alternatively or concurrently, the MBLS 400 also includes the SBLS 422A, which includes a third PMOS transistor (see...). Figure 7 The third PMOS transistor is located in SNW 408 (P5), and the third PMOS transistor includes coupling to the second power node (see P5). Figure 7 The third S / D terminal of the 770) Figure 7 ); and the fourth PMOS transistor (see Figure 7 The fourth PMOS transistor (see P6), Figure 7 The P6 transistor is located in the SNW 408, and the fourth PMOS transistor includes a fourth S / D terminal coupled to the second power node. Figure 7 ), wherein SBLS 422A receives a data output signal from input circuit 415 and converts the data output signal from a level having a first voltage domain to a level having a second voltage domain.

[0052] Alternatively or concurrently, the MBLS 400 also includes the SBLS 422B, which includes: a fifth PMOS transistor (see...). Figure 7 The fifth PMOS transistor (P16) is located in SNW 412, and the fifth PMOS transistor includes coupling to the second power node (see P16). Figure 7 The fifth S / D terminal of the 770) Figure 7 ); and the sixth PMOS transistor (see Figure 7 The sixth PMOS transistor (see P17), Figure 7 P17 is located in SNW 412, and the sixth PMOS transistor includes a sixth S / D terminal coupled to the second power node. Figure 7), wherein SBLS 422B receives a data output signal from input circuit 417 and converts the data output signal from a level having a first voltage domain to a level having a second voltage domain.

[0053] Alternatively or concurrently, the MBLS 400 also includes the SBLS 422C, which includes a seventh PMOS transistor (see...). Figure 7 The seventh PMOS transistor (P5) is located in SNW 408, and the seventh PMOS transistor includes a connection to the second power node (see P5). Figure 7 The seventh S / D terminal of the 770) Figure 7 ); and the eighth PMOS transistor (see Figure 7 The eighth PMOS transistor (see P6), Figure 7 The P6 of the PMOS transistor is located in SNW 408, and the eighth PMOS transistor includes an eighth S / D terminal coupled to the second power node. Figure 7 ), wherein SBLS 422C receives a data output signal from input circuit 416 and converts the data output signal from a level having a first voltage domain to a level having a second voltage domain.

[0054] Alternatively or concurrently, the MBLS 400 also includes the SBLS 422D, which includes: a ninth PMOS transistor (see...). Figure 7 (P16), the ninth PMOS transistor is located in SNW 412, and the ninth PMOS transistor includes coupling to the second power node (see P16). Figure 7 The ninth S / D terminal of the 770) Figure 7 ); and the tenth PMOS transistor (see Figure 7 The tenth PMOS transistor (P17) is located in SNW 412, and the tenth PMOS transistor includes a tenth S / D terminal coupled to the second power node. Figure 7 ), wherein SBLS 422D receives a data output signal from input circuit 418 and converts the data output signal from a level having a first voltage domain to a level having a second voltage domain.

[0055] In some embodiments, the MBLS 400 further includes control circuitry 480 electrically coupled to the SBLS 422A, 422B, 422C, and 422D, and the control circuitry 480 is configured to generate a TOGLd signal based on the TOGL signal 407. Figure 7The 782) is output to each of the SBLS 422A, 422B, 422C, and 422D, which allows the SBLS 422A, 422B, 422C, and 422D to switch between normal and standby states. Figure 4 In this embodiment, control circuitry 480 is partially located within SNW 408. Alternatively, control circuitry 480 is partially located within SNW 412. In some embodiments, control circuitry 480 is electrically coupled to a second power node (see [link to SNW 412]). Figure 7 770). In some embodiments, the control circuit 480 includes located at SNW 408 ( Figure 7 This can be a PMOS transistor within SNW 412. Alternatively, control circuitry 480 outputs a TOGLd signal, which, when sent to SBLS 422A, 422B, 422C, and 422D, causes each of SBLS 422A, 422B, 422C, and 422D to switch between normal and standby states. SBLS 422A and 422C are located at SNW 408, and another SBLS 422B and 422D are located at SNW 412.

[0056] In some embodiments, each input (e.g., data-1, data-2, data-3, and data-4) arrives at a level corresponding to a first voltage domain (e.g., V). DDL The input circuits 415, 416, 417, and 418. Alternatively or concurrently, the input circuits 415, 416, 417, and 418 then output values ​​at V in a manner corresponding to SBLS 422A, 422B, 422C, and 422D. DDL The data signals (e.g., ib1, ibb1, ib2, ibb2, ib3, ibb3, ib4, and ibb4). In some embodiments, SBLS 422A, 422B, 422C, and 422D acquire the data signals (e.g., ib1, ibb1, ib2, ibb2, ib3, ibb3, ib4, and ibb4) and convert them to a state at V DD The output data signals (e.g., Z1, Z2, Z3, and Z4). Alternatively or alternatively, Z1 (i.e., at V) DD ) represents data -1 (i.e., in V) DDL Z2 (i.e., at V) DD ) represents data -2 (i.e., at V) DDL Z3 (i.e., in V) DD ) represents the data -3 (i.e., at V). DDL Z4 (i.e., in V) DD ) represents the data -4 (i.e., at V). DDLTherefore, the output data signals Z1, Z2, Z3, and Z4 are level-shifted representations of the corresponding input data -1, data -2, data -3, and data -4.

[0057] Figure 5 This is a block diagram of an MBLS 500 having eight SBLS 522A, 522B, 522C, 522D, 522E, 522F, 522G and 522H according to some embodiments.

[0058] MBLS 500 comprises eight instances of SBLS (discussed below), meaning MBLS 500 is multi-bit and therefore similar to MBLS 200, 300, and 400. In some embodiments, MBLS 500 is used in region 106 of IC 100. In some embodiments, MBLS 500 is similar to MBLS 200, 300, and 400, except that MBLS 500 is configured to convert eight inputs from a first voltage domain to a second voltage domain, wherein MBLS 200 and 300 are configured to convert two inputs from the first voltage domain to the second voltage domain, and MBLS 400 is configured to convert four inputs from the first voltage domain to the second voltage domain.

[0059] In some embodiments, MBLS 500 includes FNW 550 located at the intersection of vertical axis 504 and horizontal axis 506. In some embodiments, MBLS 500 also includes SNW 508 and SNW 509 located on a first side 510 of vertical axis 504 along horizontal axis 506, and SNW 512 and SNW 511 located on a second side 514 of vertical axis 504 along horizontal axis 506. In some embodiments, horizontal axis 506 bisects each of SNW 508, 509, 511, and 512. In some embodiments, horizontal axis 506 bisects FNW 550. In some embodiments, SNW 508, 509, 511, and 512 are positioned along vertical axis 504. In some embodiments, vertical axis 504 and horizontal axis 506 are shown as bisecting MBLS 500.

[0060] Alternatively or concurrently, the MBLS 500 also includes components configured to have a first supply voltage (e.g., V). DDL The first power node (see) Figure 6 (670). In some embodiments, the first power node is at a first voltage domain voltage (V DDL And it is located within the common FNW 550. In some embodiments, the MBLS 500 also includes a second voltage domain voltage (e.g., V). DD The second power node (see) Figure 7(770). Alternatively or concurrently, a second power supply is located within SNWs 508, 509, 511, and 512. In some embodiments, the MBLS 500 further includes an input circuit 515A, which includes a first PMOS transistor (see 770). Figure 6 The first PMOS transistor (P1) is located in FNW 550 and on the first side 510 of the vertical axis 504, and the first PMOS transistor includes a first source / drain (S / D) terminal coupled to the first power node. Figure 6 The MBLS500 also includes an input circuit 517A, which includes a second PMOS transistor (see...). Figure 6 The second PMOS transistor (P12) is located in FNW 550 and on the second side 514 of the vertical axis 504, and the second PMOS transistor includes a second S / D terminal coupled to the first power node. Figure 6 ), wherein input circuits 515A, 515B, 516A, 516B, 517A, 517B, 518A and 518B are configured to receive input signals having voltage levels corresponding to a first voltage domain (see data-1, data-2, data-3, data-4, data-5, data-6, data-7 and data-8).

[0061] Alternatively or concurrently, the MBLS 500 also includes the SBLS 522A, which includes a third PMOS transistor (see...). Figure 7 The third PMOS transistor is located in SNW 508 (P5), and the third PMOS transistor includes coupling to the second power node (see P5). Figure 7 The third S / D terminal of the 770) Figure 7 ); and the fourth PMOS transistor (see Figure 7 The fourth PMOS transistor is located in the SNW 508 and includes a fourth S / D terminal coupled to the second power node (P6). Figure 7 ), wherein SBLS 522A receives a data output signal from input circuit 515A and converts the data output signal from a level having a first voltage domain to a level having a second voltage domain.

[0062] Alternatively or concurrently, the MBLS 500 also includes the SBLS 522B, which includes a fifth PMOS transistor (see...). Figure 7 The fifth PMOS transistor (P16) is located in SNW 512, and the fifth PMOS transistor includes coupling to the second power node (see P16). Figure 7 The fifth S / D terminal of the 770) Figure 7); and the sixth PMOS transistor (see Figure 7 The sixth PMOS transistor (P17) is located in SNW 512, and the sixth PMOS transistor includes a sixth S / D terminal coupled to the second power node. Figure 7 ), wherein SBLS 522B receives a data output signal from input circuit 517A and converts the data output signal from a level having a first voltage domain to a level having a second voltage domain.

[0063] Alternatively or concurrently, the MBLS 500 also includes the SBLS 522C, which includes a seventh PMOS transistor (see...). Figure 7 The seventh PMOS transistor (P5) is located in the SNW 508, and the seventh PMOS transistor includes a connection to the second power node (see P5). Figure 7 The seventh S / D terminal of the 770) Figure 7 ); and the eighth PMOS transistor (see Figure 7 The eighth PMOS transistor (P6) is located in the SNW 508, and the eighth PMOS transistor includes an eighth S / D terminal coupled to the second power node. Figure 7 ), wherein SBLS 522C receives a data output signal from input circuit 516A and converts the data output signal from a level having a first voltage domain to a level having a second voltage domain.

[0064] Alternatively or concurrently, the MBLS 500 also includes the SBLS 522D, which includes: a ninth PMOS transistor (see...). Figure 7 The ninth PMOS transistor (P16) is located in SNW 512, and the ninth PMOS transistor includes coupling to the second power node (see P16). Figure 7 The ninth S / D terminal of the 770) Figure 7 ); and the tenth PMOS transistor (see Figure 7 The tenth PMOS transistor (P17) is located in SNW 512, and the tenth PMOS transistor includes a tenth S / D terminal coupled to the second power node. Figure 7 ), wherein SBLS 522D receives a data output signal from input circuit 518A and converts the data output signal from a level having a first voltage domain to a level having a second voltage domain.

[0065] Alternatively or concurrently, the MBLS 500 also includes the SBLS 522E, which includes an eleventh PMOS transistor (see...). Figure 7The eleventh PMOS transistor (P5) is located in SNW 509, and the eleventh PMOS transistor includes coupling to the second power node (see P5). Figure 7 The eleventh S / D terminal of the 770) Figure 7 ); and the twelfth PMOS transistor (see Figure 7 The twelfth PMOS transistor (see P6), Figure 7 P6 is located in SNW 509, and the twelfth PMOS transistor includes a twelfth S / D terminal coupled to the second power node. Figure 7 ), wherein SBLS 522E receives a data output signal from input circuit 515B and converts the data output signal from a level having a first voltage domain to a level having a second voltage domain.

[0066] Alternatively or concurrently, the MBLS 500 also includes the SBLS 522F, which includes a thirteenth PMOS transistor (see...). Figure 7 The thirteenth PMOS transistor (see P16) Figure 7 P16 is located in SNW 511, and the thirteenth PMOS transistor includes a connection to the second power node (see [link]). Figure 7 The thirteenth S / D terminal of the 770) Figure 7 ); and the fourteenth PMOS transistor (see Figure 7 The fourteenth PMOS transistor (see P17), Figure 7 P17 is located in SNW 511, and the fourteenth PMOS transistor includes a fourteenth S / D terminal coupled to the second power node. Figure 7 ), wherein SBLS 522F receives a data output signal from input circuit 517B and converts the data output signal from a level having a first voltage domain to a level having a second voltage domain.

[0067] Alternatively or concurrently, the MBLS 500 also includes the SBLS 522G, which includes: a fifteenth PMOS transistor (see...). Figure 7 The fifteenth PMOS transistor (P5) is located in SNW 509, and the fifteenth PMOS transistor includes coupling to the second power node (see P5). Figure 7 The fifteenth S / D terminal of the 770) Figure 7 ); and the sixteenth PMOS transistor (see Figure 7 The sixteenth PMOS transistor (see P6), Figure 7 The P6 transistor is located in the SNW 509, and the sixteenth PMOS transistor includes a sixteenth S / D terminal coupled to the second power node. Figure 7 ), wherein SBLS 522G receives a data output signal from input circuit 516B and converts the data output signal from a level having a first voltage domain to a level having a second voltage domain.

[0068] Alternatively or concurrently, the MBLS 500 also includes the SBLS 522H, which includes: a seventeenth PMOS transistor (see...). Figure 7 The seventeenth PMOS transistor (see P16), Figure 7 P16 is located in SNW 511, and the seventeenth PMOS transistor includes a connection to the second power node (see [link]). Figure 7 The seventeenth S / D terminal of the 770) Figure 7 ); and the eighteenth PMOS transistor (see Figure 7 The eighteenth PMOS transistor (P17) is located in SNW 511, and the eighteenth PMOS transistor includes an eighteenth S / D terminal coupled to the second power node. Figure 7 ), wherein SBLS 522H receives a data output signal from input circuit 518B and converts the data output signal from a level having a first voltage domain to a level having a second voltage domain.

[0069] In some embodiments, the MBLS 500 further includes a control circuit 580 electrically coupled to the SBLS 522A, 522B, 522C, 522D, 522E, 522F, 522G, and 522H, and the control circuit 580 is configured to generate a TOGLd signal based on the TOGL signal 507. Figure 7 The 782) outputs to each of the SBLS 522A, 522B, 522C, 522D, 522E, 522F, 522G, and 522H, which allows the SBLS 522A, 522B, 522C, 522D, 522E, 522F, 522G, and 522H to switch between normal and standby states. Figure 5 In this embodiment, control circuitry 580 is partially located within SNW 508. Alternatively, control circuitry 580 may be partially located within SNW 512, SNW 509, or SNW 511. In some embodiments, control circuitry 580 is electrically coupled to a second power node (see [link to relevant documentation]). Figure 7 770). In some embodiments, control circuitry 580 includes components located at SNW 508 ( Figure 7The PMOS transistors are located in SNW 509, SNW 511, or SNW 512. Alternatively, control circuitry 580 outputs a TOGLd signal that, when sent to SBLS 522A, 522B, 522C, 522D, 522E, 522F, 522G, and 522H, causes each of SBLS 522A, 522B, 522C, 522D, 522E, 522F, 522G, and 522H to switch between normal and standby states. SBLS 522A and 522C are located at SNW 508, SBLS 522B and 522D at SNW 512, SBLS 522E and 522G at SNW 509, and SBLS 522F and 522H at SNW 511.

[0070] In some embodiments, each input (e.g., data-1, data-2, data-3, data-4, data-5, data-6, data-7, and data-8) arrives at a level corresponding to a first voltage domain (e.g., V). DDL The input circuits 515A, 515B, 516A, 516B, 517A, 517B, 518A, and 518B. Alternatively or concurrently, the input circuits 515A, 515B, 516A, 516B, 517A, 517B, 518A, and 518B then output at V in a manner corresponding to SBLS 522A, 522B, 522C, 522D, 522E, 522F, 522G, and 522H. DDL The data signals (e.g., ib1, ibb1, ib2, ibb2, ib3, ibb3, ib4, ibb4, ibb4, ib5, ibb5, ib6, ibb6, ib7, ibb7, ib8, and ibb8). In some embodiments, SBLS 522A, 522B, 522C, 522D, 522E, 522F, 522G, and 522H acquire data signals (e.g., ib1, ibb1, ib2, ibb2, ib3, ibb3, ib4, ibb4, ib5, ibb5, ib6, ibb6, ib7, ibb7, ib8, and ibb8) received from input circuits 515A, 515B, 516A, 516B, 517A, 517B, 518A, and 518B) and convert them to a state at V DD The output data signals (e.g., Z1, Z2, Z3, Z4, Z5, Z6, Z7, and Z8). Alternatively or concurrently, Z1 (i.e., at V...) DD ) represents data -1 (i.e., in V) DDL Z2 (i.e., at V) DD ) represents data -2 (i.e., at V) DDLZ3 (i.e., in V) DD ) represents the data -3 (i.e., at V). DDL Z4 (i.e., in V) DD ) represents the data -4 (i.e., at V). DDL Z5 (i.e., in V) DD ) represents the data -5 (i.e., at V). DDL Z6 (i.e., in V) DD ) indicates data -6 (i.e., at V) DDL Z7 (i.e., in V) DD ) indicates data -7 (i.e., at V) DDL And Z8 (i.e., in V) DD ) represents the data -8 (i.e., at V). DDL Z1, Z2, Z3, Z4, Z5, Z6, Z7 and Z8 are level-shifted representations of the corresponding data-1, data-2, data-3, data-4, data-5, data-6, data-7 and data-8.

[0071] Figure 6 This is a block diagram of the first voltage domain NWELL (FNW) 650 in a 2-bit MBLS according to some embodiments.

[0072] Alternatively or alternatively, the FNW 650 is similar to the FNW 250, 350, 450, and 550 of MBLS 200, 300, 400, and 500, and the input circuits 616 and 618 are similar to the input circuits 216, 218, 316, and 318. The FNW 650 is also similar to the FNW 450 because the FNW 650 includes a first input circuit and a second input circuit, for example, input circuits 616 and 618 corresponding to input circuits 415 and 417; the difference between the FNW 650 and the FNW 450 is that the FNW 650 does not include a third and fourth input circuit (for example, corresponding to additional input circuits 416 and 418). Alternatively or alternatively, the FNW 650 is similar to the FNW 550, but differs from the FNW 550 in that the FNW 650 has six fewer input circuits than the FNW 550.

[0073] In some embodiments, a data-1 signal is provided at input 660 of input circuit 616, and a data-2 signal is provided at input 662 of input circuit 618. From a first voltage domain such as voltage domain 102 (e.g., V... DDL The input circuits 616 and 618 receive data signals data-1 and data-2. Alternatively, the input circuits 616 and 618 include cascaded inverters 664A and 664B, and 668A and 668B.

[0074] In some embodiments, input circuitry 616 includes PMOS transistors P1-P2 and NMOS transistors N1-N2. Transistors P1 and N1 together represent inverter 664A. The gates of transistors P1 and N1 are coupled together and represent input 660 of inverter 664A. Specifically, transistor P1 is coupled between a first power node 670 and node nd01, which represents the output of inverter 664A, on which the data signal ib1 is provided. Transistor N1 is coupled between node nd01 and a third power node 690 (e.g., VSS).

[0075] Transistors P2 and N2 together represent inverter 664B. The gates of transistors P2 and N2 are coupled together and represent the input to inverter 664B, which is coupled to node nd01. Specifically, transistor P2 is coupled between the first power supply node 670 and node nd02, which represents the output of inverter 664B. Node nd02 also represents the output node of input circuit 616, on which signal ibb1 is provided.

[0076] In some embodiments, the input circuit 618 includes PMOS transistors P12-P13 and NMOS transistors N10-N13, as well as nodes nd03 and nd04. Depending on the arrangement or coupling, transistors P12-P13 and N10-N11 correspond to transistors P1-P2 and N1-N2, and nodes nd03-nd04 correspond to nodes nd01-nd02. A data signal ib2 is provided at node nd03. Node nd04 also represents an output node of the input circuit 618, on which the signal ibb2 is provided.

[0077] In some embodiments, the output of each of the inverters 664A, 664B, 668A, and 668B represents a voltage at the opposite logic level relative to the corresponding input voltage, i.e., inverting the signal received as an input. Additionally or alternatively, for each of the inverters 664A, 664B, 668A, and 668B, the output signal becomes high when the applied input signal is low, and vice versa. The inverters 664A, 664B, 668A, and 668B include NMOS transistors (correspondingly labeled N1, N2, N10, and N11) and PMOS transistors (correspondingly labeled P1, P2, P12, and P13).

[0078] In some embodiments, the first power node (e.g., an instance of power node 670) is configured to have a first power supply voltage (e.g., V). DDLAlternatively or additionally, input circuits 616, 618 respectively include PMOS transistors P1 and P2 and P12 and P13 located in FNW 650. In some embodiments, PMOS transistors P1 and P2 are located on a first side 610 of the vertical axis 604 and respectively include source / drain (S / D) terminals coupled to one or more power nodes 670. Alternatively or additionally, PMOS transistors P12 and P13 are located in FNW 650 and on a second side 614 of the vertical axis 604 and respectively include S / D terminals coupled to power nodes 670. In some embodiments, each of input circuits 616, 618 is configured to receive a voltage level (V) corresponding to a first voltage domain. DDL The corresponding input signals (e.g., data-1, data-2).

[0079] In some embodiments, the second power node (e.g., an instance of power node 690) is configured to have a second power supply voltage (e.g., VSS). Additionally or alternatively, the input circuits 616, 618 respectively include NMOS transistors N1 and N2, and N10 and N11, located outside the FNW 650. In some embodiments, NMOS transistors N1 and N2 are located on a first side 610 of the vertical axis 604 and respectively include source / drain (S / D) terminals coupled to the power node 690. Additionally or alternatively, NMOS transistors N10 and N11 are located outside the FNW 650 and on a second side 614 of the vertical axis 604 and include S / D terminals coupled to the power node 690.

[0080] In some embodiments, inverters 664A and 668A respectively receive data-1 and data-2 signals as inputs and respectively output inverted versions of data-1 and data-2 as outputs, i.e., as corresponding signals 1b1 and 1b2. That is, inverters 664 and 664 invert data-1 and data-2 into corresponding signals 1b1 and 1b2. Alternatively or additionally, if data-1 is high, then ib1 is low, and vice versa. In some embodiments, if data-2 is high, then ib2 is low, and vice versa. In some embodiments, inverters 664B and 668B then respectively invert the ib1 and ib2 inputs. Inverters 664B and 668B respectively receive ib1 and ib2 signals as inputs and respectively output inverted versions of ib1 and ib2 as outputs, i.e., as corresponding signals 1bb1 and 1bb2. That is, inverters 664 and 664 invert ib1 and ib2 into corresponding signals 1bb1 and 1bb2. Alternatively or concurrently, if ib1 is low, then ibb1 is high (e.g., similar to the original data-1 input), and vice versa. In some embodiments, if ib2 is low, then ibb2 is high (e.g., similar to the original data-2 input), and vice versa. Signals ibb1 and ibb2 accordingly have the same logic states as data-1 and data-2, but signals ibb1 and ibb2 are correspondingly delayed relative to data-1 and data-2. Alternatively or concurrently, cascaded inverters 664A and 664B, as well as 668A and 668B, act as corresponding buffers.

[0081] Figure 7 This is a block diagram of one SBLS 722A and 722B according to some embodiments.

[0082] Alternatively or concurrently, SBLS 722A and 722B are similar to SBLS 222, 322, 422, and 522 of MBLS 200, 300, 400, and 500, and control circuitry 780 is similar to control circuitry 280, 380, 480, and 580. In some embodiments, SNW 708 and SNW 712 are also similar to SNW 208, 212, 308, 312, 408, 412, 508, 509, 511, and 512, sharing the common feature of partially incorporating an SBLS (e.g., a PMOS transistor). In some embodiments, SNW 708 and 712 are also similar to FNW 408 and 412, the difference being that FNW 408 and 412 respectively include additional SBLS 422C and 422D. Alternatively or concurrently, in some embodiments, SNW 708 and 712 are similar to SNW 508, 509, 511 and 512, except that SNW 508, 509, 511 and 512 respectively include additional SBLS 522C, 522D, 522E, 522F, 522G and 522H.

[0083] In some embodiments, SNWs 708 and 712 are similar to SNWs 308 and 312. Alternatively or additionally, SNWs 708 and 712 are located within an MBLS, such as MBLS 200, 300, 400, or 500. In some embodiments, SNWs 708 and 712 are partially occupied, wherein SBLS 722A partially occupies SNW 708 and SBLS 722B partially occupies SNW 712. Alternatively or additionally, control circuitry 780 partially occupies SNW 708; however, control circuitry 780 is also configured to be partially located within SNW 712. In some embodiments, regardless of whether SNWs 708 and 712 are within MBLS 200, 300, 400, or 500, only one control circuitry is required for any MBLS. Alternatively or additionally, when sharing an SNW (such as...) Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 and Figure 7 As shown, limiting each MBLS circuit to a single control circuit helps reduce the amount of space required for the MBLS circuit, as well as the amount of power required, because fewer transistors are used compared to other methods.

[0084] In some embodiments, the control circuit 780 is controlled at the second power node 770 by V in the second voltage domain. DDPower supply. Alternatively or concurrently, control signal 707 (i.e., TOGL signal 707) is an input to control circuit 780 received from a second voltage domain (e.g., voltage domain 104). In some embodiments, control circuit 780 includes cascaded inverters 764A and 764B.

[0085] In some embodiments, the control circuit 780 includes PMOS transistors P10-P11 and NMOS transistors N7, N8, and N9. Transistors P10 and N8 together represent inverter 764A. The gates of transistors P10 and N8 are coupled together and represent input 7 of inverter 764A, which is coupled to node nd08, ​​providing a TOGL signal 707 at node nd08. Specifically, transistor P10 is coupled between a second power supply node 770 and node nd09, which represents the output of inverter 764A, providing a signal thereon. (Discussed below). Transistor N8 is coupled between node nd09 and third power supply node 790 (e.g., VSS). Node nd09 also represents the first output node of control circuitry 780.

[0086] Transistors P11 and N9 together represent inverter 764B. The gates of transistors P11 and N9 are coupled together and represent the input to inverter 764B, which is coupled to node nd09. Specifically, transistor P11 is coupled between the second power supply node 770 and node nd10, which represents the output of inverter 764B, on which the signal TOGLd (discussed below) is provided. Transistor N9 is coupled between node nd10 and the third power supply node 790. Node nd10 also represents the second output node of control circuitry 780.

[0087] Transistor N7 is coupled between node nd11 and the third power node 790. The gate terminal of the transistor is configured to receive the signal TOGLd (discussed below).

[0088] In some embodiments, each output of inverters 764A and 764B represents a voltage at the opposite logic level relative to the corresponding input voltage, even if the corresponding input signal is inverted. Inverter 764A receives the TOGL signal 707 and outputs an inverted version of the TOGL signal 707, i.e., the signal... Inverter 764B receives signals And output signal The inverted version of the TOGL signal 707 is the signal TOGLd. The TOGLd signal has the same logic state as the TOGL signal 707, but the TOGLd signal is delayed relative to the TOGL signal 707. Therefore, the suffix "d" indicates that the TOGLd signal is a delayed version of the TOGL signal 707. Alternatively or additionally, when the TOGL signal 707 is low, the signal TOGLd becomes high, and vice versa. In some embodiments, each of the inverters 764A and 764B includes a single NMOS transistor (labeled N8 and N9 respectively) and a single PMOS transistor (labeled P10 and P11 respectively). Alternatively or additionally, the cascaded inverters 764A and 764B together are used to buffer the TOGL signal 707 as an input to each of the SBLS 722A and 722B, wherein the buffered version of the TOGL signal 707 is the TOGLd signal.

[0089] In some embodiments, each instance of power node 770 is configured to have a second power supply voltage (e.g., V). DD Alternatively or concurrently, the control circuit 780 includes PMOS transistors P10 and P11 located in SNW 708. In some embodiments, each of PMOS transistors P10 and P11 includes an S / D terminal coupled to a corresponding instance of the power supply node 770.

[0090] In some embodiments, SNW 708 and SNW 712 are positioned along the horizontal or vertical axis of the MBLS, for example, as shown in the figure. Figure 3 , Figure 4 , Figure 5 and Figure 6 As shown. Alternatively or alternatively, SNW 708 and SNW 712 are positioned adjacent to each other, as shown. Figure 7 As shown. In some embodiments, the second power node 770 is configured to have a second power supply voltage (e.g., V). DD Alternatively or concurrently, SBLS 722A includes several PMOS transistors (P3, P4, P5, P6, P7, P8, and P9) located in SNW 708 and includes an S / D terminal coupled to a second power node 770. In some embodiments, SBLS 722B includes several other PMOS transistors (P14, P15, P16, P17, P18, P19, and P20) located in SNW 712 and includes an S / D terminal coupled to a second power node 770. In some embodiments, SBLS 722A and 722B receive input signals (e.g., ib1 and ibb1, and ib2 and ibb2) from input circuitry (e.g., input circuitry 616 and 618) and convert the input signals from a first voltage domain (e.g., V). DDL ) to switch to the second voltage domain (e.g., VDD Alternatively, the control circuit 780 is configured to switch SBLS722A and 722B between normal and standby states according to the TOGL signal 707.

[0091] exist Figure 7 In addition to PMOS transistors P3-P9, the SBLS 722A also includes NMOS transistors N3, N4, N5, and N6. Each of transistors P5-P9 has a coupling to the first power node 770 (V). DD The source terminals of the example are shown. Transistor P5 is coupled between the first power node 770 and node nd12. Transistor P3 is coupled between node nd12 and node nd14. Transistor N3 is coupled between node nd14 and node nd11. Transistor P6 is coupled between the first power node 770 and node nd13. Transistor P4 is coupled between node nd13 and node nd15. Transistor N4 is coupled between node nd15 and node nd11.

[0092] In SBLS 722A, the gate terminal of transistor P5 is coupled to node nd15. The gate terminal of transistor P6 is coupled to node nd14. In some embodiments, the gate terminals of transistors P5 and P6 are described as being cross-coupled relative to their respective nodes nd15 and nd14. The gate terminal of each of transistors P3 and N3 is coupled to signal ibb1. The gate terminal of each of transistors P4 and N4 is coupled to input signal ib1. Transistor P7 is coupled between the first power supply node 770 and node nd15.

[0093] Transistors P8 and N5 together represent an inverter. The gates of transistors P8 and N5 are coupled together and represent the input to the inverter, which is coupled to node nd15. Specifically, transistor P8 is coupled between the first power supply node 770 and node nd16, which represents the output of the inverter. Transistor N5 is coupled between node nd16 and the third power supply node 790.

[0094] Transistors P9 and N6 together represent an inverter. The gates of transistors P9 and N6 are coupled together and represent the input to the inverter, which is coupled to node nd16. Specifically, transistor P9 is coupled between the first power supply node 770 and node nd17, which represents the output of the inverter. Transistor N6 is coupled between node nd17 and the third power supply node 790. Node nd17 also represents the output node of the SBLS 722A, on which the output signal Z1 is provided.

[0095] exist Figure 7In addition to PMOS transistors P14-P20, the SBLS 722B also includes NMOS transistors N12, N13, N14, and N15, and nodes nd18, nd19, nd20, nd21, nd22, and nd23. Depending on the arrangement or coupling, transistors P14-P20 and N12-N15 correspond to transistors P3-P9 and N3-N6, and nodes nd18-nd23 correspond to nodes nd12-nd17. Node nd23 also represents the output node of the SBLS 722B, on which the output signal Z2 is provided.

[0096] exist Figure 7 In this configuration, when the signal TOGLd has a logic high value, SBLS 722A and 722B are controlled to operate in normal mode. When the signal TOGLd has a logic low value, SBLS 722A and 722B are controlled to operate in standby mode. The signal TOGLd is provided to the gate terminal of each of transistors N7, P7, and P18. For simplicity, the operation of transistors N7 and P7 related to the operation of SBLS 722A will be discussed in detail. It should be understood that the operation of transistors N7 and P18 related to the operation of SBLS 722B is similar to the operation of transistors N7 and P7 related to the operation of SBLS 722A.

[0097] In normal mode, when the signal TOGLd has a logic high value, transistor P7 is off and transistor N7 is on. When transistor P7 is off, it does not pull node nd15 up to V. DD When transistor N7 is turned on, transistor N7 attempts to pull node nd11 down to V. SS This means that (1) when transistor N3 is turned on, transistor N3 will conduct current to node nd11 and / or (2) when transistor N4 is turned on, transistor N4 will conduct current to node nd11.

[0098] The gate terminals of transistors N3 and N4 are configured to receive input signals ibb1 and ib1, respectively, with ibb1 being the inverse of ib1. When ibb1 has a logic high value, transistor N4 is turned on and transistor N3 is turned off, and vice versa. When transistor N4 is turned on, it pulls node nd15 to V through transistor N7. SS When node nd15 is pulled to V SS At this time, transistor P5 is turned on, thereby pulling node nd12 up to V. DD When transistor N4 is turned on, transistor N3 is turned off again; when transistor N3 is turned off, transistor P3 is turned on. Therefore, transistor P3 pulls node nd14 up to the voltage at node nd12, that is, pulls node nd14 up to V.DD When node nd14 is pulled up to V DD At this time, transistor P6 is turned off, therefore node nd13 will not be pulled up to V. DD When transistor N4 is on, transistor P4 is off, so transistor P4 will not attempt to pull node nd15 up to the voltage at node nd13.

[0099] In summary, regarding the normal mode, when transistor N4 is turned on due to the input signal ib1 having a logic high value, node nd15 is pulled down to V. SS When node n15 is in V SS When (i.e., logic low), node nd16 is pulled up to V. DD (That is, logic high level), and node nd17 is pulled to V. SS When node nd17 is pulled to V SS At this time, the output Z1 of the SBLS 722A is a logic low value, causing the output Z1 to follow the input signal ibb1 and be the inverted form of the input signal ib1. Therefore, in normal mode, the output Z1 of the SBLS 722A responds to changes in the logic levels of the input signals ib1 and ibb1. Furthermore, the input signals ib1 and ibb1 are actually converted from levels corresponding to the first power domain to corresponding output Z1 with levels corresponding to the second power domain.

[0100] When transistor N4 is turned off, transistor N3 turns on again; when transistor N3 is turned on, transistor N3 pulls node nd14 down to V through transistor N7. SS When node nd14 is in V SS At this time, transistor P6 is turned on, therefore transistor P6 pulls node nd13 up to V. DD When transistor N4 is turned off, it cannot pull node nd15 to V. SS However, when transistor N4 is off, transistor P4 is on, so transistor P4 attempts to pull the voltage at node nd15 up to the voltage at node nd13, i.e., V. DD When transistor P3 is off, it cannot attempt to pull node nd14 up to the voltage of node nd12. When node nd15 is pulled up to V... DD At this time, transistor P5 is turned off, therefore transistor P5 cannot attempt to pull node nd12 up to V. DD .

[0101] In summary, for normal mode, when transistor N4 is turned off due to a logic low value in input signal ib1, transistors P6 and P4 pull node nd15 up to V. DD When node n15 is in V DD When (i.e., logic high), node nd16 is pulled down to V.SS (That is, logic low), and node nd17 is pulled up to V. DD When node nd17 is pulled to V DD At this time, the output Z1 of the SBLS 722A is a logic high value, causing it to again follow the input signal ibb1 and be the inverted form of the input signal ib1. Therefore, in normal mode, the output Z1 of the SBLS 722A again responds to changes in the logic levels of the input signals ib1 and ibb1. Furthermore, the input signals ib1 and ibb1 are effectively converted from levels corresponding to the first power domain to corresponding output Z1 levels corresponding to the second power domain.

[0102] In standby mode, i.e., when the signal TOGLd has a logic low value, transistor P7 is turned on and transistor N7 is turned off. When transistor N7 is turned off, transistor N7 cannot pull node nd11 down to V. SS This means that (1) when transistor N3 is on, transistor N3 cannot conduct current to node nd11 and / or (2) when transistor N4 is on, transistor N4 cannot conduct current to node nd11. Since neither transistor N3 nor N4 can conduct current to node n11, the overall power consumption of the SBLS 722A is reduced. In other words, in standby mode, the operation of transistors N3 and N4 does not affect the voltage at node nd15. Due to the operation of transistor p7 (discussed below), the operation of transistors P3-P6 has almost no effect on node nd15.

[0103] When transistor P7 is turned on, transistor P7 pulls node nd15 up to V. DD When node n15 is in V DD When (i.e., logic high), node nd16 is pulled down to V. SS (That is, logic low), and node nd17 is pulled up to V. DD Furthermore, when the signal TOGLd has a logic low value, the output Z1 of the SBLS 722A remains statically at a logic high value regardless of the logic levels of the input signals ib1 and ibb1. Therefore, in standby mode, the output Z1 does not follow the input signal ibb1, nor does it represent the inverted form of the input signal ib1. Consequently, in standby mode, the output Z1 of the SBLS 722A does not respond to changes in the logic levels of the input signals ib1 and ibb1.

[0104] In some embodiments, alternative versions of SBLS 722A and 722B are provided, wherein transistors P7 and P18 (not shown) of the respective SBLS 722A and 722B are replaced with first and second NMOS transistors (NFETs). The first NFET is coupled between nodes nd15 and Vss. The second NFET is coupled between nodes nd22 and Vss. Each of the first and second NFETs is configured to receive a signal. Similar to the above, the discussion will focus on the operation of the alternative version of SBLS 722A, since the operation of the alternative version of SBLS 722B is similar.

[0105] In normal mode, for the alternative to SBLS 722A, when the signal TOGLd has a logic high value, the signal... Having a logic low value will turn off the first NFET. When the first NFET is turned off, it cannot pull node nd15 down to V. SS Therefore, the first NFET has almost no effect on the output Z1 of the alternative version of the SBLS 722A. Thus, in normal mode, the output Z1 of the alternative version of the SBLS 722A responds to changes in the logic levels of the input signals ib1 and ibb1. Furthermore, the input signals ib1 and ibb1 are effectively converted from levels corresponding to the first power domain to corresponding output Z1 with levels corresponding to the second power domain.

[0106] In standby mode, for the alternative to SBLS 722A, when the signal TOGLd has a logic low value, the signal... Having a logic high value will turn on the first NFET. When the first NFET is turned on, it pulls node n15 to V. SS When node n15 is in V SS When (i.e., logic low), node nd16 is pulled up to V. DD (That is, logic high level), and node nd17 is pulled to V. SS Furthermore, when the signal With a logic low value, the output Z1 of the alternative version of the SBLS 722A is statically at a logic low value regardless of the logic levels of the input signals ib1 and ibb1. Therefore, in standby mode, the output Z1 of the alternative version of the SBLS 722A does not follow the input signal ibb1, nor does it represent the inverted form of the input signal ib1. Thus, in standby mode, the output Z1 of the alternative version of the SBLS 722A does not respond to changes in the logic levels of the input signals ib1 and ibb1.

[0107] In some embodiments, a power management processing circuit (not shown) generates a TOGL signal 707 and provides it to a control circuit 780. Alternatively or additionally, the control signal 707 is used to control when SBLS 722A and 722B are not used and / or when power is saved, for example, by de-energizing SBLS 722A and 722B. A TOGLd signal 782 is received at the gate terminal of NMOS transistor N7 and the gate terminals of PMOS transistors P7 and P18. In some embodiments, the combination of the TOGLd signal 782 at transistors N7 and P7 effectively switches SBLS 722A between a normal state and a standby state. In some embodiments, the combination of the TOGLd signal 782 at transistors N7 and P18 effectively switches SBLS 722B between a normal state and a standby state. In some embodiments, in the standby state, leakage from each of SBLS 722A and 722B determines the leakage of the MBLS.

[0108] Figure 8 , Figure 9B , Figure 9C and Figure 9D These are layout diagrams of MBLS circuit structures according to some embodiments, and Figure 9A This is the layout diagram of SBLS.

[0109] Figure 8 and Figures 9A-9D The layout diagram represents according to Figure 8 and Figures 9A-9D The layout diagram is correspondingly used to partially fabricate the corresponding MBLS region in the corresponding semiconductor device. Therefore, Figure 8 and Figures 9A-9D Individual shapes (also called patterns) in the layout diagram represent according to Figure 8 and Figures 9A-9D The layout diagram corresponds to the individual structures in the corresponding MBLS regions of the corresponding semiconductor devices that are manufactured accordingly.

[0110] For the sake of simplicity in discussion, Figure 8 and Figures 9A-9D Elements in the layout diagram will be referred to by their structure, not their shape. For example, Figure 8 Each instance of shape 851 in the layout diagram is an active region shape representing an active region in the corresponding semiconductor device. In the following discussion, each instance of shape 851 is referred to accordingly as an instance of active region 851, rather than an instance of active region pattern 851.

[0111] Figure 8 This is a layout diagram of the MBLS 800 circuit structure according to some embodiments.

[0112] MBLS 800 includes two instances of SBLS (discussed below), namely, MBLS 800 is multi-bit, and therefore it is similar to MBLS 200, 300, 400, and 500. In some embodiments, MBLS 800 is used in region 106 of IC 100. In some embodiments, MBLS 800 is similar to MBLS 200, 300, 400, and 500, except that MBLS 800 is configured to convert two inputs from a first voltage domain to a second voltage domain, MBLS 400 is configured to convert four inputs from a first voltage domain to a second voltage domain, and MBLS 500 is configured to convert eight inputs from a first voltage domain to a second voltage domain.

[0113] In some embodiments, MBLS 800 includes an FNW 850 located at the intersection of a vertical axis 804 and a horizontal axis 806. In some embodiments, MBLS 800 also includes an SNW 808 located on a first side 810 of the vertical axis 804 along the horizontal axis 806 and an SNW 812 located on a second side 814 of the vertical axis 804 along the horizontal axis 806. In some embodiments, the horizontal axis 806 bisects each of SNWs 808 and 812. In some embodiments, the horizontal axis 806 bisects the FNW 850. In some embodiments, SNWs 808 and 812 are positioned along the vertical axis 804. In some embodiments, the vertical axis 804 and the horizontal axis 806 are shown as bisecting MBLS 800.

[0114] Alternatively or concurrently, the MBLS 800 also includes components configured to have a first supply voltage (e.g., V). DDL The first power node (see) Figure 6 (670). In some embodiments, the first power node is at a first voltage domain voltage (V DDL And it is located within the common FNW 850. In some embodiments, the MBLS 800 also includes a second voltage domain voltage (e.g., V). DD The second power node (see) Figure 7 (770). Alternatively or concurrently, a second power supply is located within SNWs 808 and 812. In some embodiments, MBLS 800 further includes input circuitry 816, which includes a first PMOS transistor P1 located in FNW 850 and on a first side 810 of the vertical axis 804, and the first PMOS transistor P1 includes a first source / drain (S / D) terminal coupled to the first power supply node. Figure 6The MBLS 800 also includes an input circuit 818, which includes a second PMOS transistor P12 located in the FNW 850 and on the second side 814 of the vertical axis 804. The second PMOS transistor P12 includes a second S / D terminal coupled to the first power node. Figure 6 The input circuits 816 and 818 are configured to receive input signals having voltage levels corresponding to a first voltage domain (see i1 and i2).

[0115] Alternatively or concurrently, MBLS 800 also includes SBLS 822A, which includes a third PMOS transistor P5 located in SNW 808, and the third PMOS transistor P5 includes coupling to a second power node (see...). Figure 7 The third S / D terminal of the 770) Figure 7 ); and a fourth PMOS transistor P6, which is located in SNW 808, and the fourth PMOS transistor P6 includes a fourth S / D terminal coupled to the second power node. Figure 7 ), wherein SBLS 822A receives a data output signal from input circuit 816 and converts the data output signal from a level having a first voltage domain to a level having a second voltage domain.

[0116] Alternatively or concurrently, MBLS 800 also includes SBLS 822B, which includes a fifth PMOS transistor P16 located in SNW 812, and the fifth PMOS transistor P16 includes coupling to a second power node (see...). Figure 7 The fifth S / D terminal of the 770) Figure 7 ); and a sixth PMOS transistor P17, which is located in SNW 812, and the sixth PMOS transistor P17 includes a sixth S / D terminal coupled to the second power node. Figure 7 ), wherein SBLS 822B receives a data output signal from input circuit 818 and converts the data output signal from a level having a first voltage domain to a level having a second voltage domain.

[0117] In some embodiments, the MBLS 800 further includes a control circuit 880 electrically coupled to the SBLS 822A and 822B, the control circuit 880 being configured to generate a TOGLd signal based on the TOGL signal. Figure 7The 782) outputs to each of the SBLS 822A and 822B, which allows the SBLS 822A and 822B to switch between normal and standby states. Figure 8 In this embodiment, control circuitry 880 is partially located within SNW 808. Alternatively, control circuitry 880 is partially located within SNW 812. In some embodiments, control circuitry 880 is electrically coupled to a second power node (see [link to SNW 812]). Figure 7 (770). In some embodiments, control circuitry 880 includes PMOS transistors P10 and P11 located within SNW 808. Alternatively or additionally, control circuitry 880 outputs a TOGLd signal that, when sent to SBLS 822A and 822B, causes each of SBLS 822A and 822B to switch between a normal state and a standby state. SBLS 822A is located at SNW 808, and SBLS 822B is located at SNW 812.

[0118] In some embodiments, each input (e.g., i1 and i2) arrives at a level corresponding to a first voltage domain (e.g., V). DDL The input circuits 816 and 818. Alternatively, the input circuits 816 and 818 then output at V in a manner corresponding to SBLS822A and 822B. DDL The data signals (e.g., ib1, ibb1 and ib2, ibb2). In some embodiments, SBLS 822A and 822B acquire the data signals (e.g., ib1, ibb1 and ib2, ibb2) received from input circuits 816 and 818 and convert them to a state at V DD The output data signals (e.g., Z1 and Z2). Alternatively or alternatively, Z1 (i.e., at V) DD ) represents i1 (i.e., at V) DDL Z2 (i.e., at V) DD ) represents i2 (i.e., at V) DDL That is, Z1 and Z2 are the level shift representations of the corresponding i1 and i2.

[0119] Figure 9A , Figure 9B , Figure 9C and Figure 9D These are layout diagrams of MBLS circuit structures based on some embodiments.

[0120] Alternatively or alternatively Figure 9A This is a layout diagram of SBLS 900. In some embodiments, Figure 9BThis is a layout diagram of MBLS 902. In some embodiments, MBLS 902 is similar to MBLS 200, 300, or 800. Alternatively or alternatively, Figure 9C This is a layout diagram of MBLS 904. In some embodiments, MBLS 904 is similar to MBLS 400. In some embodiments, Figure 9D This is a layout diagram of MBLS 906. In some embodiments, MBLS 906 is similar to MBLS 500. Alternatively or additionally, SBLS 900 and each of MBLS 902, 904 and 906 are used in IC 100 in region 106.

[0121] In some embodiments, each of SBLS 900 and MBLS 902, 904, and 906 is labeled using various alphanumeric representations. Alternatively, the numbers 1, 2, 3, and 4 are associated with 1 bit (1), 2 bits (2), 4 bits (3), and 8 bits (4). In some embodiments, D represents the cell pitch of each of SBLS 1400 (D1) and MBLS 902 (D2), 904 (D3), and 906 (D4). Alternatively, E represents the cell height of each of SBLS 900 (E1) and MBLS 902 (E2), 904 (E3), and 906 (E4). In some embodiments, A represents the NW gap of each of SBLS 900 (A1) and MBLS 902 (A2), 904 (A3), and 906 (A4). Alternatively or concurrently, B represents the V of each of SBLS 900 (B1, B3) and MBLS 902 (B2, B4), 904 (B5, B6) and 906 (B7, B8). DD SNW width. In some embodiments, C represents the V of each of SBLS 900 (C1) and MBLS 902 (C2), 904 (C3) and 906 (C4). DDL FNW width. Alternatively, Y represents the V of each of SBLS 900 (Y1) and MBLS 902 (Y2), 904 (Y3) and 906 (Y4). DD SNW height. In some embodiments, H represents the V of each of SBLS 900 (H1) and MBLS 902 (H2), 904 (H3) and 906 (H4). DDL FNW height.

[0122] Figure 10 This is a table based on some embodiments.

[0123] Alternatively or alternatively Figure 10 It is shown Figure 9AThe SBLS 900 and its corresponding Figure 9B-9D A table showing the relationship between the layout characteristics of MBLS 902, 904 and 906.

[0124] When implemented in an 8-bit design (e.g., MBLS 906 in some embodiments), the cell heights of each of SBLS 900 and MBLS 902-904 are the same, E1 = E2 = E3, and the height of SBLS 906 is doubled (e.g., E4 = 2E3). Additionally or alternatively, the gap between the SNW and FNW remains the same in SBLS 900 and MBLS 902, 904, and 906, i.e., A1 = A2 = A3 = A4. In some embodiments, for each of SBLS 900, MBLS 902, 904, and 906, V DD The SNW height also remains the same, Y1=Y2=Y3=Y4.

[0125] In some embodiments, the cell spacing D increases with increasing bit size, such as D3 being greater than D2 and D2 being greater than D1. Alternatively, for an 8-bit MBLS 906, the spacing D4 is smaller than D3, but still larger than D2. Therefore, in some embodiments, the MBLS 906 cell spacing is smaller than MBLS 904, but larger than MBLS 902.

[0126] In some embodiments, V in MBLS 902 DD SNW width is smaller than V in MBLS 900 DD Twice the width of SNW, V in MBLS 904 DD SNW width is smaller than V in MBLS 902 DD Twice the width of SNW, and V in MBLS 906 DD SNW width is equal to V in MBLS 904 DD SNW width. In some embodiments, V DDL The FNW width increases for each MBLS up to MBLS 906, where C4 is less than C3. Alternatively, V... DDL The FNW height remains proportional to the cell height, which is the same for all MBLS except that MBLS 906 is twice the height of the other MBLS. Alternatively, by using a separate control circuit for each of the MBLS 902, 904, and 906, area savings of 39% or greater are achieved.

[0127] Figure 11 This is a flowchart of a method 1100 for converting data between voltage domains according to some embodiments.

[0128] Although method 1100 is shown in sequential steps, it is not necessarily required to follow the steps outlined in the method. Figure 11 The steps shown are executed in the order indicated for method 1100. In some embodiments, each step of method 1100 is performed incidentally or in virtually any order unless a specific order is specified. Alternatively or alternatively, in Figure 11 Additional operations are performed before, during, and / or after the method 1100 shown, and only a few other procedures are briefly described herein.

[0129] exist Figure 11 The flowchart includes blocks 1110, 1112, 1114, 1120, 1130, and 1132. In block 1110, the MBLS receives a first supply voltage and a second supply voltage. An example of this MBLS is... Figure 3 The MBLS 300 includes input circuits 316 and 318, and SBLS 322A and 322B, wherein input circuits 616 and 618 are correspondingly more detailed examples of input circuits 316 and 318, and SBLS 722A and 722B are correspondingly more detailed examples of SBLS 322A and 322B. Continuing with this example, VDD L It is within the FNW 650 Figure 6 VDD is received at an instance of power node 670. In some embodiments, VDD is received at one or more power nodes 770 within SNW 708 and 712. The process proceeds from block 1110 to block 1112.

[0130] In block 1112, an input circuit electrically connected to a first supply voltage receives input from a first voltage domain, wherein the first voltage domain operates at the first supply voltage. An example of an MBLS including an input circuit is... Figure 3 The MBLS 300 includes input circuits 316 and 318, and wherein input circuits 616 and 618 are correspondingly more detailed examples of input circuits 316 and 318. Additional examples of input circuits include input circuits 616 and 618 ( Figure 6 The circuit receives data-1 and data-2 inputs from the first voltage domain (e.g., voltage domain 102). The process proceeds from block 1112 to block 1114.

[0131] In block 1114, the input circuitry outputs inputs from the first voltage domain to two or more corresponding SBLSs operating in the second voltage domain and electrically connected to a second power supply. Examples of the input circuitry include input circuits 316 and 318 of the MBLS 300, which output ib1, ibb1, ib2, ibb2 from the first voltage domain FNW 350 to SBLSs 322A and 322B, where SBLSs 722A-722B are electrically connected to one or more second power supply nodes 770. The flow proceeds from block 1114 to block 1120.

[0132] In block 1120, two or more corresponding SBLSs respectively transform the input from the first voltage domain to the second voltage domain (1120). Examples of two or more SBLSs include each of SBLS 322A and 322B of MBLS 300, which SBLS in V DD The system receives inputs ib1, ibb1, ib2, and ibb2, and outputs Z1 and Z2. The process proceeds from block 1120 to block 1130.

[0133] In block 1130, the SBLS receives input from control circuitry. An example of an SBLS receiving input from control circuitry includes input from control circuitry 780 (…). Figure 7 ) Receive control signals 782 via SBLS 722A and 722B. The process proceeds from block 1130 to block 1132.

[0134] In block 1132, the SBLS switches between a normal state and a standby state based on a control signal received from the control circuitry. In some embodiments, examples include switching based on a control signal received from control circuitry 780 ( Figure 7 SBLS 722A and 722B switch between normal and standby states using control signals (e.g., TOGLd signal 782).

[0135] Figure 12 This is a flowchart of a method for manufacturing a semiconductor device according to some embodiments.

[0136] Alternatively or alternatively, in Figure 12 Additional operations are performed before, during, and / or after method 1200, and only some other processes are briefly described herein. Examples of semiconductor devices manufactured according to method 1200 include those manufactured according to corresponding methods. Figure 8 , Figure 9B , Figure 9C and Figure 9D Semiconductor devices with layout diagrams, etc.

[0137] Figure 12Includes blocks 1210, 1212, 1214, and 2120. In block 1210 of method 1200, a first voltage-domain NW semiconductor structure and a second voltage-domain NW semiconductor structure are fabricated in a substrate. As a non-limiting example, in... Figure 3 In the illustrated embodiment, NW 350, 308, and 312 are fabricated on top of or within the substrate. Continuing the example, FNW 350 and SNW 308 and 312 are N-type semiconductor regions created by doping intrinsic semiconductors with electron donor elements, and the substrate is P-type and connected (body biased) to Vss, and FNW 350 is connected (body biased) to Vss. DDL And SNW 308 and 312 are connected (volume biased) to V DD The process proceeds from box 1210 to box 1212.

[0138] In block 1212 of method 1200, a transistor having a first conductivity is at least partially fabricated in each NW. As a non-limiting example, such as... Figure 6 and Figure 7 As shown, PMOS transistors P1, P2, P12, and P13 are fabricated in FNW 650, PMOS transistors P3-P11 are fabricated in SNW708, and PMOS transistors P14-P20 are fabricated in SNW 712. The process proceeds from block 1212 to block 1214.

[0139] In block 1214 of method 1200, a second transistor of a second conductivity type is fabricated at least partially in a substrate. As a non-limiting example, such as... Figure 6 and Figure 7 As shown, in some embodiments, NMOS transistors N1, N2, N10, and N11 are fabricated outside FNW 650, NMOS transistors N3-N9 are fabricated outside SNW 708, and NMOS transistors N12-N15 are fabricated outside SNW 712. The process proceeds from block 1214 to block 1220.

[0140] In method 1200, box 1220, a metal layer is deposited and patterned. As a non-limiting example, in... Figure 6 and Figure 7 In the illustrated embodiments, in some embodiments, metal interconnects electrically couple the PMOS transistors within FNW 650, SNW 708, and SNW 712 to NMOS transistors external to FNW 650, SNW 708, and SNW 712. Continuing as a non-limiting example, the metal interconnects extend between nodes (e.g., nd01-nd23) and connect inverters (e.g., 664A, 764A; see also...) Figure 8 ) and other inverters (e.g., 664B, 764B; see also...) Figure 8 ) and such as PMOS transistors (e.g., PMOS transistor P7 or P18; see also...) Figure 8 ) or NMOS transistor (e.g., NMOS transistor N7; see also...) Figure 8 Electrically coupled to other devices such as )

[0141] In some embodiments, Figure 13 This is a block diagram of an electronic design automation (EDA) system 1300 according to some embodiments. Additionally or alternatively, the EDA system 1300 includes an APR system. In some embodiments, the design layout methods described herein represent wiring arrangements according to one or more embodiments that can be implemented, for example, using the EDA system 1300 according to some embodiments.

[0142] In some embodiments, the EDA system 1300 is a general-purpose computing device including a hardware processor 1302 and a non-transitory computer-readable storage medium 1304. Additionally or alternatively, the storage medium 1304 (among other things) is encoded with (i.e., stores) computer program code 1306 (i.e., a set of executable instructions). In some embodiments, the computer program code 1306, executed by the hardware processor 1302, represents (at least partially) an EDA tool that implements some or all of the methods described herein (hereinafter, the processes and / or methods) according to one or more embodiments.

[0143] In some embodiments, processor 1302 is electrically coupled to computer-readable storage medium 1304 via bus 1308. Additionally or alternatively, processor 1302 is also electrically coupled to I / O interface 1310 via bus 1308. In some embodiments, network interface 1312 is also electrically connected to processor 1302 via bus 1308. Additionally or alternatively, network interface 1312 is connected to network 1314, enabling processor 1302 and computer-readable storage medium 1304 to be connected to external components via network 1314. In some embodiments, processor 1302 is configured to execute computer program code 1306 encoded in computer-readable storage medium 1304 to make EDA system 1300 available for performing part or all of the processes and / or methods. In one or more embodiments, processor 1302 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application-specific integrated circuit (ASIC), and / or a suitable processing unit.

[0144] In one or more embodiments, the computer-readable storage medium 1304 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or apparatus or device). For example, the computer-readable storage medium 1304 includes semiconductor or solid-state memory, magnetic tape, removable computer disk, random access memory (RAM), read-only memory (ROM), hard disk, and / or optical disk. In one or more embodiments using optical disk, the computer-readable storage medium 1304 includes optical disc read-only memory (CD-ROM), optical disc read / write (CD-R / W), and / or digital video disc (DVD).

[0145] In one or more embodiments, storage medium 1304 stores computer program code 1306, which is configured to enable EDA system 1300 (where such execution represents (at least partially) EDA tools) to perform part or all of the process and / or method. In one or more embodiments, storage medium 1304 also stores information that facilitates the execution of part or all of the process and / or method. In one or more embodiments, storage medium 1304 stores a standard cell library 1307, which includes standard cells such as those disclosed herein. In one or more embodiments, storage medium 1304 stores one or more layout diagrams 1309 corresponding to one or more layout diagrams disclosed herein.

[0146] In some embodiments, the EDA system 1300 includes an I / O interface 1310. Additionally or alternatively, the I / O interface 1310 is coupled to external circuitry. In one or more embodiments, the I / O interface 1310 includes a keyboard, buttons, a mouse, a trackball, a trackpad, a touchscreen, and / or cursor arrow keys for transmitting information and commands to the processor 1302.

[0147] In some embodiments, the EDA system 1300 further includes a network interface 1312 coupled to the processor 1302. Additionally or alternatively, the network interface 1312 allows the EDA system 1300 to communicate with a network 1314 to which one or more other computer systems are connected. In some embodiments, the network interface 1312 includes: a wireless network interface such as Bluetooth, WIFI, WIMAX, GPRS, or WCDMA; or a wired network interface such as Ethernet, USB, or IEEE-1364. In one or more embodiments, some or all of the processes and / or methods are implemented in two or more EDA systems 1300.

[0148] In some embodiments, the EDA system 1300 is configured to receive information via I / O interface 1310. Alternatively or additionally, the information received via I / O interface 1310 includes one or more of instructions, data, design rules, standard cell libraries, and / or other parameters for processing by processor 1302. In some embodiments, the information is transmitted to processor 1302 via bus 1308. Alternatively or additionally, the EDA system 1300 is configured to receive UI-related information via I / O interface 1310. In some embodiments, the information is stored as a user interface (UI) 1342 on computer-readable medium 1304.

[0149] In some embodiments, part or all of the process and / or method is implemented as a standalone software application executed by a processor. In some embodiments, part or all of the process and / or method is implemented as a software application as part of an additional software application. In some embodiments, part or all of the process and / or method is implemented as a plug-in to a software application. In some embodiments, at least one of the process and / or method is implemented as a software application as part of an EDA tool. In some embodiments, part or all of the process and / or method is implemented as a software application used by EDA system 1300. In some embodiments, a software application such as those available from CADENCE DESIGN SYSTEMS is used. Use tools like these or another suitable layout generation tool to generate layout diagrams that include standard cells.

[0150] In some embodiments, these processes are implemented as functions of a program stored in a non-transitory computer-readable recording medium. Examples of non-transitory computer-readable recording media include, but are not limited to, external / removable and / or internal / built-in storage devices or memory units, such as one or more of the following: optical discs such as DVDs, magnetic disks such as hard disks, semiconductor memories such as ROM, RAM, memory cards, etc.

[0151] Figure 14 This is a block diagram of an integrated circuit (IC) manufacturing system 1400 and its associated IC manufacturing process according to some embodiments. In some embodiments, based on the layout diagram, the manufacturing system 1400 is used to manufacture at least one of the following: (A) one or more semiconductor masks or (B) at least one component in a semiconductor integrated circuit layer.

[0152] In some embodiments, Figure 14In this IC manufacturing system 1400, entities such as design room 1420, mask room 1430, and IC manufacturer / fab (“fab”) 1450 interact in the design, development, and manufacturing cycle and / or services related to the manufacture of IC devices 1460. Additionally or alternatively, the entities in system 1400 are connected via a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as an intranet and the Internet. Additionally or alternatively, the communication network includes wired and / or wireless communication channels. In some embodiments, each entity interacts with one or more other entities and provides services to and / or receives services from one or more other entities. In some embodiments, two or more of design room 1420, mask room 1430, and IC fab 1450 are owned by a single, larger company. In some embodiments, two or more of design room 1420, mask room 1430, and IC fab 1450 coexist in a shared facility and use shared resources.

[0153] In some embodiments, a design firm (or design team) 1420 generates an IC design layout 1422. Alternatively or additionally, the IC design layout 1422 includes various geometric patterns designed for an IC device 1460. In some embodiments, the geometric patterns correspond to patterns of metal, oxide, or semiconductor layers constituting various components of the IC device 1460 to be manufactured. Alternatively or additionally, various layers are combined to form various IC features. For example, a portion of the IC design layout 1422 includes various IC features to be formed in a semiconductor substrate (e.g., a silicon wafer), such as active regions, gate terminals, source and drain terminals, metal lines or vias for interlayer interconnects, and openings for bonding pads; and various material layers disposed on the semiconductor substrate. In some embodiments, the design firm 1420 performs appropriate design procedures to form the IC design layout 1422. Alternatively or additionally, the design procedures include one or more of logic design, physical design, or place and route. In some embodiments, the IC design layout 1422 is presented in one or more data files containing geometric pattern information. For example, IC design layout diagram 1422 is represented in GDSII file format or DFII file format.

[0154] In some embodiments, mask chamber 1430 includes mask data preparation 1432 and mask fabrication 1444. Alternatively or additionally, mask chamber 1430 uses an IC design layout 1422 to fabricate one or more masks 1445 for fabricating various layers of an IC device 1460 according to the IC design layout 1422. In some embodiments, mask chamber 1430 performs mask data preparation 1432, wherein the IC design layout 1422 is converted into a representative data file (“RDF”). Alternatively or additionally, mask data preparation 1432 provides the RDF to mask fabrication 1444. In some embodiments, mask fabrication 1444 includes a mask writer. Alternatively or additionally, the mask writer converts the RDF into an image on a substrate such as a mask (mask template) 1445 or a semiconductor wafer 1453. In some embodiments, the design layout 1422 is manipulated by mask data preparation 1432 to conform to the specific characteristics of the mask writer and / or the requirements of the IC fab 1450. Alternatively or in Figure 14 In this design, mask data preparation 1432 and mask manufacturing 1444 are shown as separate elements. In some embodiments, mask data preparation 1432 and mask manufacturing 1444 are collectively referred to as mask data preparation.

[0155] In some embodiments, mask data preparation 1432 includes optical proximity correction (OPC), which uses lithographic enhancement techniques to compensate for image errors, such as those caused by diffraction, interference, other process effects, etc. Alternatively or additionally, OPC adjusts the IC design layout 1422. In some embodiments, mask data preparation 1432 includes additional resolution enhancement techniques (RET), such as off-axis illumination, subresolution auxiliary features, phase-shift masks, other suitable techniques, or combinations thereof. In some embodiments, inverse lithography (ILT) is also used, which treats OPC as an inverse imaging problem.

[0156] In some embodiments, mask data preparation 1432 includes a mask rule checker (MRC) that uses a set of mask creation rules to check the IC design layout 1422, which has been processed in the OPC, and which includes certain geometric and / or connectivity constraints to ensure sufficient margins to address variability in the semiconductor manufacturing process. In some embodiments, the MRC modifies the IC design layout 1422 to compensate for constraints during mask fabrication 1444 by undoing some modifications performed by the OPC to satisfy the mask creation rules.

[0157] In some embodiments, mask data preparation 1432 includes a lithography process inspection (LPC) simulating the process to be implemented by IC fab 1450 to manufacture IC device 1460. Alternatively or additionally, the LPC simulates this process based on IC design layout 1422 to create a simulated fabricated device, such as IC device 1460. In some embodiments, the processing parameters in the LPC simulation include parameters associated with various processes in the IC manufacturing cycle, parameters associated with the tools used to manufacture the IC, and / or other aspects of the manufacturing process. The LPC considers various factors, such as aerial image contrast, depth of focus (DOF), mask error enhancement factor (MEEF), other suitable factors, or combinations thereof. In some embodiments, after the simulated fabricated device has been created by the LPC, if the shape of the simulated device is not close enough to meet design rules, OPC and / or MRC are repeated to further refine the IC design layout 1422.

[0158] In some embodiments, for clarity, the above description of mask data preparation 1432 is simplified. In some embodiments, mask data preparation 1432 includes additional features, such as modifying the logic operations (LOPs) of the IC design layout 1422 according to manufacturing rules. Additionally, the processes applied to the IC design layout 1422 during mask data preparation 1432 are performed in various different sequences.

[0159] In some embodiments, after mask data preparation 1432 and during mask fabrication 1444, a mask 1445 or a set of masks 1445 is fabricated based on a modified IC design layout 1422. In some embodiments, mask fabrication 1444 includes performing one or more photolithographic exposures based on the IC design layout 1422. In some embodiments, a pattern is formed on the mask (photomask or photomask template) 1445 using an electron beam (e-beam) or a plurality of e-beams based on the modified IC design layout 1422. Additionally or alternatively, the mask 1445 is formed using various techniques. In some embodiments, a binary technique is used to form the mask 1445. In some embodiments, the mask pattern includes opaque areas and transparent areas. Additionally or alternatively, a radiation beam (e.g., an ultraviolet (UV) beam) used to expose an image-sensitive material layer (e.g., photoresist) coated on the wafer is blocked by the opaque areas and transmitted through the transparent areas. In one example, a binary mask version of mask 1445 includes a transparent substrate (e.g., fused silica) and an opaque material (e.g., chromium) coated on the opaque regions of the binary mask. In another example, mask 1445 is formed using a phase-shifting technique. In a phase-shifting mask (PSM) version of mask 1445, various features in the pattern formed on the phase-shifting mask are configured to have appropriate phase differences to enhance resolution and imaging quality. In various examples, the phase-shifting mask is a decaying PSM or an alternating PSM. Alternatively or additionally, one or more masks generated by mask fabrication 1444 are used in various processes. For example, one or more such masks are used in ion implantation processes to form various doped regions in semiconductor wafer 1453, one or more such masks are used in etching processes to form various etched regions in semiconductor wafer 1453, and / or such masks are used in other suitable processes.

[0160] In some embodiments, IC fab 1450 is an IC manufacturing enterprise that includes one or more manufacturing facilities for manufacturing various different IC products. In some embodiments, IC fab 1450 is a semiconductor foundry. For example, there is a manufacturing facility for front-end manufacturing (front-end process (FEOL) manufacturing) of multiple IC products, a second manufacturing facility provides back-end manufacturing (back-end process (BEOL) manufacturing) for interconnection and packaging of IC products, and a third manufacturing facility provides other services for the foundry industry.

[0161] In some embodiments, IC fab 1450 includes manufacturing tool 1452 configured to perform various manufacturing operations on semiconductor wafer 1453, such that IC device 1460 is manufactured according to one or more masks (e.g., mask 1445). In various embodiments, manufacturing tool 1452 includes one or more of the following: wafer stepper, ion implanter, photoresist coater, process chamber (e.g., CVD chamber or LPCVD furnace), CMP system, plasma etching system, wafer cleaning system, or other manufacturing equipment capable of performing one or more suitable manufacturing processes discussed herein.

[0162] In some embodiments, IC fab 1450 uses one or more masks 1445 manufactured by mask chamber 1430 to fabricate IC device 1460. Alternatively or additionally, IC fab 1450 uses IC design layout 1422 at least indirectly to fabricate IC device 1460. In some embodiments, semiconductor wafer 1453 is fabricated by IC fab 1450 using one or more masks 1445 to form IC device 1460. In some embodiments, IC fabrication includes performing one or more photolithographic exposures at least indirectly based on IC design layout 1422. In some embodiments, semiconductor wafer 1453 includes a silicon substrate or other suitable substrate on which a material layer is formed. Alternatively or additionally, semiconductor wafer 1453 also includes one or more of various doped regions, dielectric features, multilevel interconnects, etc. (formed in subsequent fabrication steps).

[0163] In some embodiments, regarding integrated circuit (IC) manufacturing systems (e.g., Figure 14 Details of the system 1400 and the associated IC manufacturing process can be found in the following applications, such as: U.S. Patent No. 9,256,709, granted February 9, 2016; U.S. Pre-Publication No. 20150278429, published October 1, 2015; U.S. Pre-Publication No. 2066640838, published February 6, 2014; and U.S. Patent No. 7,260,442, granted August 21, 2007, the entire contents of which are incorporated herein by reference.

[0164] In some embodiments, a circuit includes two or more input circuits, respectively configured to operate in a first voltage domain. The circuit also includes two or more one-bit level shifters (SBLSs) electrically coupled to the two or more input circuits and respectively configured to operate in a second voltage domain. The circuit further includes control circuitry configured to cause each of the two or more SBLSs to switch between a normal state and a standby state upon receiving a control signal from the control circuitry.

[0165] In some embodiments, each of the two or more input circuits includes at least a first P-type transistor in a first n-well (NW). In some embodiments, one of the two or more input circuits is located on a first side bisecting the vertical axis, and another of the two or more input circuits is located on a second side bisecting the vertical axis. In some embodiments, each of the two or more input circuits includes at least a first P-type transistor in a first NW at the intersection of the vertical axis and the horizontal axis. In some embodiments, each of the two or more SBLS receives an input from one of the two or more input circuits and converts the input from the first voltage domain to the second voltage domain. In some embodiments, each of the two or more input circuits includes at least a first P-type transistor in a first NW, and each of the two or more SBLS includes at least a second P-type transistor, wherein the second P-type transistor from the first SBLS is in a second NW, and the second P-type transistor from the second SBLS is in a third NW. In some embodiments, each of the two or more input circuits includes at least a first P-type transistor in the NW, and each of the two or more SBLS includes at least a second P-type transistor, wherein the second P-type transistor from at least one SBLS is in the second NW, and a third P-type transistor from another SBLS is in the third NW, wherein the second NW and the third NW are located on opposite sides bisecting the vertical axis. In some embodiments, the two or more SBLS are symmetrically located on opposite sides bisecting the vertical axis.

[0166] In some embodiments, an integrated circuit (IC) includes a first N-well (NW) located at the intersection of a vertical axis and a horizontal axis. The circuit also includes a second NW located along the horizontal axis on a first side of the vertical axis. The circuit further includes a third NW located along the horizontal axis on a second side of the vertical axis. The circuit also includes a first power node configured to have a first power supply voltage. The circuit also includes a second power node configured to have a second power supply voltage. The circuit also includes a third power node configured to have a third power supply voltage. The circuit further includes an input circuit configured to receive an input signal in a first voltage domain, the input circuit including a first PMOS transistor in the first NW, and the first PMOS transistor including a first source / drain (S / D) terminal coupled to the first power node. The input circuit also includes a second PMOS transistor in the first NW, and the second PMOS transistor including a second S / D terminal coupled to the first power node. The input circuitry further includes at least two one-bit level shifters (SBLS), each SBLS including a first SBLS comprising a third PMOS transistor in the second NW, the third PMOS transistor including a third S / D terminal coupled to the second power node. The at least two SBLS also include a second SBLS comprising a fourth PMOS transistor in the third NW, the fourth PMOS transistor including a fourth S / D terminal coupled to the second power node. The first SBLS and the second SBLS are configured to receive corresponding input signals from the input circuitry and to convert the corresponding input signals from the first voltage domain to the second voltage domain. The circuitry further includes control circuitry electrically coupled to the first SBLS and the second SBLS, the control circuitry being configured to switch the first SBLS and the second SBLS between a normal mode and a standby mode according to a switching control signal. Other embodiments of this aspect include corresponding computer systems, apparatuses, and computer programs recorded on one or more computer storage devices, each computer storage device being configured to perform the actions of the method.

[0167] In some embodiments, the control circuit further includes: a fifth PMOS transistor, in one of the second NW and the third NW, the fifth PMOS transistor including a fifth S / D terminal coupled to the second power node, the fifth S / D terminal being electrically coupled to one of the first SBLS and the second SBLS. In some embodiments, the at least two SBLS further include: a first NMOS transistor located outside the second NW and electrically coupled to the third PMOS transistor, the first NMOS transistor including a sixth S / D terminal electrically coupled to the control circuit; and a second NMOS transistor located outside the third NW and electrically coupled to the fourth PMOS transistor, the second NMOS transistor including a seventh S / D terminal electrically coupled to the control circuit. In some embodiments, the second NW is located on a first side of the horizontal axis and a first side of the vertical axis; the third NW is located on a first side of the horizontal axis and a second side of the vertical axis; and the IC further includes: a fourth NW located on a second side of the horizontal axis and a first side of the vertical axis; and a fifth NW located on a second side of the horizontal axis and a second side of the vertical axis. In some embodiments, the first power supply voltage is greater than the second power supply voltage, or the second power supply voltage is greater than the first power supply voltage; and both the first power supply voltage and the second power supply voltage are greater than the third power supply voltage. In some embodiments, the third PMOS transistor is located within the first SBLS; the fourth PMOS transistor is located within the second SBLS, and the IC further includes: a fifth PMOS transistor in the second NW, and the fifth PMOS transistor includes a sixth S / D terminal coupled to the second power node, and the fifth PMOS transistor is located within the third SBLS; and a sixth PMOS transistor in the third NW, and the sixth PMOS transistor includes a seventh S / D terminal coupled to the second power node, and the sixth PMOS transistor is located within the fourth SBLS; the first SBLS, second SBLS, third SBLS, and fourth SBLS are all electrically coupled to the control circuit; and the control circuit is further configured to switch each of the first SBLS, second SBLS, third SBLS, and fourth SBLS between a normal state and a standby state. In some embodiments, each of the second NW and the third NW supports two SBLS.

[0168] In some embodiments, a method of operating a plurality of one-bit level shifters (SBLS) includes: receiving a first power supply voltage and a second power supply voltage, the second power supply voltage being intermediate between the first power supply voltage and a third power supply voltage. The method further includes receiving input from a first voltage domain operating at the first power supply voltage at two or more input circuits electrically connected to the first power supply voltage. The method further includes outputting a version of the input from the first voltage domain from the two or more input circuits to two or more corresponding SBLS operating in a second voltage domain and electrically connected to the second power supply voltage. The method further includes correspondingly switching the version of the input from the first voltage domain to the second voltage domain via the two or more SBLS. The method further includes receiving a switching control signal from control circuitry at each of the two or more corresponding SBLS. The method further includes switching the two or more corresponding SBLS between a normal mode and a standby mode based on the control signal.

[0169] In some embodiments, the two or more input circuits all share a first n-well (NW). In some embodiments, the first NW is along a bisected vertical axis and a bisected horizontal axis. In some embodiments, a second NW is shared by two of the two or more corresponding SBLS. In some embodiments, the second NW supports the first SBLS of the two or more corresponding SBLS, and a third NW supports the second SBLS of the two or more corresponding SBLS.

[0170] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or the same advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

[0171] Example 1. A circuit for a semiconductor device, comprising:

[0172] Two or more input circuits are configured to operate in the first voltage domain accordingly;

[0173] Two or more one-bit level shifters (SBLS), electrically coupled to the two or more input circuits respectively, and configured to operate in a second voltage domain; and

[0174] The control circuit is configured to cause each of the two or more SBLS to switch between a normal state and a standby state when it receives a control signal from the control circuit.

[0175] Example 2. The circuit according to Example 1, wherein each of the two or more input circuits includes at least a first P-type transistor in a first n-well (NW).

[0176] Example 3. The circuit according to Example 1, wherein one of the two or more input circuits is located on a first side bisecting the vertical axis, and the other of the two or more input circuits is located on a second side bisecting the vertical axis.

[0177] Example 4. The circuit according to Example 1, wherein each of the two or more input circuits includes at least a first P-type transistor in a first NW located at the intersection of the vertical axis and the horizontal axis.

[0178] Example 5. The circuit according to Example 1, wherein each of the two or more SBLS receives an input from one of the two or more input circuits and converts the input from the first voltage domain to the second voltage domain.

[0179] Example 6. The circuit according to Example 1, wherein each of the two or more input circuits includes at least a first P-type transistor in a first NW, and each of the two or more SBLS includes at least a second P-type transistor, wherein the second P-type transistor from the first SBLS is in a second NW, and the second P-type transistor from the second SBLS is in a third NW.

[0180] Example 7. The circuit according to Example 1, wherein each of the two or more input circuits includes at least a first P-type transistor in an NW, and each of the two or more SBLS includes at least a second P-type transistor, wherein the second P-type transistor from at least one SBLS is in a second NW, and a third P-type transistor from another SBLS is in a third NW, wherein the second NW and the third NW are located on opposite sides bisecting the vertical axis.

[0181] Example 8. The circuit according to Example 1, wherein the two or more SBLS are symmetrically located on opposite sides of the vertical axis.

[0182] Example 9. An integrated circuit (IC) comprising:

[0183] The first N-well (NW) is located at the intersection of the vertical and horizontal axes;

[0184] The second NW is located on the first side of the vertical axis along the horizontal axis;

[0185] The third NW is located on the second side of the vertical axis along the horizontal axis;

[0186] The first power node is configured to have a first power supply voltage; and

[0187] The second power node is configured to have a second power supply voltage;

[0188] The third power node is configured to have a third power supply voltage;

[0189] An input circuit, configured to receive an input signal in a first voltage domain, the input circuit comprising:

[0190] A first PMOS transistor is located in the first NW, and the first PMOS transistor includes a first source / drain (S / D) terminal coupled to the first power node; and

[0191] A second PMOS transistor is located in the first NW, and the second PMOS transistor includes a second S / D terminal coupled to the first power node; and

[0192] At least two one-bit level shifters (SBLS), including:

[0193] The first SBLS includes a third PMOS transistor in the second NW, and the third PMOS transistor includes a third S / D terminal coupled to the second power node; and

[0194] The second SBLS includes a fourth PMOS transistor in the third NW, and the fourth PMOS transistor includes a fourth S / D terminal coupled to the second power node;

[0195] Wherein, the first SBLS and the second SBLS are configured to receive corresponding input signals from the input circuit and convert the corresponding input signals from the first voltage domain to the second voltage domain; and

[0196] A control circuit, electrically coupled to the first SBLS and the second SBLS, is configured to switch the first SBLS and the second SBLS between a normal mode and a standby mode according to a switching control signal.

[0197] Example 10. According to the IC described in Example 9, the control circuit further includes:

[0198] A fifth PMOS transistor, located in one of the second NW and the third NW, the fifth PMOS transistor including a fifth S / D terminal coupled to the second power node, the fifth S / D terminal being electrically coupled to one of the first SBLS and the second SBLS.

[0199] Example 11. According to the IC described in Example 9, the at least two SBLS further include:

[0200] A first NMOS transistor, located outside the second NW and electrically coupled to the third PMOS transistor, the first NMOS transistor including a sixth S / D terminal electrically coupled to the control circuit; and

[0201] A second NMOS transistor is located outside the third NW and electrically coupled to the fourth PMOS transistor. The second NMOS transistor includes a seventh S / D terminal electrically coupled to the control circuit.

[0202] Example 12. The IC according to Example 9, wherein:

[0203] The second NW is located on the first side of the horizontal axis and the first side of the vertical axis;

[0204] The third NW is located on the first side of the horizontal axis and the second side of the vertical axis;

[0205] The IC also includes:

[0206] The fourth NW is located on the second side of the horizontal axis and the first side of the vertical axis; and

[0207] The fifth NW is located on the second side of the horizontal axis and the second side of the vertical axis.

[0208] Example 13. The IC according to Example 9, wherein:

[0209] The first power supply voltage is greater than the second power supply voltage, or the second power supply voltage is greater than the first power supply voltage; and

[0210] Both the first power supply voltage and the second power supply voltage are greater than the third power supply voltage.

[0211] Example 14. The IC according to Example 9, wherein:

[0212] The third PMOS transistor is located within the first SBLS;

[0213] The fourth PMOS transistor is located within the second SBLS.

[0214] The IC also includes:

[0215] A fifth PMOS transistor, located in the second NW, the fifth PMOS transistor including a sixth S / D terminal coupled to the second power node, and the fifth PMOS transistor located within the third SBLS; and

[0216] A sixth PMOS transistor is located in the third NW, the sixth PMOS transistor includes a seventh S / D terminal coupled to the second power node, and the sixth PMOS transistor is located within the fourth SBLS;

[0217] The first SBLS, the second SBLS, the third SBLS, and the fourth SBLS are all electrically coupled to the control circuit; and

[0218] The control circuit is also configured to switch each of the first SBLS, the second SBLS, the third SBLS and the fourth SBLS between a normal state and a standby state.

[0219] Example 15. The IC according to Example 14, wherein each of the second NW and the third NW supports two SBLS.

[0220] Example 16. A method of operating a plurality of one-bit level shifters (SBLS), the method comprising:

[0221] Receives a first power supply voltage and a second power supply voltage, wherein the second power supply voltage is between the first power supply voltage and the third power supply voltage;

[0222] Receives input from a first voltage domain that operates under the first power supply voltage at two or more input circuits electrically connected to the first power supply voltage;

[0223] The input version from the first voltage domain is output from the two or more input circuits to two or more corresponding SBLSs that operate in the second voltage domain and are electrically connected to the second power supply voltage;

[0224] The input version is converted from the first voltage domain to the second voltage domain accordingly using the two or more SBLS;

[0225] At each of the two or more corresponding SBLSs, a switching control signal from the control circuit is received; and

[0226] Based on the switching control signal, two or more corresponding SBLSs are switched between normal mode and standby mode.

[0227] Example 17. The method according to Example 16, wherein the two or more input circuits all share a first n-well (NW).

[0228] Example 18. The method according to Example 17, wherein the first NW bisects the vertical axis and the horizontal axis.

[0229] Example 19. The method according to Example 17, wherein the second NW is shared by two of the two or more corresponding SBLS.

[0230] Example 20. The method according to Example 17, wherein the second NW supports the first SBLS of the two or more corresponding SBLS, and the third NW supports the second SBLS of the two or more corresponding SBLS.

Claims

1. A circuit for a semiconductor device, comprising: Two or more input circuits are configured to operate in the first voltage domain accordingly; Two or more one-bit level shifters (SBLS) are electrically coupled to the two or more input circuits and are configured to operate in the second voltage domain. as well as A control circuit is configured to cause each of the two or more one-bit level shifters (SBLS) to switch between a normal state and a standby state when it receives a control signal from the control circuit, wherein a portion of the control circuit shares an n-well (NW) with a portion of at least one of the two or more one-bit level shifters (SBLS).

2. The circuit according to claim 1, wherein, Each of the two or more input circuits includes at least a first P-type transistor in a first n-well NW.

3. The circuit according to claim 1, wherein, One of the two or more input circuits is located on the first side that bisects the vertical axis, and the other of the two or more input circuits is located on the second side that bisects the vertical axis.

4. The circuit according to claim 1, wherein, Each of the two or more input circuits includes at least a first P-type transistor in a first n-well NW located at the intersection of the vertical axis and the horizontal axis.

5. The circuit according to claim 1, wherein, Each of the two or more one-bit level shifters (SBLS) receives an input from one of the two or more input circuits and converts the input from the first voltage domain to the second voltage domain.

6. The circuit according to claim 1, wherein, Each of the two or more input circuits includes at least a first P-type transistor in a first n-well NW, and each of the two or more one-bit level shifters SBLS includes at least a second P-type transistor, wherein the second P-type transistor from the first SBLS is in the second n-well NW, and the second P-type transistor from the second SBLS is in the third n-well NW.

7. The circuit according to claim 1, wherein, Each of the two or more input circuits includes at least a first P-type transistor in an n-well NW, and each of the two or more one-bit level shifters SBLS includes at least a second P-type transistor, wherein the second P-type transistor from at least one SBLS is in a second n-well NW, and a third P-type transistor from another SBLS is in a third n-well NW, wherein the second n-well NW and the third n-well NW are located on opposite sides bisecting the vertical axis.

8. The circuit according to claim 1, wherein, The two or more one-bit level shifters (SBLS) are symmetrically located on opposite sides of the vertical axis.

9. An integrated circuit IC, comprising: The first N-well NW is located at the intersection of the vertical axis and the horizontal axis; The second N-well NW is located on the first side of the vertical axis along the horizontal axis; The third N-well NW is located on the second side of the vertical axis along the horizontal axis; The first power node is configured to have a first power supply voltage; as well as The second power node is configured to have a second power supply voltage; The third power node is configured to have a third power supply voltage; An input circuit, configured to receive an input signal in a first voltage domain, the input circuit comprising: A first PMOS transistor is located in the first N-well NW, and the first PMOS transistor includes a first source / drain S / D terminal coupled to the first power node; and A second PMOS transistor is located in the first N-well NW, and the second PMOS transistor includes a second S / D terminal coupled to the first power node; and At least two one-bit level shifters (SBLS), including: The first SBLS includes a third PMOS transistor in the second N-well NW, and the third PMOS transistor includes a third S / D terminal coupled to the second power node; and The second SBLS includes a fourth PMOS transistor in the third N-well NW, and the fourth PMOS transistor includes a fourth S / D terminal coupled to the second power node; Wherein, the first SBLS and the second SBLS are configured to receive corresponding input signals from the input circuit and convert the corresponding input signals from the first voltage domain to the second voltage domain; and A control circuit, electrically coupled to the first SBLS and the second SBLS, is configured to switch the first SBLS and the second SBLS between a normal mode and a standby mode according to a switching control signal.

10. The integrated circuit IC according to claim 9, wherein the control circuit further comprises: A fifth PMOS transistor is located in one of the second N-well NW and the third N-well NW, the fifth PMOS transistor including a fifth S / D terminal coupled to the second power node, the fifth S / D terminal being electrically coupled to one of the first SBLS and the second SBLS.

11. The integrated circuit IC according to claim 9, wherein the at least two SBLS further comprises: A first NMOS transistor is located outside the second N-well NW and electrically coupled to the third PMOS transistor. The first NMOS transistor includes a sixth S / D terminal electrically coupled to the control circuit. as well as A second NMOS transistor is located outside the third N-well (NW) and electrically coupled to the fourth PMOS transistor. The second NMOS transistor includes a seventh S / D terminal electrically coupled to the control circuit.

12. The integrated circuit IC according to claim 9, wherein: The second N-well NW is located on the first side of the horizontal axis and the first side of the vertical axis; The third N-well NW is located on the first side of the horizontal axis and the second side of the vertical axis; The IC also includes: The fourth N-well NW is located on the second side of the horizontal axis and the first side of the vertical axis; as well as The fifth N-well NW is located on the second side of the horizontal axis and the second side of the vertical axis.

13. The integrated circuit IC according to claim 9, wherein: The first power supply voltage is greater than the second power supply voltage, or the second power supply voltage is greater than the first power supply voltage; and Both the first power supply voltage and the second power supply voltage are greater than the third power supply voltage.

14. The integrated circuit IC according to claim 9, wherein: The third PMOS transistor is located within the first SBLS; The fourth PMOS transistor is located within the second SBLS. The IC also includes: A fifth PMOS transistor, located in the second N-well NW, includes a sixth S / D terminal coupled to the second power node, and is located within the third SBLS; and A sixth PMOS transistor is located in the third N-well NW, the sixth PMOS transistor includes a seventh S / D terminal coupled to the second power node, and the sixth PMOS transistor is located within the fourth SBLS; The first SBLS, the second SBLS, the third SBLS, and the fourth SBLS are all electrically coupled to the control circuit; and The control circuit is also configured to switch each of the first SBLS, the second SBLS, the third SBLS and the fourth SBLS between a normal state and a standby state.

15. The integrated circuit IC according to claim 14, wherein, Each of the second N-well NW and the third N-well NW supports two SBLS.

16. A method of operating a plurality of one-bit level shifters (SBLS), the method comprising: Receives a first power supply voltage and a second power supply voltage, wherein the second power supply voltage is between the first power supply voltage and the third power supply voltage; Receives input from a first voltage domain that operates under the first power supply voltage at two or more input circuits electrically connected to the first power supply voltage; The input version from the first voltage domain is output from the two or more input circuits to two or more corresponding SBLSs that operate in the second voltage domain and are electrically connected to the second power supply voltage; The input version is correspondingly converted from the first voltage domain to the second voltage domain by two or more one-bit level shifters (SBLS); A switching control signal from the control circuit is received at each of the two or more corresponding SBLS, wherein a portion of the control circuit shares an n-well NW with a portion of at least one of the two or more one-bit level shifter SBLS. as well as Based on the switching control signal, two or more corresponding SBLSs are switched between normal mode and standby mode.

17. The method according to claim 16, wherein, The two or more input circuits all share the first n-well NW.

18. The method according to claim 17, wherein, The first n-well NW bisects the vertical axis and the horizontal axis.

19. The method according to claim 17, wherein, The second n-well NW is shared by two of the two or more corresponding SBLS.

20. The method of claim 17, wherein, The second n-well NW supports the first SBLS of the two or more corresponding SBLS, and the third NW supports the second SBLS of the two or more corresponding SBLS.

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