sign bit adder circuit and binary signed number adder circuit

Abstract

This disclosure provides a sign bit addition circuit, a binary signed number addition circuit, a chip, and a computing device. The sign bit addition circuit includes an input module, a highest-value bit operation module, and a sign bit operation module. The input module receives the first and second sign bits of first and second data, as well as the carry value corresponding to the highest-value bit of the first and second data. Based on the first sign bit, the second sign bit, and the carry value, an intermediate value is generated. The sign bit operation module performs logical operations on the intermediate value to obtain and output the sign bit of the sum of the first and second data. The highest-value bit operation module receives the intermediate value, performs logical operations on it, and obtains and outputs the highest-value bit of the sum. This disclosure simplifies the circuit structure, reduces the adder area, decreases power consumption, reduces computational latency, and ultimately improves computational efficiency.

Description

Technical Field

[0001] This disclosure relates to the field of computer technology, and in particular to a sign bit addition circuit and a binary signed number addition circuit, a chip, and a computing device. Background Technology

[0002] In computers, binary numbers are divided into signed and unsigned numbers. Taking 1001 as an example, when 1001 is a 4-bit unsigned binary number, all 4 bits are numerical bits, which is equal to the decimal number 9. When 1001 is a 4-bit signed binary number, the highest bit of these 4 bits is the sign bit, where 1 indicates that the number is negative and 0 indicates that the number is positive. The remaining three bits "001" are numerical bits. Therefore, 1001 is a signed number, which is negative. According to the two's complement conversion of negative numbers, 1001 is equal to the decimal number -7.

[0003] In chip design, traditional adder logic circuits such as full adders and half adders are typically used to perform calculations on binary numbers. When calculating the addition of two multi-bit numbers, multiple adders can usually be used.

[0004] When processing the addition of multi-bit numbers with and without signed bits, current techniques require different numbers of conventional adders. For example, ... Figure 1A As shown, it illustrates an existing addition circuit for two 4-bit unsigned numbers (i.e., A3A2A1A0 and B3B2B1B0). This scheme uses a structure of four conventional adders connected in series to complete the addition calculation and generate an unsigned 5-bit binary number (i.e., S4S3S2S1S0), where the highest bit S4 is the numerical bit, which is obtained from the carry output of the highest bit adder.

[0005] like Figure 1B As shown, it illustrates an existing addition circuit for two 4-bit signed numbers. This scheme uses a structure of five conventional adders connected in series to perform the addition calculation and generate a 5-bit signed binary number, where the highest bit S4 is the sign bit, which is obtained by summing A3, B3 and carry Ci3 by the highest bit adder.

[0006] Depend on Figure 1B It can be seen that the traditional adder carry-serial structure used in the current processing of signed number addition requires two adders to process the sign bit of the input data, which leads to the complexity of the circuit structure. Summary of the Invention

[0007] Embodiments of this disclosure provide a signed bit addition circuit and a binary signed number addition circuit, a chip, and a computing device.

[0008] According to one aspect of the present disclosure, a sign bit addition circuit is provided. The circuit includes: an input module, a highest value bit operation module, and a sign bit operation module. The input module is used to receive a first sign bit and a second sign bit of first data and second data to be added, as well as a carry value corresponding to the highest value bit of the first data and the second data; and to generate an intermediate value based on the first sign bit, the second sign bit, and the carry value. The sign bit operation module is used to receive the intermediate value, perform logical operations on the intermediate value, obtain and output the sign bit of the sum of the first data and the second data. The highest value bit operation module is used to receive the intermediate value, perform logical operations on the intermediate value, obtain and output the highest value bit of the sum.

[0009] In some embodiments, the input module is used to perform logical operations on the first sign bit and the second sign bit to output an intermediate value; the highest value bit operation module includes a first inverting unit and a first selection unit, and the sign bit operation module includes a second inverting unit and a second selection unit. The first inverting unit and the second inverting unit are respectively used to perform inverting operations on the carry value; the first selection unit is used to select a value as the highest value bit of the sum from the carry value and the inverted value output by the first inverting unit according to the intermediate value; the second selection unit is used to select a value as the sign bit of the sum from the input sign bit value and the inverted value output by the second inverting unit according to the intermediate value, wherein the input sign bit value includes the first sign bit and / or the second sign bit.

[0010] In some embodiments, the input module includes an XOR gate and a NAND gate; the XOR gate is used to perform an XOR operation on the first sign bit and the second sign bit to obtain a first intermediate value; the NAND gate is used to perform an NAND operation on the first sign bit and the second sign bit to obtain a second intermediate value.

[0011] In some embodiments, the input module further includes a first amplitude expansion subunit and a second amplitude expansion subunit; the first amplitude expansion subunit is connected to the output of an XOR gate and is used to expand the level swing of the first intermediate value; the second amplitude expansion subunit is connected to the output of an XNOR gate and is used to expand the level swing of the second intermediate value.

[0012] In some embodiments, the first selection unit includes a first switch and a second switch, and the second selection unit includes a third switch and a fourth switch. The control terminals of the first, second, third, and fourth switches are used to receive intermediate values. The input terminal of the first switch is used to receive carry values, and the output terminal of the first switch is used to output the highest value bit of the sum. The two input terminals of the second switch are respectively connected to the output terminals of the first and second inverting units, and the output terminal of the second switch is used to output the highest value bit of the sum. The input terminal of the third switch is used to receive the input sign bit value, and the output terminal of the third switch is used to output the sign bit of the sum. The two input terminals of the fourth switch are respectively connected to the output terminals of the first and second inverting units, and the output terminal of the fourth switch is used to output the sign bit of the sum.

[0013] In some embodiments, the first switch and the third switch are switches of the transmission gate structure, respectively.

[0014] In some embodiments, the second switch and the fourth switch are switches consisting of two transistors connected in series.

[0015] According to another aspect of the present disclosure, a binary signed number addition circuit is provided. The circuit includes: a sign bit adder and a preset number of value bit adders. The sign bit adder is composed of the aforementioned sign bit addition circuit. The sign bit adder includes a first sign bit input terminal, a second sign bit input terminal, a carry input terminal, a sign bit output terminal, and a highest value bit output terminal. The first sign bit input terminal and the second sign bit input terminal are respectively used to receive the sign bits of the first data and the second data to be added. The carry input terminal is used to receive the carry output by the highest value bit adder among the preset number of value bit adders. The sign bit output terminal is used to output the sign bit of the sum of the first data and the second data. The highest value bit output terminal is used to output the highest value bit of the sum. The value bit output terminals of the preset number of value bit adders are respectively used to output the corresponding value bits of the sum.

[0016] According to another aspect of the present disclosure, a chip is provided that includes the above-described binary signed number addition circuit.

[0017] According to another aspect of the present disclosure, a computing device is provided, the computing device including the above-described chip.

[0018] The sign bit addition circuit, binary signed number addition circuit, chip, and computing device provided in the above embodiments of this disclosure integrate the operation process of the sign bits of the first and second binary signed data into one addition circuit based on the principle of binary signed number addition. That is, the circuit can perform operations on the input first and second sign bits and carry value, and output the sign bit and the highest value bit of the sum of the first and second data. Compared with the prior art, which requires two adders to process the first sign bit, second sign bit, and carry value when performing addition operations, the embodiments of this disclosure reduce the number of adders required for addition operations, simplify the circuit structure, reduce the area of ​​the adders, reduce the power consumption, reduce the operation delay time, and ultimately improve the operation efficiency.

[0019] The technical solutions of this disclosure will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0020] The above and other objects, features, and advantages of this disclosure will become more apparent from the more detailed description of the embodiments thereof in conjunction with the accompanying drawings. The drawings are provided to further illustrate the embodiments of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the disclosure and do not constitute a limitation thereof. In the drawings, the same reference numerals generally represent the same components or steps.

[0021] Figure 1A This is an exemplary schematic diagram of an existing 4-bit unsigned number adder circuit.

[0022] Figure 1B This is an exemplary schematic diagram of an existing 4-bit signed number adder circuit.

[0023] Figure 2 This is a schematic diagram of the sign bit adder circuit provided in an exemplary embodiment of this disclosure.

[0024] Figure 3 This is a schematic diagram of adding binary signed first data and second data according to an exemplary embodiment of this disclosure.

[0025] Figure 4 This is a schematic diagram of the sign bit addition circuit provided in another exemplary embodiment of this disclosure.

[0026] Figure 5 This is a schematic diagram of the sign bit addition circuit provided in another exemplary embodiment of this disclosure.

[0027] Figure 6 This is a schematic diagram of the structure of the first selection unit and the second selection unit provided in an exemplary embodiment of this disclosure.

[0028] Figure 7 This is a schematic diagram of the sign bit addition circuit provided in another exemplary embodiment of this disclosure.

[0029] Figure 8 This is a schematic diagram of the structure of a binary signed number addition circuit provided in an exemplary embodiment of this disclosure. Detailed Implementation

[0030] Hereinafter, exemplary embodiments according to the present disclosure will be described in detail with reference to the accompanying drawings. Obviously, the described embodiments are merely some embodiments of the present disclosure, and not all embodiments of the present disclosure, and it should be understood that the present disclosure is not limited to the exemplary embodiments described herein.

[0031] It should be noted that, unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps set forth in these embodiments do not limit the scope of this disclosure.

[0032] Those skilled in the art will understand that the terms "first," "second," etc., in the embodiments of this disclosure are only used to distinguish different steps, devices, or modules, and do not represent any specific technical meaning, nor do they indicate a necessary logical order between them.

[0033] It should also be understood that in the embodiments disclosed herein, "a plurality of" may refer to two or more, and "at least one" may refer to one, two or more.

[0034] It should also be understood that any component, data or structure mentioned in the embodiments of this disclosure can generally be understood as one or more unless expressly defined or given to the contrary in the context.

[0035] Furthermore, the term "and / or" in this disclosure is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this disclosure generally indicates that the preceding and following related objects have an "or" relationship.

[0036] It should also be understood that the description of the various embodiments in this disclosure emphasizes the differences between the various embodiments, and the similarities or similarities can be referred to each other. For the sake of brevity, they will not be described in detail.

[0037] At the same time, it should be understood that, for ease of description, the dimensions of the various parts shown in the accompanying drawings are not drawn according to actual scale.

[0038] The following description of at least one exemplary embodiment is merely illustrative and is in no way intended to limit this disclosure or its application or use.

[0039] Techniques, methods, and equipment known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and equipment should be considered part of the specification.

[0040] It should be noted that similar labels and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be discussed further in subsequent figures.

[0041] Application Overview

[0042] Existing technologies for adding signed numbers employ a traditional carry-serial structure, which requires more adders compared to unsigned data addition circuits of the same number of bits. Due to the characteristics of its delay path, the longest delay for adding two N-bit numbers is the sum of the N-stage carry chain and the computational delay of the first and last full adders. The power consumption is equal to the total power consumption of N+1 full adders, and the area is equal to the sum of the areas of N+1 full adders.

[0043] The typical adders commonly used in existing technologies usually include 28 MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors). When processing signed number addition, two adders are required, totaling 56 MOSFETs to complete the addition operation of the sign bit and the highest value bit. This results in large calculation delay, power consumption, and circuit area, and low calculation efficiency.

[0044] To address this problem, this disclosure provides a signed bit addition circuit that, when processing signed bit addition, requires only N adders to add two N-bit numbers. The longest computation delay is equal to the computation delay of the N-1-stage carry chain plus the first and last full adders, the power consumption is the total power consumption of N full adders, and the area is the sum of the areas of N full adders. Therefore, compared to the prior art, the solution of this disclosure significantly improves computational efficiency when performing signed number addition.

[0045] Exemplary Structure

[0046] Figure 2 This is a schematic diagram of the sign bit addition circuit provided in an exemplary embodiment of this disclosure. The various components of this circuit can be integrated into a single chip or disposed in discrete components, and data communication links are established between these discrete components.

[0047] like Figure 3As shown, it illustrates the addition of the first and second binary signed data. The first and second data are An An-1 An-2……A1 A0 and Bn Bn-1 Bn-2……B1 B0, respectively. Here, An and Bn are the sign bits, An-1 and Bn-1 are the highest value bits of the two numbers, Sn+1 is the sign bit of the sum of the two numbers, Sn is the highest value bit of the sum of the two numbers, and Ci is the carry value from the (n-1)th bit to the nth bit.

[0048] According to the principle of signed number addition, when both An and Bn are 0, that is, both binary numbers are positive, their sum must also be positive. Therefore, Sn+1 is 0, and Sn = Ci.

[0049] When both An and Bn are 1, that is, both binary numbers are negative, the sum must also be negative. Therefore, Sn+1 is 1, and Sn = Ci.

[0050] When An and Bn are not the same, that is, when a positive number and a negative number are added, if Ci = 0, that is, there is no carry, it means that the sum is negative, so Sn+1 is 1, and Sn = Ci is inverted; if Ci = 1, that is, there is a carry, it means that the sum is positive, so Sn+1 is 0, and Sn = Ci is inverted.

[0051] Based on the above logical relationships, the circuit logic truth table of this embodiment is shown in Table 1 below:

[0052] Table 1

[0053] 0 0 0 0 0 0 1 0 1 1 1 0 0 1 1 1 1 0 0 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 0 1 1 1 1 1

[0054] Based on the logic truth table shown in Table 1, the sign bit adder circuit provided in this embodiment can be obtained. For example... Figure 2 As shown, the circuit includes: an input module 201, a highest value bit operation module 202, and a sign bit operation module 203.

[0055] The input module 201 is used to receive the first sign bit and the second sign bit of the first data and the second data to be added, as well as the carry value corresponding to the highest value bit of the first data and the second data; and to generate an intermediate value based on the first sign bit, the second sign bit and the carry value.

[0056] Here, the first and second data mentioned above are signed binary numbers. For example... Figure 3 As shown, the first sign bit is An, the second sign bit is Bn, the highest value bits of the first and second data are An-1 and Bn-1, and Ci is the carry value from the (n-1)th bit to the nth bit.

[0057] The intermediate value can be obtained by the input module 201 after processing the first sign bit An, the second sign bit Bn, and the carry value Ci in any preset way, or it can be the value directly output by the input module 201 without any processing of the first sign bit An, the second sign bit Bn, and the carry value Ci, or indirectly output through a switching element, etc.

[0058] The sign bit operation module 203 is used to receive intermediate values, perform logical operations on the intermediate values, and obtain and output the sign bit of the sum of the first data and the second data.

[0059] The highest value bit operation module 202 is used to receive intermediate values, perform logical operations on the intermediate values, and obtain and output the highest value bit of the sum.

[0060] Optionally, based on the truth table shown in Table 1, existing logic circuit design methods (such as Karnaugh map-based simplification methods) can be used to design two logic circuits: a sign bit operation module 203 and a highest value bit operation module 202. These two logic circuits can be constructed from various types of gate circuits, switching circuits, etc. The intermediate values ​​at this time are the first sign bit An, the second sign bit Bn, and the carry value Ci, which have not been processed by the input module. The first sign bit An, the second sign bit Bn, and the carry value Ci are input to the sign bit operation module, which outputs the sign bit Sn+1 of the sum of the first and second data. The first sign bit An, the second sign bit Bn, and the carry value Ci are input to the highest value bit operation module, which outputs the highest value bit Sn of the sum of the first and second data.

[0061] The circuit provided in the above embodiments of this disclosure integrates the operation process of the sign bits of the first and second binary signed data into one addition circuit based on the principle of binary signed number addition. That is, the circuit can perform operations on the input first and second sign bits and the carry value, and output the sign bit and the highest value bit of the sum of the first and second data. Compared with the prior art, which requires two adders to process the first sign bit, the second sign bit and the carry value when performing addition operations, the embodiments of this disclosure reduce the number of adders required for addition operations, simplify the circuit structure, reduce the area of ​​the adders, reduce the power consumption of the operation, reduce the operation delay time, and ultimately improve the operation efficiency.

[0062] In some alternative implementations, the input module 201 is used to perform logical operations on the first sign bit and the second sign bit to output an intermediate value.

[0063] The method of performing logical operations on the two sign bits can be arbitrarily set as needed. For example, the input module may include an XOR gate to perform an XOR operation on the two sign bits.

[0064] like Figure 4 As shown, the highest value bit operation module 202 includes a first inverting unit 2021 and a first selection unit 2022, and the sign bit operation module 203 includes a second inverting unit 2031 and a second selection unit 2032. The first inverting unit 2021 and the second inverting unit 2031 are respectively used to perform inversion operation on the carry value.

[0065] The first selection unit 2022 is used to select a value as the highest value bit of the sum from the carry value and the inverted value output by the first inverting unit 2021, based on the intermediate value.

[0066] The second selection unit 2032 is used to select a value as the sign bit of the sum from the input sign bit value and the inverted value output by the second inverting unit 2031 based on the intermediate value, wherein the input sign bit value includes the first sign bit and / or the second sign bit.

[0067] like Figure 4 As shown, the input module 201 may include an XNOR gate 2011, which receives the first sign bit An and the second sign bit Bn. The input module directly transmits the carry value Ci corresponding to the highest value bit of the first and second data to the highest value bit operation module and the sign bit operation module. The first inverting unit 2021 and the second inverting unit 2031 may be composed of NOT gate circuits, receiving Ci and outputting CiB (i.e., the inverted value of Ci) respectively. The first selection unit 2022 and the second selection unit 2032 may be composed of circuits simulating a single-pole double-throw switch. The first selection unit 2022 receives the input Ci and CiB, and the second selection unit 2032 receives the input An / Bn (i.e., the input sign bit value, either An or Bn) and CiB. The intermediate value H output by the XOR gate 2011 is used as the control signal for the first selection unit 2022 and the second selection unit 2032. The first selection unit 2022 and the second selection unit 2032 select output Ci and CiB as Sn according to H, and select output An / Bn and CiB as Sn+1.

[0068] The specific logical operation process is as follows:

[0069] When An=0, Bn=0, or An=1, Bn=1, H=1, Sn=Ci, Sn+1=An / Bn;

[0070] When An = 0 and Bn = 1, or An = 1 and Bn = 0, H = 0, Sn = CiB, Sn+1 = CiB.

[0071] As can be seen from Table 1 above, the logic operation process conforms to the logic truth table shown in Table 1.

[0072] This embodiment achieves full addition of the sign bit of a binary signed number based on a simpler circuit by performing logical operations on the first and second sign bits through the input module, and by setting up a first inverting unit and a first selection unit, as well as a second inverting unit and a second selection unit. Compared with the prior art which requires two adders to operate on the sign bit, this embodiment can achieve the operation of adding the sign bit with a simpler circuit, thereby improving the manufacturing efficiency of the sign bit addition circuit and the calculation efficiency of the signed number.

[0073] In some alternative implementations, the input module 201 includes an XNOR gate 2011 and an XOR gate 2012.

[0074] XOR gate 2012 is used to perform an XOR operation on the first sign bit and the second sign bit to obtain a first intermediate value. XNOR gate 2011 is used to perform an XNOR operation on the first sign bit and the second sign bit to obtain a second intermediate value.

[0075] The first intermediate value and the second intermediate value can be used simultaneously as control signals for the first selection unit and the second selection unit.

[0076] like Figure 5 As shown, the input module 201 includes an XOR gate 2011 and an XOR gate 2012, which output H and HB (i.e., the inverted value of H) respectively. H and HB are the first intermediate value and the second intermediate value, and also serve as control signals for the first selection unit and the second selection unit.

[0077] like Figure 7 As shown, a sign bit adder circuit based on MOS transistor combinational logic is illustrated, which includes 20 MOS transistors, T1-T20. T1-T4 in the figure form an XOR gate 2012, and T5-T8 form an XNOR gate 2011. The output second intermediate value and first intermediate value are represented as HB and H, respectively.

[0078] This embodiment, by setting XOR gates and NAND gates in the input module, enables the first selection unit and the second selection unit to be controlled by a first intermediate value and a second intermediate value that are inverses of each other. This improves the stability of the circuit logic operation process and helps to improve the accuracy of addition operations.

[0079] In some alternative implementations, the input module may also include a first amplitude expansion subunit and a second amplitude expansion subunit.

[0080] The first swing expansion subunit is connected to the output of the XOR gate and is used to expand the level swing of the first intermediate value. The second swing expansion subunit is connected to the output of the XNOR gate and is used to expand the level swing of the second intermediate value. The purpose of setting up the first and second swing expansion subunits is to reduce the threshold loss of the levels corresponding to the first and second intermediate values, respectively. Typically, the first and second swing expansion subunits can be implemented in various ways, such as using components like MOSFETs or transistors to reduce threshold loss.

[0081] like Figure 7 As shown, it includes T9 and T10, which are the first and second swing expansion sub-units, respectively. T9 and T10 are NMOS and PMOS transistors, respectively, with their inputs connected to each other's outputs, thus achieving a complementary effect. As can be seen from the figure, when An and Bn are different, HB=1, H=0, T9 and T10 are both off, the HB signal is set to a high level (close to VDD) through T1 or T2, and the H signal is set to a low level (close to VSS) through T7 or T8, resulting in very small threshold losses for H and HB. When An and Bn are the same, HB=0, H=1, T9 is on, HB is connected to VSS, outputting a low level, and simultaneously T10 is also on, H is connected to VDD, outputting a high level. Therefore, the levels of H and HB are close to VDD and VSS, respectively, reducing the threshold losses for H and HB.

[0082] This embodiment can effectively improve the level swing corresponding to the first and second intermediate values ​​by setting a first swing extension subunit and a second swing extension subunit in the input module, reduce threshold loss, and thus further improve the stability of the circuit, that is, further improve the accuracy of addition operation.

[0083] In some alternative implementations, such as Figure 6 As shown, the first selection unit 2022 includes a first switch 20221 and a second switch 20222, and the second selection unit 2032 includes a third switch 20321 and a fourth switch 20322. The control terminals of the first switch 20221, the second switch 20222, the third switch 20321 and the fourth switch 20322 are used to receive intermediate values.

[0084] The input terminal of the first switch 20221 is used to receive the carry value Ci, and the output terminal of the first switch 20221 is used to output the highest value bit Sn of the sum; the two input terminals of the second switch 20222 are respectively connected to the output terminals of the first inverting unit 2021 and the second inverting unit 2031, and the output terminal of the second switch 20222 is used to output the highest value bit Sn of the sum.

[0085] Among them, the first switch 20221 and the third switch 20321 are single-input single-output switches, which are controlled to open or close by the intermediate value output by the input module; the second switch 20222 and the fourth switch 20322 are double-input single-output switches (i.e., single-pole double-throw switches), which are controlled by the above intermediate value to connect one of the input terminals to the output terminal.

[0086] The input terminal of the third switch 20321 is used to receive the input sign bit value An / Bn, and the output terminal of the third switch 20321 is used to output the sign bit Sn+1 of the sum value; the two input terminals of the fourth switch 20322 are respectively connected to the output terminals of the first inverting unit 2021 and the second inverting unit 2031, and the output terminal of the fourth switch 20322 is used to output the sign bit of the sum value.

[0087] like Figure 6 As shown, if the input module includes an XOR gate, and the intermediate value H controls the state of each switch, then the specific logic operation flow is as follows:

[0088] When An = 0, Bn = 0, or An = 1, Bn = 1, H = 1. At this time, the first switch 20221 and the third switch 20321 are turned on, and the second switch 20222 and the fourth switch 20322 are turned off. Sn = Ci, Sn+1 = An / Bn.

[0089] When An = 0 and Bn = 1, or An = 1 and Bn = 0, H = 0. At this time, the first switch 20221 and the third switch 20321 are closed, and the second switch 20222 and the fourth switch 20322 are open. Sn = CiB and Sn+1 = CiB.

[0090] The logic operation process conforms to the logic truth table shown in Table 1.

[0091] This embodiment sets a first switch and a second switch in the first selection unit, and a third switch and a fourth switch in the second selection unit. The state of each switch is controlled by an intermediate value. This allows for the accurate output of the sign bit and the highest value bit of the sum of the first and second data through a simple switching circuit. This helps to reduce the manufacturing difficulty of the circuit and improves the manufacturing efficiency and design flexibility of the sign bit addition circuit.

[0092] In some alternative implementations, the first switch and the third switch are respectively switches of the transmission gate structure. For example... Figure 7 As shown, T11 and T12 form the first switch of the transmission gate structure, and T13 and T14 form the second switch of the transmission gate structure. Since the switch of the transmission gate structure contains two control terminals, this embodiment can combine the first intermediate value and the second intermediate value in the above optional embodiment to control the state of the first switch and the second switch.

[0093] like Figure 7 As shown, when H=1 and HB=0, both the first and third switches are on, and Sn=Ci and Sn+1=An / Bn. When H=0 and HB=1, both the first and third switches are off, and Sn and Sn+1 need to be transmitted by the second and fourth switches.

[0094] It should be noted that, Figure 7 The transmission gate structure shown is just an example. In practical applications, the first and third switches can also be constructed using transmission gates made in other ways.

[0095] This embodiment, by setting the first and third switches as transmission gate structures, can effectively utilize the characteristics of transmission gates, which have very low on-resistance and very high off-resistance, as well as the output data level being close to the full swing, thereby improving the stability of the sign bit addition circuit, and thus further improving the accuracy of addition operations.

[0096] In some alternative implementations, the second and fourth switches are switches consisting of two transistors connected in series. For example... Figure 7 As shown, it includes T17 and T19 forming a second switch in series, and T18 and T20 forming a fourth switch in series. T15 and T16 constitute the first inverting unit and the second inverting unit, respectively.

[0097] Since the switch with two transistors connected in series contains two control terminals, this embodiment can combine the first intermediate value and the second intermediate value in the optional embodiment above, and control the state of the second switch and the fourth switch with the first intermediate value and the second intermediate value.

[0098] like Figure 7 As shown, when H = 0 and HB = 1, the first switch (T11, T12) and the third switch (T13, T14) are both off, while T17, T18, T19, and T20 are all on. If Ci = 0, then T15 is on, T16 is off, Sn = 1, and Sn+1 = 1; if Ci = 1, then T15 is off, T16 is on, Sn = 0, and Sn+1 = 0, which means Sn = CiB and Sn+1 = CiB. This logic flow conforms to the logic truth table shown in Table 1 above. Figure 7 The 20T sign bit adder circuit shown requires only 20 MOSFETs to process the sign bit, compared to the commonly used 28T adder. Existing technology requires two 28T adders, totaling 56 MOSFETs, for sign bit processing. Therefore… Figure 7 The circuit shown has significantly reduced power consumption, area, and delay compared to existing technologies.

[0099] This embodiment sets the second and fourth switches as switches of two transistors connected in series, which can more stably control the output of the inverted value of the carry value of the inverter, thereby further improving the stability of the sign bit addition circuit, that is, further improving the accuracy of the addition operation.

[0100] Figure 8 This is a schematic diagram of a binary signed number addition circuit provided in an exemplary embodiment of this disclosure. The various components of this circuit can be integrated into a single chip or disposed in discrete components, with data communication links established between these discrete components.

[0101] like Figure 8 As shown, the circuit includes: a sign bit adder 801 and a preset number of value bit adders 802. The sign bit adder 801 consists of the aforementioned... Figure 2 The sign bit adder circuit described in the corresponding embodiment includes a first sign bit input terminal, a second sign bit input terminal, a carry input terminal, a sign bit output terminal, and a highest value bit output terminal.

[0102] The first sign bit input terminal and the second sign bit input terminal are used to receive the sign bits of the first data and the second data to be added, respectively. The carry input terminal is used to receive the carry output by the highest value bit among a preset number of value bit adders.

[0103] As an example, suppose the first and second data are An An-1 An-2……A1 A0 and Bn Bn-1Bn-2……B1 B0 respectively, where An and Bn are the sign bits, An-1 and Bn-1 are the highest-value bits of the two numbers, Sn+1 is the sign bit of the sum of the two numbers, Sn is the highest-value bit of the sum of the two numbers, and Ci is the carry value from the (n-1)th bit to the nth bit. Figure 8 As shown, An and Bn are input to the sign bit adder 801 via the first sign bit input terminal and the second sign bit input terminal, respectively, and Ci is input to the sign bit adder 801 via the carry input terminal.

[0104] The sign bit output terminal is used to output the sign bit of the sum of the first and second data, the highest value bit output terminal is used to output the highest value bit of the sum, and the value bit output terminals of the preset number of value bit adders are used to output the corresponding value bits of the sum.

[0105] like Figure 8 As shown, Sn+1 is the sign bit of the sum of the first and second data, output from the sign bit output terminal. Sn is the highest value bit of the sum, output from the highest value bit output terminal. Sn-1, Sn-2, ..., S1, S0 are output from the value bit output terminals of each value bit adder. (Comparison) Figure 1B and Figure 8 It can be seen that the existing technology requires two adders to process the sign bits of the two data to be added in order to obtain the sign bit and the highest value bit of the sum. However, this embodiment only requires one sign bit adder to process the sign bits of the two data to be added and obtain the sign bit and the highest value bit of the sum.

[0106] The binary signed number addition circuit provided in the above embodiments of this disclosure integrates the operation process of the sign bits of the first and second binary signed data into one addition circuit. That is, the circuit can perform operations on the two input sign bits and the carry value, and output the sign bit and the highest value bit of the sum of the first and second data. Compared with the prior art, which requires N+1 adders to perform N-bit signed number addition operations, the embodiments of this disclosure only require N adders, thereby reducing the number of adders required for addition operations, simplifying the circuit structure, reducing the area of ​​the addition circuit, reducing the power consumption of the operation, reducing the operation delay time, and ultimately improving the operation efficiency.

[0107] Embodiments of this disclosure also provide a chip on which a binary signed number addition circuit is integrated. Technical details of the binary signed number addition circuit are as follows: Figures 2-8 As shown in the relevant descriptions, further details will not be provided here.

[0108] Embodiments of this disclosure also provide a computing device including the chip described in the above embodiments. Furthermore, the computing device may also include an input device, an output device, and necessary memory. The input device may include, for example, a mouse, keyboard, touchscreen, or communication network connector, for inputting first data and second data to be added. The output device may include, for example, a display, printer, and communication network and its connected remote output devices, for outputting the sum of the first and second data, including a sign bit and a value bit. The memory is used to store the data input by the input device and the data generated during the operation of the binary signed number addition circuit. The memory may include volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory. Non-volatile memory may include, for example, read-only memory (ROM), hard disk, flash memory, etc.

[0109] The basic principles of this disclosure have been described above with reference to specific embodiments. However, it should be noted that the advantages, benefits, and effects mentioned in this disclosure are merely examples and not limitations, and should not be considered as essential features of each embodiment of this disclosure. Furthermore, the specific details disclosed above are for illustrative and facilitative purposes only, and are not limitations. These details do not limit the scope of this disclosure to the necessity of employing the aforementioned specific details for implementation.

[0110] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0111] The block diagrams of devices, apparatuses, devices, and systems disclosed herein are merely illustrative examples and are not intended to require or imply that they must be connected, arranged, or configured in the manner shown in the block diagrams. As those skilled in the art will recognize, these devices, apparatuses, devices, and systems can be connected, arranged, and configured in any manner. Words such as “comprising,” “including,” “having,” etc., are open-ended terms meaning “including but not limited to,” and are used interchangeably with them. The terms “or” and “and” as used herein refer to the terms “and / or,” and are used interchangeably with them unless the context clearly indicates otherwise. The term “such as” as used herein refers to the phrase “such as but not limited to,” and is used interchangeably with it.

[0112] The circuits of this disclosure may be implemented in many ways. For example, they may be implemented by software, hardware, firmware, or any combination of software, hardware, and firmware. The above-described order of steps of the method in the circuit is for illustrative purposes only, and the steps of the method of this disclosure are not limited to the order specifically described above, unless otherwise specifically stated. Furthermore, in some embodiments, this disclosure may also be implemented as a program recorded on a recording medium, the program including machine-readable instructions for implementing the functions of the circuits according to this disclosure. Thus, this disclosure also covers recording media storing programs for performing the functions of the circuits according to this disclosure.

[0113] It should also be noted that in the circuits of this disclosure, the components or steps can be decomposed and / or recombined. These decompositions and / or recombinations should be considered as equivalent solutions of this disclosure.

[0114] The above description of the disclosed aspects is provided to enable any person skilled in the art to make or use this disclosure. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects without departing from the scope of this disclosure. Therefore, this disclosure is not intended to be limited to the aspects shown herein, but rather to be carried out within the widest scope consistent with the principles and novel features disclosed herein.

[0115] The above description has been given for purposes of illustration and description. Furthermore, this description is not intended to limit the embodiments of this disclosure to the forms disclosed herein. Although numerous exemplary aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, alterations, additions, and sub-combinations thereof.

Claims

1. A symbol bit addition circuit, comprising: Input module, highest value bit operation module, and sign bit operation module; The input module is used to receive the first sign bit and the second sign bit of the first data and the second data to be added, as well as the carry value corresponding to the highest value bit of the first data and the second data; and to generate an intermediate value based on the first sign bit, the second sign bit and the carry value. The sign bit operation module is used to receive the intermediate value, perform logical operations on the intermediate value, and obtain and output the sign bit of the sum of the first data and the second data. The highest value bit operation module is used to receive the intermediate value, perform logical operations on the intermediate value, and obtain and output the highest value bit of the sum. The input module is used to perform logical operations on the first sign bit and the second sign bit to output an intermediate value; The highest value bit operation module includes a first inverting unit and a first selection unit, and the sign bit operation module includes a second inverting unit and a second selection unit. The first inverting unit and the second inverting unit are respectively used to perform inverting operation on the carry value. The first selection unit is used to select a value as the highest value bit of the sum from the carry value and the inverted value output by the first inverting unit, based on the intermediate value. The second selection unit is used to select a value as the sign bit of the sum from the input sign bit value and the inverted value output by the second inverting unit according to the intermediate value, wherein the input sign bit value includes the first sign bit and / or the second sign bit.

2. The circuit of claim 1, wherein, The input module includes an XOR gate and a XNOR gate; The XOR gate is used to perform an XOR operation on the first sign bit and the second sign bit to obtain a first intermediate value; The XOR gate is used to perform an XOR operation on the first sign bit and the second sign bit to obtain a second intermediate value.

3. The circuit of claim 2, wherein, The input module further includes a first amplitude expansion subunit and a second amplitude expansion subunit; The first swing expansion subunit is connected to the output of the XOR gate and is used to expand the level swing of the first intermediate value; The second swing expansion subunit is connected to the output of the XOR gate and is used to expand the level swing of the second intermediate value.

4. The circuit of claim 1, wherein, The first selection unit includes a first switch and a second switch, and the second selection unit includes a third switch and a fourth switch. The control terminals of the first switch, the second switch, the third switch and the fourth switch are used to receive the intermediate value. The input terminal of the first switch is used to receive the carry value, and the output terminal of the first switch is used to output the highest value bit of the sum; the two input terminals of the second switch are respectively connected to the output terminals of the first inverting unit and the second inverting unit, and the output terminal of the second switch is used to output the highest value bit of the sum. The input terminal of the third switch is used to receive the input sign bit value, and the output terminal of the third switch is used to output the sign bit of the sum value; the two input terminals of the fourth switch are respectively connected to the output terminals of the first inverting unit and the second inverting unit, and the output terminal of the fourth switch is used to output the sign bit of the sum value.

5. The circuit of claim 4, wherein, The first switch and the third switch are switches of the transmission gate structure, respectively.

6. The circuit of claim 4, wherein, The second switch and the fourth switch are switches with two transistors connected in series.

7. A binary signed number adder circuit, comprising: A sign bit adder and a preset number of value bit adders, wherein the sign bit adder is composed of the sign bit adder circuit according to any one of claims 1-6, and the sign bit adder includes a first sign bit input terminal, a second sign bit input terminal, a carry input terminal, a sign bit output terminal, and a highest value bit output terminal; The first sign bit input terminal and the second sign bit input terminal are respectively used to receive the sign bits of the first data and the second data to be added, and the carry input terminal is used to receive the carry output by the highest value bit adder among the preset number of value bit adders; The sign bit output terminal is used to output the sign bit of the sum of the first data and the second data, the highest value bit output terminal is used to output the highest value bit of the sum, and the value bit output terminals of the preset number of value bit adders are respectively used to output the corresponding value bit of the sum.

8. A chip, characterized by Includes the binary signed number adder circuit according to claim 7.

9. A computing device, comprising: Includes the chip according to claim 8.

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