Data flow architecture optimization method and device, and electronic device

Abstract

The application provides a data flow architecture optimization method and device and electronic equipment, the method comprises the following steps: a directed data flow graph representing a coarse-grained reconfigurable array architecture is constructed; a critical path in the directed data flow graph is determined as an initial critical path; whether all nodes on the initial critical path need to be optimized is judged; and the nodes on the initial critical path that need to be optimized are identified and optimized. The method ensures the balance between each node in the coarse-grained data flow graph, so that the execution time of each node is similar, further improves the utilization of the PE in the CGRA, and further realizes the optimization of the coarse-grained reconfigurable array CGRA data flow architecture.

Description

Technical Field

[0001] This invention relates to the field of computer architecture technology, and in particular to a data flow architecture optimization method, apparatus, and electronic device. Background Technology

[0002] Coarse-grained reconfigurable arrays (CGRAs) are spatial computing architectures that can execute programs using a dataflow model. A typical CGRA processor consists of on-chip network connectivity, a physical executor (PE) array, a host, and cache. CGRAs offer better programmability than FPGAs, superior power efficiency compared to GPUs, and more versatile parallel capabilities. Before executing a dataflow program, a CGRA performs an instruction mapping process, mapping the directed dataflow graph (DFG) representing the entire program onto the PE array. In the DFG, nodes represent instructions, connections represent data, and the direction of the connections indicates the dependencies between instructions. By mapping the DFG to the PE array, the timing and execution location of each instruction are determined. The quality of this mapping method directly determines the execution time of a dataflow program on the PE array, and thus directly impacts the program's performance.

[0003] Most existing instruction mapping methods are optimized based on fine-grained dataflow graph mapping models, with almost no research on mapping coarse-grained dataflow graphs based on code segments. In contrast to the traditional fine-grained dataflow model based on instructions, the coarse-grained dataflow model based on code segments, where each node is a code segment rather than an instruction, significantly reduces the number of nodes and the overhead of instruction mapping. It also greatly reduces the number of times computation results are transmitted, thus reducing transmission overhead.

[0004] Research on node mapping in a coarse-grained dataflow model revealed that some excessively large code segments occupy PE (Execution Environment) for extended periods, becoming bottlenecks in the overall program execution. Other nodes may finish executing prematurely, but due to dependencies on these nodes, they are forced to wait idly, resulting in resource waste. Therefore, this invention addresses the problem of certain nodes becoming program execution bottlenecks due to the imbalance in node execution time within a coarse-grained reconfigurable array dataflow architecture, proposing a dataflow architecture optimization method. Summary of the Invention

[0005] To address the shortcomings of existing technologies, this invention proposes a data flow architecture optimization method, apparatus, and electronic device for balancing DFG mapping, shortening program execution time, and improving PE utilization.

[0006] To achieve the above objectives, the present invention provides a data flow architecture optimization method, comprising:

[0007] Construct a directed data flow graph representing the coarse-grained reconfigurable array architecture;

[0008] Determine the critical path in the directed data flow graph as the initial critical path;

[0009] Determine whether optimization is needed for all nodes on the initial critical path;

[0010] Identify and optimize the nodes that need optimization on the initial critical path.

[0011] Optionally, before determining whether optimization is needed for all nodes on the initial critical path, the method further includes:

[0012] Calculate the standard value of the start interval for the directed data flow graph under the existing number of node partitions;

[0013] A preset deviation distance is used to determine whether the number of instructions of a node falls within the deviation distance of the standard value of the startup interval and does not require optimization.

[0014] Optionally, determine whether optimization is needed for all nodes on the initial critical path, including:

[0015] If the number of instructions of the first node is greater than or equal to the difference between the standard value of the start interval and the deviation distance, and less than or equal to the sum of the standard value of the start interval and the deviation distance, no optimization is required for the first node. The first node is any node on the initial critical path.

[0016] Optionally, the step of identifying and optimizing nodes that need optimization on the initial critical path includes:

[0017] If the number of instructions at the first node is less than the difference between the standard value of the startup interval and the deviation distance, then some instructions are moved from the second node to the first node, where the second node is a downstream node of the first node.

[0018] Optionally, the step of identifying and optimizing the nodes that need optimization on the initial critical path further includes:

[0019] If the number of instructions at the first node is greater than the sum of the standard startup interval and the deviation distance, then some instructions are moved from the first node to the second node, which is a downstream node of the first node.

[0020] Optionally, if the first node does not have a downstream node on the initial critical path, then a downstream node is created for the first node as the second node.

[0021] Optionally, the standard value of the startup interval is obtained by rounding up the ratio of the total number of instructions to the number of nodes in the directed data flow graph.

[0022] Optionally, after identifying and optimizing the nodes that need optimization on the initial critical path, the process further includes:

[0023] The critical path of the directed data flow graph is redefined as the final critical path;

[0024] If the final critical path is different from the initial critical path, determine whether all nodes on the final critical path need to be optimized.

[0025] Identify and optimize the nodes that need optimization on the final critical path.

[0026] In another aspect, the present invention provides a data flow architecture optimization apparatus, employing the above-described data flow architecture optimization method, wherein the apparatus comprises at least:

[0027] The DFG building block is used to construct directed data flow graphs that characterize coarse-grained reconfigurable array architectures.

[0028] The critical path determination module is used to determine the critical path in the directed data flow graph as the initial critical path.

[0029] The node optimization module is used to determine whether all nodes on the initial critical path need optimization, and

[0030] Identify and optimize the nodes that need optimization on the initial critical path.

[0031] In another aspect, the present invention provides a storage medium for storing a computer program for performing the above-described data flow architecture optimization method.

[0032] In another aspect, the present invention provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor;

[0033] The processor is a coarse-grained reconfigurable array processor used to implement the above-described data flow architecture optimization method when executing the computer program.

[0034] As can be seen from the above solutions, the advantages of the present invention are:

[0035] The data flow architecture optimization method provided by this invention determines whether a node needs optimization by judging whether the number of instructions of a node falls within the offset distance of the standard value of the startup interval. For the node that needs optimization, the instructions of the node are balanced with those of the downstream node, which ensures the balance between the nodes in the coarse-grained data flow graph, makes the execution time of each node similar, shortens the startup interval of the program after instruction mapping, makes the program pipeline more compact, improves the efficiency of program execution, and further improves the utilization rate of PE in CGRA, thereby realizing the optimization of the coarse-grained reconfigurable array CGRA data flow architecture. Attached Figure Description

[0036] Figure 1 The example code is shown, which includes the instructions, node partitioning, and DFG directed data flow graph.

[0037] Figure 2 This is an unoptimized mapping graph;

[0038] Figure 3 A flowchart illustrating the data flow architecture optimization method provided in this embodiment of the invention;

[0039] Figure 4 This is a mapping graph optimized by nodes;

[0040] Figure 5 This is a framework diagram of the data flow architecture optimization device of the present invention;

[0041] Figure 6 This is a schematic diagram of the structure of an electronic device;

[0042] in:

[0043] 400-Dataflow Architecture Optimization Device;

[0044] 401-DFG building block;

[0045] 402 - Critical Path Determination Module;

[0046] 403 - Node Optimization Module;

[0047] 500 - Electronic Equipment;

[0048] 501-Processor;

[0049] 502 - Memory. Detailed Implementation

[0050] To make the above features and effects of the present invention clearer and easier to understand, specific embodiments are described below, and detailed descriptions are provided in conjunction with the accompanying drawings.

[0051] As mentioned earlier, a coarse-grained reconfigurable array (CGRA) is a spatial computing architecture that can execute programs using a dataflow model. A coarse-grained reconfigurable array processor typically consists of on-chip network connections, a PE array, a host, and caches. Before executing a dataflow program, the CGRA performs an instruction mapping process, mapping the directed dataflow graph (DFG) representing the entire program onto the PE array to determine when and on which PE each instruction will be executed. Research on node mapping under the coarse-grained dataflow model reveals that some excessively large code segments can occupy PEs for extended periods, becoming bottlenecks in the program's execution. Other nodes may finish executing prematurely, but due to dependencies on these nodes, they are left waiting idly, resulting in wasted resources. (See attached...) Figure 1 The program code shown in the image includes a code snippet, the compiled instructions, and a coarse-grained data flow graph. The nodes are partitioned as follows: node N1 implements the first line of code in the loop, node N2 implements the second line, and node N3 implements the third line. It can be seen that directly using the uncompiled code as the basis for node partitioning results in an imbalance in the number of instructions across nodes. The node mapping effect of this imbalanced data flow is shown in the attached image. Figure 2 As shown, nodes N1, N2, and N3 have 5, 10, and 4 instructions respectively. Node N2, with its larger number of instructions, occupies the PE (Program Execution Module) for too long, becoming a bottleneck in program execution. The program's startup interval II is equivalent to the execution time of node N2. Meanwhile, nodes N1 and N3, with fewer instructions, can execute quickly but must wait for node N2 to finish, resulting in idle PE components for nodes N1 and N3. Therefore, this invention addresses the problem of some nodes becoming bottlenecks in program execution due to the imbalance in node execution time in a coarse-grained reconfigurable array dataflow architecture. It proposes a dataflow architecture optimization method that optimizes the dataflow architecture by balancing the nodes in the coarse-grained dataflow graph.

[0052] For details, please refer to Figure 3 As shown, Figure 3 A flowchart illustrating the data flow architecture optimization method is shown;

[0053] A data flow architecture optimization method includes:

[0054] S1. Construct a directed data flow graph representing the coarse-grained reconfigurable array architecture;

[0055] S2. Determine the critical path in the directed data flow graph as the initial critical path;

[0056] S3. Determine whether all nodes on the initial critical path need optimization.

[0057] In practical implementation, the start interval II is commonly used to evaluate the performance of loop programs after CGRA mapping. It represents the time difference between the start times of two adjacent loops, which is the actual time taken for CGRA to complete one loop. In this embodiment, the start interval standard value of the directed data flow graph under the existing number of node partitions is calculated as a benchmark. Then, an offset distance from the start interval standard value is set as a safety distance to determine whether the number of instructions of a node falls within the offset distance of the start interval standard value, thereby determining whether the node needs optimization. The offset distance is used to determine that if the number of instructions of a node falls within the offset distance near the start interval standard value, optimization is not required. The start interval standard value can be obtained by rounding up the ratio of the total number of instructions to the number of nodes in the directed data flow graph.

[0058] Specifically,

[0059] If the number of instructions for the first node is greater than or equal to the difference between the standard startup interval and the deviation distance, and less than or equal to the sum of the standard startup interval and the deviation distance, then no optimization is needed for the first node, which can be any node on the initial critical path. Otherwise, optimization is required for the first node.

[0060] S4. Identify and optimize the nodes that need to be optimized on the initial critical path.

[0061] In a specific implementation, if the number of instructions at the first node is less than the difference between the standard value of the startup interval and the deviation distance, then some instructions are moved from the second node to the first node, and the second node is a downstream node of the first node.

[0062] If the number of instructions at the first node is greater than the sum of the start interval standard value and the deviation distance, then some instructions are moved from the first node to the second node, which is a downstream node of the first node. Furthermore, if there is no downstream node for the first node on the initial critical path, then a downstream node is created for the first node as the second node, and some instructions are moved from the first node to the second node. Figure 4 The text shows the information about the Chinese language learning platform. Figure 1 The example shown is an optimized program mapping diagram. As can be seen from the diagram, compared to... Figure 2 The result shown is before optimization. This embodiment optimizes the nodes so that the execution time of each node is similar, shortens the program startup interval after instruction mapping, makes the program pipeline more compact, and ensures the balance between the nodes in the coarse-grained data flow graph.

[0063] In addition, to ensure that all nodes on the initial critical path have been optimized, it is necessary to check in real time whether there are any missing nodes that have not been optimized, and to perform the above-mentioned optimization process on the missing nodes.

[0064] Furthermore, after optimizing the nodes that need optimization on the initial critical path, changes in nodes may cause changes in the critical path. Additionally, during instruction transfer between nodes, extra transfer instructions may be introduced, resulting in changes in the total number of instructions. In this case, it is necessary to redetermine the critical path and start interval of the directed data flow graph, using the redetermined critical path as the final critical path. It is then determined whether the final critical path differs from the initial critical path. If they differ, all nodes on the final critical path are assessed for optimization needs. The nodes requiring optimization on the final critical path are then optimized, repeating steps S3 and S4.

[0065] Therefore, in this embodiment, by determining whether the number of instructions of a node falls within the offset distance of the standard value of the startup interval, it is determined whether the node needs to be optimized. For the node that needs to be optimized, the instructions of the node are balanced with those of the downstream node, which ensures the balance between the nodes in the coarse-grained data flow graph, so that the execution time occupied by each node is similar, shortening the startup interval of the program after instruction mapping, making the program pipeline more compact, improving the efficiency of program execution, and further improving the utilization rate of PE in CGRA, thereby realizing the optimization of the coarse-grained reconfigurable array CGRA data flow architecture.

[0066] The above embodiments of the present invention can be applied to terminal devices that implement the data flow architecture optimization method. These terminal devices may include client terminals and host computer terminals, etc., and the embodiments of the present invention do not limit their application. The terminal can support operating systems such as Windows, Android, iOS, and Windows Phone.

[0067] Reference Figure 5 , Figure 5 A data flow architecture optimization device 400 is shown, which is applied to data flow architecture optimization methods that can be used in client terminals and host computer terminal devices. It can achieve optimization through methods such as... Figure 3 The data flow architecture optimization method shown in this application embodiment can implement each process of the above-described data flow architecture optimization method.

[0068] A data flow architecture optimization device 400, employing the above-described data flow architecture optimization method, the device comprising at least:

[0069] DFG building block 401 is used to build a directed data flow graph characterizing a coarse-grained reconfigurable array architecture;

[0070] Critical path determination module 402 is used to determine the critical path in the directed data flow graph as the initial critical path;

[0071] The node optimization module 403 is used to determine whether all nodes on the initial critical path need optimization, and

[0072] Identify and optimize the nodes that need optimization on the initial critical path.

[0073] The data flow architecture optimization device 400 provided in this embodiment ensures the balance between nodes in the coarse-grained data flow graph, making the execution time of each node similar, shortening the program startup interval after instruction mapping, making the program pipeline more compact, improving the efficiency of program execution, further improving the utilization rate of PE in CGRA, and thus realizing the optimization of the coarse-grained reconfigurable array CGRA data flow architecture.

[0074] It should be understood that the descriptions of the data flow architecture optimization methods also apply to the data flow architecture optimization apparatus 400 according to the embodiments of this application, and will not be described in detail again to avoid repetition.

[0075] Furthermore, it should be understood that the data flow architecture optimization apparatus 400 according to the embodiments of this application is only illustrated by the division of the above-described functional modules. In actual applications, the above functions can be assigned to different functional modules as needed. That is, the data flow architecture optimization apparatus can be divided into functional modules that are different from the modules illustrated above, in order to complete all or part of the functions described above.

[0076] Figure 6 This is a schematic diagram of the structure of the electronic device provided in the embodiments of this application.

[0077] like Figure 6 As shown in the illustration, this application embodiment also provides an electronic device 500, including a processor 501, a memory 502, and a program or instructions stored in the memory 502 and executable on the processor 501. The processor is a coarse-grained reconfigurable array processor, which implements the above-described data flow architecture optimization method when executing the computer program, and can achieve the same technical effect.

[0078] Therefore, the electronic device 500 according to the embodiments of this application ensures the balance between the nodes in the coarse-grained data flow graph, making the execution time occupied by each node similar, shortening the program startup interval after instruction mapping, making the program pipeline more compact, improving the efficiency of program execution, further improving the utilization rate of PE in CGRA, and thus realizing the optimization of the coarse-grained reconfigurable array CGRA data flow architecture.

[0079] This application also provides a readable storage medium storing a program or instructions that, when executed by a processor, implement the steps of the above-described data flow architecture optimization method and achieve the same technical effect.

[0080] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, it should be noted that the scope of the methods and apparatuses in the embodiments of this application is not limited to performing functions in the order shown or discussed, but may also include performing functions substantially simultaneously or in the reverse order, depending on the functions involved. For example, the described methods may be performed in a different order than described, and various steps may be applied, omitted, or combined. Additionally, features described with reference to certain examples may be combined in other examples.

[0081] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a computer software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods described in the various embodiments of this application.

[0082] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit and scope of the claims, and all of these forms are within the protection scope of this application.

Claims

1. A data flow architecture optimization method, characterized in that, include: Construct a directed data flow graph that represents a coarse-grained reconfigurable array architecture, wherein the nodes of the directed data flow graph are code segments, each node contains multiple instructions, the lines between nodes represent data, and the direction of the lines represents the dependency relationship between the data and the instructions. Determine the critical path in the directed data flow graph as the initial critical path; Determine whether optimization is needed for all nodes on the initial critical path; Identify and optimize the nodes that need optimization on the initial critical path; The critical path of the directed data flow graph is redefined as the final critical path; If the final critical path is different from the initial critical path, determine whether all nodes on the final critical path need to be optimized. Identify and optimize the nodes that need optimization on the final critical path; Before determining whether optimization is needed for all nodes on the initial critical path, the process also includes: Calculate the standard value of the start interval of the directed data flow graph under the existing number of node partitions, wherein the standard value of the start interval is obtained by rounding up the ratio of the total number of instructions to the number of nodes in the directed data flow graph; A preset deviation distance is used to determine whether the number of instructions of a node falls within the deviation distance of the standard value of the startup interval and does not require optimization. The process of determining whether optimization is needed for all nodes on the initial critical path includes: If the number of instructions of the first node is greater than or equal to the difference between the standard value of the start interval and the deviation distance, and less than or equal to the sum of the standard value of the start interval and the deviation distance, no optimization is required for the first node. The first node is any node on the initial critical path. The process of identifying and optimizing nodes that need optimization on the initial critical path includes: If the number of instructions at the first node is less than the difference between the standard value of the startup interval and the deviation distance, then some instructions are moved from the second node to the first node, and the second node is the downstream node of the first node; If the number of instructions at the first node is greater than the sum of the standard startup interval and the deviation distance, then some instructions are moved from the first node to the second node, which is a downstream node of the first node.

2. The method according to claim 1, characterized in that, If there is no downstream node for the first node on the initial critical path, then a downstream node is created for the first node as the second node, and some instructions are moved from the first node to the second node.

3. A data flow architecture optimization device, characterized in that, The data flow architecture optimization method according to any one of claims 1-2, wherein the apparatus comprises at least: The DFG building block is used to construct directed data flow graphs that characterize coarse-grained reconfigurable array architectures. The critical path determination module is used to determine the critical path in the directed data flow graph as the initial critical path. The node optimization module is used to determine whether all nodes on the initial critical path need optimization, and Identify and optimize the nodes that need optimization on the initial critical path.

4. An electronic device, characterized in that, Includes a memory, a processor, and a computer program stored in the memory and executable on the processor; The processor employs a coarse-grained reconfigurable array processor, which, when executing the computer program, implements the data flow architecture optimization method according to any one of claims 1-2.

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