A method and system for verifying a multi-core system under a write-through strategy
By designing a verification method and system for multi-core systems under a write-through strategy, the shortcomings of L1 cache verification in multi-core systems are solved, and the accuracy and consistency verification of access/store instructions are realized, supporting the scalability of processors and clusters.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- GUANGDONG STARFIVE TECH LTD
- Filing Date
- 2022-06-13
- Publication Date
- 2026-07-21
Smart Images
Figure CN115202738B_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of computer technology, specifically a verification method and system for multi-core systems under a write-through strategy. Background Technology
[0002] High-performance processors typically have L1 and L2 caches. Depending on performance requirements, these caches can be configured with write-back and write-through policies. The main difference between these two policies lies in how write requests are handled. Under a write-back policy, a storage instruction accesses the L1 cache. If a hit occurs, the new data is directly written to the L1 cache. If a miss occurs, the cache line needs to be retrieved from the L2 cache or memory and then written to the L1 cache. Under a write-through policy, a storage instruction accesses the L1 cache. If a hit occurs, the data is written to both the L1 and L2 caches or memory. If a miss occurs, the data is written directly to the L2 cache or memory without needing to be written to the L1 cache. Comparatively, the write-through policy is simpler to design, but its performance is not as good as the write-back policy in certain scenarios.
[0003] Currently, no existing tools can adequately support the verification of memory access instructions when the L1 cache uses a write-through policy in a multi-core system. Verification and design are tightly coupled in multi-core systems.
[0004] To address the aforementioned issues, this verification system verifies whether the L1 cache in a multi-core system adopts a write-through strategy. Under the write-through strategy, it verifies whether the execution instructions of the multi-core system conform to the cache consistency protocol, whether the access instructions retrieve the correct data, and whether the storage instructions correctly write the data to the cache or memory. Summary of the Invention
[0005] The purpose of this invention is to provide a verification method and system for multi-core systems under a write-through strategy, so as to solve the problems mentioned in the background art.
[0006] To achieve the above objectives, the present invention provides the following technical solution: a verification method for a multi-core system under a write-through strategy, comprising access instructions and storage instructions, the specific steps of which are as follows:
[0007] When the first-level cache uses a write-through strategy, the execution flow of access commands in the verification system is as follows:
[0008] S1. The instruction generator sends instructions to the multi-core verification system. If the memory access instruction controller determines that the instruction type is an access instruction, it stores the instruction in the access instruction queue of the corresponding core.
[0009] S2. Monitor the update information of the access instruction in the DUT, including address, attribute, access size and other information. The memory access instruction controller will synchronize this information to the corresponding instruction in the access instruction queue.
[0010] S3. When the address attribute is determined to be a cacheable address, the perform time of the access instruction is the time when the access instruction outputs data from the memory access execution unit. The memory access execution unit monitors the output data of the memory access execution unit of each core. When the memory access execution unit outputs valid data, it means that an access instruction has performed. The memory access instruction controller searches for the corresponding unit in the access instruction queue according to the write register number. When the corresponding access instruction is found, the system verifies that the instruction is executed.
[0011] S4. For cacheable addresses, since access instructions are executed speculatively, data can be obtained from the memory instruction queue, memory buffer, and memory model. The memory access instruction controller needs to select data from the correct source, obtain the data, and save it for subsequent comparison.
[0012] S5. When the access command is detected in the DUT, compare the access data stored in the verification system with the access data obtained in the DUT, and print the comparison result.
[0013] When the first-level cache uses a write-through policy, the execution flow of storage instructions in the verification system is as follows:
[0014] S1. The instruction generator sends an instruction to the verification system. If the memory access instruction controller determines that the instruction type is a memory instruction, it stores the instruction in the memory instruction queue of the corresponding core.
[0015] S2. Monitor the update information of the storage instruction in the DUT, including address, attributes, write data and size, etc. The memory access instruction controller will synchronize this information to the corresponding instruction in the storage instruction queue.
[0016] S3. When the address attribute is determined to be a cacheable address, there are two performance points for the storage instruction: one is the time when the data is written to the L1 cache, and the other is the time when the data is written to the L2 cache. The cache monitor simultaneously monitors the L1 cache write interface and the L2 cache write interface of each core.
[0017] S4. When the cache monitor detects a valid L1 cache write request, the write request is output from the storebuffer module in the DUT. The access instruction controller searches the storage instruction queue based on the write address and the state of the store buffer. After finding a matching unit, it executes the storage instruction in that unit.
[0018] S5. When the cache monitor detects a valid L2 cache write request, the access instruction controller searches the storage instruction queue of the corresponding core based on the write address and core ID, finds the oldest storage instruction with a matching address, and executes the storage instruction.
[0019] S6. When the multi-core verification system executes storage instructions, it writes the write data of the corresponding unit in the storage instruction queue into the memory model, compares the write data with the DUT write data, and prints the comparison result.
[0020] This application also proposes a verification system for a multi-core system under a write-through strategy, including a multi-core verification system in write-through mode. The multi-core verification system in write-through mode includes a cache monitor, a memory access execution unit monitor, a memory access instruction controller, an access instruction queue, a storage instruction queue, a memory model, an access data comparator, and a storage data comparator. The operation flow of this verification system for a multi-core system under the write-through strategy is as follows:
[0021] S1. The instruction generator sends information data to the multi-core processor system to be verified and the multi-core verification system in write-through mode, respectively.
[0022] S2. The multi-core processor system to be verified sends instructions to the cache monitor and the memory access execution unit monitor respectively. The cache monitor and the memory access execution unit monitor synchronously transmit the information to the memory access instruction controller, and the memory access instruction controller and the memory access execution unit monitor synchronously transmit the information to the access data comparator and the memory data comparator.
[0023] S3. The information transmitted through the instruction generator enters the multi-core verification system in write-through mode and the data is synchronously transmitted to the access instruction queue and the storage instruction queue. At the same time, the multi-core verification system in write-through mode also synchronously transmits the information data to the access instruction queue, the storage instruction queue and the memory access instruction controller.
[0024] S4, the access instruction queue and the storage instruction queue, transmit information to the memory model, while the memory access instruction controller simply follows the operation steps of S2.
[0025] Preferably, the cache monitor monitors write request information for the first-level and second-level caches in the DUT and sends the monitored information to the memory access instruction controller.
[0026] Memory access execution unit monitor: Monitors the memory access execution unit in the DUT, including memory access instruction address data update information, instruction submission information, storebuffer update information, etc., and sends the monitored information to the memory access instruction controller;
[0027] Memory access instruction controller: Receives information from the cache monitor and memory access execution unit monitor, and controls when to update memory access instruction information in the verification system, when to execute operations to access and update the memory model, and when to compare data. In addition, for DUT flushing pipeline behavior, this controller needs to refresh the queue in the verification system.
[0028] Access instruction queue: Used to store access instruction information. The instruction generator simultaneously sends instructions to the DUT and the verification system. The memory access instruction controller stores the access instructions into the access instruction queue according to the instruction type.
[0029] When the access instruction address, attributes and other information in the DUT are updated, the corresponding instruction information in the queue is updated synchronously.
[0030] When an access instruction is submitted in the DUT, the corresponding instruction is deleted from the queue;
[0031] The memory instruction queue is used to store memory instruction information. The instruction generator simultaneously sends instructions to the DUT and the verification system. The memory access instruction controller stores the memory instructions into the access instruction queue according to the instruction type.
[0032] When the instruction address, attributes, data, and other information stored in the DUT are updated, the corresponding instruction information in the queue is updated synchronously.
[0033] When an access instruction is submitted in the DUT, the corresponding instruction is deleted from the queue and the instruction information is stored in the storage buffer.
[0034] Memory Model: Verify the memory model in the system. Each core has read and write permissions. The time point when a memory access instruction accesses and updates the memory model is the time point when the memory access instruction performs. Verify that the system only has a memory model and no cache model.
[0035] Access Data Comparator: When an access command is submitted, it compares the data obtained by the command in the verification system with the data obtained by the DUT, and prints the comparison result.
[0036] Storage data comparator: When the DUT stores a instruction to update the cache, it compares the write data of the instruction in the verification system with the write data in the DUT and prints the comparison result.
[0037] The beneficial effects of this invention are as follows:
[0038] 1. The verification system of the present invention can support the verification of access / store instructions when the next level cache of a multi-core system is configured with a write-through policy. The key to verification is to accurately grasp the performance time point of the access / store instructions. The performance time point of the access instructions is the moment when the memory access execution unit in the DUT sends out the obtained data. There are two performance time points for the storage instructions: one is the time point when the data is written to the first level cache, and the other is the time point when the data is written to the second level cache.
[0039] This verification system can compare the correctness of memory access instructions executed by each core in real time, including comparing the correctness of the data obtained when the access instruction is submitted, and comparing the correctness of the data written when the storage instruction updates the cache.
[0040] This verification system supports consistency verification for caches with a write-through policy in multi-core systems;
[0041] This verification system supports configurable numbers of processors and clusters, offering strong scalability. Attached Figure Description
[0042] Figure 1 This is a flowchart of the access / storage instruction execution process in the verification system of this invention;
[0043] Figure 2 This is a structural diagram of the multi-core verification system of the present invention;
[0044] Figure 3 This invention describes the write-through strategy and write-back strategy process. Detailed Implementation
[0045] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0046] like Figures 1 to 3 As shown in the embodiment of the present invention, a verification method for a multi-core system under a write-through strategy includes access instructions and storage instructions. The specific steps of the verification method for a multi-core system under a write-through strategy are as follows:
[0047] When the first-level cache uses a write-through strategy, the execution flow of access commands in the verification system is as follows: Figure 1 As shown on the left:
[0048] S1. The instruction generator sends instructions to the multi-core verification system. If the memory access instruction controller determines that the instruction type is an access instruction, it stores the instruction in the access instruction queue of the corresponding core.
[0049] S2. Monitor the update information of the access instruction in the DUT, including address, attribute, access size and other information. The memory access instruction controller will synchronize this information to the corresponding instruction in the access instruction queue.
[0050] S3. When the address attribute is determined to be a cacheable address, the perform time of the access instruction is the time when the access instruction outputs data from the memory access execution unit. The memory access execution unit monitors the output data of the memory access execution unit of each core. When the memory access execution unit outputs valid data, it means that an access instruction has performed. The memory access instruction controller searches for the corresponding unit in the access instruction queue according to the write register number. When the corresponding access instruction is found, the system verifies that the instruction is executed.
[0051] S4. For cacheable addresses, since access instructions are executed speculatively, data can be obtained from the memory instruction queue, memory buffer, and memory model. The memory access instruction controller needs to select data from the correct source, obtain the data, and save it for subsequent comparison.
[0052] S5. When the access command is detected in the DUT, compare the access data stored in the verification system with the access data obtained in the DUT, and print the comparison result.
[0053] When the first-level cache uses a write-through strategy, the execution flow of storage instructions in the verification system is as follows: Figure 1 As shown on the right:
[0054] S1. The instruction generator sends an instruction to the verification system. If the memory access instruction controller determines that the instruction type is a memory instruction, it stores the instruction in the memory instruction queue of the corresponding core.
[0055] S2. Monitor the update information of the storage instruction in the DUT, including address, attributes, write data and size, etc. The memory access instruction controller will synchronize this information to the corresponding instruction in the storage instruction queue.
[0056] S3. When the address attribute is determined to be cacheable, there are two performance points for the stored instruction: one is the time when data is written to the L1 cache, and the other is the time when data is written to the L2 cache. The cache monitor simultaneously monitors the L1 cache write interface and the L2 cache write interface of each core.
[0057] S4. When the cache monitor detects a valid L1 cache write request, the write request is output from the storebuffer module in the DUT. The access instruction controller searches the storage instruction queue based on the write address and the state of the store buffer. After finding a matching unit, it executes the storage instruction in that unit.
[0058] S5. When the cache monitor detects a valid L2 cache write request, the access instruction controller searches the storage instruction queue of the corresponding core based on the write address and core ID, finds the oldest storage instruction with a matching address, and executes the storage instruction.
[0059] S6. When the multi-core verification system executes storage instructions, it writes the write data of the corresponding unit in the storage instruction queue into the memory model, compares the write data with the DUT write data, and prints the comparison result.
[0060] This application also proposes a verification system for a multi-core system under a write-through strategy, including a multi-core verification system in write-through mode. The multi-core verification system in write-through mode includes a cache monitor, a memory access execution unit monitor, a memory access instruction controller, an access instruction queue, a storage instruction queue, a memory model, an access data comparator, and a storage data comparator. The operation flow of this verification system for a multi-core system under the write-through strategy is as follows:
[0061] S1. The instruction generator sends information data to the multi-core processor system to be verified and the multi-core verification system in write-through mode, respectively.
[0062] S2. The multi-core processor system to be verified sends instructions to the cache monitor and the memory access execution unit monitor respectively. The cache monitor and the memory access execution unit monitor synchronously transmit the information to the memory access instruction controller, and the memory access instruction controller and the memory access execution unit monitor synchronously transmit the information to the access data comparator and the memory data comparator.
[0063] S3. The information transmitted through the instruction generator enters the multi-core verification system in write-through mode and the data is synchronously transmitted to the access instruction queue and the storage instruction queue. At the same time, the multi-core verification system in write-through mode also synchronously transmits the information data to the access instruction queue, the storage instruction queue and the memory access instruction controller.
[0064] S4, the access instruction queue, and the memory instruction queue are responsible for transferring information to the memory model. The memory access instruction controller simply follows the operation steps of S2. The specific multi-core verification system structure is as follows: Figure 2 As shown.
[0065] Among them, the cache monitor monitors the write request information of the first-level cache and second-level cache in the DUT and sends the monitored information to the memory access instruction controller;
[0066] Memory access execution unit monitor: Monitors the memory access execution unit in the DUT, including memory access instruction address data update information, instruction submission information, storebuffer update information, etc., and sends the monitored information to the memory access instruction controller;
[0067] Memory access instruction controller: Receives information from the cache monitor and memory access execution unit monitor, and controls when to update memory access instruction information in the verification system, when to execute operations to access and update the memory model, and when to compare data. In addition, for DUT flushing pipeline behavior, this controller needs to refresh the queue in the verification system.
[0068] Access instruction queue: Used to store access instruction information. The instruction generator simultaneously sends instructions to the DUT and the verification system. The memory access instruction controller stores the access instructions into the access instruction queue according to the instruction type.
[0069] When the access instruction address, attributes and other information in the DUT are updated, the corresponding instruction information in the queue is updated synchronously.
[0070] When an access instruction is submitted in the DUT, the corresponding instruction is deleted from the queue;
[0071] The memory instruction queue is used to store memory instruction information. The instruction generator simultaneously sends instructions to the DUT and the verification system. The memory access instruction controller stores the memory instructions into the access instruction queue according to the instruction type.
[0072] When the instruction address, attributes, data, and other information stored in the DUT are updated, the corresponding instruction information in the queue is updated synchronously.
[0073] When an access instruction is submitted in the DUT, the corresponding instruction is deleted from the queue and the instruction information is stored in the storage buffer.
[0074] Memory Model: Verify the memory model in the system. Each core has read and write permissions. The time point when a memory access instruction accesses and updates the memory model is the time point when the memory access instruction performs. Verify that the system only has a memory model and no cache model.
[0075] Access Data Comparator: When an access command is submitted, it compares the data obtained by the command in the verification system with the data obtained by the DUT, and prints the comparison result.
[0076] Storage data comparator: When the DUT stores a instruction to update the cache, it compares the write data of the instruction in the verification system with the write data in the DUT and prints the comparison result.
[0077] In existing technologies, when the first-level cache uses a write-through strategy, the process of writing data to a storage instruction is as follows: Figure 3 As shown on the left, the system first checks if there is a cache miss. If a miss occurs, the data is written to the L1 cache and then to the L2 cache or memory. If a miss occurs, the data is written directly to the L2 cache or memory. When the L1 cache uses a write-back policy, the data writing process for storage instructions is as follows: Figure 3As shown on the right, the process first checks if there's a cache miss. If there is, the data is written to the L1 cache, and the write operation for this storage instruction ends. If there's a miss, the L1 cache needs to allocate an available location to store the new cache line. If no available location exists, an old cache line needs to be evicted, and then the cache line containing the write address is requested from the L2 cache or memory. The new cache line is merged with the write data and written to the L1 cache, ending the write operation for this storage instruction. It can be seen that the write-through strategy is relatively simple when there's a L1 cache miss, but if subsequent instructions frequently access the same cache line, the write-back strategy performs better.
[0078] In a multi-core verification system, the L1 cache employs a write-through strategy. Compared to a write-back strategy, the main difference lies in the perform time points of access / store instructions. For access instructions, the perform time point is the point at which data acquisition is certain; for store instructions, it's the point at which written data is visible to other cores. Under the write-through strategy, the perform time point for access instructions is the moment the memory access execution unit in the DUT sends out the acquired data. There are two perform time points for store instructions: one is the moment data is written to the L1 cache, and the other is the moment data is written to the L2 cache. The key to a multi-core verification system lies in monitoring these perform time points.
[0079] Therefore, in view of the above situation, this application proposes a verification method and system for multi-core systems under the write-through strategy.
[0080] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus.
[0081] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.
Claims
1. A verification method for a multi-core system under a write-through strategy, comprising access instructions and store instructions, characterized in that: The specific steps of the verification method for multi-core systems under the write-through strategy are as follows: When the first-level cache uses a write-through strategy, the execution flow of access commands in the verification system is as follows: S1. The instruction generator sends instructions to the multi-core verification system. If the memory access instruction controller determines that the instruction type is an access instruction, it stores the instruction in the access instruction queue of the corresponding core. S2. Monitor the update information of the access instruction in the DUT, including address, attribute, access size information, and the memory access instruction controller will synchronize this information to the corresponding instruction in the access instruction queue. S3. When the address attribute is determined to be a cacheable address, the perform time of the access instruction is the time when the access instruction outputs data from the memory access execution unit. The memory access execution unit monitors the output data of the memory access execution unit of each core. When the memory access execution unit outputs valid data, it means that an access instruction has performed. The memory access instruction controller searches for the corresponding unit in the access instruction queue according to the write register number. When the corresponding access instruction is found, the system verifies that the instruction is executed. S4. For cacheable addresses, since access instructions are executed speculatively, data can be obtained from the memory instruction queue, memory buffer, and memory model. The memory access instruction controller needs to select data from the correct source, obtain the data, and save it for subsequent comparison. S5. When the access command is detected in the DUT, compare the access data stored in the verification system with the access data obtained in the DUT, and print the comparison result. When the first-level cache uses a write-through policy, the execution flow of storage instructions in the verification system is as follows: S1. The instruction generator sends an instruction to the verification system. If the memory access instruction controller determines that the instruction type is a memory instruction, it stores the instruction in the memory instruction queue of the corresponding core. S2. Monitor the update information of the storage instruction in the DUT, including address, attributes, write data and size information. The memory access instruction controller will synchronize this information to the corresponding instruction in the storage instruction queue. S3. When the address attribute is determined to be a cacheable address, there are two performance points for the storage instruction: one is the time when the data is written to the L1 cache, and the other is the time when the data is written to the L2 cache. The cache monitor simultaneously monitors the L1 cache write interface and the L2 cache write interface of each core. S4. When the cache monitor detects a valid L1 cache write request, the write request is output from the store buffer module in the DUT. The access instruction controller searches the storage instruction queue based on the write address and the state of the store buffer. After finding a matching unit, it executes the storage instruction in that unit. S5. When the cache monitor detects a valid L2 cache write request, the access instruction controller searches the storage instruction queue of the corresponding core based on the write address and core ID, finds the oldest storage instruction with a matching address, and executes the storage instruction. S6. When the multi-core verification system executes storage instructions, it writes the write data of the corresponding unit in the storage instruction queue into the memory model, compares the write data with the DUT write data, and prints the comparison result.
2. A verification system for a multi-core system under a write-through strategy, used to implement the verification method as described in claim 1, comprising a multi-core verification system in write-through mode, the multi-core verification system in write-through mode comprising a cache monitor, a memory access execution unit monitor, a memory access instruction controller, an access instruction queue, a storage instruction queue, a memory model, an access data comparator, and a storage data comparator, characterized in that, The operation flow of the verification system for multi-core systems under the write-through strategy: S1. The instruction generator sends information data to the multi-core processor system to be verified and the multi-core verification system in write-through mode, respectively. S2. The multi-core processor system to be verified sends instructions to the cache monitor and the memory access execution unit monitor respectively. The cache monitor and the memory access execution unit monitor synchronously transmit the information to the memory access instruction controller, and the memory access instruction controller and the memory access execution unit monitor synchronously transmit the information to the access data comparator and the memory data comparator. S3. The information transmitted through the instruction generator enters the multi-core verification system in write-through mode. The data is synchronously transmitted to the access instruction queue and the storage instruction queue. At the same time, the multi-core verification system in write-through mode also synchronously transmits the information data to the access instruction queue, the storage instruction queue and the memory access instruction controller. S4, the access instruction queue and the storage instruction queue, transmit information to the memory model, while the memory access instruction controller simply follows the operation steps of S2.
3. The verification system for a multi-core system under a write-through strategy according to claim 2, characterized in that: Cache monitor: Monitors write request information of the first-level cache and second-level cache in the DUT, and sends the monitored information to the memory access instruction controller; Memory access execution unit monitor: Monitors the memory access execution unit in the DUT, including memory access instruction address data update information, instruction submission information, store buffer update information, and sends the monitored information to the memory access instruction controller; Memory access instruction controller: Receives information from the cache monitor and memory access execution unit monitor, and controls when to update memory access instruction information in the verification system, when to execute operations to access and update the memory model, and when to compare data. In addition, for DUT flushing pipeline behavior, this controller needs to refresh the queue in the verification system. Access instruction queue: Used to store access instruction information. The instruction generator sends instructions to both the DUT and the verification system. The memory access instruction controller stores the access instructions into the access instruction queue according to the instruction type. When the access instruction address and attribute information in the DUT are updated, the corresponding instruction information in the queue is updated synchronously. When an access instruction is submitted in the DUT, the corresponding instruction is deleted from the queue; The memory instruction queue is used to store memory instruction information. The instruction generator simultaneously sends instructions to the DUT and the verification system. The memory access instruction controller stores the memory instructions into the memory instruction queue according to the instruction type. When the instruction address, attribute, and data information stored in the DUT are updated, the corresponding instruction information in the queue is updated synchronously. When a storage instruction is submitted in the DUT, the corresponding instruction is deleted from the queue and the instruction information is stored in the storage buffer; Memory Model: Verify the memory model in the system. Each core has read and write permissions. The time point when a memory access instruction accesses and updates the memory model is the time point when the memory access instruction performs. Verify that the system only has a memory model and no cache model. Access Data Comparator: When an access command is submitted, it compares the data obtained by the command in the verification system with the data obtained by the DUT, and prints the comparison result. Storage data comparator: When the DUT stores a instruction to update the cache, it compares the write data of the instruction in the verification system with the write data in the DUT and prints the comparison result.