Server multi-architecture storage system and processor switching method thereof

Abstract

The application discloses a server multi-architecture storage system and a processor switching method thereof, wherein a user-selected processor architecture master-slave configuration is executed in a BMC management module, and a CPLD module of an NVME storage backboard is controlled through a GPIO port; the CPLD module of the backboard performs server master-slave architecture processor interconnection communication and virtualization switching through a PCIE Switch bridge NTB link, and updates a BIOS firmware engine configuration through SPI; the BMC management module configures a main architecture processor operating system through LPC and maps to a virtualized slave processor architecture, so that each processor can access NVME storage disk data of the NVME storage backboard, thereby solving the bottleneck problem that a current domestic server storage system processor architecture is diversified, user storage data migration is difficult, software application adaptation development has a long cycle and is difficult, and a domestic server software and hardware ecological circle comprehensive competitiveness cannot be brought into play. In addition, the application simplifies manual operation, and saves maintenance time and cost.

Description

Technical Field

[0001] This invention relates to the field of servers, and more particularly to server multi-architecture storage systems and their processor switching methods. Background Technology

[0002] With the advancement of national information security, information security issues are receiving increasing attention, making it particularly important to strengthen information security construction. Driven by national policy support and market demand, a large number of domestic processors have emerged, such as Phytium processors, Loongson processors, and Hygon processors. The diverse instruction set architectures of these processors have led to difficulties in migrating user-stored data, long and challenging software application adaptation development cycles, and bottlenecks that prevent the full realization of the comprehensive competitiveness of the domestic server hardware and software ecosystem.

[0003] Therefore, the difficulty in porting user stored data due to the diversification of instruction set architectures of domestic processors has become a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0004] This invention provides a server multi-architecture storage system and its processor switching method to solve the technical problem of difficulty in migrating user stored data caused by the diversification of existing processor instruction set architectures.

[0005] To solve the above-mentioned technical problems, the technical solution proposed by this invention is as follows:

[0006] A server multi-architecture storage system includes: a BIOS module, a BMC management module, an NVMe storage backplane, multiple NVMe data storage modules, multiple PCIe switch bridges, and multiple processors; each processor corresponds one-to-one with each NVMe data storage module, and each processor corresponds one-to-one with each PCIe switch bridge; the BIOS module is connected to the BMC management module and the multiple processors; the BMC management module is also connected to the NVMe storage backplane, and the NVMe storage backplane is also connected to each NVMe data storage module, each PCIe switch bridge, and each processor; each NVMe data storage module is also connected to its corresponding processor, and each PCIe switch bridge is also connected to its corresponding processor.

[0007] The BIOS module is used to configure the master and slave processor boot process; the NVME data storage module is used for server data storage and integrates with the data stored by each processor through the backplane; the PCIe switch bridge is used as a bridge for interconnecting and switching virtualization between the server's master and slave architecture processors; the NVME storage backplane includes a CPLD module for controlling the virtualization switching between the master and slave architecture processors of the PCIe switch bridge; the BMC management module allows users to select the server's master and slave processor configuration and controls the CPLD module in the NVME storage backplane to perform interconnection and virtualization switching between the server's master and slave architecture processors through the PCIe switch bridge, and configures the operating system of the master architecture processor by updating the BIOS firmware engine configuration and mapping it to the virtualized slave processor architecture.

[0008] Preferably, the BIOS module is connected to the BMC management module and multiple processors via an SPI bus; the BMC management module is also connected to the NVME storage backplane via an LPC bus, a GPIO bus, and a UART bus; the NVME storage backplane is connected to each processor via an LPC / UART bus, the NVME storage backplane is connected to each PCIE switch via a PICE 3.0 x8 NTB bus, the NVME storage backplane is connected to each NVME data storage module via a PCIE x4 link, each NVME data storage module is connected to its corresponding processor via a PCIE bus, and each PCIE switch is connected to its corresponding processor via a PCIE bus.

[0009] Preferably, when the switch is complete, the BMC management module is also used to prompt the user to switch the status.

[0010] Preferably, when the switching fails, the BMC management module is also used to call the switching log via UART, locate the switching fault based on the switching log, and restore the original processor architecture configuration.

[0011] Preferably, the plurality of processors includes: a Phytium processor using ARM architecture, a Loongson processor using LoongArch architecture, a Zhaoxin processor using x86 architecture, and a Loongson processor using MIPS architecture.

[0012] A processor switching method based on a server multi-architecture storage system includes the following steps:

[0013] Users can select the primary architecture processor and the secondary architecture processor in the BMC management interface of the BMC management module;

[0014] The BMC management module executes the user-selected processor architecture master-slave configuration and controls the CPLD module of the NVME storage backplane through GPIO ports;

[0015] The CPLD module of the NVME storage backplane communicates with the processors in the server master-slave architecture and performs virtualization switching through the NTB link of the PCIe switch bridge, and updates the BIOS firmware engine configuration through SPI.

[0016] The BMC management module configures the primary architecture processor operating system via LPC and maps it to the virtualized slave processor architecture.

[0017] Preferably, when the switch is complete, the BMC management module is also used to prompt the user to switch the status.

[0018] Preferably, when the switching fails, the BMC management module is also used to call the switching log via UART, locate the switching fault based on the switching log, and restore the original processor architecture configuration.

[0019] The present invention has the following beneficial effects:

[0020] 1. The server multi-architecture storage system and its processor switching method of this invention, by executing the user-selected processor architecture master-slave configuration in the BMC management module, and controlling the CPLD module of the NVME storage backplane through the GPIO port; the backplane CPLD module performs server master-slave architecture processor interconnection communication and virtualization switching through the PCIE switch bridge NTB link, and updates the BIOS firmware engine configuration through SPI; the BMC management module configures the master architecture processor operating system through LPC and maps it to the virtualized slave processor architecture, thereby solving the bottleneck problem of the current diversified processor architecture of domestic server storage systems, which leads to difficulties in user storage data migration, long and difficult software application adaptation development cycles, and inability to give full play to the comprehensive competitiveness of the domestic server software and hardware ecosystem. In addition, this invention simplifies manual operation and saves maintenance time and costs.

[0021] In addition to the objectives, features, and advantages described above, the present invention has other objectives, features, and advantages. The invention will now be described in further detail with reference to the accompanying drawings. Attached Figure Description

[0022] The accompanying drawings, which form part of this application, are used to provide a further understanding of the invention. The illustrative embodiments of the invention and their descriptions are used to explain the invention and do not constitute an undue limitation of the invention. In the drawings:

[0023] Figure 1 This is a schematic diagram of a server multi-architecture storage system provided in an embodiment of the present invention;

[0024] Figure 2 This is another structural diagram of a server multi-architecture storage system provided in an embodiment of the present invention;

[0025] Figure 3 This is a schematic diagram illustrating the workflow of a server multi-architecture storage system provided in an embodiment of the present invention. Detailed Implementation

[0026] The embodiments of the present invention will be described in detail below with reference to the accompanying drawings, but the present invention can be implemented in many different ways as defined and covered by the claims.

[0027] Example 1:

[0028] This embodiment discloses a server multi-architecture storage system, including: a BIOS module, a BMC management module, an NVMe storage backplane, multiple NVMe data storage modules, multiple PCIe switch bridges, and multiple processors; each of the multiple processors corresponds one-to-one with a single NVMe data storage module, and each of the multiple processors corresponds one-to-one with a single PCIe switch bridge; the BIOS module is connected to the BMC management module and the multiple processors respectively; the BMC management module is also connected to the NVMe storage backplane, and the NVMe storage backplane is also connected to each NVMe data storage module, each PCIe switch bridge, and each processor respectively; each NVMe data storage module is also connected to its corresponding processor, and each PCIe switch bridge is also connected to its corresponding processor;

[0029] The BIOS module is used to configure the master and slave processor boot process; the NVME data storage module is used for server data storage and integrates with the data stored by each processor through the backplane; the PCIe switch bridge is used as a bridge for interconnecting and switching virtualization between the server's master and slave architecture processors; the NVME storage backplane includes a CPLD module for controlling the virtualization switching between the master and slave architecture processors of the PCIe switch bridge; the BMC management module allows users to select the server's master and slave processor configuration and controls the CPLD module in the NVME storage backplane to perform interconnection and virtualization switching between the server's master and slave architecture processors through the PCIe switch bridge, and configures the operating system of the master architecture processor by updating the BIOS firmware engine configuration and mapping it to the virtualized slave processor architecture.

[0030] Furthermore, this embodiment also discloses a processor switching method based on a server multi-architecture storage system, including the following steps:

[0031] Users can select the primary architecture processor and the secondary architecture processor in the BMC management interface of the BMC management module;

[0032] The BMC management module executes the user-selected processor architecture master-slave configuration and controls the CPLD module of the NVME storage backplane through GPIO ports;

[0033] The CPLD module of the NVME storage backplane communicates with the processors in the server master-slave architecture and performs virtualization switching through the NTB link of the PCIe switch bridge, and updates the BIOS firmware engine configuration through SPI.

[0034] The BMC management module configures the primary architecture processor operating system via LPC and maps it to the virtualized slave processor architecture.

[0035] This invention addresses the bottleneck issues that currently exist in domestic server storage systems, such as the diversification of processor architectures leading to difficulties in migrating user stored data, long and complex software application adaptation development cycles, and the inability to fully leverage the comprehensive competitiveness of the domestic server hardware and software ecosystem. This invention simplifies manual operations and saves maintenance time and costs.

[0036] Example 2:

[0037] Example 2 is a preferred embodiment of Example 1. The differences between Example 2 and Example 1 are described in the specific structure of the server multi-architecture storage system:

[0038] like Figure 1-2As shown, this embodiment discloses a server multi-architecture storage system, including: a Phytium processor using ARM architecture, a Loongson processor using LoongArch architecture, a Zhaoxin processor using x86 architecture, and a Loongson processor using MIPS architecture; a BIOS module; an NVME data storage module; a PCIe switch bridge; an NVME storage backplane; and a BMC management module. The BIOS module is connected to the BMC management module and multiple processors via an SPI bus; the BMC management module is connected to the NVME storage backplane via an LPC bus, a GPIO bus, and a UART bus; the NVME storage backplane is connected to each processor via an LPC / UART bus; the NVME storage backplane is connected to each PCIe switch bridge via a PICE 3.0 x8 NTB bus; the NVME storage backplane is connected to each NVME data storage module via a PCIe x4 link; each NVME data storage channel corresponds to one set of PCIe x4 link channels; each NVME data storage module is connected to its corresponding processor via a PCIe bus; and each PCIe switch bridge is connected to its corresponding processor via a PCIe bus. The BIOS module is used to configure the master and slave processor boot process; Phytium processors, Loongson processors, and Hygon processors all support processor and I / O virtualization technology;

[0039] The NVME data storage module is used for server data storage and is integrated with the data stored by each processor through the backplane;

[0040] The PCIe Switch bridge chip has NTB and DMA functions and is used as a bridge for interconnecting server master and slave processor architectures and switching virtualization.

[0041] The NVME storage backplane includes a CPLD module for controlling the master / slave processor virtualization switching of the PCIe switch bridge chip;

[0042] The BMC management module has a server processor architecture switching control function. Users can select one of the processors as the master architecture processor and the other processors as slave architecture processors in the BMC management interface.

[0043] In this embodiment, the workflow of the server multi-architecture storage system is as follows: Figure 3 As shown:

[0044] Users can select the primary architecture processor and the secondary architecture processor in the BMC management interface of the BMC management module;

[0045] The BMC management module executes the user-selected processor architecture master-slave configuration and controls the CPLD module of the NVME storage backplane through GPIO ports;

[0046] The CPLD module of the NVME storage backplane communicates with the processors in the server master-slave architecture and performs virtualization switching through the NTB link of the PCIe switch bridge, and updates the BIOS firmware engine configuration through SPI.

[0047] The BMC management module configures the primary architecture processor operating system via LPC and maps it to the virtualized slave processor architecture.

[0048] When the switch is complete, the BMC management module is also used to prompt the user about the switch status.

[0049] When the switchover fails, the BMC management module is also used to call the switchover log via UART, locate the switchover fault based on the switchover log, and restore the original processor architecture configuration.

[0050] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A server multi-architecture storage system, characterized in that, include: BIOS module, BMC management module, NVMe storage backplane, multiple NVMe data storage modules, multiple PCIe switch bridges, and multiple processors; Each of the multiple processors corresponds one-to-one with a multiple NVMe data storage module, and each of the multiple processors corresponds one-to-one with a multiple PCIe switch bridge. The BIOS module is connected to the BMC management module and the multiple processors respectively. The BMC management module is also connected to the NVMe storage backplane, and the NVMe storage backplane is also connected to each NVMe data storage module, each PCIe switch bridge, and each processor respectively. Each NVMe data storage module is also connected to its corresponding processor, and each PCIe switch bridge is also connected to its corresponding processor. The BIOS module is used to configure the master and slave processor boot process; the NVME data storage module is used for server data storage and integrates with the data stored by each processor through the backplane; the PCIe switch bridge is used as a bridge for interconnecting and switching virtualization between the server's master and slave architecture processors; the NVME storage backplane includes a CPLD module for controlling the virtualization switching between the master and slave architecture processors of the PCIe switch bridge; the BMC management module allows users to select the server's master and slave processor configuration and controls the CPLD module in the NVME storage backplane to perform server master and slave architecture processor interconnection and virtualization switching through the PCIe switch bridge, and configures the operating system of the master architecture processor by updating the BIOS firmware engine configuration and mapping it to the virtualized slave processor architecture.

2. The server multi-architecture storage system according to claim 1, characterized in that, The BIOS module is connected to the BMC management module and multiple processors via the SPI bus. The BMC management module is also connected to the NVME storage backplane via the LPC bus, GPIO bus, and UART bus. The NVME storage backplane is connected to each processor via the LPC / UART bus, to each PCIe switch bridge via the PICE 3.0 x8 NTB bus, to each NVME data storage module via a PCIe x4 link, to each NVME data storage module and its corresponding processor via the PCIe bus, and to each PCIe switch bridge and its corresponding processor via the PCIe bus.

3. The server multi-architecture storage system according to claim 2, characterized in that, When the switch is complete, the BMC management module is also used to prompt the user about the switch status.

4. The server multi-architecture storage system according to claim 2, characterized in that, When the switchover fails, the BMC management module is also used to call the switchover log via UART, locate the switchover fault based on the switchover log, and restore the original processor architecture configuration.

5. The server multi-architecture storage system according to claim 2, characterized in that, The multiple processors include: Phytium processors using ARM architecture, Loongson processors using LoongArch architecture, Hygon processors using x86 architecture, and Loongson processors using MIPS architecture.

6. A processor switching method based on a server multi-architecture storage system, characterized in that, Applied to any one of the server multi-architecture storage systems as described in claims 1-5, the method includes the following steps: Users can select the primary architecture processor and the secondary architecture processor in the BMC management interface of the BMC management module; The BMC management module executes the user-selected processor architecture master-slave configuration and controls the CPLD module of the NVME storage backplane through GPIO ports; The CPLD module of the NVME storage backplane communicates with the processors in the server master-slave architecture and performs virtualization switching through the NTB link of the PCIe switch bridge, and updates the BIOS firmware engine configuration through SPI. The BMC management module configures the primary architecture processor operating system via LPC and maps it to the virtualized slave processor architecture.

7. The processor switching method based on a server multi-architecture storage system according to claim 6, characterized in that, When the switch is complete, the BMC management module is also used to prompt the user about the switch status.

8. The processor switching method based on a server multi-architecture storage system according to claim 6, characterized in that, When the switchover fails, the BMC management module is also used to call the switchover log via UART, locate the switchover fault based on the switchover log, and restore the original processor architecture configuration.

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