Chip operation state monitoring method and system and chip

Abstract

The application relates to a chip operation state monitoring method, a system and a chip. The method is applied to a chip, the chip comprising a central processor, peripherals and a debugging module; the central processor and the peripherals comprise a plurality of storage devices, and the debugging module is electrically connected with the central processor and the peripherals respectively. The method comprises the following steps: the debugging module receives a state monitoring request sent by a monitoring terminal, and determines a target storage device in the plurality of storage devices according to the state monitoring request; the debugging module acquires content information stored in the target storage device, and sends the content information to the monitoring terminal, so that the monitoring terminal shows the content information to a user; and the content information is used for reflecting the operation state of the chip. By adopting the method, the operation state of the chip can be accurately monitored, and the monitoring effect of the operation state of the chip is improved.

Description

Technical Field

[0001] This application relates to the field of chip technology, and in particular to a chip operation status monitoring method, system and chip. Background Technology

[0002] In automotive electronics, chips (typically Microcontroller Units (MCUs)) are often affected by interference from static electricity and electromagnetic radiation during their application due to the complex environment. Typically, a watchdog timer (WTD) system can be designed to monitor the MCU's operating status. If the MCU program is running normally, the MCU's central processing unit (CPU) outputs a reset signal to the WTD at preset intervals, causing the WTD to restart its count. If the MCU program malfunctions, the reset signal will not be output when the preset time is reached. In this case, the WTD overflows due to timeout and outputs a reset signal to the MCU, forcing the MCU program to reset.

[0003] However, the method of monitoring chip operation status through watchdog logic circuit reset system cannot inform users of the specific situation during chip operation, resulting in poor monitoring effectiveness. There is an urgent need for a chip operation status monitoring method that can improve monitoring effectiveness. Summary of the Invention

[0004] Therefore, it is necessary to provide a chip operation status monitoring method, system, and chip that can improve the chip operation status monitoring effect in response to the above-mentioned technical problems.

[0005] In a first aspect, this application provides a method for monitoring the operating status of a chip. The method is applied to a chip, the chip including a central processing unit (CPU), peripherals, and a debugging module; the CPU and the peripherals include several storage devices, and the debugging module is electrically connected to the CPU and the peripherals respectively; the method includes:

[0006] The debugging module receives a status monitoring request sent by the monitoring terminal and determines the target storage device among the plurality of storage devices according to the status monitoring request.

[0007] The debugging module acquires the content information stored in the target storage device and sends the content information to the monitoring terminal so that the monitoring terminal can display the content information to the user; the content information is used to reflect the operating status of the chip.

[0008] In one embodiment, the debugging module includes a debugging bus, an arbitration module, and a debugging interface; the arbitration module is electrically connected to the central processing unit, the peripheral device, and the debugging interface via the debugging bus.

[0009] The debugging module acquires the content information stored in the target storage device and sends the content information to the monitoring terminal, including:

[0010] The arbitration module obtains the content information stored in the target storage device through the debugging bus, and sends the content information to the monitoring terminal through the debugging interface.

[0011] In one embodiment, the arbitration module obtains the content information stored in the target storage device through the debug bus, including:

[0012] If the target storage device is a storage device included in the central processing unit, the arbitration module sends an information read instruction for the target storage device to the central processing unit through the debug bus; the central processing unit sends the content information stored in the target storage device to the arbitration module through the debug bus according to the information read instruction.

[0013] If the target storage device is a storage device included in the peripheral device, the arbitration module reads the content information from the target storage device through the debug bus.

[0014] In one embodiment, the debugging module further includes a cache module, which is electrically connected to the arbitration module;

[0015] The arbitration module obtains the content information stored in the target storage device through the debugging bus, and sends the content information to the monitoring terminal through the debugging interface, including:

[0016] The arbitration module reads content information from the target storage device via the debugging bus at a first transmission rate and stores the content information in the cache module;

[0017] The arbitration module sends the content information in the cache module to the monitoring terminal through the debugging interface at a second transmission rate; the second transmission rate is less than the first transmission rate.

[0018] In one embodiment, the method further includes:

[0019] Upon receiving a status monitoring stop command from the monitoring terminal, the debugging module stops acquiring the content information stored in the target storage device.

[0020] Secondly, this application also provides a chip. The chip includes a central processing unit (CPU), peripherals, and a debugging module; the CPU and peripherals include a plurality of storage devices; the debugging module is electrically connected to both the CPU and the peripherals; wherein:

[0021] The debugging module is used to receive status monitoring requests sent by the monitoring terminal, and to determine the target storage device among the plurality of storage devices according to the status monitoring requests.

[0022] The debugging module is also used to acquire the content information stored in the target storage device and send the content information to the monitoring terminal so that the monitoring terminal can display the content information to the user; the content information is used to reflect the operating status of the chip.

[0023] In one embodiment, the debugging module includes a debugging bus, an arbitration module, and a debugging interface; the arbitration module is electrically connected to the central processing unit, the peripheral device, and the debugging interface via the debugging bus; wherein:

[0024] The arbitration module is used to receive status monitoring requests sent by the monitoring terminal and determine the target storage device among the plurality of storage devices according to the status monitoring requests.

[0025] The arbitration module is also used to obtain the content information stored in the target storage device through the debugging bus, and send the content information to the monitoring terminal through the debugging interface.

[0026] In one embodiment, the arbitration module is specifically used to send an information read instruction for the target storage device to the central processing unit via the debug bus when the target storage device is a storage device included in the central processing unit; the central processing unit is used to send the content information stored in the target storage device to the arbitration module via the debug bus according to the information read instruction.

[0027] The arbitration module is specifically used to read content information from the target storage device via the debug bus when the target storage device is a storage device included in the peripheral device.

[0028] In one embodiment, the debugging module further includes a cache module, which is electrically connected to the arbitration module;

[0029] The arbitration module is specifically used to read content information from the target storage device at a first transmission rate via the debug bus and store the content information in the cache module; and to send the content information in the cache module to the monitoring terminal at a second transmission rate via the debug interface; the second transmission rate is less than the first transmission rate.

[0030] In one embodiment, the debugging module is further configured to stop acquiring the content information stored in the target storage device upon receiving a status monitoring stop command sent by the monitoring terminal.

[0031] Thirdly, this application also provides a chip operation status monitoring system. The chip operation status monitoring system includes a chip and a monitoring terminal. The chip includes a central processing unit (CPU), peripherals, and a debugging module. The CPU and peripherals include several storage devices. The debugging module is electrically connected to both the CPU and the peripherals.

[0032] The monitoring terminal is used to send status monitoring requests to the debugging module;

[0033] The debugging module is used to receive a status monitoring request sent by the monitoring terminal, determine a target storage device among the plurality of storage devices according to the status monitoring request, obtain the content information stored in the target storage device, and send the content information to the monitoring terminal.

[0034] The monitoring terminal is also used to receive the content information and display the content information to the user; the content information is used to reflect the operating status of the chip.

[0035] The aforementioned chip operation status monitoring method, system, and chip send a status monitoring request to a debugging module via a monitoring terminal. The debugging module can then determine the target storage device (such as registers or memory) among several storage devices included in the CPU and peripherals based on the status monitoring request. The debugging module can then obtain the content information stored in the target storage device and send this information to the monitoring terminal, allowing the monitoring terminal to display the content information to the user. This allows the user to understand the chip's operating status based on the content information of the target storage device. In this method, a debugging module is added to the chip (such as an MCU chip in automotive electronics) to receive status monitoring requests, obtain the content information stored in the target storage device, and return it to the monitoring terminal. Since the content information stored in the target storage device is relevant data generated during chip operation, the information obtained by the debugging module can reflect the chip's true operating status. Furthermore, different storage devices are involved when the chip runs different programs. The user can set different target storage devices (reflected in the status monitoring request) to understand the specific operating status of different programs within the chip based on the content information displayed by the monitoring terminal. If an abnormal operation of a certain program is detected, targeted processing can be performed to improve the chip's performance. Therefore, this method can accurately monitor the chip's operating status, help users analyze and solve chip anomalies, and improve the monitoring effect of chip operating status. Attached Figure Description

[0036] Figure 1 This is a schematic diagram of a chip operation status monitoring system in an example.

[0037] Figure 2 This is a flowchart illustrating a chip operation status monitoring method in one embodiment;

[0038] Figure 3 This is a schematic diagram of the chip structure in an example;

[0039] Figure 4 Here is a schematic diagram of the chip structure in another example;

[0040] Figure 5 This is a schematic diagram illustrating the process of the arbitration module sending content information to the monitoring terminal in one embodiment. Detailed Implementation

[0041] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0042] First, before introducing the technical solutions of the embodiments of this application, the technical background or evolution of the embodiments of this application will be introduced. During the application of automotive electronic chips (generally MCU chips (Microcontroller Units)), due to their complex application environment, the normal operation of the MCU program is often affected by interference from static electricity and electromagnetic radiation. Typically, the operating status of the MCU can be monitored by designing a watchdog logic circuit reset system (also known as a watchdog timer (WTD)). However, the method of monitoring the chip's operating status through a watchdog logic circuit reset system cannot allow users to know the specific situation during chip operation, thus making it impossible to find the cause of the abnormal operation and handle it specifically. Therefore, the monitoring effect of this method is poor. Based on this background, the applicant, through long-term research and development and experimental verification, proposes the chip operating status monitoring method of this application, which can improve the monitoring effect of chip operating status, help users analyze the specific causes of chip operating abnormalities, and thus solve the abnormal problems in a targeted manner. Furthermore, it should be noted that the applicant has devoted a great deal of creative effort to discovering the technical problems of this application and the technical solutions described in the following embodiments.

[0043] The chip operation status monitoring method provided in this application embodiment can be applied to, for example... Figure 1 The chip operation status monitoring system 100 shown is a chip operation status monitoring system 100. The chip operation status monitoring system 100 includes a monitoring terminal 102 and a chip 104, and the monitoring terminal 102 can communicate with the chip 104.

[0044] The chip 104 may include a central processing unit (CPU) 121, peripherals 122, and a debugging module 123. The chip 104 may be an MCU chip for automotive electronics or a chip for other fields. Peripherals 122 may include general-purpose peripherals such as timers, digital-to-analog converters (DAC modules), analog-to-digital converters (ADC modules), read-only memory (ROM), and random access memory (RAM), or other peripherals. The CPU and peripherals may include several storage devices. For example, the CPU may include storage devices such as a program counter, stack register, status register, and system register; peripherals may include memory and related registers, such as the general-purpose control register, sampling time register, injection channel data offset register, injection sequence register, and general-purpose status register of the ADC module. The debugging module 123 may be electrically connected to both the CPU 121 and peripherals 122.

[0045] The monitoring terminal 102 may be, but is not limited to, various personal computers, laptops, smartphones, tablets, IoT devices, and portable wearable devices.

[0046] In one embodiment, such as Figure 2 As shown, a chip operating status monitoring method is provided, which can be applied to... Figure 1 Taking chip 104 as an example, the method includes the following steps:

[0047] Step 201: The debugging module receives the status monitoring request sent by the monitoring terminal and determines the target storage device among several storage devices according to the status monitoring request.

[0048] In implementation, the user can send a status monitoring request to the debugging module 123 of the chip 104 through the monitoring terminal 102. For example, if the ADC value collected by the chip 104 fluctuates abnormally when used in a low-temperature environment, the operating status of the chip can be monitored using this method. Specifically, the chip can run its relevant programs in an application environment where abnormal phenomena occur (such as collecting ADC values ​​in a low-temperature environment). At the same time, the user can send a status monitoring request to the debugging module 123 of the chip 104 through the monitoring terminal to obtain relevant data generated by the chip when running in an abnormal application environment. The status monitoring request may include the identification information of the storage devices involved when the chip runs its relevant programs. The debugging module 123 can receive the status monitoring request sent by the monitoring terminal 102 and, based on the identification information of the storage devices contained in the status monitoring request, determine the target storage device corresponding to the identification information from among the several storage devices included in the CPU 121 and peripheral 122. That is, the user can specify the target storage device by configuring the status monitoring request. There can be multiple target storage devices, which can be set by the user according to the situation.

[0049] Step 202: The debugging module obtains the content information stored in the target storage device and sends the content information to the monitoring terminal so that the monitoring terminal can display the content information to the user.

[0050] In implementation, after receiving a status monitoring request and identifying the target storage device, the debugging module 123 can obtain the content information stored in the target storage device. For example, the debugging module 123 can directly read the content information stored in the target storage device. The target storage device stores relevant data (i.e., content information) generated during the chip's operation, which can be used to reflect the chip's operating status. For example, when acquiring ADC values, each register of the ADC module will store corresponding data, so each register (or some key registers) of the ADC module can be set as the target storage device. The debugging module 123 can then directly read the content information stored in the target storage device (such as all or some registers) of the ADC module during the chip's operation and send this content information to the monitoring terminal 102. After receiving this content information, the monitoring terminal 102 can display it to the user so that the user can understand the specific operating status of the chip based on this content information.

[0051] In the above-described chip operation status monitoring method, the user can send a status monitoring request to the debugging module 123 through the monitoring terminal 102 to specify a target storage device. The debugging module 123 can determine the target storage device (such as registers, memory, etc.) among several storage devices included in the CPU and peripherals based on the storage device identification information contained in the status monitoring request. Then, the debugging module 123 can obtain the content information stored in the target storage device and send it to the monitoring terminal 102, so that the monitoring terminal 102 can display the content information of the target storage device to the user. Thus, the user can understand the chip's operating status based on the content information of the target storage device. In this method, by adding a debugging module to the chip (such as an MCU chip in automotive electronics), the debugging module receives the status monitoring request, obtains the content information stored in the target storage device, and returns it to the monitoring terminal. Since the content information stored in the target storage device is relevant data generated during chip operation, the content information obtained by the debugging module can reflect the chip's true operating status. Furthermore, different programs run on the chip involve different storage devices. Users can set different target storage devices as needed (reflected in the status monitoring request) to understand the specific running status of different programs on the chip based on the information displayed on the monitoring terminal. If an abnormality is detected in a certain program, targeted measures can be taken to improve chip performance. Therefore, this method can accurately monitor the chip's operating status, help users analyze and resolve chip anomalies, and improve the effectiveness of chip operating status monitoring.

[0052] In one embodiment, such as Figure 3The schematic diagram of chip 104 shown indicates that the debugging module 123 may include a debugging bus 301, an arbitration module 302, and a debugging interface 303. The arbitration module 302 is electrically connected to the central processing unit 121, peripheral device 122, and debugging interface 303 via the debugging bus 301. Step 102, in which the debugging module acquires content information and sends it to the monitoring terminal, specifically includes: the arbitration module acquiring the content information stored in the target storage device via the debugging bus and sending the content information to the monitoring terminal via the debugging interface.

[0053] In implementation, the debug module 123 may include a debug bus 301, an arbitration module 302, and a debug interface 303. The arbitration module 302 can be electrically connected to the central processing unit 121, peripherals 122, and debug interface 303 via the debug bus 301. The CPU 121 and peripherals 122 can be electrically connected via the system bus 124. That is, the data transmission channel between the CPU and peripherals and the data transmission channel between the debug module and the CPU and peripherals are different channels.

[0054] Specifically, chip 104 can communicate with monitoring terminal 102 through debug interface 303. The communication protocol can use standard protocols such as IIC (Inter-Integrated Circuit), SPI (Serial Peripheral Interface), and UART (Universal Asynchronous Receiver / Transmitter). In one example, debug interface 303 can serve as the interface for chip 104 to communicate with peripherals during application, achieving interface reuse and eliminating the need for a separate interface specifically for monitoring status, thus efficiently utilizing resources.

[0055] The monitoring terminal 102 can transmit a status monitoring request via the debug interface 303 to the arbitration module 302 in the chip 104 via the debug bus 301. Upon receiving the status monitoring request, the arbitration module 302 can identify the target storage device. Then, the arbitration module 302 can obtain the content information stored in the target storage device (a storage device included in the CPU or peripherals) via the debug bus 301 and send this content information to the monitoring terminal 102 via the debug interface 303. In one example, the arbitration module 302 can be implemented using a selector, register, clock module, logic judgment circuit, etc.

[0056] In this embodiment, the arbitration module is electrically connected to the CPU, peripherals, and debugging interface via the debugging bus. This separates the data transmission channel during chip operation from the data transmission channel during chip status monitoring (including status monitoring requests, target storage device content information, etc.). As a result, monitoring the chip's operating status can be done without affecting the chip's operation, and the monitored data (target storage device content information) can better reflect the true situation of the chip's operation, thus improving the effectiveness of monitoring.

[0057] In one embodiment, the process by which the arbitration module obtains the content information stored in the target storage device specifically includes the following steps: if the target storage device is a storage device included in the central processing unit, the arbitration module sends an information read instruction for the target storage device to the central processing unit through the debug bus; the central processing unit sends the content information stored in the target storage device to the arbitration module through the debug bus according to the information read instruction; if the target storage device is a storage device included in a peripheral device, the arbitration module reads the content information from the target storage device through the debug bus.

[0058] In implementation, after the arbitration module 302 identifies the target storage device based on the status monitoring request, it can further determine the type of the target storage device and retrieve content information accordingly. Specifically, the arbitration module 302 can distinguish the type of the target storage device based on its identification information. If the arbitration module 302 determines that the target storage device is a storage device contained within the CPU 121 (such as a critical register inside the CPU), the arbitration module 302 can send an information read instruction for the target storage device to the CPU 121 via the debug bus 301. After receiving the information read instruction, the CPU 121 can parse the identification information of the target storage device contained in the information read instruction, read the content information stored in the target storage device, and send it to the arbitration module 302 via the debug bus 301.

[0059] If the arbitration module 302 determines that the target storage device is a storage device included in the peripheral 122, the arbitration module 302 can directly read the content information from the target storage device through the debugging bus 301.

[0060] Understandably, if there are multiple target storage devices, including both internal CPU storage devices and peripheral storage devices, the arbitration module can obtain the stored content information for each target storage device using a corresponding method.

[0061] In this embodiment, the arbitration module can obtain the content information stored in the target storage device in a corresponding manner according to the type of the target storage device (belonging to the CPU or to a peripheral device), so as to ensure that the relevant data (i.e., content information) stored in each storage device involved in the chip operation can be obtained, so that users can understand the chip's operating status based on the relevant data and improve the monitoring effect.

[0062] In one embodiment, such as Figure 4 The schematic diagram of chip 104 shown indicates that the debugging module 123 also includes a cache module 304. The cache module 304 is electrically connected to the arbitration module 302. Correspondingly, as... Figure 5 As shown, the arbitration module obtains the content information stored in the target storage device through the debug bus and sends the content information to the monitoring terminal through the debug interface. The specific steps include the following:

[0063] Step 501: The arbitration module reads the content information from the target storage device via the debugging bus at the first transmission rate and stores the content information in the cache module.

[0064] In implementation, after the arbitration module 302 reads content information from the target storage device via the debug bus 301, it can store the read content information in the cache module 304. The data transfer rate at which the arbitration module 302 reads the content information stored in the target storage device via the debug bus 301 is called the first transfer rate, which is generally relatively high.

[0065] Step 502: The arbitration module sends the content information in the cache module to the monitoring terminal through the debugging interface at the second transmission rate.

[0066] The second transmission rate is less than the first transmission rate.

[0067] In implementation, after the arbitration module 302 stores the content information in the cache module 304, it can send the content information in the cache module 304 to the monitoring terminal 102 via the debugging interface 303 at a second transmission rate. Specifically, the arbitration module 302 can read the content information from the cache module 304 and send it to the monitoring terminal 102 via the debugging interface 303. The arbitration module 302 can also control the cache module 304 to send its stored content information to the monitoring terminal 102 via the debugging interface 303; in this case, the cache module 304 should be electrically connected to the debugging interface 303. The data transmission rate at which the content information in the cache module 304 is transmitted from the debugging interface 303 to the monitoring terminal 102 is called the second transmission rate. The second transmission rate is specifically related to the performance parameters of the debugging interface and is generally less than the first transmission rate.

[0068] In this embodiment, by setting up a caching module, the content information of the target storage device read at high speed (first transmission rate) by the arbitration module is first stored in the caching module. Then, the content information in the caching module is sent to the monitoring terminal at a lower speed (second transmission rate, the rate matched with the debugging interface). High-speed reading and caching of content information ensures the integrity of the acquired information, while low-speed transmission to the monitoring terminal ensures performance matching with the debugging interface, allowing the monitored content information to be successfully sent to the monitoring terminal. This enables the display of content information reflecting the chip's true operating status to the user, helping the user analyze and resolve chip anomalies and improving monitoring effectiveness.

[0069] In one embodiment, the method further includes the following step: when the debugging module receives a status monitoring stop command sent by the monitoring terminal, it stops acquiring the content information stored in the target storage device.

[0070] In implementation, the user can also send a status monitoring stop command to the debugging module 123 via the monitoring terminal 102. If the debugging module 123 receives the status monitoring stop command from the monitoring terminal 102, it can stop acquiring the content information stored in the target storage device. Optionally, after receiving the monitoring stop command, the debugging module can switch to silent mode, i.e., shut down, to save resources. If the user sends a status monitoring request to the debugging module 123 again via the monitoring terminal 102, the debugging module 123 can switch to interactive mode, parse the status monitoring request to determine the target storage device, and then switch back to monitoring mode to continuously read and send the content information of the target storage device until it receives the status monitoring stop command.

[0071] In this embodiment, if the debugging module receives a status monitoring stop command, it stops acquiring and sending the content information of the target storage device, and the monitoring task is completed. Thus, the starting and stopping of the debugging module can be controlled according to actual needs, which is convenient to use and can make efficient use of resources.

[0072] It should be understood that although the steps in the flowcharts of the embodiments described above are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the embodiments described above may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0073] Based on the same inventive concept, this application also provides a chip for implementing the chip operation status monitoring method described above. The solution provided by this chip is similar to the implementation scheme described in the above method; therefore, the specific limitations in one or more chip embodiments provided below can be found in the limitations of the chip operation status monitoring method described above, and will not be repeated here.

[0074] In one embodiment, a chip is provided, which can be seen in [reference]. Figure 1 The schematic diagram of chip 104 shows that the chip includes a central processing unit (CPU), peripherals, and a debugging module. The CPU and peripherals include several storage devices, and the debugging module is electrically connected to both the CPU and peripherals.

[0075] The debugging module is used to receive status monitoring requests sent by the monitoring terminal and determine the target storage device from several storage devices based on the status monitoring requests.

[0076] The debugging module is also used to acquire the content information stored in the target storage device and send the content information to the monitoring terminal so that the monitoring terminal can display the content information to the user; the content information is used to reflect the operating status of the chip.

[0077] In one embodiment, see [reference] Figure 3 The schematic diagram of chip 104 shown illustrates that the debugging module includes a debugging bus, an arbitration module, and a debugging interface. The arbitration module is electrically connected to the central processing unit, peripherals, and the debugging interface via the debugging bus. Wherein:

[0078] The arbitration module is used to receive status monitoring requests sent by the monitoring terminal and determine the target storage device from several storage devices based on the status monitoring requests.

[0079] The arbitration module is also used to obtain the content information stored in the target storage device through the debug bus, and send the content information to the monitoring terminal through the debug interface.

[0080] In one embodiment, the arbitration module is specifically used to send an information read instruction for the target storage device to the central processing unit via a debug bus when the target storage device is a storage device included in the central processing unit; the central processing unit is used to send the content information stored in the target storage device to the arbitration module via the debug bus according to the information read instruction.

[0081] The arbitration module is specifically used to read content information from the target storage device via the debug bus when the target storage device is a storage device included in a peripheral device.

[0082] In one embodiment, one can participate Figure 4The schematic diagram of chip 104 shown shows that the debugging module also includes a cache module, which is electrically connected to the arbitration module.

[0083] The arbitration module is specifically used to read content information from the target storage device at a first transmission rate via the debugging bus and store the content information in the cache module; and to send the content information in the cache module to the monitoring terminal at a second transmission rate via the debugging interface; the second transmission rate is less than the first transmission rate.

[0084] In one embodiment, the debugging module is also used to stop acquiring the content information stored in the target storage device upon receiving a status monitoring stop command sent by the monitoring terminal.

[0085] Based on the same inventive concept, this application also provides a chip operating status monitoring system for implementing the chip operating status monitoring method described above. The solution provided by this system is similar to the implementation scheme described in the above method; therefore, the specific limitations in one or more chip operating status monitoring system embodiments provided below can be found in the limitations of the chip operating status monitoring method described above, and will not be repeated here.

[0086] In one embodiment, a chip operating status monitoring system is provided, which can participate in... Figure 1 The diagram shows the structure of a chip operation status monitoring system. The system includes a chip and a monitoring terminal. The chip includes a central processing unit (CPU), peripherals, and a debugging module. The CPU and peripherals contain several storage devices. The debugging module is electrically connected to both the CPU and the peripherals. Wherein:

[0087] The monitoring terminal is used to send status monitoring requests to the debugging module.

[0088] The debugging module is used to receive status monitoring requests sent by the monitoring terminal, determine the target storage device among several storage devices according to the status monitoring request, obtain the content information stored in the target storage device, and send the content information to the monitoring terminal.

[0089] The monitoring terminal is also used to receive content information and display it to the user; the content information reflects the chip's operating status.

[0090] In one embodiment, the debugging module includes a debugging bus, an arbitration module, and a debugging interface. The arbitration module is electrically connected to the central processing unit, peripherals, and the debugging interface via the debugging bus.

[0091] The arbitration module is used to receive status monitoring requests sent by the monitoring terminal and determine the target storage device from several storage devices based on the status monitoring requests.

[0092] The arbitration module is also used to obtain the content information stored in the target storage device through the debug bus, and send the content information to the monitoring terminal through the debug interface.

[0093] In one embodiment, the arbitration module is specifically used to send an information read instruction for the target storage device to the central processing unit (CPU) via a debug bus when the target storage device is a storage device included within the CPU. The CPU then sends the content information stored in the target storage device to the arbitration module via the debug bus according to the information read instruction.

[0094] The arbitration module is specifically used to read content information from the target storage device via the debug bus when the target storage device is a storage device included in a peripheral device.

[0095] In one embodiment, the debugging module further includes a cache module, which is electrically connected to the arbitration module. Specifically, the arbitration module is used to read content information from the target storage device via the debugging bus at a first transmission rate and store the content information in the cache module; and to send the content information in the cache module to the monitoring terminal via the debugging interface at a second transmission rate; the second transmission rate is less than the first transmission rate.

[0096] In one embodiment, the debugging module is also used to stop acquiring the content information stored in the target storage device upon receiving a status monitoring stop command sent by the monitoring terminal.

[0097] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, data stored, data displayed, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties.

[0098] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0099] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A method for monitoring the operating status of a chip, characterized in that, The method is applied to a chip, which includes a central processing unit, peripherals, and a debugging module; the central processing unit and the peripherals include several storage devices; the debugging module includes a debugging bus, an arbitration module, and a debugging interface. The arbitration module is electrically connected to the central processing unit, the peripheral device, and the debugging interface via the debugging bus. The central processing unit and the peripheral device are electrically connected via a system bus; the data transmission channels between the central processing unit and the peripheral device, and the data transmission channels between the debugging module and the central processing unit and the peripheral device are different channels; The target storage device included in the central processing unit includes at least one of a program counter, a stack register, a status register, and a system register; The method includes: The debugging module receives a status monitoring request sent by the monitoring terminal and determines the target storage device among the plurality of storage devices according to the status monitoring request. The arbitration module obtains the content information stored in the target storage device through the debug bus, and sends the content information to the monitoring terminal through the debug interface, so that the monitoring terminal can display the content information to the user; the content information is used to reflect the operating status of the chip. The arbitration module obtains the content information stored in the target storage device through the debug bus, including: If the target storage device is a storage device included in the central processing unit, the arbitration module sends an information read instruction for the target storage device to the central processing unit through the debug bus; the central processing unit sends the content information stored in the target storage device to the arbitration module through the debug bus according to the information read instruction. If the target storage device is a storage device included in the peripheral device, the arbitration module reads the content information from the target storage device through the debug bus.

2. The method according to claim 1, characterized in that, The debugging module also includes a cache module, which is electrically connected to the arbitration module. The arbitration module obtains the content information stored in the target storage device through the debugging bus, and sends the content information to the monitoring terminal through the debugging interface, including: The arbitration module reads content information from the target storage device via the debugging bus at a first transmission rate and stores the content information in the cache module; The arbitration module sends the content information in the cache module to the monitoring terminal through the debugging interface at a second transmission rate; the second transmission rate is less than the first transmission rate.

3. The method according to claim 1, characterized in that, The method further includes: Upon receiving a status monitoring stop command from the monitoring terminal, the debugging module stops acquiring the content information stored in the target storage device.

4. A chip, characterized in that, The chip includes a central processing unit, peripherals, and a debugging module; the central processing unit and the peripherals include several storage devices; the debugging module includes a debugging bus, an arbitration module, and a debugging interface. The arbitration module is electrically connected to the central processing unit, the peripheral device, and the debugging interface via the debugging bus. The central processing unit and the peripheral device are electrically connected via a system bus; the data transmission channels between the central processing unit and the peripheral device, and the data transmission channels between the debugging module and the central processing unit and the peripheral device are different channels; The target storage device included in the central processing unit includes at least one of a program counter, a stack register, a status register, and a system register; wherein: The debugging module is used to receive status monitoring requests sent by the monitoring terminal, and to determine the target storage device among the plurality of storage devices according to the status monitoring requests. The arbitration module obtains the content information stored in the target storage device through the debug bus, and sends the content information to the monitoring terminal through the debug interface, so that the monitoring terminal can display the content information to the user; the content information is used to reflect the operating status of the chip. Specifically, the arbitration module is used to send an information read instruction for the target storage device to the central processing unit via the debug bus when the target storage device is a storage device included in the central processing unit; the central processing unit is used to send the content information stored in the target storage device to the arbitration module via the debug bus according to the information read instruction. The arbitration module is specifically used to read content information from the target storage device via the debug bus when the target storage device is a storage device included in the peripheral device.

5. The chip according to claim 4, characterized in that, The debugging module also includes a cache module, which is electrically connected to the arbitration module. The arbitration module is specifically used to read content information from the target storage device via the debug bus at a first transmission rate, and store the content information in the cache module; The content information in the cache module is sent to the monitoring terminal through the debugging interface at a second transmission rate; the second transmission rate is less than the first transmission rate.

6. The chip according to claim 4, characterized in that, Upon receiving a status monitoring stop command from the monitoring terminal, the debugging module stops acquiring the content information stored in the target storage device.

7. A chip operating status monitoring system, characterized in that, The chip operation status monitoring system includes a chip and a monitoring terminal. The chip includes a central processing unit, peripherals, and a debugging module. The central processing unit and the peripherals include several storage devices. The debugging module includes a debugging bus, an arbitration module, and a debugging interface. The arbitration module is electrically connected to the central processing unit, the peripheral device, and the debugging interface via the debugging bus. The central processing unit and the peripheral device are electrically connected via a system bus; the data transmission channels between the central processing unit and the peripheral device, and the data transmission channels between the debugging module and the central processing unit and the peripheral device are different channels; The target storage device included in the central processing unit includes at least one of a program counter, a stack register, a status register, and a system register; in: The monitoring terminal is used to send status monitoring requests to the debugging module; The debugging module is used to receive a status monitoring request sent by the monitoring terminal, and determine the target storage device among the plurality of storage devices according to the status monitoring request. The arbitration module obtains the content information stored in the target storage device through the debugging bus, and sends the content information to the monitoring terminal through the debugging interface; The monitoring terminal is also used to receive the content information and display the content information to the user; the content information is used to reflect the operating status of the chip. The arbitration module obtains the content information stored in the target storage device through the debug bus, including: If the target storage device is a storage device included in the central processing unit, the arbitration module sends an information read instruction for the target storage device to the central processing unit through the debug bus; the central processing unit sends the content information stored in the target storage device to the arbitration module through the debug bus according to the information read instruction. If the target storage device is a storage device included in the peripheral device, the arbitration module reads the content information from the target storage device through the debug bus.

8. The system according to claim 7, characterized in that, The debugging module also includes a cache module, which is electrically connected to the arbitration module. The arbitration module is specifically used to read content information from the target storage device via the debug bus at a first transmission rate, and store the content information in the cache module; The content information in the cache module is sent to the monitoring terminal through the debugging interface at a second transmission rate; the second transmission rate is less than the first transmission rate.

9. The system according to claim 7, characterized in that, Upon receiving a status monitoring stop command from the monitoring terminal, the debugging module stops acquiring the content information stored in the target storage device.

10. The system according to claim 7, characterized in that, The peripheral device includes storage devices comprising at least one of the following: a general-purpose control register, a sampling time register, an injection channel data offset register, an injection sequence register, and a general-purpose status register of the ADC module.

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