Ultra-small region support for storage devices

Abstract

Aspects of a memory device including a memory and a controller are provided. The memory includes a first partition having a plurality of dies as channels allocated to one or more zones. The controller can receive a write command and data from a host device, where the write command indicates that the data is to be written to a first zone. The controller can perform a write operation that writes the received data to one or more of the plurality of dies allocated to the first zone. When the memory device and the host device are in an idle state, the controller can transfer the data from the first zone to a second partition of the memory associated with the first zone. Accordingly, the controller can reduce an oversupply of small zone memory block allocations, thereby improving memory capacity and utilization of the memory device.

Description

Technical Field

[0001] This disclosure generally relates to electronic devices, and more specifically, to storage devices. Background Technology

[0002] Storage devices enable users to store and retrieve data. Examples of storage devices include non-volatile memory devices. Non-volatile memory typically retains data after a power cycle. An example of non-volatile memory is flash memory, which may contain an array of NAND cells on one or more dies. Flash memory can be found in solid-state drives (SSDs), secure digital cards (SD cards), and so on.

[0003] Flash memory devices can store control information associated with data. For example, a flash memory device can maintain a control table, which contains a mapping from logical addresses to physical addresses. This control table is used to track the physical location of logical sectors or blocks within the flash memory. The control table is stored in non-volatile memory so that the stored data can be accessed after a power cycle.

[0004] Partitioned Namespaces (ZNS) are a namespace architecture for SSDs where non-volatile memory is divided into fixed-size logical address groups, or fixed-size regions. Each region is used for a specific application. For example, a host can write data associated with different applications in different regions. Regions are distributed across a single die, with each region typically being 48MB or 64MB in size. The flash memory device interfaces with the host to obtain the defined regions and maps the regions to blocks in the flash memory. Therefore, the host can write individual application-specific data to separate blocks in the flash memory.

[0005] Traditionally, for example, when the host overwrites data, data in a flash memory device may become invalid in small blocks (e.g., 4KB of data). To remove invalid data from the flash memory, the flash memory device performs a garbage collection (GC) process, in which valid data is copied to new blocks and invalid data is erased from old blocks. However, in ZNS, regions are written sequentially before the data in a region becomes invalid, and therefore, an entire region may become invalid immediately (e.g., 48 or 64MB of data). This feature of ZNS reduces or eliminates GC, which in turn reduces write amplification. Therefore, ZNS optimizes the durability of flash memory devices and improves the consistency of input / output (I / O) command latency.

[0006] There may be specific ZNS architecture requirements to support ultra-small region sizes (e.g., 2MB, 4MB, 8MB, or similar sizes) for specific applications. As block sizes in NAND cell arrays increase, supporting ultra-small region sizes becomes increasingly challenging without wasting significant flash memory capacity or compromising storage device performance. Summary of the Invention

[0007] This document discloses one aspect of a storage device. The storage device includes a memory and a controller. The memory includes a first partition having a plurality of dies as channels allocated to one or more regions. The controller is configured to perform a write operation that writes received data to one or more of the dies allocated to the first region. The controller is also configured to transfer data from the first region to a second partition in the memory associated with the first region when the storage device is idle.

[0008] This document discloses another aspect of a storage device. The storage device includes a memory and a controller. The memory includes a first partition having a plurality of dies as channels allocated to one or more regions. The controller is configured to receive write commands and data from a host device, the write commands instructing data to be written to a first region among the one or more regions. The controller is also configured to perform write operations that write data to one or more of the dies allocated to the first region. The controller is further configured to transfer data from the first region to a second partition in the memory associated with the first region when the storage device is idle.

[0009] This document discloses another aspect of a storage device. The storage device includes a memory and a controller. The memory includes a first partition having a plurality of dies as channels allocated to one or more regions, each of the plurality of dies comprising a plurality of blocks. The controller is configured to allocate each of the plurality of blocks of each of the plurality of dies as a lowest-level erase unit to one or more regions. The controller is also configured to receive write commands and data from a host device, the write commands instructing data to be written to a first region within the one or more regions. The controller is further configured to perform a write operation that writes data to one or more of the dies allocated to the first region. The controller is also configured to transfer data from the first region to a second partition in the memory associated with the first region when the storage device is idle.

[0010] It should be understood that other aspects of the storage device will become apparent to those skilled in the art from the following detailed description, in which various aspects of the apparatus and method are shown and described as illustrative. It will be appreciated that these aspects may be implemented in other and different forms, and that certain details may be modified in various other aspects. Therefore, the drawings and detailed description should be considered illustrative rather than limiting in nature. Attached Figure Description

[0011] Various aspects of the present invention will now be presented in detail with reference to the accompanying drawings, by way of example but not as limitation, in which:

[0012] Figure 1 A block diagram illustrating an exemplary embodiment of a storage device communicating with a host device.

[0013] Figure 2 To show Figure 1 A conceptual diagram of an instance of a logical-to-physical mapping table in the non-volatile memory of a storage device.

[0014] Figure 3 To show Figure 1 A conceptual diagram of an example of a memory cell array in a storage device.

[0015] Figure 4 To show Figure 1 A conceptual diagram of an instance of a block array in a storage device.

[0016] Figure 5 To show Figure 1 An example of a voltage distribution chart for a three-layer cell in a storage device.

[0017] Figure 6 To demonstrate that it can be implemented Figure 1 A conceptual diagram of an instance of the garbage collection (GC) process in a storage device.

[0018] Figure 7 To show the area and by Figure 1 A conceptual diagram of instances of the association between groups of logical addresses received by a storage device.

[0019] Figure 8 To illustrate writing data to blocks mapped to different regions Figure 1 A conceptual diagram of an instance of a controller for a storage device.

[0020] Figure 9 An example diagram of a storage device is shown, having a first partition containing a die plane block and a second partition associated with a different region.

[0021] Figure 10 This diagram illustrates an example of memory transfer between a first partition with multiple bare blocks and a second partition associated with a specific region after a write operation.

[0022] Figure 11 An example diagram of a memory read operation at the first partition having multiple die blocks is shown.

[0023] Figure 12An example diagram of a storage device is shown, the storage device having a first partition containing a block of die planes and a second partition associated with different areas for read operations.

[0024] Figure 13 This is an example flowchart illustrating the process of storing data in memory blocks allocated to small regions.

[0025] Figure 14 A conceptual diagram illustrating an example of a controller for a memory coupled to a storage device. Detailed Implementation

[0026] The detailed description set forth below with reference to the accompanying drawings is intended to describe various exemplary embodiments of the invention and is not intended to imply that only certain embodiments may be practiced. The detailed description includes specific details for the purpose of providing a thorough understanding of the invention. However, it will be apparent to those skilled in the art that the invention may be practiced without these specific details. In some instances, well-known structures and components are illustrated in block diagram form to avoid obscuring the concept of the invention. Acronyms and other descriptive terms may be used only for convenience and clarity and are not intended to limit the scope of the invention.

[0027] The terms “exemplary” and “example” are used herein to mean serving as an example, illustration, or description. Any exemplary embodiment described herein as “exemplary” should not be construed as preferred or advantageous over other exemplary embodiments. Similarly, the term “exemplary embodiment” for apparatus, method, or article of manufacture does not require that all exemplary embodiments of the invention encompass the described components, structures, features, functionality, processes, advantages, benefits, or modes of operation.

[0028] As used herein, the term "coupled" is used to indicate a direct connection between two components, or, where appropriate, an indirect connection to each other via an intermediary or intermediate component. In contrast, when a component is referred to as being "directly coupled" to another component, there is no intermediary element.

[0029] In the following detailed description, various aspects of a storage device communicating with a host device will be presented. These aspects are more applicable to flash memory devices, such as SSDs and SD cards. However, those skilled in the art will recognize that these aspects are extendable to all types of storage devices capable of storing data. Therefore, any references to particular devices or methods are intended only to illustrate various aspects of the invention, and it should be understood that such aspects can have a wide range of applications without departing from the spirit and scope of this disclosure.

[0030] Typically, in a ZNS, the host provides the definition of regions or logical address groups to the flash memory device. For example, the host may indicate that a group of LBAs corresponding to 48 or 64 MB of data is associated with a first region, another group of LBAs corresponding to another 48 or 64 MB of data is associated with a second region, and so on. The flash memory device then maps each region to a single block in the flash memory. For example, the flash memory device may map the LBAs associated with the first region to a first physical block, the LBAs associated with the second region to a second physical block, and so on. This one-to-one mapping of each region to a block allows for reduction or elimination of GC by effectively making regions independent. For example, after data has been sequentially written to a block mapped to a region, the host can invalidate that region by instructing the flash memory device to erase only that block without affecting data in other regions / blocks.

[0031] However, as flash memory devices move towards next-generation architectures, there is a trend towards increasing physical block sizes (e.g., the number of word lines and strings). For example, BICs4 flash memory devices currently have 96 word lines per block, BICs5 flash memory devices can have 112 word lines per block, and BICs6 flash memory devices are expected to have even more word lines per block. However, while flash memory devices can support progressively larger physical block sizes, the host may not be able to support different region sizes (i.e., region sizes are fixed in ZNS). This could result in unused storage space in each block and thus wasted storage capacity. For example, even if the capacity of each block increases from 64MB to 128MB in future generations, the host may still only be able to write up to 64MB of data to the regions mapped to each block, leaving the remaining 64MB of each block unused.

[0032] Furthermore, there may be specific ZNS architecture requirements for supporting significantly smaller region sizes (e.g., 2MB, 4MB, 8MB, or similar sizes) to support particular applications. As block sizes in NAND cell arrays increase, supporting ultra-small region sizes becomes increasingly challenging without wasting significant amounts of flash memory capacity or compromising storage device performance.

[0033] Next-generation flash memory devices contain multiple dies, and each die can contain multiple blocks. Flash memory devices can combine multiple blocks to form large blocks, known as gigabytes. For example, a BICs6 flash memory device can contain gigabytes of up to 400MB. By allocating larger blocks, flash memory devices can achieve maximum parallelism, thereby maximizing performance in write and read operations. However, utilizing gigabyte allocation is becoming increasingly challenging because physical block sizes continue to increase as flash memory devices move towards next-generation architectures.

[0034] Typically, in a ZNS (Zero-Number Serving), a block (or blocks) is allocated to a specific region, and sequential writes can be performed within that region. As discussed above, this eliminates the need for the flash memory device to perform any garbage collection, thus achieving maximum performance. Application-specific requirements may exist, where region sizes may need to be varied. For example, the host device may allocate different region sizes to different applications. In a particular application, a region size allocation of 400MB might be appropriate, for example. However, in regions with significantly smaller sizes (e.g., 4MB), the region provisioning method used by the host device may be substantially inefficient.

[0035] Another approach in ZNS might not allocate blocks across all dies, but instead limit region allocation to a single physical block (or a die plane block), which reduces the block size in terms of a die plane block or die plane. However, read / write performance can be reduced by the same amount, as this approach may not scale efficiently to other regions.

[0036] The aforementioned method contains drawbacks that arise when large blocks are allocated to smaller regions. For example, a gigablock allocated as a complete block of 400MB can be over-provisioned because sequential data may not require the capacity allocated within that block, as the block can be partially or completely rewritten. In this respect, provisioning large blocks for small regions can be inefficient.

[0037] To mitigate the aforementioned limitations or effects of ZNS (e.g., inefficient oversupply of regions due to increased block size), this disclosure implements the provisioning of a first partition in the flash memory, the first partition having multiple dies as channels allocated to ultra-small regions to perform storage operations in parallel across all dies, wherein each block (or sub-block) in the die is allocated to the first partition as the lowest-level erase unit. Data written to the first partition is synchronized with a second partition in memory dedicated to a specific region, such that when the host device and storage device are idle, region-specific data written in the first partition is then transferred to the second partition for said region, while maintaining region attributes and reducing oversupply.

[0038] In some aspects, the memory controller may allocate the lowest-level erase units (e.g., physical blocks or sub-blocks) to regions within a first partition of the flash memory. In some aspects, the controller may use sub-blocks for regions and mapping. In response to receiving a region definition (e.g., a region-to-logical address mapping) or another message indicating that a ZNS will be used from the host, the controller may map regions to sub-blocks. Each block mapped to a region is divided into multiple sub-blocks. Such mapping prevents unused space in each block from appearing due to increased block size, thereby eliminating the storage capacity waste that may occur in conventional ZNS implementations. Sub-blocks may be configured to be independently programmable, readable, and erasable; for example, a different voltage may be applied to word lines in selected sub-blocks than to word lines in unselected sub-blocks, so that data can only be read, programmed, or erased in selected sub-blocks.

[0039] In some aspects, the memory controller can use a single-level cell (SLC) block (e.g., an SLC giant block) for multiple regions. For example, the SLC giant block can be accessed across all dies (or channels) to be shared by all the smaller regions allocated to the block. In some aspects, data for multiple regions can be written to the same SLC giant block. In some aspects, data can be tracked by sequentially writing to multiple regions. In some aspects, the first partition in the flash memory can be represented as an optional reference to the SLC giant block, and there is no compression within the SLC block. For example, even after the block becomes full, there may be no data movement within the SLC block. In some aspects, a synchronous write pointer between the first and second partitions can be used to track write operations in the SLC block using the second partition.

[0040] In this regard, the memory controller can perform write operations on SLC blocks in parallel across all dies for a specified region, with only one-dimensional (1D) writes in the first partition. In some aspects, the memory controller can perform read operations from the first partition involving the SLC blocks using an optional reference to the SLC blocks to achieve faster reads. In some aspects, the second partition contains three-level cell (TLC) blocks. In this regard, data movement between SLC blocks and TLC blocks can be performed via horizontal read operations across all dies in the megablock and single-die writes in the background (e.g., when the host device and storage device are idle).

[0041] Figure 1 An exemplary block diagram 100 shows a storage device 102 communicating with a host device 104 (also a "host") according to an exemplary embodiment. The host device 104 and the storage device 102 may form a system, such as a computer system (e.g., a server, desktop computer, mobile phone / laptop computer, tablet computer, smartphone, etc.). Figure 1The components may or may not be physically co-located. In this regard, the host device 104 may be located remotely from the storage device 102. Although Figure 1 The host device 104 is shown as separate from the storage device 102, but in other embodiments, the host device 104 may be wholly or partially integrated into the storage device 102. Alternatively, the host device 104 may be distributed across multiple remote entities, or alternatively, it may have some of the functionality of the storage device 102.

[0042] Those skilled in the art will understand that other exemplary embodiments may include more Figure 1 The elements shown may be more or less than those shown, and the disclosed processes may be implemented in other environments. For example, other exemplary embodiments may include different numbers of hosts communicating with storage device 102, or multiple storage devices 102 communicating with hosts.

[0043] Host device 104 can store data to and / or retrieve data from storage device 102. Host device 104 may include any computing device, such as a computer server, network attached storage (NAS) unit, desktop computer, notebook computer, tablet computer, mobile computing device such as a smartphone, television, camera, display device, digital media player, video game console, video streaming device, etc. Host device 104 may include at least one processor 101 and host memory 103. At least one processor 101 may include any form of hardware capable of processing data, and may include general-purpose processing units (e.g., central processing unit (CPU)), special-purpose hardware (e.g., application-specific integrated circuit (ASIC)), digital signal processors (DSP), configurable hardware (e.g., field-programmable gate array (FPGA)), or any other form of processing unit configured by means of software instructions, firmware, etc. Host memory 103 may be used by host device 104 to store data or instructions processed by the host, or data received from storage device 102. In some instances, host memory 103 may include non-volatile memory, such as magnetic storage devices, optical storage devices, holographic storage devices, flash memory devices (e.g., NAND or NOR), phase-change memory (PCM) devices, resistive random access memory (ReRAM) devices, magnetoresistive random access memory (MRAM) devices, ferroelectric random access memory (F-RAM) devices, and any other type of non-volatile memory device. In other instances, host memory 103 may include volatile memory, such as random access memory (RAM), dynamic random access memory (DRAM), static RAM (SRAM), and synchronous dynamic RAM (SDRAM) (e.g., DDR1, DDR2, DDR3, DDR3L, LPDDR3, DDR4, etc.). Host memory 103 may also include both non-volatile and volatile memory, whether integrated together or as discrete units.

[0044] Host interface 106 is configured to interface storage device 102 with host device 104 via bus / network 108, and can use, for example, Ethernet or WiFi or bus standards (e.g., Serial Advanced Technology Attachment (SATA), PCIe, Small Computer System Interface (SCSI), or Serial Attached SCSI (SAS)) and other possible candidates for interface. Alternatively, host interface 106 may be wireless, and can use, for example, cellular communications (e.g., 5G NR, 4G LTE, 3G, 2G, GSM / UMTS, CDMA One / CDMA2000, etc.), wireless distribution methods via access points (e.g., IEEE 802.11, WiFi, HiperLAN, etc.), infrared (IR), Bluetooth, Wi-Fi, or other wireless wide area network (WWAN), wireless local area network (WLAN), wireless personal area network (WPAN) technologies or similar wide area, local area, and personal area technologies to interface storage device 102 with host device 104.

[0045] Storage device 102 includes a memory. For example, in Figure 1 In an exemplary embodiment, storage device 102 may include non-volatile memory (NVM) 110 for persistently storing data received from host device 104. NVM 110 may include, for example, flash memory, NAND memory (e.g., SLC memory, multi-level cell (MLC) memory, TLC memory, quad-level cell (QLC) memory, five-level cell (PLC) memory, or any combination thereof), or NOR memory. NVM 110 may include multiple memory locations 112 for storing system data used to operate storage device 102 or user data stored in storage device 102 from the receiving host. For example, the NVM may have a cross-point architecture comprising a 2-D NAND array of memory locations 112, the 2-D NAND array having n rows and m columns, where m and n are predefined according to the size of the NVM. Figure 1 In an exemplary embodiment, each memory location 112 may be a die 114 comprising multiple planes, each plane comprising multiple blocks of multiple cells 116. Alternatively, each memory location 112 may be a plane comprising multiple blocks of cells 116. For example, cells 116 may be single-level cells, multi-level cells, three-level cells, four-level cells, and / or five-level cells. Other instances of memory location 112 are possible; for example, each memory location may be a block or a group of blocks. Each memory location may contain one or more blocks in a 3-D NAND array. Each memory location 112 may contain one or more logical blocks mapped to one or more physical blocks. Alternatively, the memory and each memory location may be implemented in other ways known to those skilled in the art.

[0046] Storage device 102 also includes volatile memory 118, which may include, for example, dynamic random access memory (DRAM) or static random access memory (SRAM). Data stored in volatile memory 118 may include data read from NVM 110 or data to be written to NVM 110. In this regard, volatile memory 118 may include write buffers or read buffers for temporary data storage. Although Figure 1 The volatile memory 118 is shown as a controller 123 located remotely from the storage device 102, but the volatile memory 118 may be integrated into the controller 123.

[0047] The memory (e.g., NVM 110) is configured to store data 119 received from the host device 104. Data 119 may be stored in cell 116 of any of the memory locations 112. As an example, Figure 1 The data 119 is shown to be stored in different memory locations 112, but data can also be stored in the same memory location. In another example, memory locations 112 can be different dies, and data can be stored in one or more of the different dies.

[0048] Each of the data 119 can be associated with a logical address. For example, the NVM 110 may store a logical-to-physical (L2P) mapping table 120 of the storage device 102 that associates each of the data 119 with a logical address. The L2P mapping table 120 stores a mapping between the logical address specified for data written from the host device 104 and the physical address in the NVM 110 that indicates the location of each of the stored data. This mapping can be performed by the controller 123 of the storage device. The L2P mapping table can be a table or other data structure that contains identifiers, such as the logical block address (LBA) associated with each memory location 112 in the NVM where data is stored. Although Figure 1 A single L2P mapping table 120 is shown in one of the memory locations 112 of the NVM to avoid excessive confusion. Figure 1 The concept is the same, but the L2P mapping table 120 can actually contain multiple tables stored in one or more memory locations of the NVM.

[0049] Figure 2 Conceptual diagram 200 for an instance of L2P mapping table 205, which shows data 202 received from the host device and Figure 1 The mapping between logical and physical addresses in the NVM 110. Data 202 can correspond to... Figure 1 Data 119 in the table, and L2P mapping table 205 can correspond to Figure 1The L2P mapping table 120 is used in the NVM 110. In one exemplary embodiment, data 202 may be stored in one or more pages 204 (e.g., pages 1 to x), where x is the total number of pages of data written to the NVM 110. Each page 204 may be associated with one or more entries 206 in the L2P mapping table 205, which identify a logical block address (LBA) 208, a physical address 210 associated with the data written to the NVM, and a length 212 of the data. The LBA 208 may be a logical address specified in a write command for data received from a host device. The physical address 210 may indicate the block and offset to which the data associated with the LBA 208 is physically written. The length 212 may indicate the size of the data written (e.g., 4KB or some other size).

[0050] Return to reference Figure 1 The volatile memory 118 also stores a cache 122 for the storage device 102. The cache 122 contains entries showing a mapping between the logical address specified for data requested by the host device 104 and the physical address in the NVM 110 indicating the location where the data is stored. This mapping can be executed by the controller 123. When the controller 123 receives a read command or write command for data 119, the controller checks the logical-to-physical mapping for each piece of data in the cache 122. If no mapping exists (e.g., for the first request for data), the controller accesses the L2P mapping table 120 and stores the mapping in the cache 122. When the controller 123 executes the read command or write command, the controller accesses the mapping from the cache and reads data from the NVM 110 or writes data to the specified physical address in the NVM 110. The cache may be stored in the form of a table or other data structure containing a logical address associated with each memory location 112 in the NVM where data is being read.

[0051] NVM 110 includes a sense amplifier 124 and a data latch 126 connected to each memory location 112. For example, memory location 112 may be a block containing cells 116 on multiple bit lines, and NVM 110 may contain a sense amplifier 124 on each bit line. Additionally, one or more data latches 126 may be connected to the bit lines and / or the sense amplifiers. The data latches may be, for example, shift registers. When data is read from a cell 116 of memory location 112, the sense amplifier 124 senses the data by amplifying the voltage on the bit lines to a logic level (e.g., readable as '0' or '1'), and the sensed data is stored in the data latch 126. The data is then transferred from the data latch 126 to the controller 123, and subsequently stored in volatile memory 118 until it is transferred to the host device 104. When data is written to cell 116 at memory location 112, controller 123 stores the programmed data in data latch 126, and the data is subsequently transferred from data latch 126 to cell 116.

[0052] The storage device 102 includes a controller 123, which includes circuitry for one or more processors, for example, for executing instructions, and the storage device may include a microcontroller, a digital signal processor (DSP), an ASIC, a field-programmable gate array (FPGA), hardwired logic, analog circuitry, and / or combinations thereof.

[0053] Controller 123 is configured to receive data transmitted from one or more cells 116 in various memory locations 112 in response to a read command. For example, controller 123 can read data 119 by activating sense amplifier 124 to sense data from cell 116 into data latch 126, and controller 123 can receive data from data latch 126. Controller 123 is also configured to program data into one or more cells 116 in response to a write command. For example, controller 123 can write data 119 by sending data to data latch 126 to be programmed into cell 116. Controller 123 is further configured to access L2P mapping table 120 in NVM 110 when reading data or writing data to cell 116. For example, controller 123 may receive a logical-to-physical address mapping from NVM 110 in response to a read or write command from host device 104, identify the physical address mapped to the logical address identified in the command (e.g., translate the logical address to a physical address), and access or store data in unit 116 located at the mapped physical address.

[0054] The controller 123 and its components may be implemented using embedded software that performs the various functions of the controller described herein. Alternatively, the software for implementing each of the foregoing functions and components may be stored in memory external to the NVM 110, storage device 102, or host device 104, and may be accessed by the controller 123 for execution by one or more processors of the controller 123. Alternatively, the functions and components of the controller may be implemented using hardware within the controller 123, or a combination of the foregoing hardware and software may be used.

[0055] In operation, host device 104 stores data in storage device 102 by sending a write command to storage device 102, the write command specifying one or more logical addresses (e.g., LBAs) and the length of the data to be written. Interface element 106 receives the write command, and the controller allocates memory location 112 in the NVM 110 of storage device 102 for storing the data. Controller 123 stores an L2P mapping in the NVM (and cache 122) to map the logical address associated with the data to the physical address of the memory location 112 allocated to the data. The controller also stores the length of the L2P-mapped data. Controller 123 then stores the data in memory location 112 by sending the data to one or more data latches 126 connected to the allocated memory location, the data being programmed from the allocated memory location into cell 116.

[0056] Host device 104 can retrieve data from storage device 102 by sending a read command specifying one or more logical addresses associated with the data to be retrieved from storage device 102, and the length of the data to be read. Interface 106 receives the read command, and controller 123 accesses the L2P mapping in cache 122 or another NVM to translate the logical address specified in the read command into a physical address indicating the location of the data. Controller 123 then reads the requested data from the memory location 112 specified by the physical address by sensing the data using sense amplifier 124 and storing it in data latch 126, until the read data is returned to host device 104 via host interface 106.

[0057] Figure 3 An example of a NAND memory array 300 with cell 302 is shown. Cell 302 may correspond to Figure 1Cell 116 in the NVM 110. Multiple cells 302 are coupled to word lines 304 and bit lines 306. For example, the memory array 300 may contain n word lines and m bit lines within a block of die 114 of the NVM 110, where n and m are predefined according to the block size. Each word line and bit line may be associated with a row and column address, respectively, which the controller 123 may use to select specific word lines and bit lines (e.g., using column and row decoders). For example, word lines 0-n may each be associated with their own row address (e.g., word line 0 may correspond to word line address 0, word line 1 may correspond to word line address 1, etc.), and bit lines 0-m may each be associated with their own column address (e.g., bit line 0 may correspond to bit line address 0, bit line 1 may correspond to bit line address 1, etc.). Select gate source (SGS) cell 308 and select gate drain (SGD) cell 310 are coupled to memory cells 302 on each bit line 306. SGS unit 308 and SGD unit 310 connect memory unit 302 to source line 312 (e.g., ground) and bit line 306, respectively. String 314 may contain a group of units 302 coupled to a bit line within the block (including SGS unit 308 and SGD unit 310), while page 316 may contain a group of units 302 coupled to a word line within the block.

[0058] Figure 4 An example of a NAND memory array 400 comprising a block 402 containing multiple strings 404 is shown. Block 402 may correspond to... Figure 1 The blocks of bare die 114 in NVM 110, and the strings 404 can each correspond to blocks of bare die 114. Figure 3 The string 314. For example, in Figure 3 In the memory array 300, each string 404 may contain a group of memory cells each coupled to a bit line 406 and individually coupled to a corresponding word line 408. Similarly, each string may contain an SGS cell 410 and an SGD cell 412, which respectively connect the memory cells in each string 404 to the source line 414 and the bit line 406.

[0059] When controller 123 reads data from or writes data to page 316 of cell 302 (i.e., on word lines 304, 408), controller 123 may send a command to apply a read voltage or programming voltage to the selected word line and a pass voltage to the other word lines. The read or programming state of the cell (e.g., logic '0' or logic '1' for SLC) can then be determined based on a threshold voltage of cell 302. For example, during an SLC read operation, if the threshold voltage of cell 302 is less than the read voltage (i.e., current flows through the cell in response to the read voltage), then controller 123 may determine that the cell stores logic '1', and if the threshold voltage of cell 302 is greater than the read voltage (i.e., current does not flow through the cell in response to the read voltage), then controller 123 may determine that the cell stores logic '0'. Similarly, during an SLC programming operation, the controller can store logic '0' by sending a command to apply a programming voltage to cell 302 on word lines 304, 408 until the cell reaches a threshold voltage, and during an erase operation, the controller can send a command to apply an erase voltage to block 402 containing cell 302 (e.g., to the substrate of a cell, such as a p-well) until the cell shrinks back below the threshold voltage (returning to logic '1').

[0060] For cells storing multiple bits (e.g., MLC, TLC, etc.), each word line 304, 408 may contain multiple pages 316 of cell 302, and the controller may similarly send commands to apply read or program voltages to the word lines to determine the read or program state of the cell based on the cell's threshold voltage. For example, in the case of a TLC, each word line 304, 408 may contain three pages 316, which contain the next page (LP), middle page (MP), and previous page (UP) corresponding to different bits stored in the TLC, respectively. In one instance, when programming the TLC, the LP may be programmed first, followed by the MP and then the UP. For example, the programming voltage may be applied to the cells on word lines 304, 408 until the cell reaches a first intermediate threshold voltage corresponding to the cell's least significant bit (LSB). Next, LP can be read to determine a first intermediate threshold voltage, and then a programming voltage can be applied to the cell on the word line until the cell reaches a second intermediate threshold voltage corresponding to the next bit of the cell (between the LSB and the most significant bit (MSB)). Finally, MP can be read to determine a second intermediate threshold voltage, and then a programming voltage can be applied to the cell on the word line until the cell reaches a final threshold voltage corresponding to the MSB of the cell. Alternatively, in other instances, LP, MP, and UP can be programmed together (e.g., in full-sequence programming or fuzzy-fine programming), or LP and MP can be programmed first, followed by UP (e.g., LM-fuzzy-fine programming). Similarly, when reading the TLC, controller 123 can read LP to determine whether the LSB stores logic 0 or 1 depending on the threshold voltage of the cell, the controller can read MP to determine whether the next bit stores logic 0 or 1 depending on the threshold voltage of the cell, and the controller can read UP to determine whether the final bit stores logic 0 or 1 depending on the threshold voltage of the cell.

[0061] Figure 5 An example of a voltage distribution chart 500 is shown, illustrating different NAND states of a TLC (e.g., cells 116, 302) storing three data bits (e.g., logic 000, 001, etc., up to logic 111). The TLC may contain an erase state 502 corresponding to logic '111' and multiple programming states 504 (e.g., AG) corresponding to other logic values ​​'000-110'. The programming states 504 may be separated by different threshold voltages 506. Initially, for example, after controller 123 erases block 402 containing the cells, cells 116, 302 may be in erase state 502. When controller 123 programs LP, MP, and UP as described above, the voltage of cells 116, 302 may increase until it meets the threshold voltage 506 corresponding to the logic value to be stored, at which point the cell transitions to its corresponding programming state 504. Although Figure 5 Eight NAND states are shown for TLC, but the number of states may vary depending on the amount of data stored in each cell 116, 302. For example, SLC may have two states (e.g., logic 0 and logic 1), MLC may have four states (e.g., logic 00, 01, 10, 11), and QLC may have sixteen states (e.g., erase and AN).

[0062] When controller 123 attempts to program cells 116, 302 of selected word lines 304, 408 into one of programming states 504, the controller may perform incremental step pulse programming (ISPP) over several programming cycles or ISPP cycles. For example, a programming voltage (e.g., high voltage) may be applied to selected word lines 304, 408; a pass voltage (e.g., high voltage less than the programming voltage) may be applied to other word lines 304, 408; a bit line programming voltage (e.g., low voltage) may be applied to bit lines 306, 406 connected to the selected cell being programmed on the selected word line; and a bit line inhibit voltage (e.g., high voltage) may be applied to bit lines 306, 406 connected to other cells not programmed on the selected word line. Applying a high programming voltage to the selected word line and a low voltage to the selected word line allows electrons to tunnel from the channel into the charge trapping layer of the selected cell, thereby increasing the cell's threshold voltage. On the other hand, applying a high voltage to the unselected bit line prevents electrons from tunneling from the channel into the charge trapping layer of the unselected cell, thereby preventing the threshold voltage of the cell from increasing. Therefore, bit lines coupled to cells programmed to lower states can be disabled to prevent the threshold voltage of those cells from increasing, while other cells are programmed to higher states. For example, in the case of TLC, the bit lines of cells initially programmed to state A can be disabled first, followed by the bit lines of different cells programmed to state B, then the bit lines of cells reaching state C, then state D, and so on, until the remaining cells on the selected word line finally reach state G and all cells on the selected word line are programmed.

[0063] After applying a programming voltage in a programming cycle or ISPP cycle, a programming verification voltage (e.g., a low voltage) may be applied to word lines 304, 408 to determine whether the cell's threshold voltage has increased beyond the corresponding threshold voltage to enter the expected programming state. If none of the cells transition to the expected programming state, another programming cycle or ISPP cycle is executed, in which a higher programming voltage may be applied to further increase the cell's threshold voltage. Subsequently, the programming verification voltage may be applied again to determine whether the cell's threshold voltage has transitioned to the expected programming state. This process of increasing the programming voltage and verifying the voltage threshold of the selected cell may be repeated over several programming cycles. If the cell transitions to its corresponding programming state and the total number of programming cycles does not exceed a predetermined cycle count, the controller determines that the cell has entered its expected programming state and has therefore been successfully programmed. Otherwise, if the total number of programming cycles exceeds the predetermined cycle count before the cell transitions to its corresponding programming state, the controller determines that a programming failure has occurred.

[0064] Figure 6 A conceptual diagram 600 illustrates an example of a garbage collection process, where data stored in page 604 of block 602 of the SLC unit is relocated to page 608 of block 606 of the QLC unit. The data may correspond to... Figure 1 Data 119, blocks 602 and 606 can correspond to Figure 4 Block 402, and the SLC / QLC unit can correspond to Figure 1 and 3 Units 116 and 302. Each page 604 and 608 contains data stored in multiple units along the same row or word line (e.g., word lines 304 and 408) of the NVM. Therefore, each page 604 may contain data stored in one row of units 116 within a block, while each page 608 may contain data stored in one row of units 116 within another block. For simplicity, Figure 6 Examples are shown as blocks 602 and 606, each containing only four pages 604 and 608. However, it should be recognized that each block can contain any number of pages.

[0065] exist Figure 6 In this example, the data represented by identifiers A, B, and C is stored in different pages 604 of block 602. Initially, data A, B, and C are stored in the three pages of block 602 in response to write commands from the host device, thus leaving one page idle in this example. When the storage device receives new or updated data, this data is stored in the idle page 610. For example, updated data A' may be received from the host device and written to the idle page 610. Since data cannot be overwritten in flash memory, invalid data A remains stored in block 602. Due to the combination of new and invalid data, block 602 can quickly become full.

[0066] To free up space in the SLC block, the original and updated data in block 602 can be transferred to block 606. Invalid data remains in the old block. For example, in Figure 6 In this instance, the original data B and C, and the updated data A', are read from page 604 of block 602 and written to one or more pages 608 of block 606. Invalid data A remains in block 602. When block 602 is subsequently erased, the invalid data is discarded, and block 602 can be reused to store new data.

[0067] However, for example, in situations where multiple 4KB data overwrites occur, such GC processes can lead to increased write amplification of storage device 102. To reduce or eliminate GC and thus reduce write amplification of the storage device, storage device 102 may implement ZNS, in which groups of contiguous, non-overlapping logical addresses are divided into regions.

[0068] Figure 7 A conceptual diagram 700 illustrates an example of region 702. Each region 702 has a fixed size and contains a contiguous range of sequential logical addresses 704 within the NVM 110. For example, as shown, the NVM 110 may contain a total of z LBAs divided into x regions, where each region contains a range of nm sequential LBAs, where z represents the total number of sectors in the flash memory, x represents the number of regions, m represents the first LBA in the region, and n represents the last LBA in the same region. Each region may be used exclusively by the host device 104 to store data associated with one or more applications running by the host device 104. Therefore, the host device 104 may divide the LBAs into several regions depending on the number of applications running by the host device 104.

[0069] Figure 8 An example diagram 800 illustrates a controller 802 for a storage device that writes data 804 received from a host device 806 into block 808 of a die 810 according to region 812. For example, controller 802 may correspond to... Figure 1 The memory controller 123 of the storage device 102 in the host device 806 can correspond to the memory controller 123 of the storage device 102. Figure 1 The host device 104 and block 808 in the middle can correspond to Figure 4 Block 402, data 804 can correspond to Figure 1 Data 119. Traditionally, host device 806 can define region 812 (e.g., region and...). Figure 6The mapping of logical address 604 in the region is sent to controller 802, and controller 802 can generate L2P mapping table 814 (e.g., L2P mapping tables 120, 205), which maps the LBA (e.g., logical address 604) of each region 812 to a single physical block (e.g., block 402). Figure 8 In this example, assume each region is 64MB in size, with a sector size of 512 bytes, and therefore each region can contain 125,000 LBAs. Furthermore, assume each block can store 64MB of data. Therefore, region 0 can be mapped to only one block (e.g., PBA 0), region 1 can be mapped to only another block (e.g., PBA 1), and so on. Each application on the host can then write data to the corresponding region, for example, by instructing the controller of the sequential range of LBAs. For instance, host device 806 can send a write command to controller 802 to write data sequentially from LBA 0 to LBA 124999 and / or sequentially from LBA 125000 to LBA 249999. The controller can translate the indicated LBAs into mapped physical addresses (e.g., PBA 0 or 1 respectively), and thus write the data in mapped block 808. Therefore, host device 806 can write data from different applications to different physical blocks individually corresponding to different regions.

[0070] In some respects, the host device 806 may not be as described above. Figure 5 The text describes writing data page by page and invalidating the data (e.g., between 4KB commands). For example, when writing data to... Figure 6 When in region 1 of the region, the host device 806 can not only write data to LBA m, but also immediately write new data to LBA m while invalidating the old data at LBA m. Specifically, the entire region must be fully written (i.e., from LBA m to LBA n-1 in one or more writes) before data is written again to the previous LBA in the region. Therefore, in Figure 8 In an instance concerning region 0, if a host writes data to LBA 0, then the host must continue writing data sequentially from LBA 1 up to LBA 124999 (in one or more writes, at various times) until the host can finally write the new data back to LBA 0. This feature of ZNS prevents blocks mapped to various regions from containing partially invalid data that will require GC (e.g., ...). Figure 5 (as shown in the document), thus reducing or eliminating GC.

[0071] While region sizes remain fixed within a ZNS, block sizes tend to scale or increase over time. This scaling can result in additional, unused storage space when fixed-size regions are mapped to individual physical blocks. Allocating this extra space to another region negates the benefits of a ZNS, as garbage collection (GC) may be required in such cases. For example, if one region is completely written to a scaled block (and therefore can be invalid) while another region is only partially written to the remainder of a scaled block (and therefore cannot be invalid), then GC will still be needed to protect valid data.

[0072] To mitigate these limitations of ZNS, this disclosure implements a first partition in the flash memory, the first partition having multiple dies as channels allocated to ultra-small regions (e.g., 4MB, 8MB, etc.) to perform storage operations in parallel across all dies, wherein each 808 (or sub-block) in the die (e.g., 810) is allocated as the lowest-level erase unit. Data written to the first partition is synchronized with a second partition in memory designated to said region, such that when the host device and storage device are idle, data in said region is then transferred to the second partition, while maintaining region attributes and reducing over-provisioning.

[0073] The memory controller 802 can allocate the lowest-level erase units (e.g., physical blocks or sub-blocks) to regions within the first partition of the flash memory. In some aspects, the memory controller 802 can utilize SLC blocks (e.g., SLC giant blocks) as the first partition of multiple regions. For example, the SLC giant block can be accessed across all dies (or channels) to be shared by all the smaller regions allocated to the SLC block. In some aspects, data for multiple regions can be written to the same SLC giant block.

[0074] In some aspects, the first partition in a flash memory can be represented as an optional reference to an SLC giant block, and there is no compression within the SLC block. For example, even after the block becomes full, there may be no data movement within the SLC block. In some aspects, data can be tracked by sequentially writing to multiple regions. For example, a synchronous write pointer between the first and second partitions can be used to track write operations within the SLC block using the second partition.

[0075] In this regard, memory controller 802 can perform write operations on the SLC block in parallel across all dies for a specified region, with only 1D writes in the first partition. In some aspects, memory controller 802 can perform read operations from the first partition involving the SLC block using an optional reference to the SLC block to achieve faster reads. In some aspects, data movement between SLC blocks and TLC blocks can be performed via horizontal read operations across all dies in the megablock and single-die writes in the background (e.g., when host device 806 and storage device 102 are idle).

[0076] Figure 9 An example diagram 900 of a storage device is shown, the storage device having a first partition 902 containing die planar blocks 910, 912, 920, 922, 930, 932, 940, 942 and second partitions 950, 952 associated with different regions. In some aspects, such as Figure 9 The storage device depicted herein may correspond to a BICs6 flash memory device utilizing SLC cells, wherein the main partition 902 may correspond to an SLC block representing a gigabyte of size 400MB, and each region may be 1MB in size; however, the block size and / or region size may vary depending on the implementation.

[0077] As discussed above, if an entire gigabyte of 400MB is allocated to support a region of 1MB, then the gigabyte is over-provisioned to support the smaller region because many open blocks can remain within the gigabyte after sequential writes are complete. Also, as previously discussed, other ZNS methods may involve forming regions allocated to a single die plane block (e.g., two planes within a die) or a single die plane block. However, this method may not benefit from die parallelism used for specific regions, thus negatively impacting performance.

[0078] To mitigate the aforementioned limitations, this disclosure provides an SLC massive block designated as first partition 902, which is shared by all regions allocated to the block, and data written to the block can be mixed across all regions. Data written to first partition 902 can be immediately moved to actual region blocks in second partitions (e.g., 950, 952), and optional references can be maintained in first partition 902. In this regard, data in the SLC cells of first partition 902 can be discarded at any point in time to avoid any compression.

[0079] In a storage device, there are multiple integrated circuit packages (e.g., chips and / or dies) coupled to each other, allowing parallel access to multiple dies. For example... Figure 9As shown, each row represents a die plane block, where p0 and p1 each represent a plane, and D0-D3 each represent a die. The first partition 902 contains: a first die (depicted as "D0") containing die plane blocks 910 and 912; a second die (depicted as "D1") containing die plane blocks 920 and 922; a third die (depicted as "D2") containing die plane blocks 930 and 932; and a fourth die (depicted as "D3") containing die plane blocks 940 and 942. In this respect, the primary partition 902 contains a total of eight die plane blocks. In some embodiments, each of the die plane blocks may correspond to a complete block, or in other embodiments, to a sub-block. If the first partition 902 has a block size of 400 MB, then each die plane block may correspond to a block size of 50 MB.

[0080] The first partition 902 is not limited to a single block allocation and can accommodate multiple regions, thus maintaining performance. When a gigabyte block is used as the first partition 902 that spans all raw dies, data can be written in parallel to all raw die plane blocks of the first partition 902 to achieve maximum parallelism in data storage. As discussed above, there can be multiple regions that can be allocated to blocks and shared with other regions. For example, each of the raw die plane blocks 910, 912, 920, 922, 930, 932, 940, 942 can be allocated to a region (e.g., region 0, region 1... region N), where each region can correspond to a block size of 4MB or 8MB. Figure 9 As shown, region 0 and region 1 can be combined.

[0081] In some aspects, when deleting or resetting regions, criteria can be defined for a region-based approach, such as ZNS. In this regard, the criteria used for writing / reading regions can be defined by the host. As discussed above, regions can be negotiated and allocated between the host and the storage device. For example, there may be a pre-existing agreement between the host and the storage device regarding how the storage device can handle region data by deciding which write operations to perform in multiple regions. If the storage device has a 128GB non-volatile memory capacity, the host can divide the logical range of the non-volatile memory capacity into multiple logical regions. For example, the host may intend to write 100GB of data, whereby the host can write 1GB data blocks on 100 allocated regions. Within a 1GB block, the memory controller can maintain a sequential write sequence. The memory controller can write 0 to 1 GB in one row of allocated areas spanning all die plane blocks 910, 912, 920, 922, 930, 932, 940, 942, and return to write 0 to 1 GB in the next row of allocated areas spanning all die plane blocks 910, 912, 920, 922, 930, 932, 940, 942, and so on.

[0082] When a host interacts with a storage device to store host data, the host may first determine the number of available regions and initiate the allocation of those regions. During this region allocation, the host may specify to the memory controller the region size allocation and the manner in which storage operations will occur at each region (e.g., sequential or random). In some aspects, region attributes may be defined by the host when allocating regions based on host applications. For example, these region attributes may be defined when the host sets region attributes for the storage device (e.g., region size, region usage), and when regions are allocated dynamically in real time. In some aspects, when the host attempts to use regions for applications requiring high throughput, the host may allocate a contiguous number of regions with higher allocated block sizes (e.g., 4MB, 8MB, or larger per region). In some aspects, the host may recognize that regions with smaller coverage areas may be needed, but data may need to be accessed sequentially, thus allocating smaller regions. In some situations, the host may need to access a series of logical block addresses in a random manner, and therefore the host may not allocate sequential regions, but rather random regions. The memory controller is configured in advance to know that, for a specific range of logical block addresses, the regions may be accessed randomly rather than sequentially. In some aspects, the memory controller may handle these logical block address ranges in different ways between sequential and random operation modes.

[0083] In one or more embodiments, the data written to the first partition 902 spans different die plane blocks 910, 912, 920, 922, 930, 932, 940, and 942. Once data is written, the next write operation is performed on the next row of the area until the block is full. In some aspects, the memory controller may perform a first write operation with 16KB of data on the first die plane block 910 (e.g., p0 of D0). Figure 9 As shown, there are a total of eight planes, where each die contains a first plane (e.g., p0) and a second plane (e.g., p1), and the memory controller can write 16KB of data to each plane in parallel, thus writing a 128KB data block in parallel across all die planes. In this example, 16KB of data can be written based on a plane, and 128KB of data can be written based on a jumbo block. This sequential write sequence represents the performance gain due to parallelism.

[0084] While an application running on the host is writing data to die plane blocks (e.g., 910, 912, 920, 922, 930, 932, 940, 942), storage operations can be performed at the foreground visible to the host within the massive blocks. As described above, different data can be written across the die for maximum performance. When the application becomes idle (e.g., the host is not performing any operations), the storage device becomes idle. The host can write smaller blocks of data while it is writing, where the amount of data written does not need to be a large burst. On the storage device side, data arrives sequentially. In some aspects, write operations can be performed sequentially across all dies in each region (e.g., D0-D3), and erase operations can be performed on each die plane block (e.g., 910, 912, 920, 922, 930, 932, 940, 942). In ZNS, for example, it might not be necessary to erase not just 16KB blocks, but rather to first erase the entire die plane block so that the die plane block can be rewritten subsequently.

[0085] Each of partitions 950 and 952 may have an allocation corresponding to the smallest unit size allocated to the region (e.g., 1 / 8 of the total jumbo block size at 400MB corresponds to 50MB). When the host and storage device are idle, the memory controller may move data stored in the jumbo die plane block to a corresponding location in one of the second partitions 650 and 652 in the background. For example, the memory controller may transfer data from region 0 to second partition 950 and data from region 1 to second partition 952. In this respect, when high-throughput data storage is required, write operations are performed on the jumbo, and parallel writes are performed across all die plane blocks 910, 912, 920, 922, 930, 932, 940, and 942. On the other hand, when high-throughput data storage is not required, data is moved to slower blocks in each region (e.g., second partitions 950 and 952). The host may not see the data movement between the jumbo die plane block and the second partition blocks in the background.

[0086] Figure 10 This diagram 1000 illustrates an example memory transfer between a first partition having multiple die blocks and a second partition associated with a specific region after a write operation. Diagram 1000 depicts a first partition 1002 containing die planar blocks 1010, 1012, 1020, 1022, 1030, 1032, 1040, and 1042, and a second partition 1050 associated with a first region (e.g., region 0). For example, die planar blocks 1010, 1012, 1020, 1022, 1030, 1032, 1040, and 1042 may correspond to... Figure 9 The bare die planar blocks 910, 912, 920, 922, 930, 932, 940, and 942, and the second partition 1050 can correspond to Figure 9 The second partition 950. In some aspects, the second partition 1050 may be associated with a region, such that data in the region is specifically transferred and written to the second partition 1050 in the background. In some embodiments, the second partition 1050 contains a bare die.

[0087] In some aspects, the memory controller uses a first write pointer 1060 to indicate the location of written data within the first partition 1002, so as to specify the area to be transferred to the second partition 1050. Similarly, the memory controller uses a second write pointer 1064 to indicate a location within the second partition 1050 that is synchronized with the memory location of the first partition 1002. In this respect, the second write pointer 1064 moves to synchronize with the first write pointer 1060. Thus, the second partition 1050 may contain the same data stored in the memory location of the first partition 1002 up to the location indicated by the write pointer 1060.

[0088] In some aspects, the memory controller can perform write operations to write data horizontally and in parallel across all dies to achieve maximum write performance. At each time increment, the written data, indicated by write pointer 1060 and current region write pointer 1062, moves sequentially to the corresponding region block. For example, after each data transfer from the first partition 1002 to the second partition 1050, the first write pointer 1060 is advanced. The current region write pointer 1062 can indicate the last written location in the first partition 1002, such that after each write operation at a specified die plane block, the current region write pointer 1062 is advanced. In some aspects, the first write pointer 1060 and the current region write pointer 1062 are maintained for each region.

[0089] When data is written to a region (e.g., z0) at die plane block 1042, write pointer 1062 is advanced or updated to point to or indicate the next available die plane block in the region to be written, in order to track the next write start point (i.e., the completion point of a previous write is equivalent to the start point of a subsequent write). Therefore, write pointer 1062 indicates the position where a subsequent write to the region will begin. Subsequent write commands are 'region append' commands, where the data associated with the subsequent write command is appended to the region at the position indicated by write pointer 1062 as the next start point. An ordered list of LBAs within the region can be stored for write ordering. In some aspects, each region may have its own write pointer 1062. Thus, when a write command is received, write pointer 1062 determines where within the identified region 1062 the writing of data begins.

[0090] In a read operation, data can be read horizontally from all dies and moved to a single die in the background. For example... Figure 10 As shown, when a read operation is performed at the first partition 1002, the read data is moved to the second partition 1050 in the background (e.g., when the host and storage device are idle).

[0091] When a write operation is performed in a faster access region (e.g., at a die plane block in the first partition 1002), data is written to the first region (e.g., region 0), and region 0 is updated (represented by region 0 via updated data block 1054). For each region, the previous write pointer position, already synchronized with this particular portion of the first region, is maintained, along with any additional data being written by the memory controller. In the background, write pointers 1060 and 1064 are synchronized. When a 128KB data block is written, for example, to a sequential region of the first row (e.g., region 0 spanning die plane blocks 1010, 1012, 1020, 1022, 1030, 1032, 1040, 1042), data is written in the background to the second partition 1050 to synchronize the second partition 1050 with the data in region 0 of the first partition 1002. When the memory controller writes another 128KB data block to region 0, the first partition 1002 provides the additional updated data for region 0, which is then moved to the second partition 1050 in the background. Prior to the synchronization event between the first partition 1002 and the second partition 1050, the data written to the first partition 1002 is a unique copy (or primary copy). For a period of time, two copies (e.g., replicated versions) of the data stored in the flash memory exist, with different physical locations between the first partition 1002 and the second partition 1050. Once the synchronization between the first partition 1002 and the second partition 1050 is complete, the data in the first partition 1002 becomes optional data for retention.

[0092] Figure 11 Example diagram 1100 illustrates a memory read operation at a first partition 1102 having multiple die blocks 1110, 1112, 1120, 1122, 1130, 1132, 1140, and 1142. For example, die block 1110, 1112, 1120, 1122, 1130, 1132, 1140, and 1142 may correspond to... Figure 9 The raw die blocks 910, 912, 920, 922, 930, 932, 940, and 942. If a read operation is performed on the second partition 1150, the read performance may be lower compared to a read from the first partition 1102 because reads are performed sequentially (e.g., line by line). To improve read performance, the data written to the first partition 1102 is maintained as an optional reference. Data is read from the first partition 1102 to perform faster reads and achieve maximum parallelism, rather than reading region data from a single raw die block, such as the second partition 1150. In this respect, read operations on the first partition 1102 are performed using parallel reads.

[0093] Figure 12An example diagram 1200 of a storage device is shown, the storage device having a first partition 1202 containing die planar blocks 1210, 1212, 1220, 1222, 1230, 1232, 1240, 1242 and second partitions 1250, 1252 associated with different regions for read operations. For example, die planar blocks 1210, 1212, 1220, 1222, 1230, 1232, 1240, 1242 may correspond to... Figure 9 The bare die planar blocks 910, 912, 920, 922, 930, 932, 940, and 942, and the second partitions 1250 and 1250 can correspond to Figure 9 The second partition is 950 and 950.

[0094] In some cases, when the first partition 1202 becomes full, even if valid data exists in the first partition 1202, optional references to the written area data will be erased, and the entire first partition 1202 will also be erased. For example... Figure 12 As shown, each of the bare die planar blocks 1210, 1212, 1220, 1222, 1230, 1232, 1240, and 1242 contains invalid data, valid data in region 0, and valid data in region 1. Compressing can be reduced or removed by erasing the entire SLC cache block (e.g., the first partition 1202) when the block becomes full.

[0095] Immediately after erasing the first partition 1202, data can be rewritten to the first partition 1202 in the background (e.g., when the host and storage devices are idle), depending on the specific region, using stored data from the second partitions 1250, 1250. In this regard, region blocks and optional references can be recreated based on information within the data written to the corresponding region blocks in the second partitions 1250, 1252. For example, a region block in the first partition 1202 concerning region 0 can be rewritten using data read from the second partition 1250 associated with region 0. Similarly, a region block in the first partition 1202 concerning region 1 can be rewritten using data read from the second partition 1252 associated with region 1.

[0096] By using, as referenced Figures 8 to 12 The aforementioned scheme can reduce the over-stress of ultra-small areas to the smallest erase unit, while maintaining an optional reference to the written area data in the SLC big block to meet the read / write performance of the flash memory. In this respect, defragmentation or compaction can be avoided in the SLC big block.

[0097] When a write operation is completed in an SLC giant block, the data written to the giant block is synchronized with the corresponding region data stored in a separate primary partition designated for that region. In this respect, there are two copies of the same data. Eventually, the giant block becomes full and needs to be erased. When erasing the SLC giant block, the SLC giant block can be rewritten using the data stored in the primary partition designated for that region. A copy of the region data can be regenerated in the background. After the block is regenerated in the SLC giant block, the storage device can perform faster writes and faster reads.

[0098] Figure 13 An example flowchart of a process 1300 for storing data in a memory block allocated to a small region is shown. For example, process 1300 may be performed in, for instance... Figure 1 This is performed in the storage device 102 shown. Each step in the flowchart can be controlled using a controller (e.g., controller 123) as described below, by a component or module of the controller, or by some other suitable component.

[0099] As indicated by block 1302, the controller can assign each of a plurality of blocks of each of a plurality of dies as a lowest-level erase unit to one or more regions. For example, refer to Figure 1 , 8 And 9, controller 123 can physical blocks as the lowest-level erase unit to the region. In another example, such as Figure 6 As shown, the controller can assign sub-blocks to regions as the lowest-level erasure units.

[0100] As indicated by block 1304, the controller can receive write commands and data from the host device, the write commands instructing data to be written to a first area of ​​one or more areas. For example, refer to... Figure 1 , 8 9. Controller 123 may receive write commands from host device 104 to perform one or more write operations at a specified area.

[0101] As indicated by block 1306, the controller can perform a write operation, which writes received data to one or more of a plurality of dies allocated to a first region. For example, refer to Figure 9 The controller 123 can write data in parallel across multiple dies allocated to the first region.

[0102] As indicated by block 1308, when the storage device is in an idle state, the controller can transfer data from a first region to a second partition in the memory associated with the first region. For example, refer to... Figure 10The controller 123 can transfer data written to the first area to a second partition, which is designated to store data used in the first area.

[0103] As indicated by block 1310, the controller can select a first partition between a first partition and a second partition to perform one or more read operations on data from one or more regions. For example, refer to... Figure 11 Instead of reading data sequentially from the second partition, the controller 123 can read data from the first partition by accessing the stored data in parallel from multiple dies.

[0104] Figure 14 This is a conceptual diagram illustrating an example 1400 of a controller 1402 coupled to a memory 1404 in a storage device. For example, controller 1402 may correspond to controller 123, and memory 1404 may correspond to... Figure 1 The NVM 110 is a storage device 102 within the system. The controller can be implemented in software, hardware, or a combination of both. In one exemplary embodiment, the controller is implemented using several software modules executing on one or more processors; however, as those skilled in the art will appreciate, the controller can be implemented in different ways. Those skilled in the art will readily understand how the controller can be optimally implemented based on the specific design parameters of the system.

[0105] Controller 1402 provides means for allocating each of a plurality of blocks of a plurality of dies as a lowest-level erase unit to one or more regions. For example, controller 1402 may perform the aforementioned process described at 1302. In one configuration, controller 1402 may be further configured to receive write commands and data from a host device, for example, as described in conjunction with 1304. In one configuration, controller 1402 may be further configured to perform a write operation that writes the received data to one or more of the plurality of dies allocated to a first region, for example, as described in conjunction with 1306. Controller 1402 provides means for transferring data from the first region to a second partition in memory associated with the first region when the storage device is idle. For example, controller 1402 may perform the aforementioned process described at 1308. In one configuration, controller 1402 may be further configured to select a first partition between a first partition and a second partition to perform one or more read operations on data from one or more regions, for example, as described in conjunction with 1310.

[0106] Therefore, the controller described in this disclosure improves the memory capacity of the storage device by reducing the amount of over-provisioning of memory blocks allocated to small regions. For example, the storage device supplies a first partition in a flash memory, the first partition having multiple dies as channels allocated to ultra-small regions to perform storage operations in parallel across all dies, wherein each block (or sub-block) in the die is allocated to the first partition as the lowest-level erase unit. In this way, the controller can perform faster writes by accessing multiple dies in parallel to store data intended for different regions, while simultaneously moving the stored data from the faster write region to the lower write region in the background. Thus, reducing the over-provisioning of memory blocks allocated to small regions can be achieved with minimal changes to the controller logic and architecture.

[0107] Various aspects of this disclosure are provided to enable those skilled in the art to practice the invention. Various modifications to the exemplary embodiments presented throughout this disclosure will be apparent to those skilled in the art, and the concepts disclosed herein are extendable to other magnetic storage devices. Therefore, the claims are not intended to limit them to the various aspects of this disclosure, but are to be accorded the full scope consistent with the language of the claims. All structural and functional equivalents of the various components throughout the exemplary embodiments described in this disclosure that are known to or will later be known to those skilled in the art are expressly incorporated herein by reference and are intended to be covered by the claims. Furthermore, nothing disclosed herein is intended to be exclusive to the public, whether or not it is expressly stated in the claims. No element of any claim shall be construed under U.S. 35 USC § 112(f) or similar statutes or rules of law of another jurisdiction, unless the element is explicitly stated using the phrase “for…component” or, in the case of a method claim, enumerated using the phrase “for…step.”

Claims

1. A storage device comprising: A memory comprising a first partition having a plurality of dies as channels allocated to one or more regions; and The controller is configured to: Perform a write operation, wherein the write operation writes the received data to one or more of the plurality of dies allocated to the first region; and When the storage device is idle, the data is transferred from the first region to a second partition in the memory associated with the first region.

2. The storage device of claim 1, wherein each of the plurality of dies comprises a plurality of blocks, wherein the controller is further configured to allocate the plurality of blocks in each of the plurality of dies to different regions.

3. The storage device of claim 2, wherein the controller is further configured to assign each of the plurality of blocks of each of the plurality of dies as a lowest-level erase unit to the one or more regions.

4. The storage device of claim 3, wherein the lowest level erase unit corresponds to a physical block.

5. The storage device of claim 3, wherein the lowest level erase unit corresponds to a physical sub-block.

6. The storage device of claim 1, wherein the second partition corresponds to a die plane block having one or more physical blocks.

7. The storage device of claim 1, wherein the first partition and the second partition are located at different physical locations within the memory.

8. The storage device of claim 1, wherein one or more write pointers between the first partition and the second partition are used to synchronize the data written to the first partition with the second partition.

9. The storage device of claim 1, wherein after synchronization between the first partition and the second partition, the data written in the first region of the first partition is a copy of the data written in the second partition.

10. The storage device of claim 9, wherein after the synchronization between the first partition and the second partition, the data written in the first area of ​​the first partition becomes optional data for retention.

11. The storage device of claim 1, wherein the controller is further configured to: Determine whether the first partition is full; When it is determined that the first partition is full, the entire first partition is erased; and Data corresponding to at least one region is rewritten to at least a portion of the first partition using stored data associated with at least one region from the second partition.

12. The storage device of claim 1, wherein the controller is further configured to write data corresponding to different regions in the first partition, and wherein the different regions allocated to the first partition are accessible across the plurality of dies.

13. The storage device of claim 1, wherein the controller is further configured to perform write operations on the first partition in parallel across all of the plurality of dies for a specified region.

14. The storage device of claim 1, wherein the controller is further configured to select the first partition between the first partition and the second partition to perform one or more read operations on data from the one or more regions.

15. A storage device comprising: A memory comprising a first partition having a plurality of dies as channels allocated to one or more regions; and The controller is configured to: Receive a write command and data from the host device, wherein the write command instructs the data to be written into a first region of the one or more regions; A write operation is performed, wherein the write operation writes the data to one or more of the plurality of dies allocated to the first region; and When the storage device and the host device are idle, the data is transferred from the first region to a second partition in the memory associated with the first region.

16. The storage device of claim 15, wherein each of the plurality of dies comprises a plurality of blocks, wherein the controller is further configured to allocate the plurality of blocks in each of the plurality of dies to different regions.

17. The storage device of claim 15, wherein the controller is further configured to perform write operations on the first partition in parallel across all of the plurality of dies for a specified region.

18. The storage device of claim 15, wherein one or more write pointers between the first partition and the second partition are used to synchronize the data written to the first partition with the second partition.

19. The storage device of claim 15, wherein after synchronization between the first partition and the second partition, the data written in the first area of ​​the first partition becomes optional data for retention.

20. A storage device comprising: A memory comprising a first partition having a plurality of dies as channels allocated to one or more regions, each of the plurality of dies comprising a plurality of blocks; and The controller is configured to: Each of the plurality of blocks in each of the plurality of bare dies is assigned as the lowest level erasure unit to the one or more regions; Receive a write command and data from the host device, wherein the write command instructs the data to be written into a first region of the one or more regions; A write operation is performed, wherein the write operation writes the data to one or more of the plurality of dies allocated to the first region; and When the storage device and the host device are idle, the data is transferred from the first region to a second partition in the memory associated with the first region.

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