A RS422 serial port

Abstract

This application provides an RS422 serial port, including: a bus serial port controller and a bus interface transceiver; the bus serial port controller is connected to the bus interface transceiver, and the bus serial port controller sends first transmission data, receives second transmission data, and sends a first enable signal and a second enable signal to the bus interface transceiver; the bus interface transceiver determines the level values ​​of the first enable signal and the second enable signal, and if the level value is greater than a preset threshold, the first transmission data and / or the second transmission data are buffered; otherwise, the first transmission data and / or the second transmission data are inverted. This application detects reverse connection and uses the enable signal to control whether the data is buffered or inverted, enabling the RS422 serial port to be connected in both directions, avoiding significant losses due to design errors, and increasing the usability of the RS422 serial port.

Description

Technical Field

[0001] This application claims protection for a wiring device, and more particularly relates to an RS422 serial port. Background Technology

[0002] RS422 serial communication is a type of asynchronous serial communication transceiver. Asynchronous serial communication transceivers specifically implement the conversion between serial and parallel bus for the data to be transmitted.

[0003] RS422 bus devices are widely used in various fields due to their low cost and reliable performance; this interface can be found on various computer devices.

[0004] Please refer to Figure 1 As shown, Figure 1 This diagram illustrates a bus interface transceiver for an existing RS422 serial port. A / B represent differential signals 011 and 012, respectively. When data is present on the bus, conversion module 01 converts the differential signals into single-ended signals and transmits them to 013. Z / Y represent differential signals 021 and 022, respectively. When data needs to be sent, conversion module 02 converts data 023 into differential signals 021 and 022, which are then introduced into the bus via Z / Y. However, if the user reverses A / B or Z / Y connections, or if a cable design error causes A / B and Z / Y connections to be reversed between the two devices, the entire system communication will malfunction. This necessitates a redesign, potentially even a complete redesign of the computer motherboard, resulting in economic losses and increased time and labor costs. Summary of the Invention

[0005] The bus interface transceiver determines the level values ​​of the first enable signal and the second enable signal. If the level value is greater than a preset threshold, the first transmitted data and / or the second transmitted data are buffered; otherwise, the first transmitted data and / or the second transmitted data are inverted.

[0006] Optionally, the bus interface transceiver includes: a first logic gate, a second logic gate, a third logic gate, a fourth logic gate, a fifth logic gate, a sixth logic gate, a seventh logic gate, and an eighth logic gate;

[0007] The first and third logic gates form the first buffer for the second transmitted data; the second and fourth logic gates form the first inverter for the second transmitted data; the fifth and seventh logic gates form the second inverter for the first transmitted data; and the sixth and eighth logic gates form the second buffer for the first transmitted information signal.

[0008] Optionally, when the level of the first enable signal is greater than the preset threshold, the second buffer is turned on and the second inverter is turned off; otherwise, the second buffer is turned off and the second inverter is turned on.

[0009] When the level of the second enable signal is greater than a preset threshold, the first buffer is turned on and the first inverter is turned off. When the level of the second enable signal is greater than a preset threshold, the first buffer is turned on and the first inverter is turned on.

[0010] Optionally, the level values ​​of the first enable signal and the second enable signal include, depending on the serial port wiring relationship:

[0011] When the wiring of the first transmitted data is reversed, the level of the first enable signal is less than a preset threshold; otherwise, it is greater than the preset threshold.

[0012] When the wiring of the second transmitted data is reversed, the level of the second enable signal is less than a preset threshold; otherwise, it is greater than the preset threshold.

[0013] Optionally, the controller is implemented using a programmable logic array.

[0014] The advantages of this application compared to the prior art are:

[0015] This application provides an RS422 serial port, including: a bus serial port controller and a bus interface transceiver; the bus serial port controller is connected to the bus interface transceiver, and the bus serial port controller sends first transmission data, receives second transmission data, and sends a first enable signal and a second enable signal to the bus interface transceiver; the bus interface transceiver determines the level values ​​of the first enable signal and the second enable signal, and if the level value is greater than a preset threshold, the first transmission data and / or the second transmission data are buffered; otherwise, the first transmission data and / or the second transmission data are inverted. This application detects reverse connection and uses the enable signal to control whether the data is buffered or inverted, enabling the RS422 serial port to be connected in both directions, avoiding significant losses due to design errors, and increasing the usability of the RS422 serial port. Attached Figure Description

[0016] Figure 1 A schematic diagram of a bus interface transceiver for an existing RS422 serial port is shown.

[0017] Figure 2 This is a schematic diagram of the connection framework for the RS422 serial port in this application.

[0018] Figure 3 This is a schematic diagram of the RS422 bus interface transceiver in this application. Detailed Implementation

[0019] The following are examples of specific implementation processes provided to illustrate the technical solutions to be protected in this application. However, this application may also be implemented in other ways different from those described herein. Those skilled in the art can implement this application by different technical means under the guidance of the concept of this application. Therefore, this application is not limited to the specific embodiments below.

[0020] This application provides an RS422 serial port, including: a bus serial port controller and a bus interface transceiver; the bus serial port controller is connected to the bus interface transceiver, and the bus serial port controller sends first transmission data, receives second transmission data, and sends a first enable signal and a second enable signal to the bus interface transceiver; the bus interface transceiver determines the level values ​​of the first enable signal and the second enable signal, and if the level value is greater than a preset threshold, the first transmission data and / or the second transmission data are buffered; otherwise, the first transmission data and / or the second transmission data are inverted. This application detects reverse connection and uses the enable signal to control whether the data is buffered or inverted, enabling the RS422 serial port to be connected in both directions, avoiding significant losses due to design errors, and increasing the usability of the RS422 serial port.

[0021] Figure 2 This is a schematic diagram of the connection framework for the RS422 serial port in this application.

[0022] Please refer to Figure 2 As shown, the RS422 serial port bus serial port controller 101 and the bus interface transceiver 102 are connected through at least four channels, which are respectively used to send the first transmission data 103, receive the second transmission data 104, send the first enable signal 105 and send the second enable signal 106.

[0023] When sending the first transmission data 103, the bus interface transceiver 102 receives the first transmission data 103 from the bus serial port controller, converts the first transmission data 103 into a differential signal, and outputs the data through two channels. When receiving the second transmission data 104, the bus interface transceiver 102 combines the differential signals into the second transmission data 104 and sends it to the bus serial port controller.

[0024] Figure 3 This is a schematic diagram of the RS422 bus interface transceiver in this application.

[0025] Please refer to Figure 3 As shown, after the first transmission data 103 is input to the bus interface transceiver 102, the first transmission data 103 is divided into a first differential signal 2011 (RS422 TX+) and a second differential signal 2012 (RS422 TX-) by the signal separation unit 201 (TXD), and then output.

[0026] Before being output to the bus interface transceiver 102, the second transmission data 104 is generated by the external third differential signal 2021 (RS422RX-) and fourth differential signal 2022 (RS422 RX+) being converted into the second transmission data 104 via the signal aggregation unit 202 (RXD) and input to the bus serial port controller 101.

[0027] The bus serial port controller 101 is implemented using a programmable logic array (FPGA). The bus controller 101 outputs a first enable signal 105 (RS422_TXD_POLARITY) and a second enable signal 106 (RS422_RXD_POLARITY). These signals output different voltage levels depending on the orientation of the wiring of the first transmission data 103 and the second transmission data 104. If the wiring is correct, the voltage level is high, meaning the voltage value is greater than a preset threshold. If the wiring is reversed, the first enable signal 105 is low if the wiring of the first transmission data 103 is reversed, and the second enable signal 106 is low if the wiring of the second transmission data 104 is reversed. The low voltage level is meaning the voltage value is less than a preset threshold.

[0028] Please continue to refer to Figure 3 As shown, the signal separation unit 201 is connected to the fifth logic gate 203, the sixth logic gate 204, the seventh logic gate 205 and the eighth logic gate 206 respectively. The seventh logic gate 205 and the eighth logic gate 206 are connected in parallel to the first differential signal 2011, and the fifth logic gate 203 and the sixth logic gate 204 are connected in parallel to the second differential signal 2012.

[0029] The signal aggregation unit 202 is connected to the first logic gate 207, the second logic gate 208, the third logic gate 209 and the fourth logic gate 210 respectively, wherein the third logic gate 209 and the fourth logic gate 210 are connected in parallel to the third differential signal 2021, and the first logic gate 207 and the second logic gate 208 are connected in parallel to the fourth differential signal 2022.

[0030] The first logic gate 207 and the third logic gate 209 are the second buffers of the second transmitted data 104, and the fifth logic gate 203 and the seventh logic gate 205 are the first inverters of the first transmitted data 103. The second logic gate 208 and the fourth logic gate 210 are the first inverters of the second transmitted data 104, and the sixth logic gate 204 and the eighth logic gate 206 are the second buffers of the first transmitted data 103.

[0031] The first enable signal 105 controls the fifth, sixth, seventh, and eighth logic gates. When the first enable signal 105 is greater than a preset threshold, the fifth and seventh logic gates are closed, and the sixth and eighth logic gates are open, and vice versa. The second enable signal 106 controls the first, second, third, and fourth logic gates. When the second enable signal is greater than a preset threshold, the second and fourth logic gates are closed, and the first and third logic gates are open, and vice versa.

[0032] When the first and second buffers are turned on, all differential signals are transmitted normally. When the first or second inverter is turned on, the corresponding differential signals are transmitted in reverse phase, so that correct data access can be performed regardless of the wiring orientation.

Claims

1. An RS422 serial port, characterized in that, include: Bus serial port controller and bus interface transceiver; The bus serial port controller is connected to the bus interface transceiver. The bus serial port controller sends first transmission data to the bus interface transceiver, receives second transmission data, and sends a first enable signal and a second enable signal. The bus interface transceiver determines the level values ​​of the first enable signal and the second enable signal. If the level value is greater than a preset threshold, the first transmitted data and / or the second transmitted data are buffered; otherwise, the first transmitted data and / or the second transmitted data are inverted. Specifically, this includes: If the level of the first enable signal is greater than a preset threshold, the first transmitted data is buffered; otherwise, the first transmitted data is inverted. If the level of the second enable signal is greater than a preset threshold, the second transmitted data is buffered; otherwise, the second transmitted data is inverted.

2. The RS422 serial port according to claim 1, characterized in that, The bus interface transceiver includes: a first logic gate, a second logic gate, a third logic gate, a fourth logic gate, a fifth logic gate, a sixth logic gate, a seventh logic gate, and an eighth logic gate; The first and third logic gates form the first buffer of the second transmitted data; the second and fourth logic gates form the first inverter of the second transmitted data; the fifth and seventh logic gates form the second inverter of the first transmitted data; and the sixth and eighth logic gates form the second buffer of the first transmitted data.

3. The RS422 serial port according to claim 2, characterized in that, When the level of the first enable signal is greater than the preset threshold, the second buffer is turned on and the second inverter is turned off; otherwise, the second buffer is turned off and the second inverter is turned on. When the level of the second enable signal is greater than a preset threshold, the first buffer is turned on and the first inverter is turned off; otherwise, the first buffer is turned off and the first inverter is turned on.

4. The RS422 serial port according to claim 3, characterized in that, The level values ​​of the first and second enable signals, depending on the serial port wiring, include: When the wiring of the first transmitted data is reversed, the level of the first enable signal is less than a preset threshold; otherwise, it is greater than the preset threshold. When the wiring of the second transmitted data is reversed, the level of the second enable signal is less than a preset threshold; otherwise, it is greater than the preset threshold.

5. The bus serial port according to claim 1, characterized in that, The controller is implemented using a programmable logic array.

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