System on chip, computing device and method for regulating two voltages

Abstract

Provided are a system on chip, a computing device, and a method for regulating two voltages. The system on chip comprises a processing unit configured to send a frequency-voltage regulation instruction; a dual-rail memory comprising a logic device and a memory array; and a frequency-voltage regulation controller comprising a voltage determination unit configured to determine a first target value and a second target value according to the frequency-voltage regulation instruction, wherein the first target value is any value in a first interval, and any value in the first interval and the second target value satisfy a voltage constraint relationship set for the logic device and the memory array; and a voltage regulation signal generation unit configured to generate a voltage regulation signal according to the first target value and the second target value and send the voltage regulation signal to a power management circuit, so that the power management circuit adjusts a supply voltage according to the voltage regulation signal. According to the embodiment, the constraint relationship is not destroyed in the process of reaching the target value, thereby achieving stability of voltage regulation.

Description

Technical Field

[0001] This disclosure relates to the field of chips, and more specifically, to a system-on-a-chip, a computing device, and a method for regulating two voltages. Background Technology

[0002] The miniaturization trend in integrated circuits has fueled processor manufacturers' enthusiasm for reducing power consumption. There are two main methods for reducing system power consumption: Dynamic Voltage and Frequency Scaling (DVFS) and Adaptive Voltage and Frequency Scaling (AVFS). DVFS dynamically adjusts the system's clock frequency and supply voltage based on the computing power requirements of the applications running on the processor, thereby achieving energy savings. AVFS uses sensors to detect the system's application environment in real time to determine the supply voltage.

[0003] However, the inventors discovered during their research that most small integrated circuits use dual-track memory. In dual-track memory, the storage array used for actual data storage and the logic devices used to control the read / write process use different supply voltages. The supply voltage of the logic devices is also the system supply voltage (used by all components except the storage array). Therefore, when adjusting the supply voltage based on AVFS or DVFS, it is actually necessary to adjust both the system supply voltage and the supply voltage of the dual-track memory's storage array. This raises a new problem: how to adjust the two voltages. Existing technology uses a parallel voltage regulation scheme (i.e., synchronous adjustment of the two voltages). However, the drawback of this scheme is that during parallel voltage regulation, the simultaneous change of the two voltages may disrupt the constraint relationship between them. This constraint relationship refers to the voltage constraint relationship that the supply voltages of the logic devices and storage array of the dual-track memory must constantly meet. Summary of the Invention

[0004] In view of this, the purpose of this disclosure is to provide a system-on-a-chip, a computing device, and a method for regulating two voltages to solve the problems existing in the prior art.

[0005] In a first aspect, embodiments of this disclosure provide a system-on-a-chip coupled to a power management circuit, comprising:

[0006] The processing unit is used to send frequency modulation and voltage regulation commands;

[0007] Dual-track memory, comprising logic devices and a memory array;

[0008] The frequency and voltage regulation controller includes:

[0009] A voltage determination unit is used to determine a first target value to which the power supply voltage of the logic device should be adjusted according to the frequency modulation and voltage regulation command, and to determine a second target value to which the power supply voltage of the memory array should be adjusted according to the first target value. The first target value is any value within a first interval, and any value within the first interval and the second target value conform to the voltage constraint relationship set for the logic device and the memory array.

[0010] A voltage regulation signal generation unit is used to generate a voltage regulation signal based on the first target value and the second target value and send it to the power management circuit so that the power management circuit can synchronously adjust the power supply voltage of the logic device and the memory array according to the voltage regulation signal.

[0011] Optionally, the frequency and voltage regulation controller stores voltage relationship data, which is used to characterize the configuration of multiple fixed values ​​for the power supply voltage of the logic array, and to divide the value range of the power supply voltage of the logic device into multiple intervals corresponding to the multiple fixed values ​​respectively, wherein any value in each interval and its corresponding fixed value conform to the voltage constraint relationship.

[0012] The frequency and voltage regulation controller then retrieves the voltage relationship data based on the first target value to determine the first interval, and uses the fixed value corresponding to the first interval as the second target value.

[0013] Optionally, the voltage constraint relationship is as follows: the power supply voltage of the storage array is not greater than the sum of the power supply voltage of the logic device and the first set value, and at the same time, it is not less than the difference between the power supply voltage of the logic device and the second set value.

[0014] Optionally, the upper boundary value of each interval is equal to the fixed value corresponding to that interval plus the second set value, and its lower boundary value is equal to the fixed value corresponding to that interval minus the first set value.

[0015] Optionally, the upper boundary value of each interval is equal to the fixed value corresponding to that interval, or the lower boundary value of each interval is equal to the fixed value of that interval.

[0016] Optionally, the voltage regulation signal generation unit generates two voltage regulation signals based on the first target value and the second target value and sends them to the power management circuit.

[0017] Optionally, during the process of synchronously adjusting the power supply voltages of the logic device and the memory array, the difference in the rate of change of the two power supply voltages does not exceed a set value.

[0018] Optionally, when the frequency modulation and voltage regulation controller is a DVFS controller, the voltage determination unit includes:

[0019] The target register is used to store the target frequency obtained from the frequency modulation and voltage modulation command;

[0020] Multiple comparators are used to compare the target frequency with a pre-established correspondence between frequency and voltage, take the voltage corresponding to the target frequency as the first target value, and obtain the second target value from the voltage relationship data based on the first target value;

[0021] A selector is used to output the first target value and the first target value to the voltage regulation signal generation unit;

[0022] Multiple first registers are used to store the correspondence between the frequency and the voltage;

[0023] Multiple second registers are used to store the voltage relationship data.

[0024] Optionally, when the frequency modulation and voltage regulation controller is an AVFS controller, the voltage determination unit includes:

[0025] Multiple third registers are used to store the voltage relationship data;

[0026] The calculation unit is used to calculate the first target value based on the detected real-time temperature and process deviation, and retrieve the voltage relationship data based on the first target value to obtain the second target value;

[0027] The selector is used to output the first target value and the first target value to the voltage regulation signal generation unit.

[0028] Secondly, embodiments of this disclosure provide a method for adjusting two voltages, including:

[0029] Determine the first target value to which the first voltage channel should be adjusted;

[0030] The first target value is used to retrieve predefined voltage relationship data to determine the first interval to which the first target value belongs and the first fixed value corresponding to the first interval, and the first fixed value is used as the second target value to which the second voltage is to be adjusted.

[0031] Adjust the first voltage and the second voltage to the first target value and the second target value, respectively.

[0032] The voltage relationship data represents the multiple intervals in which the value range of the first voltage is divided and the multiple fixed values ​​used for the second voltage. Any value in each interval and its corresponding fixed value satisfy the constraint relationship between the two voltages. The first interval is one of the multiple intervals, and the first fixed value is one of the multiple fixed values.

[0033] Optionally, the constraint relationship includes: the first voltage is not greater than the sum of the second voltage and the first set value, and at the same time, it is not less than the difference between the second voltage and the second set value.

[0034] Thirdly, embodiments of this disclosure provide a computing device, including:

[0035] The system-on-a-chip described in any of the above items;

[0036] External bus;

[0037] Storage devices coupled to the on-chip system via the off-chip bus;

[0038] A power management circuit coupled to the system-on-chip.

[0039] In this embodiment, the frequency and voltage regulation controller synchronously adjusts the power supply voltage of the logic device of the dual-track memory to a first target value and adjusts the power supply voltage of the memory array to a second target value. Since any value in the first interval to which the first target value belongs conforms to the voltage constraint relationship preset by the logic device and memory array of the dual-track memory with the second target value, the constraint relationship will not be broken during the process of the two voltages reaching the target value at approximately the same rate, thereby ensuring the stability of voltage regulation. Attached Figure Description

[0040] The above and other objects, features, and advantages of this disclosure will become clearer from the following description of embodiments with reference to the accompanying drawings, in which:

[0041] Figure 1 This is a schematic diagram of the structure of a system-on-a-chip provided in an embodiment of this disclosure;

[0042] Figure 2 This is a structural diagram of a DVFS controller provided in an embodiment of this disclosure;

[0043] Figure 3 This is an example diagram illustrating the voltage relationship between two voltage sources constructed according to an embodiment of this disclosure;

[0044] Figure 4 This is a structural diagram of an AVFS controller provided in an embodiment of this disclosure;

[0045] Figure 5 This is a flowchart of a two-channel voltage adjustment method provided in an embodiment of this disclosure;

[0046] Figure 6 This is a schematic diagram of the structure of the general-purpose computer system used in the embodiments of this disclosure;

[0047] Figure 7 This is a schematic diagram of the embedded system used in the embodiments of this disclosure. Detailed Implementation

[0048] The present disclosure is described below based on embodiments, but it is not limited to these embodiments. In the detailed description of the present disclosure below, certain specific details are described in detail. Those skilled in the art will fully understand the present disclosure even without these details. To avoid obscuring the substance of the present disclosure, well-known methods, processes, and procedures are not described in detail. Furthermore, the accompanying drawings are not necessarily drawn to scale.

[0049] The two-channel voltage adjustment method provided in this disclosure is applicable to any system integrating dual-track memory, regardless of whether the dual-track memory is embedded or standalone, and regardless of the memory type, such as random access memory (RAM), static random access memory (SRAM), read-only memory (ROM), content-addressable memory (CAM), flash memory, register file, etc. Furthermore, those skilled in the art will understand that although the following embodiments describe how to adjust the two voltages of the dual-track memory based on the DVFS or AVFS controller of an on-chip system, the two-channel voltage adjustment method provided in this disclosure can be used in other scenarios as long as there is a voltage constraint relationship between the two voltages.

[0050] The terminology used in this document.

[0051] Sign-off: From module-level design to tape-out, design costs increase exponentially due to design changes during the chip design process. "Sign-off" signifies that a specific department (e.g., timing, power, or functional verification department) has committed to meeting measurable standards for completing its work. "Corner" refers to the measurable standards defined at the time of the sign-off.

[0052] System-on-a-Chip

[0053] Referring to the diagram, the on-chip bus 102 couples various components to the processing unit 101. The on-chip bus 102 is, for example, the AXI bus. The AXI bus is the most important part of the AMBA (Advanced Microcontroller Bus Architecture) 3.0 and above protocols proposed by ARM. It is an on-chip bus designed for high performance, high bandwidth, and low latency. The AIX bus separates address / control and data phases, supports unaligned data transmission, and supports burst and out-of-order transmissions, thus meeting the needs of ultra-high performance and complex on-chip system designs.

[0054] As shown in the figure, the frequency modulation and voltage regulation controller 103 and the high-speed memory 104 are coupled to the processing unit 101 via the on-chip bus 102. The frequency modulation and voltage regulation controller 103 is coupled to the clock management unit 105 and the off-chip power management circuit 211.

[0055] In some embodiments, the power management circuitry 211 may also be located internally within the system-on-chip 100. The system-on-chip 100 may also include interface circuitry (not shown) coupled to external devices off-chip. External devices may include, for example, text, audio, and video input / output devices and various other memories. The system-on-chip 100 can access these external devices via the interface circuitry. Unlike the high-speed memory 104 located on the system-on-chip, off-chip memory can have larger capacity but is slower and less expensive. In some implementations, the high-speed memory 104 may be static random access memory (SRAM), while the off-chip memory may be DRAM (dynamic random access memory) or flash memory.

[0056] The system-on-a-chip 100 embeds basic software (e.g., embedded control system 121) and application programs (e.g., application program AN). Other applications, not shown, may be stored in memory outside the system-on-a-chip 100. These applications can be copied to the high-speed memory 104 in the system-on-a-chip 100 for execution via interface circuitry, or access resources on the system-on-a-chip 100 via interface circuitry.

[0057] The frequency modulation and voltage regulation controller 103 generates a frequency modulation signal REGF and a voltage regulation signal REGV. It sends the frequency modulation signal REGF to the clock circuit management unit 105 and the voltage regulation signal REGV to the power management circuit 211. The frequency modulation and voltage regulation controller 103 is also used to send an alarm signal ALARM in abnormal conditions and provide it to the processing unit 101 so that appropriate measures can be taken.

[0058] In this embodiment, the frequency modulation and voltage regulation controller 103 can be a DVFS controller or an AVFS controller.

[0059] When the high-speed memory 104 is not a dual-track memory, all components, including the processing unit, the high-speed memory 104, and the frequency and voltage regulation controller 103, share the system power supply voltage.

[0060] Based on this, when the frequency modulation and voltage regulation controller 103 is an AVFS controller, the implementation logic of the DVFS controller 103 is as follows: The DVFS controller 103 receives the frequency configuration command and frequency modulation and voltage regulation command sent from the processing unit 101 via the on-chip bus 102. It reads multiple frequency-voltage pairs (these frequency-voltage pairs are verified frequencies and voltages that enable the system to work normally) from the frequency configuration command and stores them in the DVFS controller. At the same time, the DVFS controller 103 obtains the target frequency from the frequency modulation and voltage regulation command, compares the target frequency with each of the multiple frequency-voltage pairs, and when the frequency in a certain frequency-voltage pair matches the target frequency, it retrieves the corresponding voltage value, generates a voltage regulation signal REGV, and sends it to the power management circuit 211. The power management circuit 211 adjusts the power supply voltage VCPU of the processing unit accordingly. At the same time, the DVFS controller generates a frequency modulation signal REGF and sends it to the clock management unit 105. The clock management unit 105 generates a clock signal FCPU and provides it to the processing unit 101.

[0061] When the frequency modulation and voltage regulation controller 103 is an AVFS controller, its implementation logic is as follows: It receives a frequency configuration command and a frequency modulation and voltage regulation command from the system-on-chip 102. It reads at least one frequency from the frequency configuration command and stores it in the AVFS controller 103. Simultaneously, the AVFS controller obtains the target frequency from the frequency modulation and voltage regulation command, compares the target frequency with at least one frequency, and when a frequency matches the target frequency, calculates the voltage value based on the real-time detection data obtained from the sensor and the target frequency. It then generates a voltage regulation signal REGV based on the voltage value and sends it to the power management circuit 211. The power management circuit 211 adjusts the supply voltage VCPU provided to the processing unit accordingly. Simultaneously, the AVFS controller generates a frequency modulation signal REGF based on the target frequency and sends it to the clock management unit 105. The clock management unit 105 generates the clock signal FCPU for the processing unit 101. It should be noted that the frequencies included in the frequency configuration command should be verified to enable the system-on-chip 100 to operate normally.

[0062] However, when the high-speed memory 104 is a dual-track memory, the processing unit 101, the high-speed memory 104, the frequency and voltage regulation controller 103, and the logic devices of the dual-track memory 104 share a single system power supply voltage, while the storage array of the dual-track memory 104 uses a different power supply voltage. In this case, both circuits need to be adjusted, and during voltage adjustment, the system power supply voltage and the storage array power supply voltage must constantly meet voltage constraints. Therefore, the power management circuit 211 adjusts the system power supply voltage VCPU and the storage array power supply voltage VSTG according to the voltage regulation signal. It should be understood that in a dual-track memory system, the frequency and voltage regulation controller 103 can send one voltage regulation signal to the power management circuit 211, which indicates the adjustment of both power supply voltages, or send two voltage regulation signals, each adjusting one power supply voltage.

[0063] To achieve voltage regulation of the dual-track memory, embodiments of this disclosure provide, as follows: Figure 2 and 3 The frequency and voltage regulation controller shown. Figure 2 This is a structural diagram of a DVFS controller according to an embodiment of the present disclosure.

[0064] As shown in the figure, the voltage determination unit 203 is used to determine the first target value to which the system power supply voltage should be adjusted and the second target value to which the power supply voltage of the storage array should be adjusted. The first target value is any value within a first interval, and the arbitrary value within the first interval and the second target value conform to a preset voltage constraint relationship between the system power supply voltage and the power supply voltage of the storage array. The voltage regulation signal generation unit 202 generates a voltage regulation signal REGV1 for the system power supply voltage and a voltage regulation signal REGV2 for the power supply voltage of the storage array based on the first and second target values. These voltage regulation signals REGV1 and REGV2 are provided to the power management circuit 211, which can perform voltage regulation operations, simultaneously adjusting the system power supply voltage to Vk and the power supply voltage of the storage array to vltg_j. The frequency conversion signal generation unit 201 generates a frequency modulation signal REGF to adjust the clock frequency of the processing unit. The error handling unit 204 is used to generate an alarm signal ALARM when it detects that the target frequency does not match the frequency in any frequency voltage pair, and provides the alarm signal ALARM to the corresponding processing unit.

[0065] Further, as shown in the figure, the voltage determination unit 203 includes a register F, multiple comparators 203, a register group FV, a register group VV, and a selector 2032. Register F stores the target frequency. Register group FV stores the correspondence between frequency and voltage. Register group VV stores the voltage relationship data between the two voltages of the dual-track memory. The voltage determination unit 203 obtains the target frequency from the frequency modulation and voltage regulation command and stores it in register F. Multiple comparators 203 compare the target frequency in register F with the correspondence between frequency and voltage in register group FV. If the target frequency matches one of the frequencies, the corresponding voltage value, such as Vk, is obtained and used as the first target value. Then, Vk is compared with multiple sub-intervals [v01, v02], [v02, v03], etc., to determine the interval to which Vk belongs, such as [v0j, v0j+1]. Then, the fixed value vltg_j corresponding to the interval [v0j, v0j+1] is obtained, and this fixed value vltg_j is used as the second target value. Then, Vk and vltg_j are provided to the voltage regulation signal generation unit 202 via selector 2032. Here, k, j, and n are all integers greater than or equal to 1.

[0066] As shown in the figure, register group VV stores the voltage relationship data of the two power supply voltages of the dual-track memory, which is pre-established. This voltage relationship data represents a one-to-one correspondence between multiple sub-intervals (i.e., intervals [v01,v02], [v02,v03], etc.) that divide the value range of the power supply voltage of the logic device and multiple fixed values ​​(vltg_0, vltg_1, etc. in the figure) that can be used for the power supply voltage of the memory array, and any value in each interval and its corresponding fixed value satisfy the voltage constraint relationship between the logic device and the memory array of the dual-track memory.

[0067] Optionally, the frequency-voltage correspondence in register group FV and the voltage relationship data in register group VV are pre-stored in off-chip read-only memory (which can be hard-coded into read-only memory during hardware design) and loaded into registers when the system powers on.

[0068] Optionally, a correspondence between each register in register FV and each register in VV can be established based on the data correspondence within the register groups. In this way, when the register containing the first target value is determined, the second target value can be obtained from the register corresponding to it, thus avoiding the need to compare the first target value with the voltage relationship data range.

[0069] The above embodiments are illustrated by examples. Figure 3As shown, VDDM represents the power supply voltage of the memory array, and VDD represents the power supply voltage of the logic device. The value range of VDDM is [0.675V, 1.1V], and the value range of VDD is [0.55V, 1.05V]. The constraint relationship between VDD and VDDM is: VDD>=VDDM-300mV, VDD<=VDDM+100mV.

[0070] The voltage relationship data between VDD and VDDM can be constructed as follows: For VDDM, three fixed values ​​are set: 0.75V, 0.85V, and 1V. For VDD, three intervals are constructed that correspond one-to-one with the three fixed values: [0.55V, 0.75V] (corresponding to the VDDM fixed value of 0.75V), [0.75V, 0.85V] (corresponding to the VDDM fixed value of 0.85V), and [0.85V, 1.05V] (corresponding to the VDDM fixed value of 1V). The term "one-to-one correspondence" means that any value in each interval conforms to the voltage constraint relationship between its fixed value and the supply voltage of the logic devices and memory array of the dual-track memory.

[0071] In an exemplary embodiment, when VDD is less than 0.75V and falls within the range [0.55V, 0.75V], VDDM takes the fixed value of 0.75V corresponding to the range [0.55V, 0.75V].

[0072] In another exemplary embodiment, when VDD is in the range [0.75V, 0.85V], VDDM takes a fixed value of 0.85V corresponding to the range [0.75V, 0.85V].

[0073] In another exemplary embodiment, when VDD is in the range [0.85V, 1.05V], VDDM takes a fixed value of 1V corresponding to the range [0.85V, 1.05V].

[0074] The resulting VDD and VDDM consistently conform to the voltage constraints of the power supply voltages of the logic devices and memory arrays in the dual-track memory described above.

[0075] In the above embodiments, when VDD belongs to [0.55V, 0.75V], since VDDM is fixed at 0.75, the constraint relationship can be expressed as: 0.75V-300mV(0.45)<=VDD<=0.75V+100mV(0.85), which is undoubtedly valid; when VDD belongs to [0.75V, 0.85V], since VDDM is fixed at 0.85, the constraint relationship can be... This can be expressed as: 0.85V-300mv(0.55)<=VDD<=0.85V+100mv(0.95), which is undoubtedly valid. When VDD belongs to [0.85V, 1.05V], since VDDM is fixed at 1V, the constraint can be expressed as: 1V-300mv(0.7V)<=VDD<=1V+100mv(1.1V), which is also undoubtedly valid.

[0076] When performing a step-down operation using the VDD-VDDM method described above, for example, changing VDD from 1.05V to 0.55V, VDDM needs to be stepped down from 1V to 0.75V accordingly. Assuming the VDD / VDDM regulation rates are the same, because the voltage drop of VDDM is smaller, VDD only drops from 1.05V to 0.8V when VDDM is gradually stepped down from 1V to 0.75V. However, there is still a +0.05V margin at this point, so the voltage is further stepped down by +0.05V to reach 0.75V.

[0077] Furthermore, the construction of voltage relationship data is not limited to the above-mentioned voltage relationship data. Below, we introduce another voltage relationship data constructed based on VDD and VDDM. First, VDDM is still set to three fixed values: 0.75V, 0.85V, and 1V. Then, for VDD, three intervals are constructed corresponding to these three fixed values: [0.45V, 0.80V] (corresponding to the VDDM fixed value of 0.75V), [0.80V, 0.90V] (corresponding to the VDDM fixed value of 0.85V), and [0.90V, 1.1V] (corresponding to the VDDM fixed value of 1V). This is derived based on VDD >= VDDM - 300mV and VDD <= VDDM + 100mV. Other aspects of this voltage relationship data can be referred to the relevant description of the previous exemplary voltage relationship data above, and will not be detailed here.

[0078] It should be noted that when establishing the voltage relationship data between VDD and VDDM, you can first determine multiple intervals of VDD and then determine multiple fixed values ​​of VDDM, or first determine multiple fixed values ​​of VDDM and then determine multiple intervals of VDD.

[0079] It should be noted that dual-track memory typically comes pre-loaded with several fixed voltage values ​​(enumerated values) for the power supply voltages of several memory arrays. Therefore, the frequency and voltage regulation controller in this embodiment can use these fixed values ​​to plan the voltage relationship data. This approach has a significant advantage: when the chip signs off, it only needs to sign off at the upper and lower boundaries of the power supply voltage interval corresponding to each memory array. For interval 2, sign-off needs to be performed at the two boundary values ​​{VDD,VDDM} = {0.85V, 0.85V} and {0.85V, 0.75V}. Even if there is a deviation in the voltage adjustment rate during simultaneous VDD / VDDM voltage regulation, the sign-off voltage can still cover VDD within this interval. In other words, this method solves the problem of inability to achieve fully synchronous voltage regulation and difficulty in back-end sign-off when VDD / VDDM cannot be powered by a single source.

[0080] Figure 4 This is a structural diagram of an AVFS controller according to another embodiment of this disclosure. Figure 4 As shown, the AVFS controller 103 includes a register group for storing a frequency point table 1031, a frequency converter control unit 406, a voltage determination unit 402, a voltage regulation signal generation unit 409, a temperature sensor controller 403, a process sensor controller 404, and a voltage sensor controller 405. The frequency point table 1031 includes multiple frequencies, which are generated by the AVFS controller 103 according to frequency configuration instructions. When the frequency converter control unit 406 determines that the target frequency specified in the frequency configuration instruction matches a frequency in the frequency point table 1031, it generates a frequency modulation signal REGF.

[0081] Temperature sensor controller 403 and temperature sensor 406 are coupled to form a temperature sensor assembly; process sensor controller 404 and process sensor 407 are coupled to form a process sensor assembly; and voltage sensor controller 405 and voltage sensor 408 are coupled to form a voltage sensor assembly. Temperature sensor 406, process sensor 407, and voltage sensor 408 are located inside the system-on-chip (SoC) but outside the AVFS controller 450. Sensor controllers 403-405 acquire real-time temperature, process deviation, and real-time voltage of the SoC through temperature sensor 406, process sensor 407, and voltage sensor 408.

[0082] The voltage determination unit 402 is used to determine a first target value to which the system power supply voltage should be adjusted and a second target value to which the power supply voltage of the storage array should be adjusted. Specifically, although not shown, the voltage determination unit 402 includes a calculation unit, including, for example, a calculation unit ... Figure 2The diagram shows a register group VV for storing voltage relationship data and a selector. The calculation unit calculates the first target value to which the system supply voltage should be adjusted based on the target frequency, the system's real-time temperature, and process deviations. Alternatively, it determines the first target value based on the target frequency and real-time temperature according to predefined voltage calculation rules, then applies a voltage bias based on the process deviation. The voltage relationship data in register group VV is then retrieved using the first target value to obtain the sub-interval to which the first target value belongs and the corresponding fixed value, which is then used as the second target value. The selector outputs the first target value and the second target value to the voltage regulation signal generation unit 409.

[0083] The voltage regulation signal generation unit 409 generates a voltage regulation signal REGV1 for the system power supply voltage and a voltage regulation signal REGV2 for the memory array power supply voltage. These signals are provided to the power management circuit 211, which adjusts the two power supply voltages in parallel. After the voltage regulation operation is completed, the voltage determination unit 402 can also compare the final target value with the real-time voltage collected by the voltage sensor 408 to determine the effectiveness of the voltage regulation operation.

[0084] Based on the above embodiments, the frequency modulation and voltage regulation controller pre-establishes a correspondence between multiple value ranges of the first voltage of the dual-track memory and multiple fixed values ​​of the second voltage. Thus, when the target value of the first voltage falls within its value range, the corresponding fixed value is obtained as the target value of the second voltage, and the two voltages are adjusted in parallel. Since the adjustment rates of the two voltages are roughly the same, the constraint relationship will not be broken during the process of the two voltages reaching the target value, thereby ensuring the stability of voltage regulation.

[0085] The method for adjusting two voltages according to embodiments of this disclosure

[0086] like Figure 5 As shown, the adjustment method includes steps S01, S02 and S03.

[0087] In step S01, the first target value to which the first voltage channel needs to be adjusted is determined.

[0088] In step S02, the first target value is used to retrieve predefined voltage relationship data to determine the first sub-interval to which the first target value belongs and the first fixed value corresponding to the first sub-interval, and the first fixed value is used as the second target value to which the second voltage is adjusted.

[0089] In step S03, the first voltage and the second voltage are adjusted to the first target value and the second target value.

[0090] For step S01, the first target value can be determined in several ways. For example, the received voltage regulation command may specify the first target value, or it can be determined in other ways. Figure 2 Based on the target frequency to be adjusted, the first target value to be adjusted can be determined, or... Figure 4 The first target value is calculated based on the real-time detection data obtained from the sensor components and the target frequency to be adjusted.

[0091] For step S02, predefined voltage relationship data can be loaded into the register group of the frequency and voltage modulation controller during system-on-chip startup. This voltage relationship data can be generated in a laboratory. It consists of multiple records, which represent a one-to-one correspondence between multiple sub-intervals of the value range of the first voltage and multiple fixed values ​​that can be used for the second voltage.

[0092] Step S03 is executed by the dual-voltage power supply unit, which synchronously adjusts the two power supply voltages according to their respective target values.

[0093] Based on the target values ​​of the two voltages obtained by this method, it can be ensured that when the two voltages are adjusted from their current values ​​to their respective target values, the two voltages always satisfy the constraint relationship during the adjustment process. However, it should be noted that the two voltages should also satisfy the constraint relationship in the initial state, and when the two voltages are adjusted synchronously, the rate of change of the two voltages should be equal or approximately equal (usually expressed as the difference in the rate of change of the two voltages not exceeding a set value, which is a very small positive number). Only in this way can the phenomenon of the two voltages not satisfying the constraint relationship during the adjustment process due to the difference in the rate of change occur during parallel adjustment.

[0094] Although this adjustment method can be applied to adjust the two voltages of a dual-track memory, it should be understood that the application of this method is not limited to this. In fact, as long as there is a constraint relationship between the two voltages, the above adjustment method can be used.

[0095] Specific applications of system-on-a-chip

[0096] Figure 6 This is a schematic diagram of the structure of a general-purpose computer system used in the embodiments of this disclosure. As shown in the figure, the computer system 600 may include one or more processors 12 and a memory 14. The system-on-a-chip provided in the above embodiments can be used as the processor 12.

[0097] The memory 14 in the computer system 600 can be main memory (or simply main memory or RAM). It is used to store instruction information and / or data information represented by data signals, such as data provided by the processor 12 (e.g., calculation results), and can also be used to realize data exchange between the processor 12 and the external storage device 16 (or auxiliary memory or external memory).

[0098] In some situations, the processor 12 may need to access memory 14 to retrieve or modify data in memory 14. Because memory 14 has a relatively slow access speed, to alleviate the speed difference between the processor 12 and memory 14, the computer system 600 also includes a cache memory 18 coupled to the bus 11. The cache memory 18 is used to cache program data or message data that may be repeatedly accessed in memory 14. The cache memory 18 is implemented, for example, by a storage device of the type Static Random Access Memory (SRAM). The cache memory 18 can be a multi-level structure, such as a three-level cache structure with a level 1 cache (L1 cache), a level 2 cache (L2 cache), and a level 3 cache (L3 cache), or a cache structure with more than three levels or other types of cache structures. In some embodiments, a portion of the cache memory 18 (e.g., the level 1 cache, or the level 1 cache and the level 2 cache) can be integrated inside the processor 12 or integrated with the processor 12 on the same on-chip system.

[0099] Based on this, the processor 12 may include an instruction execution unit 121, a memory management unit 122, and other components. When executing instructions that require memory modification, the instruction execution unit 121 initiates a write access request, which specifies the data to be written into memory and the corresponding physical address. The memory management unit 122 is used to translate the virtual address specified by these instructions into the physical address mapped by that virtual address. The physical address specified by the write access request can be the same as the physical address specified by the corresponding instruction.

[0100] Information exchange between memory 14 and cache memory 18 is typically organized in blocks. In some embodiments, cache memory 18 and memory 14 may be divided into data blocks of the same spatial size, and a data block may serve as the smallest unit of data exchange between cache memory 18 and memory 14 (including one or more data of a preset length). For clarity, each data block in cache memory 18 will be referred to as a cache block (or cache line), and different cache blocks will have different cache block addresses; each data block in memory 14 will be referred to as a memory block, and different memory blocks will have different memory block addresses. Cache block addresses may include, for example, physical address tags used to locate the data blocks.

[0101] Due to space and resource limitations, cache memory 18 cannot cache all the contents of memory 14; that is, the storage capacity of cache memory 18 is usually smaller than that of memory 14, and the addresses of individual cache blocks provided by cache memory 18 cannot correspond to all the memory block addresses provided by memory 14. When processor 12 needs to access memory, it first accesses cache memory 18 via bus 11 to determine whether the content to be accessed is already stored in cache memory 18. If it is, cache memory 18 is hit, and processor 12 directly retrieves the content to be accessed from cache memory 18. If the content to be accessed by processor 12 is not in cache memory 18, processor 12 needs to access memory 14 via bus 11 to find the corresponding information in memory 14. Because the access speed of cache memory 18 is very fast, when cache memory 18 is hit, the efficiency of processor 12 can be significantly improved, thereby improving the performance and efficiency of the entire computer system 600.

[0102] In addition, the computer system 600 may also include input / output devices such as storage device 16, display device 13, audio device 19, and mouse / keyboard 15. Storage device 16 may be a hard disk, optical disk, or flash memory, etc., coupled to bus 11 via a corresponding interface, for storing and retrieving information. Display device 13 may be coupled to bus 11 via a corresponding graphics card, for displaying information according to display signals provided by bus 11.

[0103] Computer system 600 typically also includes communication device 17, thus enabling communication with networks or other devices in various ways. Communication device 17 may include, for example, one or more communication modules. As an example, communication device 17 may include a wireless communication module adapted to a specific wireless communication protocol. For instance, communication device 17 may include a WLAN module for implementing Wi-Fi™ communication conforming to the IEEE 602.11 standard; communication device 17 may also include a WWAN module for implementing wireless wide area communication conforming to cellular or other wireless wide area protocols; communication device 17 may also include communication modules employing other protocols, such as Bluetooth modules, or other custom-type communication modules; communication device 17 may also be a port for serial data transmission.

[0104] Of course, the structure of different computer systems may vary depending on the motherboard, operating system, and instruction set architecture. For example, many current computer systems have an input / output control center connected between the bus 11 and various input / output devices, and this input / output control center may be integrated into the processor 12 or independent of the processor 12.

[0105] Figure 7 This is a structural diagram of the embedded system to which this disclosure is applied. The system-on-chip provided in the above embodiments can be used as a processor 701.

[0106] Although embedded systems are highly similar to computer systems in terms of hardware structure, the characteristics of embedded system applications lead to significant differences in hardware composition and implementation compared to general-purpose computer systems.

[0107] First, to meet the requirements of embedded systems 700 in terms of speed, size and power consumption, data that needs to be stored for a long time, such as operating systems, application software and special data, usually do not use storage media with large capacity and slow speed, such as disks, but mostly use random access memory 702 or flash memory 703.

[0108] Additionally, the embedded system 700 requires an A / D (analog-to-digital) interface 705 and a serial interface 706 for measurement and control needs, which are rarely used in general-purpose computers. The A / D interface 705 primarily performs the conversion between analog and digital signals required for testing. Embedded systems 700 are frequently used in industrial production for testing. Since the microcontroller generates digital signals, these need to be converted to analog signals for testing; therefore, unlike general-purpose computers, the A / D interface 705 is required to perform the relevant conversions. Furthermore, in industry, multiple embedded systems are often connected in series to perform related functions, thus requiring a serial interface 706 for connecting multiple embedded systems, which is largely unnecessary in general-purpose computers.

[0109] Furthermore, as a basic processing unit, the embedded system 700 often needs to be networked in industrial designs, requiring a network interface 707 to connect the embedded system 700 to the network. This is generally unnecessary in general-purpose computers. In addition, depending on the specific application and scale, some embedded systems 700 require an external bus 704. With the rapid expansion of the application areas of embedded systems 700, they are becoming increasingly customized, and the types of buses used are also increasing. Furthermore, to test the internal circuitry of the embedded processor 701, boundary scan testing technology is commonly used. A debug interface 708 is employed to accommodate this testing.

[0110] With the rapid development of very large scale integrated circuits (VLSI) and semiconductor technology, some or all of the aforementioned embedded systems can be implemented on a single silicon chip, which is called a system-on-a-chip (SoC).

[0111] The commercial value of the embodiments disclosed herein

[0112] The system-on-a-chip (SoC) provided in this disclosure provides a frequency and voltage modulation controller that obtains the target voltages for two circuits based on voltage relationship data that satisfies constraints, and adjusts the two voltages accordingly to ensure voltage regulation stability. Such an SoC can be used to form computing devices for various scenarios, such as cloud servers in data centers with a large number of users; or electronic devices used in daily life, including terminal devices such as laptops and mobile phones, and certain consumer electronics products. Therefore, the SoC and the computing devices built from it, according to the embodiments of this disclosure, possess not only practical value but also commercial and economic value.

[0113] Those skilled in the art will understand that this disclosure can be implemented as a system, method, and computer program product. Therefore, this disclosure can be implemented as entirely hardware, entirely software (including firmware, resident software, and microcode), or a combination of software and hardware. Furthermore, in some embodiments, this disclosure can also be implemented as a computer program product contained in one or more computer-readable media, the computer-readable media containing computer-readable program code.

[0114] Any combination of one or more computer-readable media may be used. A computer-readable medium can be a computer-readable signal medium or a computer-readable storage medium. A computer-readable storage medium is, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of a computer-readable storage medium include: an electrical connection of one or more wires, a portable computer disk, hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage, magnetic storage, or any suitable combination thereof. In this document, a computer-readable storage medium can be any tangible medium containing or storing a program that can be used by or in conjunction with a processing unit, apparatus, or device.

[0115] Computer-readable signal media may include data signals propagated in baseband or as part of a chopped signal, carrying computer-readable program code. Such propagated data signals may take various forms, including but not limited to electromagnetic signals, optical signals, or any other suitable combination. Computer-readable signal media may also be any computer-readable medium other than computer-readable storage media, capable of transmitting, propagating, or transmitting programs for use by or in connection with an instruction system, apparatus, or device.

[0116] The program code contained on a computer-readable medium may be transmitted using any suitable medium, including but not limited to wireless, wire, optical fiber, RF, and any suitable combination thereof.

[0117] Computer program code for executing embodiments of this disclosure can be written in one or more programming languages ​​or combinations thereof. The programming languages ​​include object-oriented programming languages ​​such as JAVA and C++, and may also include conventional procedural programming languages ​​such as C. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0118] The above description is merely a preferred embodiment of this disclosure and is not intended to limit this disclosure. Various modifications and variations can be made to this disclosure by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the protection scope of this disclosure.

Claims

1. A system-on-a-chip coupled to a power management circuit, comprising: The processing unit is used to send frequency modulation and voltage regulation commands; Dual-track memory, comprising logic devices and a memory array; The frequency and voltage regulation controller includes: A voltage determination unit is configured to determine a first target value to which the power supply voltage of the logic device should be adjusted according to the frequency modulation and voltage regulation command, and to determine a second target value to which the power supply voltage of the memory array should be adjusted according to the first target value. The first target value is any value within a first interval, and any value within the first interval conforms to a voltage constraint relationship with the second target value. The frequency modulation and voltage regulation controller stores voltage relationship data, which characterizes the configuration of multiple fixed values ​​for the power supply voltage of the memory array and divides the power supply voltage range of the logic device into multiple intervals corresponding to the multiple fixed values. Any value within each interval and its corresponding fixed value conform to the voltage constraint relationship. The frequency modulation and voltage regulation controller retrieves the voltage relationship data using the first target value to determine the first interval and uses the fixed value corresponding to the first interval as the second target value. A voltage regulation signal generation unit is configured to generate a voltage regulation signal based on the first target value and the second target value and send it to the power management circuit, so that the power management circuit can synchronously adjust the power supply voltage of the logic device and the memory array according to the voltage regulation signal.

2. The system-on-a-chip according to claim 1, wherein, The voltage constraint relationship is as follows: the power supply voltage of the logic device is not greater than the sum of the power supply voltage of the memory array and the first set value, and at the same time, it is not less than the difference between the power supply voltage of the memory array and the second set value.

3. The system-on-a-chip according to claim 2, wherein, The upper boundary value of each interval is equal to the fixed value corresponding to that interval plus the second set value, and the lower boundary value is equal to the fixed value corresponding to that interval minus the first set value.

4. The system-on-a-chip according to claim 2, wherein, The upper boundary value of each interval is equal to the fixed value corresponding to that interval, or the lower boundary value of each interval is equal to the fixed value of that interval.

5. The system-on-a-chip according to claim 1, wherein, The voltage regulation signal generation unit generates two voltage regulation signals based on the first target value and the second target value, and sends them to the power management circuit.

6. The system-on-a-chip according to claim 1, wherein, During the process of synchronously adjusting the power supply voltage of the logic device and the memory array, the difference in the rate of change of the two power supply voltages does not exceed a set value.

7. The system-on-a-chip according to claim 1, wherein, When the frequency modulation and voltage regulation controller is a DVFS controller, the voltage determination unit includes: The target register is used to store the target frequency obtained from the frequency modulation and voltage modulation command; Multiple comparators are used to compare the target frequency with a pre-established correspondence between frequency and voltage, take the voltage corresponding to the target frequency as the first target value, and obtain the second target value from the voltage relationship data based on the first target value; A selector is used to output the first target value and the first target value to the voltage regulation signal generation unit; Multiple first registers are used to store the correspondence between the frequency and the voltage; Multiple second registers are used to store the voltage relationship data.

8. The system-on-a-chip according to claim 1, wherein, When the frequency modulation and voltage regulation controller is an AVFS controller, the voltage determination unit includes: Multiple third registers are used to store the voltage relationship data; The calculation unit is used to calculate the first target value based on the detected real-time temperature and process deviation, and retrieve the voltage relationship data based on the first target value to obtain the second target value; The selector is used to output the first target value and the first target value to the voltage regulation signal generation unit.

9. A method for regulating two-channel voltage, comprising: Determine the first target value to which the first voltage channel should be adjusted; The first target value is used to retrieve predefined voltage relationship data to determine the first interval to which the first target value belongs and the first fixed value corresponding to the first interval, and the first fixed value is used as the second target value to which the second voltage is to be adjusted. Adjust the first voltage and the second voltage to the first target value and the second target value, respectively. The voltage relationship data represents the multiple intervals in which the value range of the first voltage is divided and the multiple fixed values ​​used for the second voltage. Any value in each interval and its corresponding fixed value satisfy the constraint relationship between the two voltages. The first interval is one of the multiple intervals, and the first fixed value is one of the multiple fixed values.

10. The adjustment method according to claim 9, wherein, The constraint relationship includes: the first voltage is not greater than the sum of the second voltage and the first set value, and at the same time, it is not less than the difference between the second voltage and the second set value.

11. A computing device, comprising: System-on-a-chip as described in any one of claims 1 to 8; External bus; Storage devices coupled to the on-chip system via the off-chip bus; A power management circuit coupled to the system-on-chip.

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