Apparatus and method having multi-bit operation

Abstract

Disclosed are an apparatus and a method having a multi-bit operation. A multi-bit cell includes a memory storing a weight resistance corresponding to a multi-bit weight, a current source configured to apply a current to the memory to generate a weight voltage from the weight resistance, a plurality of multiplexers connected in parallel to each other and in series to the memory, each of the plurality of multiplexers configured to output one of the weight voltage and a first fixed voltage based on a multi-bit input, and a plurality of capacitors connected to the plurality of multiplexers, respectively, each of the plurality of capacitors configured to store a respective weight capacitance and generate charge data by performing an operation on an output signal and the weight capacitance.

Description

[0001] This application claims the benefit of Korean Patent Application No. 10-2021-0048025, filed on April 13, 2021, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference for all purposes. Technical Field

[0002] This disclosure relates to apparatus and methods for performing multi-bit operations. Background Technology

[0003] The operations of a neural network may include repeated multiplication and summation multiplicative summation (MAC) operations. At a node in a neural network, the following operations can be performed: the values ​​of nodes in previous layers are multiplied by the weights mapped to the corresponding nodes, the resulting products are summed, and then an appropriate activation function is applied to the sum. To perform such operations, memory access operations to load the appropriate inputs and weights at the desired time, and MAC operations to multiply and sum the loaded inputs and weights, can be repeated. Furthermore, in fields other than neural networks, operations on inputs and weights may be required. Instead of using known digital computers to handle operations on inputs and weights, methods for more efficiently handling operations on inputs and weights can utilize other hardware architectures, etc. Summary of the Invention

[0004] The present invention is provided in a brief form to introduce the choice of concepts further described in the following detailed description. This summary is not intended to identify key or essential features of the claimed subject matter, nor is it intended to help determine the scope of the claimed subject matter.

[0005] In one general aspect, a multi-bit unit includes: a memory storing weighted resistors corresponding to multi-bit weights; a current source configured to apply current to the memory to generate weighted voltages from the weighted resistors; a plurality of multiplexers connected in parallel to each other and in series with the memory, each of the plurality of multiplexers being configured to: output a signal of one of a weighted voltage and a first fixed voltage based on a multi-bit input; and a plurality of capacitors respectively connected to the plurality of multiplexers, each of the plurality of capacitors being configured to: store a corresponding weighted capacitance and generate charge data by performing operations on the output signal and the weighted capacitance.

[0006] The memory may include a plurality of resistive elements connected in series with each other, the number of which may correspond to the number of bits of a multi-bit weight, and the multi-bit unit may be configured to adjust the weight resistance by controlling the on / off state of each of the plurality of resistive elements.

[0007] Each of the plurality of multiplexers can be configured to: receive input 1 or 0; output a weighted voltage in response to receiving input 1; and output a first fixed voltage in response to receiving input 0.

[0008] In response to all multiplexers outputting a first fixed voltage, the multi-bit unit can be configured to reduce power consumption by turning off the current source.

[0009] The magnitude of the second fixed voltage sent to the terminal opposite to the terminal to which the output signal is sent can be the same as the magnitude of the first fixed voltage, and in response to receiving the first fixed voltage, each of the plurality of capacitors can be configured to receive a voltage of 0V based on the fact that the potentials at the two terminals of the capacitor are the same, and generate charge data of 0C.

[0010] The weighting resistor can be set to increase linearly with the increase of the multi-bit weight, and the magnitude of the second fixed voltage can be set such that the difference between the second fixed voltage and the weighting voltage is proportional to the multi-bit weight.

[0011] The number of capacitors may correspond to the number of bits in the multi-bit input, and each of the capacitors may be configured as a weighted capacitor that stores the value corresponding to the position of the corresponding digit in the multi-bit input.

[0012] The value of each digit constituting a multi-digit input can be input to a multiplexer connected to a capacitor in one of the multiple capacitors corresponding to the position of the digit.

[0013] Each of the plurality of capacitors may be configured to: receive an output signal at one terminal of the capacitor; receive a second fixed voltage at a terminal opposite to the one terminal; perform a subtraction operation of the second fixed voltage relative to the output signal; and multiply the difference by a weighted capacitor to generate charge data.

[0014] The multi-bit unit can be configured to output a first summation data generated by summing the charge data generated by each of the plurality of capacitors.

[0015] The memory may include a first memory and a second memory, each storing different weighted resistors. The multi-bit unit may also include a symbol multiplexer configured to determine, based on symbol input, a memory in the first and second memories from which a current will be applied. The multi-bit unit may be configured to generate a weighted voltage from the weighted resistors stored in the determined memory.

[0016] The memory may include a first memory and a second memory, the first memory storing a first weighted resistor and the second memory storing a second weighted resistor. The current source may include a first current source and a second current source, the first current source being configured to apply current to the first memory to generate a first weighted voltage and the second current source being configured to apply current to the second memory to generate a second weighted voltage. Each of the plurality of multiplexers may be configured to output any one of the first weighted voltage, the second weighted voltage, and a first fixed voltage based on a multi-bit input including a symbolic input.

[0017] A multi-bit arithmetic device may include a plurality of multi-bit units, wherein the multi-bit arithmetic device may be configured to output a second summation data generated by summing a first summation data from each of the plurality of multi-bit units.

[0018] The multi-bit arithmetic device may include a converter configured to convert a second summation data, which is analog data, into digital data, wherein the converter may include a comparator, a plurality of reference voltage units, and successive approximation register (SAR) logic.

[0019] In another general aspect, a method for performing multi-bit operations includes: applying a current to a memory storing weighted resistors corresponding to multi-bit weights to generate weighted voltages from the weighted resistors; receiving multi-bit inputs for a plurality of capacitors, each capacitor storing a corresponding weighted capacitance; outputting a signal of either the weighted voltage or a first fixed voltage to each of the plurality of capacitors based on the multi-bit inputs; and generating charge data stored in each of the plurality of capacitors by performing operations on the output signals and the weighted capacitances.

[0020] The method may include: outputting first summation data generated by summing charge data stored in each of the plurality of capacitors.

[0021] The method may include: performing the step of outputting first summation data at each of a plurality of multi-bit cells; and outputting second summation data generated by summing the first summation data output from each of the plurality of multi-bit cells.

[0022] The method may include converting a second summation data, which is used as analog data, into digital data.

[0023] In one general aspect, one or more embodiments include a non-transitory computer-readable storage medium storing instructions that, when executed by a processor, configure the processor to perform any one, any combination, or all of the operations and methods described herein.

[0024] In another general aspect, a multi-bit unit includes: a memory storing weighted resistors corresponding to multi-bit weights, wherein a weighted voltage is generated in response to a current being applied to the memory; and a plurality of capacitors, each configured to store a corresponding weighted capacitance, and to generate charge data by performing operations on either the weighted voltage and a first fixed voltage and the weighted capacitance.

[0025] The multi-bit unit may include: a plurality of multiplexers connected in parallel and in series with a memory, each of the plurality of multiplexers being configured based on either a multi-bit input-output weighted voltage or a first fixed voltage.

[0026] The memory may include multiple resistive elements, and the number of resistive elements is equal to the maximum number of bits in the multi-bit weight.

[0027] The multi-bit unit can be configured to linearly adjust the weighting resistor by controlling the on / off state of the resistive elements of the memory in response to changes in the multi-bit weights.

[0028] The multi-bit unit can be configured to shut off the current source in response to a multi-bit input being 0.

[0029] Other features and aspects will become clear from the following detailed description, drawings, and claims. Attached Figure Description

[0030] Figure 1 A neural network node model is shown according to one or more embodiments;

[0031] Figure 2 A neural network according to one or more embodiments is shown;

[0032] Figure 3A and Figure 3B It is a diagram used to describe a multi-bit computing device according to one or more embodiments;

[0033] Figure 4 This is a block diagram illustrating the configuration of a multi-bit unit according to one or more embodiments;

[0034] Figure 5 It is a circuit diagram of a multi-bit unit according to one or more embodiments;

[0035] Figure 6 It is a circuit diagram of a memory according to one or more embodiments;

[0036] Figure 7 It is a circuit diagram of a multi-bit unit in which a first fixed voltage is output from all multiplexers according to one or more embodiments;

[0037] Figure 8It is a circuit diagram of a multi-bit cell according to one or more embodiments in which all capacitors store the same weighted capacitance;

[0038] Figure 9 It is a circuit diagram of a multi-bit unit including multiple memories according to one or more embodiments;

[0039] Figure 10 It is a circuit diagram of a multi-bit unit including multiple memories according to one or more embodiments;

[0040] Figure 11 This is a flowchart illustrating an operation method of a multi-bit unit according to one or more embodiments;

[0041] Figure 12 This is a block diagram illustrating the configuration of a multi-bit computing device according to one or more embodiments;

[0042] Figure 13 It is a circuit diagram of a multi-bit arithmetic device according to one or more embodiments;

[0043] Figure 14 It is a graph showing the relationship between the time period for multi-bit operations and the time period for digital conversion according to one or more embodiments;

[0044] Figure 15 This is a flowchart illustrating a method of operating a multi-bit computing device according to one or more embodiments;

[0045] Figure 16 This is a block diagram illustrating the configuration of a multi-bit computing device array according to one or more embodiments; and

[0046] Figure 17 This is a block diagram illustrating an electronic system according to one or more embodiments.

[0047] Throughout the accompanying drawings and detailed embodiments, unless otherwise described or provided, the same reference numerals denote the same or similar elements. The drawings may not be to scale, and for clarity, illustration, and convenience, the relative dimensions, scale, and depiction of elements in the drawings may be exaggerated. Detailed Implementation

[0048] The following detailed embodiments are provided to aid the reader in gaining a comprehensive understanding of the methods, apparatus, and / or systems described herein. However, various changes, modifications, and equivalents of the methods, apparatus, and / or systems described herein will become apparent upon understanding this disclosure. For example, the order of operations described herein is merely illustrative and is not limited to the order set forth herein, but may be changed as will become clear upon understanding this disclosure, except for operations that must occur in a specific order. Furthermore, for clarity and brevity, descriptions of features known in the art upon understanding this disclosure may be omitted.

[0049] Referring now to the embodiments, examples of which are shown in the accompanying drawings, wherein the same reference numerals always denote the same elements. In this respect, one or more embodiments may have different forms and should not be construed as limited to the description set forth herein. Therefore, the embodiments are described below only by reference to the accompanying drawings to explain various aspects. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. Expressions such as “at least one of…” following a column of elements modify the entire column of elements, rather than a single element within the column.

[0050] The terminology used herein is for the purpose of describing particular examples only and is not intended to limit disclosure. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. As used herein, the term “and / or” includes any one and any combination of any two or more of the associated listed items. As used herein, the terms “comprising,” “including,” and “having” indicate the presence of the stated features, quantities, operations, elements, components, and / or combinations thereof, but do not exclude the presence or addition of one or more other features, quantities, operations, elements, components, and / or combinations thereof. The use of the term “may” herein with respect to examples or embodiments (e.g., regarding what an example or embodiment may include or implement) indicates the presence of at least one example or embodiment that includes or implements such features, while all examples are not limited thereto.

[0051] Throughout this specification, it will be understood that when a component or element is referred to as being "on," "connected to," or "joined to" another component or element, it may be directly on, directly connected to, or joined to the other component or element, or there may be one or more intermediate elements in between. Conversely, when a component or element is referred to as being "directly on," "directly connected to," or "directly joined to" another component or element, there are no intermediate components or elements. Similarly, expressions such as "between" and "immediately between," as well as "adjacent to" and "closely adjacent to," may also be interpreted as described above.

[0052] Although the terms "first" or "second" are used to explain various components, assemblies, regions, layers, or parts, the components, assemblies, regions, layers, or parts are not limited to the terms used. These terms should only be used to distinguish one component, assembly, region, layer, or part from another component, assembly, region, layer, or part. For example, within the scope of the claims of the concept of this disclosure, the "first" component, "first" assembly, "first" region, "first" layer, or "first" part referred to in the examples described herein may also be referred to as a "second" component, "second" assembly, "second" region, "second" layer, or "second" part, or similarly, a "second" component, "second" assembly, "second" region, "second" layer, or "second" part may be referred to as a "first" component, "first" assembly, "first" region, "first" layer, or "first" part.

[0053] It should be understood that the scope of the embodiments is not limited to the description of the specific embodiments below, and that what can be readily derived by those skilled in the art falls within the scope of the embodiments. Exemplary embodiments will now be described in detail with reference to the accompanying drawings.

[0054] Figure 1 A neural network node model according to one or more embodiments is shown.

[0055] Various attempts have been made to develop computing devices for efficiently processing large amounts of information by simulating biological neurons or biological neural networks composed of interconnected biological neurons. The neural network node model 11 can be an example of neuromorphic operations performed by a hardware computing device or a hardware computing processor. The neural network node model 11 may include: a multiplication operation that multiplies information from multiple neurons with synaptic weights; a summation operation (Σ) that sums the products of the multiplication operations (w0x0, w1x1, and w2x2); and an operation that applies a feature function b and an activation function f to the result of the summation operation. The results of the neuromorphic operations can be provided by performing these operations. Here, the values ​​x0, x1, x2, ... can correspond to axon values, and the values ​​w0, w1, w2, ... can correspond to synaptic weights. Although the nodes, values, and weights of the neural network node model 11 may be referred to as “neurons,” “axon values,” and “synaptic weights,” respectively, such designations are not intended to impose any relation on how the neural network architecture is computationally mapped or thereby intuitively identified as how information operates in human neurons. In other words, the terminology refers only to the technical terms for nodes, values, and weights in the hardware implementation of the neural network node model 11.

[0056] Figure 2 A neural network (e.g., neural network 20) ​​according to one or more embodiments is shown.

[0057] Figure 2An example of a neural network (i.e., neural network 20, which comprises a neural network of nodes connected to each other) is shown. Neural network 20 may correspond to an example of a deep neural network (DNN). For ease of description, neural network 20 is shown as comprising two hidden layers, but may comprise a variety of numbers of hidden layers. Furthermore, although... Figure 2 The neural network 20 is shown to include a separate input layer 21 for receiving input data, but the input data can be directly fed into the hidden layer.

[0058] In neural network 20, nodes in layers other than the output layer are connected to nodes in the next layer via links used to transmit output signals. Through these links, the output of an activation function, weighted for the inputs of nodes included in previous layers, can be input to the node. The weighted input is the product of the node's input (node ​​value) and its weights; the input corresponds to the axon value, and the weights correspond to the synaptic weights. The weights can be referred to as parameters of neural network 20. Activation functions can include sigmoid functions, hyperbolic tangent functions, and modified linear unit (ReLU) functions, and nonlinearity can be introduced into neural network 20 through activation functions.

[0059] The output of a node 22 included in neural network 20 can be represented by the following equation 1.

[0060] Equation 1:

[0061]

[0062] Equation 1 can represent the output value y of the i-th node 22 in any layer for m input values. i Here, x j w can represent the output value of the j-th node in the previous layer. j,i This can represent the weights corresponding to the output value of node j and the weights of node i in the current layer. f() can represent the activation function. As shown in Equation 1, it will be related to x... j The corresponding input value and w j,i The sum of the products of the corresponding weights can be applied to the activation function. In other words, it applies the appropriate input value x at the desired time. j With weight w j,i The operation of multiplying and summing the products (MAC operation) can be repeated. In addition to this purpose, there are various application areas for performing MAC operations, for which multi-bit computing devices capable of processing MAC operations in the analog domain can be used.

[0063] Figure 3A and Figure 3B It is a diagram used to describe a multi-bit computing device according to one or more embodiments.

[0064] Figure 3A This is a diagram illustrating the architecture of the multi-bit computing device 30 according to an embodiment. Figure 3B It shows that it will include what is to be passed Figure 3A A diagram illustrating the neural network operations performed by the multi-bit computing device 30.

[0065] Reference Figure 3A The multi-bit arithmetic device 30 may include a plurality of multi-bit units connected in parallel and a power source (e.g., a voltage source or a current source) for applying voltage or current to the multi-bit units. Figure 3A Only those used for description are shown. Figure 3B The neural network has several components, which will be referred to below. Figure 12 The description may include other components in the multi-bit computing device 30.

[0066] A multi-bit unit is included in the multi-bit arithmetic device 30 and is a unit circuit for receiving multi-bit inputs. The number of multi-bit units connected in parallel is not particularly limited, but can be, for example, 2. n (n is a natural number), and in the following text, for ease of description, the structure of three multi-bit units connected in parallel will be used as an example.

[0067] Reference Figure 3B This illustrates a neural network with three nodes in the first layer and two nodes in the second layer. The first layer can be... Figure 2 One of the input layer and hidden layer. A node in the second layer receives the product of the output value of the first layer and its weights, takes the result obtained by inputting the product into an activation function as its node value, and provides this node value as input to the next layer. Specifically, for example, as shown in Equation 2 below, in the first node a1 of the second layer, three multiplication operations and an addition operation of the sum of the accumulated products can be performed, each multiplication operation multiplying the output value of the first layer by the weight corresponding to each link. Here, for ease of description, the description of the activation function will be omitted. In Equation 2, a1 can represent the output value of the first node of the second layer.

[0068] Equation 2:

[0069] a1=X1·W 11 +X2·W 21 +X3·W 31

[0070] Figure 3A The multi-bit arithmetic device 30 shown is a device that can be used to perform calculations in Equation 2. (Refer to...) Figure 3A The first to third multi-bit units can have different resistance values ​​for the power supply. The first multi-bit unit can correspond to the first node of the first layer, and similarly, the second and third multi-bit units can correspond to the second and third nodes of the first layer, respectively.

[0071] The resistance value of a multi-bit cell relative to the power supply can be determined by the inputs X1, X2, and X3 applied to the corresponding multi-bit cell and the weight W. 11 W 21 and W 31 The inputs and weights can be multi-bit. Here, input "X1" represents the output or node value of the first node (in the first layer) and is the input applied to the first multi-bit unit. Similarly, inputs "X2" and "X3" represent the output or node values ​​of the second and third nodes, respectively, and are the inputs applied to the second and third multi-bit units, respectively. The weights "W" are determined by... 11 In the diagram, the "1" on the left represents the first node of the first layer, and the "1" on the right represents the first node of the second layer. The weight "W"... 11 " represents the weight of the link between the first node of the first layer and the first node of the second layer, and is applied to the first multi-bit unit. Similarly, the weight "W" 21 "and weight "W 31 "" indicates the weights applied to the second and third multi-bit units respectively.

[0072] Figure 4 This is a block diagram illustrating the configuration of a multi-bit unit (e.g., multi-bit unit 100) according to one or more embodiments.

[0073] Reference Figure 4 The multi-bit unit 100 may include a memory 110, a current source 120, multiple multiplexers 130, and multiple capacitors 140. Figure 4 The multi-bit unit 100 shown includes components relevant to this embodiment. Therefore, those skilled in the art will understand upon understanding this disclosure that, in non-limiting examples, the multi-bit unit 100 may also include components other than… Figure 4 Other general components besides those shown in the diagram.

[0074] Memory 110 can store multi-bit weights in the form of resistors. The multi-bit weights stored in memory 110 in the form of resistors are called weighting resistors. When the multi-bit weight is 3 and the resistor corresponding to multi-bit weight 3 is 12kΩ, memory 110 can store multi-bit weight 3 in the form of a 12kΩ weighting resistor. For example, memory 110 can be a non-volatile memory and can correspond to resistive random access memory (ReRAM), phase-change memory (PCM), magnetic RAM (MRAM), etc. However, the type of memory 110 described above is merely exemplary and can be any type of memory capable of storing resistance information.

[0075] Current source 120 can apply current to memory 110. Current source 120 can apply a constant current to memory 110 regardless of the resistance or voltage. For example, current source 120 can apply a DC bias current (e.g., I0) that sets the operating point of multi-bit cell 100. BIAS Although current source 120 applies a current of the same magnitude to memory 110, the voltage of memory 110 can vary depending on the resistance of memory 110. When current source 120 applies current to memory 110, a weighted voltage can be generated from the weighted resistor stored in memory 110. According to Ohm's law, a weighted voltage is generated when the weighted resistor is multiplied by the current. (Refer to the following...) Figure 5 A non-limiting example of weighted voltages is described in more detail.

[0076] Multi-bit unit 100 can receive multi-bit inputs. Unlike a 1-bit input, which is represented only by 1 or 0, a multi-bit input can include multiple inputs. For example, a multi-bit input can consist of the value representing each digit of the multi-bit input. When the multi-bit input is a 3-bit input, it can be represented, for example, as 3'b101, where 3'b101 is represented by the value corresponding to 2... 2 The "1" at the position corresponds to 2 1 The "0" at the position and the corresponding 2 0 The position is composed of "1"s. In this case, "1", "0" and "1" can correspond to the values ​​of the individual inputs included in the multi-bit input. The number of bits in the multi-bit weight and the number of bits in the multi-bit input can be equal to each other.

[0077] Multiple multiplexers 130 may be connected in series to memory 110 to receive a weighted voltage and a fixed voltage via another line. The fixed voltage may be a voltage of constant magnitude applied to multiplexer 131. Furthermore, multiplexer 131 may receive one of multiple inputs constituting a multi-bit input. Multiplexer 131 may output one of a weighted voltage and a fixed voltage based on the received input. For example, multiplexer 131 may output a weighted voltage in response to receiving a 1 and output a fixed voltage in response to receiving a 0. Reference will be made below. Figure 5 A non-limiting example thereof is described in more detail. Optionally, multiplexer 131 may receive multiple fixed voltages and output a weighted voltage and one of the multiple fixed voltages based on the multiple inputs. Multiplexer 131 may output a signal and may send that signal to capacitor 141.

[0078] Multiple multiplexers 130 can be connected in parallel with each other. Multiple multiplexers 130 can be connected in series with memory 110 and can receive the same signal (weighted voltage or fixed voltage). Multiple multiplexers 130 can receive multi-bit inputs and output one of a weighted voltage and a fixed voltage based on the multi-bit inputs. The signal output from the weighted voltage and the fixed voltage by each multiplexer can be determined based on the received input value. For example, when the multi-bit input is 3'b101, the signal received corresponds to 2... 2 The multiplexer of the "1" at position and the received number corresponding to 2 0 The multiplexer of the "1" at position 2 can output the same signal and receive the signal corresponding to position 2. 1 The multiplexer of the "0" at the position can output different signals.

[0079] Capacitor 141 can be connected to multiplexer 131 to receive signals output from multiplexer 131. Capacitor 141 can store weighted capacitance. Capacitor 141 can generate zero-charge data by performing operations on the received signal and the weighted capacitance. (Refer to...) Figure 5 Describe the operation of capacitor 141 in detail.

[0080] Multiple capacitors 140 may be connected in parallel with each other. Each of the multiple capacitors 140 may be connected in series with a corresponding multiplexer 130. Thus, a capacitor 141 may be connected to a multiplexer 131. Each of the multiple capacitors 140 may store a corresponding weighted capacitance. The weighted capacitances may be different from each other, may be equal to each other, or only some of the weighted capacitances may be different from each other.

[0081] Figure 5 It is a circuit diagram of a multi-bit unit (e.g., multi-bit unit 100) according to one or more embodiments.

[0082] Reference Figure 5 The multi-bit unit 100 may include a memory 110, a current source 120, multiple multiplexers (MUX) 130, and multiple capacitors (e.g., CAP0 to CAP2) 140. The multi-bit unit 100 may receive multiple inputs 150 (e.g., IN[0]-IN[2] and INB[0]-INB[2]), and a single input 151 included in the multiple inputs 150 may be input to the multiplexer 131.

[0083] exist Figure 5 The circuit diagram only shows components relevant to this embodiment. Therefore, it will be clear to those skilled in the art that, in addition to... Figure 5 In addition to the components shown, other common components may also be included in the circuit diagram.

[0084] Reference Figure 5 The circuit diagram, weighted voltage (e.g., V) W) and a first fixed voltage (e.g., V) A The input can be fed into multiplexer 131. Furthermore, multiplexer 131 can receive a single input 151 that constitutes a multi-bit input 150. The single input 151 received by multiplexer 131 can be used as a selector signal (SEL) with respect to multiplexer 131 to cause one of the weighted voltage and the first fixed voltage to be output from multiplexer 131.

[0085] A signal output from multiplexer 131 can be sent to capacitor 141. The signal output from multiplexer 131 can be sent to the left terminal of capacitor 141, and a second fixed voltage (e.g., V) is applied. B The signal can be sent to the right terminal of capacitor 141. Therefore, a voltage having the potential difference between the signal output from multiplexer 131 and the second fixed voltage can be applied to capacitor 141. The method of performing operations on multi-bit input 150 and multi-bit weights will be described in detail below.

[0086] Memory 110 can store weight resistors corresponding to multiple weights. The value of the weight resistor can vary according to the value of the corresponding multiple weight. The weight resistor can be set to increase linearly as the corresponding multiple weight increases. For example, like an arithmetic sequence, the weight resistor can increase by a constant difference as the corresponding multiple weight increases by a constant difference. Table 1 shows an example of a weight resistor with 3 weights.

[0087] Table 1:

[0088] -7 7 -5 8 -3 9 -1 10 1 11 3 12 5 13 7 14

[0089] Multi-bit cell 100 can generate a weighted voltage from a weighted resistor by applying current to memory 110 using current source 120. When current is applied to the weighted resistor stored in memory 110, the current is multiplied by the weighted resistor according to Ohm's law, resulting in a weighted voltage. Because current source 120 outputs a constant current, the weighted voltage is proportional to the weighted resistor. Table 2 shows an example of a weighted voltage for a 3-bit weight.

[0090] Table 2:

[0091]

[0092]

[0093] The multi-bit unit 100 can receive the multi-bit input 150 by using multiple capacitors 140 that receive the corresponding 1-bit input 151. The number and weighting of the capacitors 140 can be set to enable the reception of the multi-bit input 150.

[0094] For example, the multi-bit unit 100 may include a plurality of capacitors 141, such that the number corresponds to the number of bits in the multi-bit input 150, and each capacitor 141 may store a weighted capacitance corresponding to the position of each digit in the multi-bit input 150. When the multi-bit input 150 is 3 bits, the multi-bit input 150 may be represented as 3'b000 to 3'b111, and the factor multiplied by the digits of the multi-bit input 150 may be 2. 0 2 1 and 2 2 In this case, the multi-bit unit 100 may include three capacitors 140, and each capacitor 140 may store 2 0 Weighted capacitor of multiple times the unit capacitance, 2 1 The weighted capacitance of the unit capacitor and 2 2 The weighted capacitance is times that of the unit capacitance. (Refer to...) Figure 5 Multiple inputs 150 (3 bits) are applied, and three capacitors 140 store weighted capacitances of 1x, 2x, and 4x the unit capacitance, respectively.

[0095] Capacitor 140 can indirectly receive multi-bit input 150 via multiplexer 130. As described above, multi-bit input 150 can include multiple inputs, and each input can be received by a multiplexer connected to a corresponding capacitor. The value of each digit constituting multi-bit input 150 can be input to a multiplexer connected to the capacitor corresponding to the position of that digit. For example, when multi-bit input 150 is 3-bit, the AND of multi-bit input 150 with 2... 0 The corresponding numerical value can be indirectly input into capacitor CAP0, which stores a capacitance weight of 1 unit capacitance. Multiple inputs of 150 and 2... 1 The corresponding numerical value can be indirectly input into capacitor CAP1, which stores a capacitance weight of twice the unit capacitance. Multiple inputs of 150 AND 2... 2 The corresponding digital value can be indirectly input to capacitor CAP2, which stores a capacitance weight of 4 times the unit capacitance. The value of each position of the multi-bit input 150 can be directly input to the multiplexer, and the signal output from the multiplexer can be sent to the capacitor based on the input, so the value of each position can be indirectly input to the capacitor.

[0096] When the multi-bit input 150 is 3'b110 (i.e., 6), a "1" can be input to the multiplexer corresponding to capacitor CAP2, a "1" can be input to the multiplexer corresponding to capacitor CAP1, and a "0" can be input to the multiplexer corresponding to capacitor CAP0. Table 3 shows examples of values ​​input to the corresponding multiplexers based on the value of the multi-bit input 150 (i.e., 3 bits).

[0097] Table 3:

[0098]

[0099]

[0100] As described above, each of the plurality of multiplexers 130 can receive an input of 1 or 0. Among the plurality of multiplexers 130, a multiplexer receiving an input "1" can output a weighted voltage, and a multiplexer receiving an input "0" can output a first fixed voltage. However, this is only an example, and the multiplexer can be modified and implemented in various ways such that, for example, the multiplexer is configured to operate in the opposite manner to the example, the multiplexer receives different types of inputs, or the multiplexer determines the signal to be output based on multiple inputs. Table 4 shows an example of a signal sent from multiplexer 130 to a corresponding capacitor according to the example in Table 3.

[0101] Table 4:

[0102]

[0103]

[0104] One terminal of capacitor 141 can receive a signal output from multiplexer 131, and the opposite terminal of capacitor 141 can receive a second fixed voltage. Capacitor 141 can perform a subtraction operation of the second fixed voltage relative to the signal output from multiplexer 131. Therefore, capacitor 141 can perform a subtraction operation of the second fixed voltage relative to a weighted voltage or a first fixed voltage. The difference can be the potential difference between the two terminals of capacitor 141 and can correspond to the voltage applied to capacitor 141. For example, when the first fixed voltage is set to have the same value as the second fixed voltage, the difference between the second fixed voltage and the first fixed voltage can correspond to 0V. However, the first fixed voltage and the second fixed voltage can be set to different values ​​depending on the structure and configuration of the multi-bit unit 100, in which case the difference can correspond to a value other than 0V.

[0105] The magnitude of the second fixed voltage can be set such that the difference between it and the weighted voltage is proportional to the weights. In the example in Table 5, the second fixed voltage can be 525mV, which is the average of the weighted voltages. Table 5 summarizes the relationship between the weighted voltage, the second fixed voltage, and the difference between the second fixed voltage and the weighted voltage.

[0106] Table 5:

[0107]

[0108]

[0109] As shown in Table 5, the magnitude of the second fixed voltage can be set such that the difference is proportional to the weighting of the multiple digits. In the example in Table 5, the first fixed voltage can also be set to be the same as the second fixed voltage.

[0110] Table 6 shows the multi-bit input 150, multi-bit weight, weighted voltage based on the multi-bit weight, and the difference between the second fixed voltage and the weighted voltage for each of the multiple multi-bit units 100 according to the example in Table 2.

[0111] Table 6:

[0112] 1 4 -1 500 -25 2 4 -1 500 -25 3 2 1 550 25 4 7 7 700 175 5 2 3 600 75 6 1 -1 500 -25 7 0 3 600 75 8 0 -5 400 -125 9 1 1 550 25 10 5 7 700 175 11 0 -1 500 -25 12 4 -5 400 -125 13 1 3 600 75 14 1 7 700 175 15 6 -7 350 -175 16 3 3 600 75

[0113] The values ​​of the multi-bit inputs 150 and multi-bit weights shown in Table 6 are based on arbitrary settings of the 3-bit inputs and can be modified in various ways. Each row in Table 6 corresponds to one multi-bit unit 100. Therefore, Table 6 shows a configuration of 16 multi-bit units 100.

[0114] The first fixed voltage can be set to be equal to the second fixed voltage. Therefore, among the plurality of capacitors 140, the capacitor receiving the first fixed voltage can have the same potential at its two terminals, thus having a potential difference of 0V. In this case, the capacitor can receive a voltage of 0V and generate 0C of charge data.

[0115] Table 7 shows the difference obtained by each capacitor in each of the multi-bit units 100 (i.e., the potential difference between the two terminals of each capacitor according to the example in the table above).

[0116] Table 7:

[0117]

[0118] Capacitor 141 generates charge data by multiplying the difference by the weighted capacitance. In other words, capacitor 141 generates charge data by multiplying the weighted capacitance by the difference (voltage) according to the equation Q = C × V.

[0119] Table 8 shows the charge data generated for each capacitor according to the example in Table 7.

[0120] Table 8:

[0121]

[0122]

[0123] The multi-bit unit 100 can output a first summed data generated by summing the charge data generated by each of the plurality of capacitors 140. In the example of Table 8, the multi-bit unit 100 corresponding to row 1 can output a first summed data of -100mC, and the multi-bit unit 100 corresponding to row 4 can output a first summed data of 1225mC. After the charge data is summed, the first summed data of each row can be converted into a digital signal. The following will refer to... Figure 12 Describe a non-restrictive example.

[0124] Simultaneously, the operation method of the multi-bit unit 100 can be verified by comparing the result of multiplying the multi-bit input 150 and the multi-bit weight with the first summed data. The product of the multi-bit input 150 and the multi-bit weight in row 1 is -4, and the product of the multi-bit input 150 and the multi-bit weight in row 4 is 49. Referring to Table 5, it can be confirmed that the difference between the second fixed voltage and the weighted voltage is 25 times the multi-bit weight. Here, since the first summed data in row 1 is (-4 × 25) mC, and the first summed data in row 4 is (49 × 25) mC, it is confirmed that the first summed data corresponds to the result of the above multiplication.

[0125] Therefore, the multi-bit unit 100 can perform multi-bit operations by receiving multi-bit inputs 150 via multiple capacitors 140 storing corresponding capacitance weights and converting the multi-bit weights into voltage weights, instead of directly multiplying the multi-bit inputs 150 with the multi-bit weights.

[0126] Figure 6 It is a circuit diagram of a memory (e.g., memory 110) according to one or more embodiments.

[0127] Reference Figure 6 The memory 110 may include a plurality of resistive elements 111.

[0128] The memory 110 may include a number of resistive elements 111, such that the number corresponds to the number of bits in the multi-bit weight. For example, when the multi-bit weight is N bits, the memory 110 may include (2 N -1) resistive element 111. In Figure 6 In this embodiment, the multi-bit weight can be 3 bits, and the memory 110 may include (2 3 -1) seven (i.e., seven) resistive elements 111.

[0129] Resistive elements 111 can be connected in series with each other. Because resistive element 111a can indicate 0 in the on state and indicate a specific resistance value in the off state, the memory 110 can be used by using two elements connected in series. N -1 resistive element 111 is configured to have 2 NEach resistor value. The multi-bit unit 100 can adjust the weighted resistor by controlling the on / off state of each resistive element 111. The multi-bit unit 100 can determine the on / off state of each resistive element using the signal WR_SEL, and can apply current or voltage to each resistive element via signal lines “sub-bit line [0] to sub-bit line [7]”. For example, the application of current or voltage via signal lines “sub-bit line [0] to sub-bit line [7]” can be controlled by the enable signal MAC_EN.

[0130] For example, when the correspondence between multiple weights and weighted resistors is as shown in the examples in Table 1, one resistive element can store a 7kΩ resistance, while other resistive elements can store a 1kΩ resistance, or each resistive element can store a 1kΩ or 2kΩ resistance. By controlling the on / off state of each series-connected resistive element 111, the multiple-bit unit 100 can store weighted resistors of any one of 7kΩ, 8kΩ, ..., 13kΩ, and 14kΩ in the memory 110. Therefore, weighted resistors from 7kΩ to 14kΩ can be indicated by the memory 110 in units of 1kΩ.

[0131] The resistive element 111a may correspond to a magnetic tunnel junction (MTJ) or a magnetoresistive random access memory (MRAM). However, this is merely an example, and the resistive element may correspond to any device that stores resistance and is controlled by a transistor, without limitation.

[0132] Figure 7 It is a circuit diagram of a multi-bit unit (e.g., multi-bit unit 100) according to one or more embodiments, in which a first fixed voltage is output from all multiplexers (e.g., multiplexer 130).

[0133] Reference Figure 7 When the weighted voltage is not used in the multi-bit cell 100, the current source 120 can be disabled, and only the first fixed voltage can be applied to the multiplexer 130.

[0134] For example, when the multi-bit input 150 is 0, no weighting voltage is used in the multi-bit unit 100, and only the first fixed voltage can be applied to the multiplexer 130. The case of the multi-bit input 150 being 0 means that all the individual inputs 151 constituting the multi-bit input 150 are 0. When the multi-bit input 150 is 3-bit, the multi-bit input 150 "0" can be represented as 3'b000. Input 0 can be received by all multiplexers 130. Multiplexers 130 can output the first fixed voltage in response to input 0. Because the weighting voltage is not sent to the capacitor 140, the current source 120 used to generate the weighting voltage does not need to operate. Accordingly, the multi-bit unit 100 can reduce its power consumption by disabling the current source 120. For example, the multi-bit unit 100 can control the current applied from the current source 120 to 0uA by using the signal I_EN, which serves as an enable signal for controlling the current source 120.

[0135] However, in all cases except when the multi-bit input 150 is 0, all multiplexers 130 can output a first fixed voltage according to the structure and configuration of the multi-bit cell 100. When all multiplexers 130 output the first fixed voltage, the current source 120 can be turned off and the power consumption of the multi-bit cell 100 can be reduced because no weighting voltage is used in the multi-bit cell 100.

[0136] Figure 8 It is a circuit diagram of a multi-bit cell (e.g., multi-bit cell 100) according to one or more embodiments in which all capacitors (e.g., capacitor 140) store the same weighted capacitance.

[0137] Reference Figure 8 All capacitors 140 can store a weighted capacitance equal to the unit capacitance.

[0138] The multi-bit unit 100 may include a number of capacitors 140 such that the number corresponds to the number of bits in the multi-bit input 150. For example, the multi-bit unit 100 may include (2) capacitors for the N-bit multi-bit input 150. N -1) capacitors 140. Here, all the weighted capacitance stored in capacitors 140 can be equal to the unit capacitance. (2) N -1) One capacitor 140 can receive 0 to 2 N The value of -1 can be entered as 150.

[0139] exist Figure 8 In the structure of the embodiment, the multi-bit unit 100 can receive various forms of input. For example, the multi-bit unit 100 can receive various forms of input (such as thermometer code input, binary input, or ternary input).

[0140] Figure 9It is a circuit diagram of a multi-bit unit (e.g., multi-bit unit 100) including a plurality of memories according to one or more embodiments.

[0141] Reference Figure 9 The multi-bit unit 100 may include multiple memories 110 (e.g., a first memory 110a and a second memory 110b) that store resistors with different weights, and the multi-bit unit 100 may also include a symbol multiplexer (MUX) 132 that receives symbol input 152.

[0142] The weighting resistors of the first memory 110a and the second memory 110b can be set differently (e.g., set to have the same absolute value but different signs or have different values ​​but the same sign). A symbol multiplexer 132 can be connected to the first memory 110a and the second memory 110b. In addition to the multi-bit input 150, the multi-bit unit 100 can also receive a symbol input 152 via the symbol multiplexer 132. Based on the symbol input 152, the symbol multiplexer 132 can determine one of the memories 110 in the first memory 110a and the second memory 110b to be energized from the current source 120. The symbol multiplexer 132 can establish a line to connect the determined memory 110 to the current source 120 to apply current to the determined memory 110. The multi-bit unit 100 can generate a weighting voltage from the weighting resistors stored in the memory 110 determined based on the symbol input 152.

[0143] The multi-bit unit 100 may include multiple memories 110 storing resistors with different weights in order to receive more diverse inputs and perform operations on various weights. When the resistor weight (e.g., the weight corresponding to the weighted resistor) of the first memory 110a is positive and the resistor weight of the second memory 110b is negative, the multi-bit unit 100 may receive signed integer inputs and perform operations on them.

[0144] Figure 10 It is a circuit diagram of a multi-bit unit (e.g., multi-bit unit 100) including a plurality of memories according to one or more embodiments.

[0145] Reference Figure 10 The memory 110 may include a first memory 110a and a second memory 110b storing resistors with different weights, and the current source 120 may include a first current source 120a that applies current to the first memory 110a and a second current source 120b that applies current to the second memory 110b. The multi-bit unit 100 may receive a multi-bit input 150 including a symbol input.

[0146] The first memory 110a can store a first weighted resistor, and the second memory 110b can store a second weighted resistor. The first weighted resistor and the second weighted resistor can be set differently (e.g., set to have the same absolute value but different signs or have different values ​​but the same sign).

[0147] The first current source 120a and the second current source 120b can apply currents of the same magnitude. The first current source 120a can apply current to the first memory 110a to generate a first weighting voltage (e.g., V). W1 The second current source 120b can apply current to the second memory 110b to generate a second weighting voltage (e.g., V). W2 ).

[0148] Each of the multiplexers 130 can output one of a first weighted voltage, a second weighted voltage, and a first fixed voltage based on a multi-bit input 150 including a symbol input. For example, multiplexer 131 can output a first fixed voltage in response to an absolute value of 0 for an input, and can determine one of a first weighted voltage and a second weighted voltage based on a symbol input in response to an absolute value of 1 for an input.

[0149] The multi-bit unit 100 may include multiple memories 110 storing resistors with different weights to receive more diverse inputs and perform operations on various weights. When the resistor weight of the first memory 110a is positive and the resistor weight of the second memory 110b is negative, the multi-bit unit 100 may receive signed integer inputs and perform operations on them.

[0150] Figure 11 This is a flowchart illustrating an operation method of a multi-bit unit (e.g., a multi-bit cell) according to one or more embodiments.

[0151] Reference Figure 11 The operation methods for multi-bit units include via Figure 4 The operation of processing multiple units in a time series is shown in the diagram. Therefore, it can be seen that even if the following is omitted, the above references... Figures 4 to 10 Information regarding multi-unit descriptions also applies to... Figure 11 The method.

[0152] In operation 1110, the multi-bit cell can generate a weight voltage from the weight resistor by applying current to a memory that stores weight resistors that correspond to the multi-bit weights respectively.

[0153] The memory may include a number of resistive elements connected in series with each other, such that the number corresponds to the number of bits in a multi-bit weight. The multi-bit cell can adjust the weight resistance by controlling the on / off state of each resistive element.

[0154] The weighted resistor can be set to increase linearly as the corresponding multi-bit weight increases.

[0155] In operation 1120, the multi-bit unit can receive multi-bit inputs for multiple capacitors, each capacitor storing a corresponding weighted capacitance.

[0156] The value of each digit constituting the multi-digit input 150 can be input to a multiplexer connected to a capacitor corresponding to the position of the digit.

[0157] In operation 1130, the multi-bit unit can send one of the weighted voltage and the reference voltage to each of the multiple capacitors based on the multi-bit input.

[0158] Each of the multiplexers can receive an input of 1 or 0, and among the multiplexers, the multiplexer that receives 1 can output a weighted voltage, and the multiplexer that receives 0 can output a first fixed voltage.

[0159] When the multi-bit input is 0, all multiplexers in the multiple multiplexers can output a first fixed voltage, and the multi-bit unit can reduce its power consumption by turning off the current source.

[0160] The magnitude of the second fixed voltage sent to the capacitor at the other terminal opposite to the terminal to which the output signal is sent can be the same as the magnitude of the first fixed voltage, and the magnitude of the second fixed voltage can be set such that the difference between the second fixed voltage and the weighted voltage is proportional to the weighted multi-bit weight.

[0161] A multi-bit unit may include a number of capacitors such that the number corresponds to the number of bits in the multi-bit input, and each capacitor may store a weighted capacitor that corresponds to the position of each digit in the multi-bit input.

[0162] In operation 1140, the multi-bit unit can generate charge data stored in each of the multiple capacitors by performing operations on the transmitted signal and weighted capacitors.

[0163] Among multiple capacitors, the capacitor that receives the first fixed voltage can receive a voltage of 0V because the potentials at its two terminals are the same, and can generate charge data of 0C.

[0164] Each of the multiple capacitors can receive the output signal at one of its terminals, receive a second fixed voltage at its opposite terminal, perform a subtraction operation of the second fixed voltage relative to the output signal, and multiply the difference by a weighted capacitor to generate charge data.

[0165] The multi-bit unit can output the first summation data generated by summing the charge data generated by each of the multiple capacitors.

[0166] In one embodiment, the memory may include a first memory and a second memory storing resistors with different weights. The multi-bit cell may also include a symbol multiplexer that determines, based on the symbol input, which of the first and second memories will be subject to a current. The multi-bit cell may generate a weighted voltage from the weighted resistors stored in the determined memory.

[0167] In another embodiment, the memory may include a first memory storing a first weighted resistor and a second memory storing a second weighted resistor. The current source may include a first current source and a second current source that apply currents of the same magnitude. The first current source may apply current to the first memory to generate a first weighted voltage, and the second current source may apply current to the second memory to generate a second weighted voltage. Each of the plurality of multiplexers may output one of a first weighted voltage, a second weighted voltage, and a first fixed voltage based on a multi-bit input including a symbolic input.

[0168] Figure 12 This is a block diagram illustrating the configuration of a multi-bit computing device 1200 (e.g., multi-bit computing device 1200) according to one or more embodiments.

[0169] Reference Figure 12 The multi-bit arithmetic device 1200 may include multiple multi-bit units 200 and a converter 300. The converter 300 may include a comparator 310, multiple reference voltage units 320, and successive approximation register (SAR) logic 330. Figure 12 In the multi-bit arithmetic device 1200 shown, only components relevant to this embodiment are shown. Therefore, it will be clear to those skilled in the art that, in addition to... Figure 12 In addition to the components shown, the multi-bit computing device 1200 may also include other general-purpose components. Figure 12 The multi-bit unit 100 can correspond to Figure 4 100 multi-bit units.

[0170] The multi-bit arithmetic device 1200 may include a plurality of multi-bit units 200. The multi-bit arithmetic device 1200 may generate second summed data by summing all first summed data output from each of the plurality of multi-bit units 200. The multi-bit arithmetic device 1200 may output the second summed data and input the second summed data to a converter 300. The converter 300 may convert the second summed data, which is analog data, into digital data.

[0171] Figure 13 It is a circuit diagram of a multi-bit arithmetic device (e.g., multi-bit arithmetic device 1200) according to one or more embodiments.

[0172] Reference Figure 13Multiple multi-bit units 200 can be connected in parallel with each other, and a number of reference voltage units 320 corresponding to the number of multi-bit units 200 can also be connected in parallel with each other.

[0173] The multi-bit arithmetic unit 1200 can convert the second summed data, which is analog data, into digital data. The multi-bit arithmetic unit 1200 can input the second summed data to a comparator 310 to convert the summed data into digital data. The comparator 310 can store data indicating that the range of the second summed data from its minimum to its maximum value is divided into a predetermined number of intervals, and can classify the second summed data based on this data. The comparator 310 can output data indicating the specific interval to which the value of the second summed data within the predetermined number of intervals belongs.

[0174] SAR logic 330 can convert data received from comparator 310 into digital data based on reference voltage data received from reference voltage unit 320. For example, SAR logic 330 can output a signal DOUT. SAR logic 330 can perform digital conversion by comparing the data received from comparator 310 with the reference voltage data. For example, SAR logic 330 can perform digital conversion by repeating the following operations: maintaining the bit value in response to the data received from comparator 310 being greater than the reference voltage data, and erasing the bit value in response to the data being less than the reference voltage data.

[0175] at the same time, Figure 13 The circuit diagram of the multi-bit arithmetic device shown is merely an example, and the multiple multi-bit units 200 and the multiple reference voltage units 320 may be separate from each other. For example, each of the multiple multi-bit units 200 and each of the multiple reference voltage units 320 may receive a signal from a separate voltage source or a separate current source.

[0176] Figure 14 It is a graph showing the relationship between the time period for multi-bit operations and the time period for digital conversion according to one or more embodiments.

[0177] like Figure 14 As shown, the time periods for performing multi-bit operations to generate charge data, the first summed data, and the second summed data, as well as the time periods for performing digital conversion to convert the second summed data into digital data, can be separated from each other. Multi-bit computing devices can improve computational efficiency and power efficiency by performing multi-bit operations and digital conversions at different times.

[0178] During the multi-bit operation period (e.g., t0 to t1), a sampling voltage can be applied to the multi-bit unit, and the multi-bit unit can receive multi-bit inputs, allowing multi-bit operations to be performed through the multi-bit unit. In response to a first summation data output from each of the multi-bit units, the multi-bit operation device can generate a second summation data by summing the first summation data.

[0179] During the period used for digital conversion (e.g., t2 to t3), the sampling voltage applied to the multi-bit unit is disabled, and the converter, including SAR logic, can operate. The converter can convert the second summed data, which is analog data, into digital data.

[0180] Figure 15 This is a flowchart illustrating an operation method of a multi-bit computing device (e.g., a multi-bit computing apparatus) according to one or more embodiments.

[0181] Reference Figure 15 The operation method of a multi-bit arithmetic device includes through Figure 12 The multi-bit arithmetic unit shown in the diagram processes operations in a time sequence. Therefore, it can be seen that even if the following is omitted, the above references... Figures 12 to 14 Information regarding the description of multi-bit arithmetic devices also applies to Figure 15 The method.

[0182] In operation 1510, each of the multiple multi-bit cells can output the first summation data.

[0183] In operation 1520, the multi-bit arithmetic unit can output a second summation data generated by summing a first summation data from each of the multiple multi-bit units.

[0184] In operation 1530, the multi-bit arithmetic unit can convert the second summation data, which is analog data, into digital data.

[0185] The multi-bit arithmetic device may include a converter that converts a second summed data, which is analog data, into digital data. The converter may include a comparator, multiple reference voltage units, and SAR logic.

[0186] Figure 16 This is a block diagram illustrating the configuration of a multi-bit computing device array (e.g., multi-bit computing device array 1600) according to one or more embodiments.

[0187] Reference Figure 16 The multi-bit arithmetic device array 1600 may include a plurality of multi-bit arithmetic devices 1100a to 1100n. Each multi-bit arithmetic device 1100a may include a converter 300a, and the converter 300a may output digital data 301a. Figure 14 The multi-bit computing device array 1600 shown only includes components relevant to this embodiment. Therefore, it will be clear to those skilled in the art that, in addition to... Figure 16 In addition to the components shown, the multi-bit computing device array 1600 may also include other general-purpose components. Figure 16 The multi-bit arithmetic unit 1100a and the converter 300a can correspond to Figure 12The multi-bit arithmetic unit 1100 and the converter 300.

[0188] Each of the multi-bit arithmetic devices 1100a to 1100n can generate and output digital data by transforming the second summation data output from the multi-bit unit. The multi-bit arithmetic device array 1600 can output the final computation result for the input of the multi-bit arithmetic device array 1600 by combining the digital data 301a to 301n output from each of the individual multi-bit arithmetic devices 1100a to 1100n. The multi-bit arithmetic device array 1600 may correspond to, for example, a combination of multiple layers including an input layer and an output layer. Figure 2 20. Neural network.

[0189] Figure 17 This is a block diagram illustrating an electronic system (e.g., electronic system 1700) according to one or more embodiments.

[0190] Reference Figure 17 The electronic system 1700 can extract useful information by analyzing input data based on the multi-bit computing device 1730, and can determine the situation or control the components of the electronic device on which the electronic system 1700 is installed based on the extracted information. For example, the electronic system 1700 can be applied to robotic devices (such as drones or advanced driver assistance systems (ADAS)), smart TVs, smartphones, medical devices, mobile devices, image display devices, measuring devices, or IoT devices, and can be installed on various types of electronic devices.

[0191] In addition to the multi-bit arithmetic device 1730, the electronic system 1700 may also include a central processing unit (CPU) 1710, random access memory (RAM) 1720, external memory 1740, a sensor module 1750, and a communication (transmitter / receiver (Tx / Rx)) module 1760. Furthermore, the electronic system 1700 may also include input / output modules, security modules, power control devices, etc. Some of the hardware components of the electronic system 1700 may be mounted on a semiconductor chip. The multi-bit arithmetic device 1730 may be implemented on-chip using the multi-bit arithmetic device described with reference to the above figures, or it may be a device that includes the multi-bit arithmetic device described with reference to the above figures as a part thereof.

[0192] The CPU 1710 controls the overall operation of the electronic system 1700. The CPU 1710 may include a single processor core (single-core) or multiple processor cores (multi-core). The CPU 1710 can process or execute programs and / or data stored in external memory 1740. The CPU 1710 can control the functions of the multi-bit arithmetic device 1730 by executing programs stored in external memory 1740. The functions of the CPU 1710 may be implemented by a graphics processing unit (GPU), application processor (AP), etc.

[0193] RAM 1720 may temporarily store programs, data, or instructions. For example, programs and / or data stored in external memory 1740 may be temporarily stored in RAM 1720 according to the control or boot code of CPU 1710. RAM 1720 may be implemented as a memory device (such as dynamic RAM (DRAM) or static RAM (SRAM)).

[0194] The multi-bit computing device 1730 can perform multi-bit operations based on received input data and can generate information signals based on the results of the multi-bit operations. The multi-bit computing device 1730 can be used as a neuromorphic device or a neural network device. Neural networks may include, but are not limited to, convolutional neural networks (CNNs), recurrent neural networks (RNNs), deep belief networks, restricted Boltzmann machines, etc. The multi-bit computing device 1730 may correspond to a hardware accelerator dedicated to neural networks. In addition to neuromorphic devices or neural network devices, the multi-bit computing device 1730 can be applied to various systems that perform operations on multi-bit inputs and multi-bit weights.

[0195] Information signals may include various types of recognition signals (such as voice recognition signals, object recognition signals, image recognition signals, biometric information recognition signals, etc.). For example, the multi-bit processing device 1730 may receive frame data included in a video stream as input data and may generate recognition signals about objects included in an image represented by the frame data. The multi-bit processing device 1730 may receive various types of input data depending on the type or function of the electronic device on which the electronic system 1700 is installed, and may generate recognition signals based on the input data.

[0196] External memory 1740 is a storage space used to store data and can store the operating system (OS), various programs, and various types of data. External memory 1740 may include volatile memory or non-volatile memory. Non-volatile memory includes read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, phase-change RAM (PRAM), MRAM, resistive RAM (RRAM), ferroelectric RAM (FeRAM), etc. Volatile memory includes DRAM, SRAM, synchronous DRAM (SDRAM), phase-change RAM (PRAM), MRAM, resistive RAM (RRAM), FeRAM, etc. External memory 1740 may include, for example, hard disk drives (HDDs), solid-state drives (SSDs), compact flash memory (CF), secure digital storage (SD), micro-secure digital storage (Micro-SD), mini-secure digital storage (Mini-SD), extreme digital storage (xD), or Memory Stick.

[0197] Sensor module 1750 can collect ambient information about the electronic device on which electronic system 1700 is installed. Sensor module 1750 can sense or receive signals (e.g., image signals, voice signals, magnetic signals, biometric signals, or touch signals) from outside the electronic device, and can convert the sensed or received signals into data. For this purpose, sensor module 1750 can be any of various types of sensing devices (e.g., microphone, image capturing device, image sensor, light detection and ranging (LIDAR) sensor, ultrasonic sensor, infrared sensor, biosensor, touch sensor, etc.).

[0198] Sensor module 1750 can provide converted data to multi-bit processing device 1730 as input data. For example, sensor module 1750 may include an image sensor that can generate a video stream by capturing images of the external environment of the electronic device, and can sequentially provide continuous data frames of the video stream as input data to multi-bit processing device 1730. However, this disclosure is not limited thereto, and sensor module 1750 can provide various types of data to multi-bit processing device 1730.

[0199] The communication module 1760 may include various wired or wireless interfaces capable of communicating with external devices. For example, the communication module 1760 may include a local area network (LAN), a wireless LAN (WLAN) (such as Wi-Fi), a wireless personal area network (WPAN) (such as Bluetooth), a wireless universal serial bus (USB), ZigBee, near field communication (NFC), radio frequency identification (RFID), power line communication (PLC), or a communication interface capable of accessing a mobile cellular network (such as third-generation (3G), fourth-generation (4G), long-term evolution (LTE), or fifth-generation (5G)).

[0200] The electronic system 1700 may also include a processor, a memory device for storing and executing program data, a permanent storage device (such as a disk drive), a communication port for communicating with external devices, and a user interface device (such as a touch panel, buttons, or keypads). Methods implemented as software modules or algorithms may be stored in a computer-readable recording medium as computer-readable code or program instructions executable by a processor.

[0201] Regarding Figures 1 to 17The described components include a multi-bit arithmetic device, a multi-bit unit, a memory, a current source, a multiplexer, a capacitor, a resistive element, a symbol multiplexer, a first memory, a second memory, a first current source, a second current source, a converter, a comparator, a reference voltage unit, SAR logic, a multi-bit arithmetic device array, an electronic system, a CPU, RAM, external memory, a sensor module, a Tx / Rx module, a multi-bit arithmetic device 30, a multi-bit unit 100, a memory 110, a current source 120, a multiplexer 130, a capacitor 140, and a multiplexer 13. 1. Capacitor 141, resistive element 111, resistive element 111a, symbol multiplexer 132, first memory 110a, second memory 110b, first current source 120a, second current source 120b, multi-bit arithmetic unit 1200, multi-bit unit 200, converter 300, comparator 310, reference voltage unit 320, SAR logic 330, multi-bit arithmetic unit array 1600, multi-bit arithmetic units 1100a to 1100n, converter 300a, electronic system 1700, CPU 1710, RAM 1720, external memory 1740, sensor module 1750, Tx / Rx module 1760, multi-bit arithmetic unit 1730, and other devices, apparatuses, units, modules, and components are implemented by or represent hardware components. Examples of hardware components that can be used to perform the operations described in this application include, where appropriate, controllers, sensors, generators, drivers, memories, comparators, arithmetic logic units, adders, subtractors, multipliers, dividers, integrators, and any other electronic components configured to perform the operations described in this application. In other examples, one or more of the hardware components performing the operations described in this application are implemented by computing hardware (e.g., by one or more processors or computers). The processor or computer may be implemented by one or more processing elements, such as logic gate arrays, controllers and arithmetic logic units, digital signal processors, microcomputers, programmable logic controllers, field-programmable gate arrays, programmable logic arrays, microprocessors, or any other means or combination of means configured to respond to and execute instructions in a defined manner to achieve a desired result. In one example, the processor or computer includes or is connected to one or more memories storing instructions or software executed by the processor or computer. The hardware components implemented by the processor or computer can execute instructions or software (such as an operating system (OS) and one or more software applications running on the OS) for performing the operations described in this application. Hardware components may also access, manipulate, process, create, and store data in response to the execution of instructions or software. For the sake of brevity, the singular terms “processor” or “computer” may be used in the description of the examples described in this application, but in other examples, multiple processors or computers may be used, or a processor or computer may include multiple processing elements, or multiple types of processing elements, or both.For example, a single hardware component, or two or more hardware components, may be implemented by a single processor, or two or more processors, or a processor and a controller. One or more hardware components may be implemented by one or more processors, or a processor and a controller, and one or more other hardware components may be implemented by one or more other processors, or additional processors and additional controllers. One or more processors, or processors and controllers, may implement a single hardware component, or two or more hardware components. Hardware components may have any one or more different processing configurations, examples of which include: a single processor, a discrete processor, a parallel processor, Single Instruction Single Data (SISD) multiple processing, Single Instruction Multiple Data (SIMD) multiple processing, Multiple Instruction Single Data (MISD) multiple processing, and Multiple Instruction Multiple Data (MIMD) multiple processing.

[0202] Figures 1 to 17 The methods for performing the operations described in this application, as shown, are executed by computing hardware (e.g., one or more processors or a computer), which is implemented to execute instructions or software as described above to perform the operations performed by the methods described in this application. For example, a single operation, or two or more operations, may be executed by a single processor, or two or more processors, or a processor and a controller. One or more operations may be executed by one or more processors, or a processor and a controller, and one or more other operations may be executed by one or more other processors, or additional processors and additional controllers. One or more processors, or a processor and a controller, may execute a single operation, or two or more operations.

[0203] Instructions or software for controlling computing hardware (e.g., one or more processors or computers) to implement hardware components and perform the methods described above can be written as computer programs, code segments, instructions, or any combination thereof to individually or collectively instruct or configure one or more processors or computers to operate as a machine or special-purpose computer to perform operations performed by the hardware components and methods described above. In one example, the instructions or software include machine code (such as machine code generated by a compiler) that is directly executed by one or more processors or computers. In another example, the instructions or software include high-level code that is executed by one or more processors or computers using an interpreter. The instructions or software can be written using any programming language based on the block diagrams and flowcharts shown in the accompanying drawings and the corresponding description used herein, which disclose algorithms for performing operations performed by the hardware components and methods described above.

[0204] Instructions or software for controlling computing hardware (e.g., one or more processors or computers) to implement hardware components and perform the methods described above, as well as any associated data, data files, and data structures, may be recorded, stored, or fixed in, or may be recorded, stored, or fixed on, one or more non-transitory computer-readable storage media. Examples of non-transitory computer-readable storage media include: read-only memory (ROM), random access programmable read-only memory (PROM), electrically erasable programmable read-only memory (EEPROM), random access memory (RAM), dynamic random access memory (DRAM), static random access memory (SRAM), flash memory, non-volatile memory, CD-ROM, CD-R, CD+R, CD-RW, CD+RW, DVD-ROM, DVD-R, DVD+R, DVD-RW, DVD+RW, DVD-RAM, BD-ROM, BD-R, BD-R LTH, BD-RE, Blu-ray or optical disc storage devices, hard disk drives (HDDs), solid-state drives (SSDs), flash memory, card storage (such as multimedia cards or microcards (e.g., Secure Digital (SD) or Extreme Digital (XD))), magnetic tape, floppy disks, magneto-optical data storage devices, optical data storage devices, hard disks, solid-state drives, and any other device configured to store instructions or software and any associated data, data files, and data structures in a non-transitory manner and to provide the instructions or software and any associated data, data files, and data structures to one or more processors or computers, enabling one or more processors or computers to execute the instructions. In one example, the instructions or software and any associated data, data files, and data structures are distributed across a networked computer system, such that the instructions and software and any associated data, data files, and data structures are stored, accessed, and executed in a distributed manner by one or more processors or computers.

[0205] While this disclosure includes specific examples, it will be clear upon understanding this disclosure that various changes in form and detail may be made in these examples without departing from the spirit and scope of the claims and their equivalents. The examples described herein should be considered descriptive only and not for limiting purposes. The description of features or aspects in each example should be considered applicable to similar features or aspects in other examples. Suitable results may be achieved if the described techniques are performed in a different order, and / or if components in the described system, architecture, apparatus, or circuit are combined in a different manner, and / or replaced or supplemented by other components or their equivalents.

Claims

1. A multi-bit unit, comprising: The memory stores the weight resistors corresponding to the multi-bit weights; A current source is configured to apply a current of constant magnitude to the memory to generate a weighted voltage from the weighted resistor; Multiple multiplexers are connected in parallel to each other and in series to a memory. Each of the multiple multiplexers is configured to receive the value of each digit constituting a multi-bit input and, based on the value of each digit constituting the multi-bit input, output a signal of either a weighted voltage or a first fixed voltage. as well as Multiple capacitors are connected to the multiple multiplexers, each of which is configured to: store a corresponding weighted capacitance and generate charge data by performing operations on the output signal and the weighted capacitance.

2. The multi-bit unit according to claim 1, wherein, The memory comprises multiple resistive elements connected in series with each other. The number of the plurality of resistive elements corresponds to the number of bits in the multi-bit weighting, and The multi-bit unit is configured to adjust the weighted resistor by controlling the on / off state of each of the plurality of resistive elements.

3. The multi-bit unit according to claim 1, wherein, Each of the plurality of multiplexers is configured to: Receive input 1 or 0; In response to receiving input 1, the output weighted voltage is generated; and It outputs a first fixed voltage in response to receiving an input of 0.

4. The multi-bit unit according to claim 1, wherein, In response to all multiplexers outputting a first fixed voltage, the multi-bit unit is configured to reduce power consumption by turning off the current source.

5. The multi-bit unit according to claim 1, wherein, The magnitude of the second fixed voltage sent to the terminal opposite to the terminal to which the output signal is sent is the same as the magnitude of the first fixed voltage, and In response to receiving a first fixed voltage, each of the plurality of capacitors is configured to receive a voltage of 0 V based on the fact that the potentials at the two terminals of the capacitor are the same, and to generate charge data of 0 C.

6. The multi-bit unit according to claim 5, wherein, The weighting resistor is set to increase linearly with the increase of the multi-bit weight, and The magnitude of the second fixed voltage is set such that the difference between the second fixed voltage and the weighted voltage is proportional to the multi-digit weight.

7. The multi-bit unit according to claim 1, wherein, The number of capacitors corresponds to the number of bits in the multi-bit input, and Each of the plurality of capacitors is configured as a weighted capacitor that stores the value corresponding to the position of the corresponding digit of the multi-bit input.

8. The multi-bit unit according to claim 7, wherein, The value of each digit constituting a multi-digit input is input to a multiplexer that is connected to a capacitor in one of the multiple capacitors corresponding to the position of the digit.

9. The multi-bit unit according to claim 1, wherein, Each of the plurality of capacitors is configured as follows: The output signal is received at one terminal of the capacitor; A second fixed voltage is received at a terminal opposite to the first terminal; Perform a subtraction operation between the second fixed voltage and the output signal; as well as The difference is multiplied by the weighted capacitor to generate charge data.

10. The multi-bit unit according to claim 1, wherein, The multi-bit unit is configured to output a first summation data generated by summing the charge data generated by each of the plurality of capacitors.

11. The multi-bit unit according to any one of claims 1 to 10, wherein, The memory includes a first memory and a second memory, each storing different weighted resistors. The multi-bit unit further includes: a symbol multiplexer configured to determine, based on the symbol input, one of the first and second memories to which current will be applied, and The multi-bit unit is configured to generate a weighted voltage from a weighted resistor stored in a defined memory.

12. The multi-bit unit according to any one of claims 1 to 10, wherein, The memory includes a first memory and a second memory. The first memory stores a first weighted resistor, and the second memory stores a second weighted resistor. The current source includes a first current source and a second current source. The first current source is configured to apply current to a first memory to generate a first weighted voltage, and the second current source is configured to apply current to a second memory to generate a second weighted voltage. Each of the plurality of multiplexers is configured to output any one of a first weighted voltage, a second weighted voltage, and a first fixed voltage based on a multi-bit input including a symbolic input.

13. A multi-bit arithmetic device, comprising a plurality of multi-bit units according to claim 10, wherein, The multi-bit arithmetic device is configured to output a second summation data generated by summing a first summation data from each of the multiple multi-bit units.

14. The multi-bit arithmetic device according to claim 13, further comprising: The converter is configured to convert the second summed data, which is analog data, into digital data. The converter includes a comparator, multiple reference voltage units, and successive approximation register logic.

15. A method for performing multi-bit operations, the method comprising: A constant current is applied to a memory that stores weight resistors corresponding to multiple weights through a current source to generate a weight voltage from the weight resistors. Each of a plurality of multiplexers receives the value of each digit constituting a multi-bit input, and based on the value of each digit constituting a multi-bit input, outputs a signal of either a weighted voltage or a first fixed voltage to each of a plurality of capacitors, wherein the plurality of multiplexers are connected in parallel to each other and in series to a memory, and the plurality of capacitors are respectively connected to the plurality of multiplexers and each stores a corresponding weighted capacitor. as well as By performing operations on the output signal and the weighted capacitors, charge data stored in each of the plurality of capacitors is generated.

16. The method of claim 15, further comprising: The output is a first summation data generated by summing the charge data stored in each of the plurality of capacitors.

17. The method of claim 16, further comprising: Perform the step of outputting the first summed data at each of the multiple multi-bit cells; as well as The output is a second summation data generated by summing the first summation data from each of the plurality of multi-bit units.

18. The method of claim 17, further comprising: The second summation data, which is used as analog data, is converted into digital data.

19. A non-transitory computer-readable storage medium for storing instructions, which, when executed by a processor, configure the processor to perform the method according to any one of claims 15 to 18.

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