Display device

Abstract

A display device is provided. The display device includes a plurality of pixels, an emission control driver, a scan driver, and a timing controller configured to select whether the display device operates in a first display mode or a second display mode based on input image data, the display device being driven at a first frequency in the first display mode and at a second frequency lower than the first frequency in the second display mode. The first display mode includes a first frame period, and the second display mode includes a second frame period having at least two subframe periods each having a period equal to the first frame period. A total time required to supply a scan signal to a scan line in one of the first frame periods and a total time required to supply the scan signal to the scan line in one of the subframes of one of the second frame periods are substantially the same.

Description

[0001] Cross-references to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2021-0042663, filed on April 1, 2021, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure generally relates to display devices. Background Technology

[0004] With the development of information technology, display devices, as the connection medium between users and information, have become increasingly important. Consequently, display devices such as liquid crystal displays (LCDs) and organic light-emitting diode (OLEDs) are being used more and more frequently.

[0005] The display device displays an image by using a combination of light emitted from the pixels to write data voltages to them. A scan driver is required to select the pixels to be written with data voltages. The scan driver can be driven using progressive scan or interlaced scan, depending on the driving method.

[0006] In progressive scanning, the scan driver sequentially outputs the scan signal to all scan lines for each frame, resulting in high power consumption. However, since all scan lines are driven for each frame, progressive scanning is suitable for displaying moving images. On the other hand, in interlaced scanning, the scan driver alternately drives odd-numbered and even-numbered scan lines for each frame, resulting in low power consumption. However, only half of the scan lines are driven during a subframe period, making interlaced scanning suitable for displaying still images.

[0007] The display device can operate using either progressive or interlaced scanning depending on the type of input image. In the display device, the speed at which the scan signal is supplied can be varied between progressive and interlaced scanning. Therefore, a flickering phenomenon, which may be observed by the user, in the displayed image may occur. Summary of the Invention

[0008] The implementation provides a display device capable of performing mode switching between progressive scan and interlaced scan while preventing flickering.

[0009] According to an aspect of this disclosure, a display device is provided, comprising a plurality of pixels, an emission control driver configured to provide emission control signals to the plurality of pixels, a scan driver configured to provide scan signals to the plurality of pixels, and a timing controller configured to select, based on input image data, whether the display device operates in either a first display mode or a second display mode, wherein in the first display mode the display device is driven at a first frequency, and in the second display mode the display device is driven at a second frequency lower than the first frequency.

[0010] The first display mode includes a plurality of first frame periods, and the second display mode includes a plurality of second frame periods, each of the plurality of second frame periods having at least two subframe periods, each of the at least two subframe periods being equal to a first frame period. The total time required to supply scan signals to the plurality of scan lines in the first frame period, the total time required to supply scan signals to odd-numbered scan lines in one subframe period, and the total time required to supply scan signals to even-numbered scan lines in another subframe period are substantially the same.

[0011] The timing controller can receive input image data and output clock signals, scan start signals and image data.

[0012] A scan driver may include multiple stages connected to multiple clock signal lines provided with clock signals, which generate scan signals in response to a scan start signal.

[0013] The carry signal can be transmitted to the next level after the previous level. The second frame period may include a first subframe period and a second subframe period. In the first subframe period, odd-numbered scan signals from a plurality of scan signals are provided to a plurality of pixels, and in the second subframe period, even-numbered scan signals from a plurality of scan signals are provided to a plurality of pixels.

[0014] The period of the clock signal in the first frame period can be equal to each of the periods of the clock signal in the first subframe period and the period of the clock signal in the second subframe period.

[0015] The clock signal period of the first frame period, the clock signal period of the first subframe period, and the clock signal period of the second subframe period can each have four horizontal periods.

[0016] Multiple clock signal lines may include a first clock line, a second clock line, a third clock line, and a fourth clock line. The first clock line and the third clock line may be alternately connected to the first clock input terminal and the second clock input terminal of the odd-numbered level among the multiple levels, and the second clock line and the fourth clock line may be alternately connected to the first clock input terminal and the second clock input terminal of the even-numbered level among the multiple levels.

[0017] During the first frame period, the timing controller can sequentially supply a first clock signal to the first clock line, a second clock signal to the second clock line, a third clock signal to the third clock line, and a fourth clock signal to the fourth clock line.

[0018] During the first subframe period, the timing controller can provide the first clock signal and the third clock signal with the conduction level to the first clock line and the third clock line, respectively, and provide the second clock signal and the fourth clock signal with the deactivation level to the second clock line and the fourth clock line, respectively.

[0019] During the second subframe period, the timing controller can provide the first clock signal and the third clock signal at the off level to the first clock line and the third clock line, respectively, and provide the second clock signal and the fourth clock signal at the on level to the second clock line and the fourth clock line, respectively.

[0020] The display device may also include a data driver configured to generate a data signal based on image data. Each of the plurality of pixels may emit light with a brightness corresponding to the data signal in response to a scan signal.

[0021] The timing controller may include a brightness controller configured to adjust the duty cycle to the number of pulses of the transmit control signal included in a predetermined time period.

[0022] The brightness controller can set the duty cycle of the transmit control signal to 4 during the first frame period of the first display mode and the sub-frame period of the second display mode.

[0023] During the first and second frame periods, the ratio of the off period to the frame period for transmitting control signals can be 50% across all regions of multiple pixels.

[0024] The timing controller can select a first display mode when the grayscale values ​​of the corresponding input image data in each consecutive frame are substantially different from each other, and select a second display mode when the grayscale values ​​of the corresponding input image data in each consecutive frame are substantially the same. Attached Figure Description

[0025] Exemplary embodiments will now be described more fully below with reference to the accompanying drawings; however, exemplary embodiments may be implemented in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the exemplary embodiments to those skilled in the art.

[0026] It will be understood that when an element is referred to as being "between" two elements, that element can be the only element between the two elements, or there may be one or more intervening elements. Throughout the specification, similar reference numerals refer to similar elements.

[0027] Figure 1 This is a diagram illustrating a display device according to an embodiment of the present disclosure.

[0028] Figure 2A This diagram illustrates an AMOLED pulse drive (AID) dimming method that adjusts the duty cycle of a control signal.

[0029] Figure 2B It shows the use Figure 2A The waveform diagram shows the change in the duty cycle of the transmit control signal in the AID dimming method.

[0030] Figure 3 This is a diagram illustrating pixels according to an embodiment of the present disclosure.

[0031] Figure 4 This is a diagram illustrating a scan driver according to an embodiment of the present disclosure.

[0032] Figure 5 This is a diagram illustrating the hierarchy according to an embodiment of the present disclosure.

[0033] Figure 6 This is a diagram illustrating a driving method of a scan driver according to an embodiment of the present disclosure.

[0034] Figure 7 , Figure 8 , Figure 9 , Figure 10 , Figure 11 and Figure 12 This is a diagram illustrating the first frame time period and the second frame time period according to an embodiment of the present disclosure.

[0035] Figure 13 , Figure 14 , Figure 15 and Figure 16 This is a diagram illustrating the first frame time period and the second frame time period according to an embodiment of the present disclosure.

[0036] Figure 17A and Figure 17B This is a diagram illustrating the first and third frame time periods according to another embodiment of the present disclosure.

[0037] Figure 18A and Figure 18B This is a diagram illustrating the first and fourth frame time periods according to another embodiment of the present disclosure. Detailed Implementation

[0038] In the following detailed description, embodiments are given with reference to the accompanying drawings to enable those skilled in the art to readily practice this disclosure. This disclosure may be implemented in various different forms and is not limited to the embodiments described herein.

[0039] Parts irrelevant to the description will be omitted in order to clearly describe this disclosure, and throughout the specification, the same or similar constituent elements will be indicated by the same reference numerals. Therefore, the same reference numerals may be used in different drawings to identify the same or similar elements.

[0040] In the description, the expression "equal" may mean "substantially equal." That is, it may mean to the extent that a person skilled in the art would understand them to be equal. Other expressions may omit the word "substantially."

[0041] Figure 1 This is a diagram illustrating a display device according to an embodiment of the present disclosure. Figure 2A This diagram illustrates an AMOLED pulse drive (AID) dimming method that adjusts the duty cycle of a control signal.

[0042] Figure 2B It shows the use Figure 2A The waveform diagram shows the change in the duty cycle of the transmit control signal in the AID dimming method shown. Figure 2A The diagram shows that the state in which the transmit control signals EM1 and EM2 are logic high is the non-transmit state, and the state in which the transmit control signals EM1 and EM2 are logic low is the transmit state. However, this disclosure is not limited thereto.

[0043] Reference Figure 1 The display device 10 according to embodiments of the present disclosure may include a timing controller 11, a data driver 12, a scan driver 13, a plurality of pixels 14, an initialization driver 15, and an emission control driver 16.

[0044] The timing controller 11 can receive external input signals from an external processor. These external input signals may include a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, and RGB data (or input image data), etc. The vertical synchronization signal may include multiple pulses, and the timing of generating each of these pulses may indicate the end of the previous frame period and the beginning of the current frame period. The interval between adjacent pulses of the vertical synchronization signal may correspond to a frame period. The horizontal synchronization signal may include multiple pulses, and the timing of generating each of these pulses may indicate the end of the previous horizontal period and the beginning of a new horizontal period. The interval between adjacent pulses of the horizontal synchronization signal may correspond to a horizontal period. The data enable signal may indicate the supply of RGB data during a horizontal period. The RGB data may be supplied in pixel rows during a horizontal period in accordance with the data enable signal. The RGB data corresponding to a frame may be referred to as an input image.

[0045] The timing controller 11 can determine whether the display device 10 operates in either a first display mode driven by a first frequency (e.g., 60Hz) or a second display mode driven by a second frequency (e.g., 30Hz) lower than the first frequency. For example, when the grayscale values ​​of the input images in consecutive frames are substantially the same, the timing controller 11 can determine the consecutive input images as still images. Furthermore, when the grayscale values ​​of the input images in consecutive frames are substantially different from each other, the timing controller 11 can determine the consecutive input images as moving images.

[0046] At the same time, such as Figure 1 As shown, the timing controller 11 may include a brightness controller 11a. According to an embodiment, the brightness controller 11a can adjust the busy / idle state of the transmission control signal, where the busy / idle state is the ratio of the transmission control signal's on-time to its off-time. The display device 10 can adjust the emission brightness of a plurality of pixels 14 in accordance with the busy / idle state. (See below for further details.) Figure 2A and Figure 2B The busy / idle status of the transmit control signals is described in detail.

[0047] The data driver 12 can provide a data voltage corresponding to the grayscale of the input image to the pixels. For example, the data driver 12 can sample the grayscale using a clock signal and apply the data voltage corresponding to the grayscale to the data lines DL1, DL2, DL3, ..., DLn in units of scan lines. Here, n can be an integer greater than 0.

[0048] The scan driver 13 can receive clock signals and scan start signals from the timing controller 11, and generate scan signals to be provided to scan lines SL1, SL2, SL3, ... and SLm. Here, m can be an integer greater than 0.

[0049] Each pixel PXij can be connected to the corresponding data line among data lines DL1, DL2, DL3, ..., DLn, and the corresponding scan line among scan lines SL1, SL2, SL3, ..., SLm. Here, i and j are integers greater than 0. For example, pixel PXij could mean a pixel whose scan transistor is connected to the i-th scan line and the j-th data line.

[0050] Under the control of the timing controller 11, the initialization driver 15 can supply initialization signals to the initialization lines GBL1, GBL2, GBL3, ... and GBLm. For example, the initialization driver 15 can sequentially supply initialization signals to the initialization lines GBL1, GBL2, GBL3, ... and GBLm.

[0051] Under the control of the timing controller 11, the transmit control driver 16 can supply transmit control signals to transmit control lines EL1, EL2, EL3, ..., and ELm. In an example, the transmit control driver 16 can sequentially supply transmit control signals to transmit control lines EL1, EL2, EL3, ..., and ELm. According to an embodiment, the transmit control signals can be configured to have a width wider than the width of the scan signals. For example, the transmit control signals can be supplied to overlap with two scan signals.

[0052] Reference Figure 2A The AID dimming method adjusts brightness by controlling the duty cycles of the emission control signals EM1 and EM2 to correspond to the set dimming steps. In the AID dimming method, brightness is changed by altering the off-duty period P1 (or P3) or on-duty period P2 (or P4) within one cycle (e.g., one frame 1F) of the emission control signal used to control the emission and non-emission of pixel PXij. That is, brightness is adjusted by controlling the duty cycle of the emission control signal, and the duty cycle can be set to 0%, 20%, 40%, 60%, 80%, and 95%. However, this is merely illustrative, and various duty cycles can be set by the user.

[0053] Reference Figure 2A In the 100-nit dimming step, the on-time P4 of the emission control signal EM2 is shorter than the on-time P2 of the emission control signal EM1 in the 300-nit dimming step. Conversely, the off-time P3 of the emission control signal EM2 in the 100-nit dimming step is longer than the off-time P1 of the emission control signal EM1 in the 300-nit dimming step. Pixels emit light during the on-time of emission control signals EM1 and EM2, and do not emit light during the off-time of emission control signals EM1 and EM2. Therefore, brightness can decrease as the on-time of the emission control signals decreases and the off-time of the emission control signals increases.

[0054] Reference Figure 2A and Figure 2B , Figure 2A The transmit control signal EM1 or EM2 shown represents the case where the duty cycle (or number of periods) of transmit control signal EM1 or EM2 is 1. That is, the number of pulses of transmit control signal EM1 or EM2 included in one period (e.g., one frame 1F) is 1. Meanwhile, Figure 2B The (1-1)th transmit control signal EM11 shown represents the case where the duty cycle of the (1-1)th transmit control signal EM11 is 4. That is, the number of pulses of the (1-1)th transmit control signal EM11 included in one period (e.g., one frame 1F) is 4. For ease of description, Figure 2BOnly the case with a duty cycle of 4 is shown. However, a duty cycle of 2 means that the number of pulses of the transmit control signal included in one period (e.g., one frame 1F) is 2, and a duty cycle of 8 means that the number of pulses of the transmit control signal included in one period (e.g., one frame 1F) is 8. The brightness may decrease as the number of pulses of the transmit control signal EM1, transmit control signal EM2, or the (1-1)th transmit control signal EM11 included in the same period (e.g., one frame 1F) increases. In other words, the brightness may decrease as the duty cycle of the transmit control signal EM1, transmit control signal EM2, or the (1-1)th transmit control signal EM11 increases.

[0055] Figure 3 This is a diagram illustrating pixels according to an embodiment of the present disclosure. Figure 3 The image shows pixel PXij connected to the i-th scan line SLi and the j-th data line DLj.

[0056] Reference Figure 3 According to embodiments of the present disclosure, the pixel PXij may include a light-emitting diode LD, a first transistor T1 to a seventh transistor T7, and a storage capacitor Cst.

[0057] The anode of the light-emitting diode (LD) can be connected to the pixel circuit PXC, and the cathode of the LD can be connected to the second pixel power line VSSL. The LD can generate light with a predetermined brightness corresponding to the amount of current supplied from the pixel circuit PXC.

[0058] The pixel circuit PXC can control the amount of current flowing from the first pixel power line VDDL through the light-emitting diode LD to the second pixel power line VSSL in accordance with the data signal. In an example, when the scan signal is supplied to the (i-1)th scan line SLi-1, the pixel circuit PXC can initialize the gate electrode of the fourth transistor T4 (or the driving transistor), and when the scan signal is supplied to the i-th scan line SLi, the pixel circuit PXC can store the data signal supplied from the j-th data line DLj to the storage capacitor Cst. Furthermore, when the transmit control signal is supplied to the i-th transmit control line ELi, the pixel circuit PXC can control the amount of current supplied to the light-emitting diode LD in accordance with the data signal.

[0059] The pixel circuit PXC can be implemented using various types of circuits currently known in the art. Furthermore, the first pixel power line VDDL can be set to a higher voltage than the second pixel power line VSSL, so that current can flow from the first pixel power line VDDL through the light-emitting diode LD to the second pixel power line VSSL.

[0060] The first transistor T1 can be connected between the initialization power supply Vint and the anode of the light-emitting diode LD. Furthermore, the gate electrode of the first transistor T1 can be connected to the i-th initialization line GBLi (or control line). The first transistor T1 can be turned on when the initialization signal is supplied to the i-th initialization line GBLi to supply the voltage of the initialization power supply Vint to the anode of the light-emitting diode LD. The initialization power supply Vint can be set to a voltage lower than the data signal.

[0061] The second transistor T2 can be connected between the fourth transistor T4 and the anode of the light-emitting diode LD. Furthermore, the gate electrode of the second transistor T2 can be connected to the i-th emitter control line ELi. The second transistor T2 can be turned off when the emitter control signal is supplied to the i-th emitter control line ELi, and turned on under other conditions.

[0062] The third transistor T3 can be connected between the first pixel power line VDDL and the fourth transistor T4. Furthermore, the gate electrode of the third transistor T3 can be connected to the i-th emitt control line ELi. The third transistor T3 can be turned off when the emitt control signal is supplied to the i-th emitt control line ELi, and turned on under other conditions.

[0063] The first electrode of the fourth transistor T4 (or driving transistor) can be connected to the first pixel power line VDDL via the third transistor T3, and the second electrode of the fourth transistor T4 can be connected to the anode of the light-emitting diode LD via the second transistor T2. Furthermore, the gate electrode of the fourth transistor T4 can be connected to the first node N1. The fourth transistor T4 can control the amount of current flowing from the first pixel power line VDDL to the second pixel power line VSSL via the light-emitting diode LD, corresponding to the voltage of the first node N1.

[0064] The fifth transistor T5 can be connected between the second electrode of the fourth transistor T4 and the first node N1. Additionally, the gate electrode of the fifth transistor T5 can be connected to the i-th scan line SLi. The fifth transistor T5 can be turned on when the scan signal is supplied to the i-th scan line SLi, thereby electrically connecting the second electrode of the fourth transistor T4 and the first node N1. Therefore, when the fifth transistor T5 is turned on, the fourth transistor T4 can be connected as a diode.

[0065] The sixth transistor T6 can be connected between the first node N1 and the initialization power supply Vint. Additionally, the gate electrode of the sixth transistor T6 can be connected to the (i-1)th scan line SLi-1. The sixth transistor T6 can be turned on when the scan signal is supplied to the (i-1)th scan line SLi-1 to supply the voltage of the initialization power supply Vint to the first node N1.

[0066] The seventh transistor T7 can be connected between the j-th data line DLj and the first electrode of the fourth transistor T4. Additionally, the gate electrode of the seventh transistor T7 can be connected to the i-th scan line SLi. The seventh transistor T7 can be turned on when the scan signal is supplied to the i-th scan line SLi, thereby electrically connecting the j-th data line DLj and the first electrode of the fourth transistor T4 to each other.

[0067] The storage capacitor Cst can be connected between the first pixel power line VDDL and the first node N1. The storage capacitor Cst can store the voltage corresponding to the data signal and the threshold voltage of the fourth transistor T4.

[0068] Figure 4 This is a diagram illustrating a scan driver according to an embodiment of the present disclosure.

[0069] The scan driver 13 may include odd-numbered levels ST1, ST3, and ... connected to odd-numbered scan lines SL1, SL3, and ..., and even-numbered levels ST2, ST4, and ... connected to even-numbered scan lines SL2, SL4, and ... For example, the first scan line SL1 and the third scan line SL3 may be connected to the first level ST1 and the third level ST3, respectively. Additionally, the second scan line SL2 and the fourth scan line SL4 may be connected to the second level ST2 and the fourth level ST4, respectively.

[0070] Each of the first level ST1 to the fourth level ST4 may include a first input terminal 1001, a second input terminal 1002 (or a first clock input terminal), a third input terminal 1003 (or a second clock input terminal), and an output terminal 1004.

[0071] The first level ST1 of odd-numbered levels ST1, ST3, and ... and the second level ST2 of even-numbered levels ST2, ST4, and ... can be connected to the same scan start line FLML. For example, the first input terminal 1001 of the first level ST1 and the first input terminal 1001 of the second level ST2 can be connected to the same scan start line FLML. The output terminal 1004 of the first level ST1 can be connected to the first scan line SL1, and the output terminal 1004 of the second level ST2 can be connected to the second scan line SL2.

[0072] Each of the odd-numbered levels ST3 and ... (excluding the first level ST1) can be connected to the scan line (or carry line) of the previous odd-numbered level. Each of the even-numbered levels ST4 and ... (excluding the second level ST2) can be connected to the scan line (or carry line) of the previous even-numbered level. For example, the first input terminal 1001 of the third level ST3 can be connected to the first scan line SL1 of the first level ST1. Additionally, the first input terminal 1001 of the fourth level ST4 can be connected to the second scan line SL2 of the second level ST2.

[0073] Odd-numbered stages ST1, ST3, and... can be connected to the first clock line CKL1 and the third clock line CKL3. The first clock line CKL1 and the third clock line CKL3 can be alternately connected to the second input terminal 1002 and the third input terminal 1003 of the odd-numbered stages ST1, ST3, and... Even-numbered stages ST2, ST4, and... can be connected to the second clock line CKL2 and the fourth clock line CKL4, which are different from the first clock line CKL1 and the third clock line CKL3. The second clock line CKL2 and the fourth clock line CKL4 can be alternately connected to the second input terminal 1002 and the third input terminal 1003 of the even-numbered stages ST2, ST4, and...

[0074] Each of the first stage ST1 through the fourth stage ST4 can be connected to the first power supply line VHPL and the second power supply line VLPL. The voltage of the first power supply line VHPL can be set to the off level (gate off voltage, logic high). Furthermore, the voltage of the second power supply line VLPL can be set to the on level (gate on voltage, logic low).

[0075] Figure 5 This is a diagram illustrating the hierarchy according to an embodiment of the present disclosure.

[0076] For ease of description, Figure 5 The diagram shows the first level ST1 and the third level ST3. (See reference...) Figure 5 The first stage ST1 may include a first driver 1210, a second driver 1220 and an output circuit 1230.

[0077] The output circuit 1230 controls the voltage supplied to the output terminal 1004 in response to the voltages of the first node NP1 and the second node NP2. For this purpose, the output circuit 1230 includes a fifth transistor M5 and a sixth transistor M6.

[0078] A fifth transistor M5 is connected between the first power supply line VHPL and the output terminal 1004, and the gate electrode of the fifth transistor M5 is connected to the first node NP1. The fifth transistor M5 controls the connection between the first power supply line VHPL and the output terminal 1004 in response to the voltage applied to the first node NP1.

[0079] A sixth transistor M6 is connected between output terminal 1004 and third input terminal 1003, and the gate electrode of the sixth transistor M6 is connected to the second node NP2. The sixth transistor M6 controls the connection between output terminal 1004 and third input terminal 1003 in response to a voltage applied to the second node NP2. Output circuit 1230 is a buffer circuit. Additionally, the fifth transistor M5 and the sixth transistor M6 can be configured such that multiple transistors are connected in parallel.

[0080] The first driver 1210 controls the voltage of the third node NP3 in response to signals supplied to the first input terminals 1001 to the third input terminals 1003. For this purpose, the first driver 1210 includes a second transistor M2 to a fourth transistor M4.

[0081] The second transistor M2 is connected between the first input terminal 1001 and the third node NP3, and the gate electrode of the second transistor M2 is connected to the second input terminal 1002. The second transistor M2 controls the connection between the first input terminal 1001 and the third node NP3 in response to a signal supplied to the second input terminal 1002.

[0082] The third transistor M3 and the fourth transistor M4 are connected in series between the third node NP3 and the first power line VHPL. The third transistor M3 is connected between the fourth transistor M4 and the third node NP3, and the gate electrode of the third transistor M3 is connected to the third input terminal 1003. The third transistor M3 controls the connection between the fourth transistor M4 and the third node NP3 in response to a signal supplied to the third input terminal 1003.

[0083] The fourth transistor M4 is located between the third transistor M3 and the first power supply line VHPL, and the gate electrode of the fourth transistor M4 is connected to the first node NP1. The fourth transistor M4 controls the connection between the third transistor M3 and the first power supply line VHPL in response to the voltage of the first node NP1.

[0084] The second driver 1220 controls the voltage of the first node NP1 in response to the voltage at the second input terminal 1002 and the third node NP3. For this purpose, the second driver 1220 includes a first transistor M1, a seventh transistor M7, an eighth transistor M8, a first capacitor CP1, and a second capacitor CP2.

[0085] The first capacitor CP1 is connected between the second node NP2 and the output terminal 1004. The first capacitor CP1 is charged with the voltage corresponding to the on and off states of the sixth transistor M6.

[0086] The second capacitor CP2 is connected between the first node NP1 and the first power line VHPL. The second capacitor CP2 charges the voltage applied to the first node NP1.

[0087] A seventh transistor M7 is connected between the first node NP1 and the second input terminal 1002, and the gate electrode of the seventh transistor M7 is connected to the third node NP3. The seventh transistor M7 controls the connection between the first node NP1 and the second input terminal 1002 in response to the voltage of the third node NP3.

[0088] The eighth transistor M8 is connected between the first node NP1 and the second power line VLPL, and the gate electrode of the eighth transistor M8 is connected to the second input terminal 1002. The eighth transistor M8 controls the connection between the first node NP1 and the second power line VLPL in response to the signal at the second input terminal 1002.

[0089] A first transistor M1 is connected between the third node NP3 and the second node NP2, and the gate electrode of the first transistor M1 is connected to the second power supply line VLPL. The first transistor M1 maintains the electrical connection between the third node NP3 and the second node NP2 while remaining in the ON state. Furthermore, the first transistor M1 limits the voltage drop across the third node NP3. In other words, even if the voltage of the second node NP2 drops to a voltage lower than the voltage of the second power supply line VLPL, the voltage of the third node NP3 does not become lower than the voltage obtained by subtracting the threshold voltage of the first transistor M1 from the voltage of the second power supply line VLPL.

[0090] Figure 6 This is a diagram illustrating a driving method for a scan driver according to an embodiment of the present disclosure. Figure 6 For ease of description, the operation process in the first level ST1 will be described in detail.

[0091] Reference Figure 6 The first clock signal CK1 and the third clock signal CK3 have a period of four horizontal time intervals of 4H, and are supplied in different horizontal time intervals. In other words, the third clock signal CK3 is set to be a signal shifted from the first clock signal CK1 by half a cycle (i.e., two horizontal time intervals). Additionally, the scan start signal FLM supplied to the first input terminal 1001 of the first stage ST1 can be synchronized with the first clock signal CK1 supplied to the second input terminal 1002 of the first stage ST1. One horizontal time interval 1H can correspond to the period of the pulse of the horizontal synchronization signal Hsync.

[0092] Supplying a specific signal can mean supplying a specific signal with an on level (i.e., logic low). Pausing the supply of a specific signal can mean supplying a specific signal with an off level (i.e., logic high).

[0093] Additionally, when a scan start signal (FLM) is supplied, the first input terminal 1001 can be set to a logic low level. When no scan start signal (FLM) is supplied, the first input terminal 1001 can be set to a logic high level. Furthermore, when a clock signal is supplied to the second input terminal 1002 and the third input terminal 1003, the second input terminal 1002 and the third input terminal 1003 can be set to a logic low level. When no clock signal is supplied to the second input terminal 1002 and the third input terminal 1003, the second input terminal 1002 and the third input terminal 1003 can be set to a logic high level.

[0094] The operation process will be described in detail. First, the scan start signal FLM, which is synchronized with the first clock signal CK1, is supplied to the first stage ST1.

[0095] When the first clock signal CK1 is supplied, the second transistor M2 and the eighth transistor M8 are turned on. When the second transistor M2 is turned on, the first input terminal 1001 and the third node NP3 are electrically connected to each other. The first transistor M1 is set to the on state most of the time, and therefore the second node NP2 remains electrically connected to the third node NP3.

[0096] When the first input terminal 1001 and the third node NP3 are electrically connected to each other, the voltage VNP2 of the second node NP2 and the voltage VNP3 of the third node NP3 are set to low level by the scan start signal FLM supplied to the first input terminal 1001. When the voltage VNP2 of the second node NP2 and the voltage VNP3 of the third node NP3 are set to low level, the sixth transistor M6 and the seventh transistor M7 are turned on.

[0097] When the sixth transistor M6 is turned on, the third input terminal 1003 and the output terminal 1004 are electrically connected to each other. The third input terminal 1003 is set to a high level voltage (i.e., no third clock signal CK3 is supplied), and therefore, this high level voltage is also output to the output terminal 1004. When the seventh transistor M7 is turned on, the second input terminal 1002 and the first node NP1 are electrically connected. According to the first clock signal CK1 supplied to the second input terminal 1002, the voltage VNP1 of the first node NP1 is set to a low level.

[0098] Additionally, when the first clock signal CK1 is supplied, the eighth transistor M8 is turned on. When the eighth transistor M8 is turned on, the voltage of the second power supply line VLPL is supplied to the first node NP1. The voltage of the second power supply line VLPL is set to be equal to (or similar to) the low-level voltage of the first clock signal CK1, and therefore, the first node NP1 is stably maintained at a low level.

[0099] When the first node NP1 is set to a low voltage, the fourth transistor M4 and the fifth transistor M5 are turned on. When the fourth transistor M4 is turned on, the first power supply line VHPL and the third transistor M3 are electrically connected to each other. The third transistor M3 is turned off, and therefore, even when the fourth transistor M4 is turned on, the third node NP3 maintains a stable low voltage. When the fifth transistor M5 is turned on, the voltage of the first power supply line VHPL is supplied to the output terminal 1004. The voltage of the first power supply line VHPL is set to a voltage equal to (or similar to) the high voltage supplied to the third input terminal 1003, and therefore the output terminal 1004 maintains a stable high voltage.

[0100] Subsequently, the supply of the scan start signal FLM and the first clock signal CK1 is paused. When the supply of the first clock signal CK1 is paused, the second transistor M2 and the eighth transistor M8 are turned off. The sixth transistor M6 and the seventh transistor M7 remain on due to the voltage stored in the first capacitor CP1. That is, the second node NP2 and the third node NP3 are kept at a low voltage level due to the voltage stored in the first capacitor CP1.

[0101] When the sixth transistor M6 remains on, the output terminal 1004 and the third input terminal 1003 maintain their electrical connection. When the seventh transistor M7 remains on, the first node NP1 maintains its electrical connection with the second input terminal 1002. Because the supply of the first clock signal CK1 is suspended, the voltage at the second input terminal 1002 is set to a high level, and therefore, the voltage VNP1 at the first node NP1 is also set to a high level. When a high-level voltage is supplied to the first node NP1, the fourth transistor M4 and the fifth transistor M5 are turned off.

[0102] Subsequently, the third clock signal CK3 is supplied to the third input terminal 1003. The sixth transistor M6 is set to the on state, and therefore, the third clock signal CK3 supplied to the third input terminal 1003 is supplied to the output terminal 1004. The output terminal 1004 outputs the third clock signal CK3 as the first scan signal SS1 at the on level to the first scan line SL1.

[0103] Meanwhile, when the third clock signal CK3 is supplied to the output terminal 1004, the voltage of the second node NP2 drops to a voltage lower than the voltage of the second power line VLPL, and therefore the sixth transistor M6 remains stably turned on.

[0104] Meanwhile, although the voltage of the second node NP2 drops, the third node NP3 can maintain the voltage of the second power line VLPL (e.g., the voltage obtained by subtracting the threshold voltage of the first transistor M1 from the voltage of the second power line VLPL) due to the conduction of the first transistor M1.

[0105] After the first scan signal SS1, at the conduction level, is output to the first scan line SL1, the supply of the third clock signal CK3 is paused. When the supply of the third clock signal CK3 is paused, the output terminal 1004 outputs a high-level voltage. In addition, the voltage VNP2 of the second node NP2 rises approximately to the voltage of the second power line VLPL, which corresponds to the high-level voltage output from the output terminal 1004.

[0106] Subsequently, a first clock signal CK1 is supplied. When the first clock signal CK1 is supplied, the second transistor M2 and the eighth transistor M8 are turned on. When the second transistor M2 is turned on, the first input terminal 1001 and the third node NP3 are electrically connected to each other. The scan start signal FLM is not supplied to the first input terminal 1001, and therefore, the third node NP3 is set to a high level voltage. Therefore, a high level voltage is supplied to the third node NP3 and the second node NP2, and thus the sixth transistor M6 and the seventh transistor M7 are turned off.

[0107] When the eighth transistor M8 is turned on, the voltage of the second power line VLPL is supplied to the first node NP1, and thus the fourth transistor M4 and the fifth transistor M5 are turned on. When the fifth transistor M5 is turned on, the voltage of the first power line VHPL is supplied to the output terminal 1004. Subsequently, the fourth transistor M4 and the fifth transistor M5 remain turned on due to the voltage charged in the second capacitor CP2, and thus the output terminal 1004 is stably supplied with the voltage of the first power line VHPL.

[0108] Additionally, when the third clock signal CK3 is supplied, the third transistor M3 is turned on. The fourth transistor M4 is set to the on state, and therefore the voltage of the first power line VHPL is supplied to the third node NP3 and the second node NP2. The sixth transistor M6 and the seventh transistor M7 remain stably off.

[0109] The third stage ST3 is supplied with an output signal (i.e., a scan signal) synchronized with the third clock signal CK3 from the first stage ST1. The third stage ST3 outputs a third scan signal SS3 with a conduction level synchronized with the first clock signal CK1 to the third scan line SL3. Odd-numbered stages ST1, ST3, and ... sequentially output conduction level scan signals to odd-numbered scan lines SL1, SL3, and ... while repeating the above process.

[0110] exist Figure 5and Figure 6 In this context, the descriptions of odd-numbered numbering classes ST1, ST3, and ... can be applied essentially equivalently to even-numbered numbering classes ST2, ST4, and ... Figure 5 and Figure 6 The driving methods for levels shown are merely illustrative, and conventional driving methods for levels can be used to construct embodiments of this disclosure.

[0111] Figures 7 to 12 This is a diagram illustrating the first and second frame time periods according to embodiments of the present disclosure. (See diagram below.) Figure 2B As shown, it is assumed that the duty cycle (or number of periods) of the (1-1) transmit control signal EM11 of the display device 10 is 4. That is, the number of pulses of the (1-1) transmit control signal EM11 included in one period (e.g., FP1, SFP1, or SFP2) is 4 (or the duty cycle included in the first frame period FP1 is 4, and the duty cycle included in the second frame period FP2 is 8). However, the duty cycle (or number of periods) of the transmit control signal is merely illustrative, and this disclosure is not limited thereto.

[0112] The display device 10 can operate in a first display mode including a plurality of first frame periods FP1, or in a second display mode including a plurality of second frame periods FP2. The second frame periods FP2 can be longer than the first frame periods FP1. For example, the second frame periods FP2 can be an integer multiple of the first frame periods FP1. In other words, the second frame periods FP2 can be 2p times the first frame periods FP1. Here, p can be an integer greater than 0. Figure 7 In the embodiment shown, the second frame time period FP2 is twice the first frame time period FP1.

[0113] The first display mode is suitable for displaying moving images because the input images (frames) are displayed at a high frequency, and the second display mode is suitable for displaying still images because the input images (frames) are displayed at a low frequency. When a still image is detected while displaying moving images, the mode of the display device 10 can be changed from the first display mode to the second display mode. Furthermore, when a moving image is detected while displaying still images, the mode of the display device 10 can be changed from the second display mode back to the first display mode.

[0114] Reference Figure 7 For ease of description, the description will primarily focus on the j-th data line DLj and pixels PX1j and PX2j. The first pixel PX1j is connected to the j-th data line DLj and the first scan line SL1, and the second pixel PX2j is connected to the j-th data line DLj and the second scan line SL2.

[0115] In each first frame period FP1, the data driver 12 can sequentially apply data voltages corresponding to the scan lines to the data lines. For example, the data driver 12 can sequentially apply data voltages DT1, DT2, ..., DT(n-1), and DTn to the j-th data line DLj. Assuming the first frame period FP1 is 1 / 60 second, the first data voltage DT1 can be supplied to the first pixel PX1j at 60Hz. Therefore, the first pixel PX1j emits light with the highest brightness at the time the first data voltage DT1 is applied, and then the brightness may gradually decrease due to leakage current. (Refer to...) Figure 7 The image shows the brightness waveform of the first pixel PX1j in multiple first frame time periods FP1.

[0116] Each second frame period FP2 may include a first subframe period SFP1 and a second subframe period SFP2. The first subframe period SFP1 and the second subframe period SFP2 may have the same length. For example, when assuming the second frame period FP2 is 1 / 30 of a second, the first subframe period SFP1 and the second subframe period SFP2 may each be 1 / 60 of a second.

[0117] In each first subframe period SFP1, data driver 12 can sequentially apply data voltages corresponding to odd-numbered pixel rows to the data lines. For example, data driver 12 can sequentially apply data voltages DT1, DT3, ..., DT(n-1) to the j-th data line DLj. In each second subframe period SFP2, data driver 12 can sequentially apply data voltages corresponding to even-numbered pixel rows to the data lines. For example, data driver 12 can sequentially apply data voltages DT2, DT4, ..., DTn to the j-th data line DLj.

[0118] Therefore, the first data voltage DT1 can be supplied to the first pixel PX1j at 30Hz. Thus, the first pixel PX1j emits light with the highest brightness during the time the first data voltage DT1 is applied, and then the brightness gradually decreases due to leakage current. (Refer to...) Figure 7 The figure shows the brightness waveform of the second pixel PX2j during multiple second frame periods FP2.

[0119] The first pixel PX1j and the second pixel PX2j are positioned adjacent to each other, for example, along the column direction, and therefore, the first data voltage DT1 and the second data voltage DT2 in a normal input image can usually be equal to or similar to each other.

[0120] Because the times when the first pixel PX1j has the highest brightness and the times when the second pixel PX2j has the highest brightness are alternately positioned, the user can perceive the image as 60Hz and perceive the average brightness waveform AVG of the first pixel PX1j and the second pixel PX2j as brightness. In this case, even when the image is displayed at 30Hz, the user can perceive the image as if it were displayed at 60Hz. Therefore, although a mode change occurs between the first display mode and the second display mode, flickering observed due to the difference in brightness waveforms can be prevented. However, as will be explained later... Figure 12 As described, when the mode of the display device 10 changes from a first display mode to a second display mode or from a second display mode to a first display mode during operation of a display device using an AID dimming method that adjusts the duty cycle of the transmission control signal, the duty cycle of the transmission control signal can be changed for each position of the plurality of pixels 14. Therefore, a brightness difference occurs for each position of the plurality of pixels 14, and thus the image quality characteristics may deteriorate.

[0121] Reference Figure 8 This shows the control signals in the first frame time period FP1.

[0122] During the first frame period FP1, the timing controller 11 can apply a first clock signal CK1 and a third clock signal CK3 at the conduction level to the first clock line CKL1 and the third clock line CKL3, respectively, and apply a second clock signal CK2 and a fourth clock signal CK4 at the conduction level to the second clock line CKL2 and the fourth clock line CKL4, respectively. The first clock signal CK1 to the fourth clock signal CK4 can have different phases. For example, the first clock signal CK1, the second clock signal CK2, the third clock signal CK3, and the fourth clock signal CK4 at the conduction level can be supplied sequentially in the order of first clock line CKL1, second clock line CKL2, third clock line CKL3, and fourth clock line CKL4. For example, the period of each of the first clock signal CK1, the second clock signal CK2, the third clock signal CK3, and the fourth clock signal CK4 at the conduction level can have four horizontal periods.

[0123] Furthermore, the timing controller 11 can apply a pass-through level scan start signal FLM to the scan start line FLML. The pass-through level scan start signal FLM can be configured to overlap with a pass-through level first clock signal CK1 and a pass-through level second clock signal CK2. For example, the length of the pass-through level scan start signal FLM can cover two horizontal time periods.

[0124] During the first frame period FP1, the scan driver 13 can sequentially apply the on-level scan signals SS1, SS2, SS3 and SS4 to the first scan line SL1, the second scan line SL2, the third scan line SL3 and the fourth scan line SL4.

[0125] Reference Figure 6 The driving method shown generates a first scan signal SS1 at the conduction level, corresponding to the third clock signal CK3 at the conduction level. Furthermore, a second scan signal SS2 at the conduction level is generated, corresponding to the fourth clock signal CK4 at the conduction level. Similarly, a third scan signal SS3 at the conduction level is generated, corresponding to the first clock signal CK1 at the conduction level. Furthermore, a fourth scan signal SS4 at the conduction level is generated, corresponding to the second clock signal CK2 at the conduction level.

[0126] The data driver 12 can supply data voltage to the data lines synchronously with the first scan signal SS1, the second scan signal SS2, the third scan signal SS3, and the fourth scan signal SS4. For example, the data driver 12 can supply data voltage in the current horizontal period in accordance with the grayscale latched by the data enable signal DE with a logic high level in the previous horizontal period.

[0127] Reference Figure 9 The diagram illustrates the control signals during the first subframe period SFP1 within the second frame period FP2. Specifically, it shows the control signals during the first subframe period SFP1, excluding the data blank period BPC.

[0128] During the first subframe period SFP1, the timing controller 11 can apply the first clock signal CK1 and the third clock signal CK3 at the on level to the first clock line CKL1 and the third clock line CKL3, and keep the second clock signal CK2 and the fourth clock signal CK4 at the off level. In this embodiment, the period of the first clock signal CK1 and the third clock signal CK3 at the on level in the first subframe period SFP1 applied to the first clock line CKL1 and the third clock line CKL3 can be shorter than the period of the first clock signal CK1 and the third clock signal CK3 at the on level in the first frame period FP1 applied to the first clock line CKL1 and the third clock line CKL3. For example, the period of each of the first clock signal CK1 and the third clock signal CK3 at the on level can have two horizontal periods.

[0129] The timing controller 11 can apply a pass-through level scan start signal FLM to the scan start line FLML. The pass-through level scan start signal FLM can be configured to overlap with a pass-through level first clock signal CK1. For example, the length of the pass-through level scan start signal FLM can cover a horizontal time period.

[0130] During the first subframe period SFP1, the scan driver 13 can apply the first scan signal SS1 and the third scan signal SS3 at the on level to the first scan line SL1 and the third scan line SL3, and maintain the second scan signal SS2 and the fourth scan signal SS4 at the off level. The period during which the first scan signal SS1 and the third scan signal SS3 at the on level in the first subframe period SFP1 is applied to the first scan line SL1 and the third scan line SL3 can be shorter than the period during the first frame period FP1.

[0131] The data driver 12 can supply data voltage to the data line synchronously with the first scan signal SS1 and the third scan signal SS3 at the on level.

[0132] Reference Figure 10 The diagram illustrates the control signals during the data blanking period BPC in the second frame period FP2. During the data blanking period BPC, the following signals are maintained at off levels: a first clock signal CK1, a second clock signal CK2, a third clock signal CK3, and a fourth clock signal CK4; a first scan signal SS1, a second scan signal SS2, a third scan signal SS3, and a fourth scan signal SS4 at off levels; and a scan start signal FLM at off levels.

[0133] During the data blank period (BPC), the entire or at least part of the data driver 12 (gamma amplifier, digital logic circuit) is de-energized, thereby reducing power consumption.

[0134] Reference Figure 11 This illustrates the control signals during the second subframe period SFP2 within the second frame period FP2. Specifically, Figure 11 The control signals are shown during the second subframe period SFP2, excluding the data blank period BPC.

[0135] During the second subframe period SFP2, the timing controller 11 may apply the on-level second clock signal CK2 and the fourth clock signal CK4 to the second clock line CKL2 and the fourth clock line CKL4, and maintain the first clock signal CK1 and the third clock signal CK3, which are applied to the first clock line CKL1 and the third clock line CKL3, at the off level. The period of the on-level second clock signal CK2 and the fourth clock signal CK4 applied to the second clock line CKL2 and the fourth clock line CKL4 during the second subframe period SFP2 may be shorter than the period of the on-level second clock signal CK2 and the fourth clock signal CK4 applied to the second clock line CKL2 and the fourth clock line CKL4 during the first frame period FP1. For example, the period of each of the on-level second clock signal CK2 and the fourth clock signal CK4 may have two horizontal periods.

[0136] Furthermore, the timing controller 11 can apply a pass-through level scan start signal FLM to the scan start line FLML. The pass-through level scan start signal FLM can be configured to overlap with a pass-through level second clock signal CK2. For example, the length of the pass-through level scan start signal FLM can cover a horizontal time period.

[0137] During the second subframe period SFP2, scan driver 13 can apply the on-level second scan signal SS2 and the fourth scan signal SS4 to the second scan line SL2 and the fourth scan line SL4, and maintain the first scan signal SS1 and the third scan signal SS3, which are applied to the first scan line SL1 and the third scan line SL3, at the off level. The period during which the on-level second scan signal SS2 and the fourth scan signal SS4 are applied to the second scan line SL2 and the fourth scan line SL4 in the second subframe period SFP2 can be shorter than the period during the first frame period FP1.

[0138] The data driver 12 can supply data voltage to the data line synchronously with the on-level second scan signal SS2 and fourth scan signal SS4.

[0139] The data blank period (BPC) can be the remaining period after the data driver 12 in each of the first subframe period (SFP1) and the second subframe period (SFP2) stops supplying data voltage. During the data blank period (BPC), all or at least a portion of the data driver 12 (gamma amplifier, digital logic circuitry) is de-energized, thereby reducing power consumption.

[0140] Reference Figure 12 As mentioned above Figure 2BAs described in the description, in the display device 10 according to the embodiments of the present disclosure, the duty cycle (or number of periods) of the transmitted control signal can be approximately 4 (or the duty cycle is 4 when the display device 10 is driven in a first display mode, and 8 when the display device 10 is driven in a second display mode). That is, in each of the first frame period FP1, the first subframe period SFP1, and the second subframe period SFP2, the number of pulses of the transmitted control signal can be 4, except for the time when the mode of the display device 10 changes from the first display mode (e.g., 60Hz) to the second display mode (e.g., 30Hz) or the time when the mode of the display device 10 changes from the second display mode to the first display mode. For the convenience of description, Figure 12 In the diagram, the off period EM_OFF of the transmit control signal is indicated by a black square, and the on period EM_ON of the transmit control signal is indicated by a blank area.

[0141] In the first display mode, during the first frame period FP1, feed is provided to all scan lines SL1, SL2, SL3, ... and SLm (see... Figure 1 The scan signals (e.g., first scan signal SS1 to fourth scan signal SS4, see...) Figure 8 (They can be supplied sequentially.) For the sake of convenience, in Figure 12 In the middle, this is indicated by the first slash SS_all.

[0142] During the time period between the first diagonal line SS_all, multiple pixels 14 (see...) Figure 1 The device can emit no light during the off period EM_OFF of the (1-1) transmission control signal EM11, and emit light during the on period EM_ON of the (1-1) transmission control signal EM11. Therefore, when the interval between the first diagonal lines SS_all is constant in the first display mode, the emission time of the plurality of pixels 14 is also constant. Therefore, the user of the display device 10 does not observe flickering.

[0143] In the second display mode, during the first subframe period SFP1, odd-numbered scan lines SL1, SL3, ... and SLm-1 are supplied (see... Figure 1 The scan signals (e.g., first scan signal SS1 and third scan signal SS3, see...) Figure 9 (They can be supplied sequentially.) For the sake of convenience, in Figure 12 In this context, this is indicated by the second slash SS_odd. Similarly, during the second subframe period SFP2, even-numbered scan lines SL2, SL4, ... and SLm are supplied (see...). Figure 1 The scan signals (e.g., the second scan signal SS2 and the fourth scan signal SS4, see...) Figure 11(They can be supplied sequentially.) For the sake of convenience, in Figure 12 In this context, it is indicated by the third slash SS_even. See above for reference. Figures 8 to 11 As described, the total time required to supply odd-numbered scan signals during the first subframe period SFP1 and the total time required to supply even-numbered scan signals during the second subframe period SFP2 can each be half the time required to supply all scan signals in the first frame period FP1. In other words, the slopes of the second slash SS_odd and the third slash SS_even can be twice the slope of the first slash SS_all.

[0144] During the time period between the second slash SS_odd and the third slash SS_even, multiple pixels 14 (see...) Figure 1 The device can emit no light during the off period EM_OFF of the first (1-1) transmission control signal EM11, and emit light during the on period EM_ON of the first (1-1) transmission control signal EM11. Therefore, when the interval between the second diagonal line SS_odd and the third diagonal line SS_even is constant in the second display mode, the emission time of the multiple pixels 14 is also constant. Therefore, the user of the display device 10 does not observe flickering.

[0145] On the other hand, the boundary where the display device 10 changes from the first display mode to the second display mode will be described. Since the slopes of the first diagonal line SS_all and the second diagonal line SS_odd are different from each other, the interval between the first diagonal line SS_all and the second diagonal line SS_odd may not be constant. For example, the interval between the first diagonal line SS_all and the second diagonal line SS_odd may vary. Figure 1 The ratio of the off-time of the transmission control signal to the frame period (FP1, SFP1, or SFP2) shown in the diagram decreases as the first scan line SL1 approaches the m-th scan line SLm. Therefore, the ratio of the off-time of the transmission control signal to the frame period (FP1, SFP1, or SFP2) can be varied depending on the position of the plurality of pixels 14. For example, at 1 / 4 and 3 / 4 points in one direction (e.g., the vertical direction) of the plurality of pixels 14, the ratio of the off-time of the transmission control signal to the frame period (FP1, SFP1, or SFP2) can be approximately 43.75%. At 2 / 4 and 4 / 4 points, the ratio of the off-time of the transmission control signal to the frame period (FP1, SFP1, or SFP2) can be approximately 50%. Therefore, because the transmission period varies depending on the position of the plurality of pixels 14, the user of the display device 10 may perceive flickering.

[0146] Furthermore, the boundary where the display device 10 changes from the second display mode to the first display mode will be described. Since the slopes of the first diagonal line SS_all and the third diagonal line SS_even are different from each other, the interval between the first diagonal line SS_all and the third diagonal line SS_even may not be constant. For example, the interval between the first diagonal line SS_all and the third diagonal line SS_even may vary. Figure 1 The ratio of the off-time of the transmission control signal to the frame period (FP1, SFP1, or SFP2) shown in the diagram increases as the first scan line SL1 approaches the m-th scan line SLm. Therefore, the ratio of the off-time of the transmission control signal to the frame period (FP1, SFP1, or SFP2) can be varied depending on the position of the plurality of pixels 14. For example, at 1 / 4 and 3 / 4 points in one direction (e.g., the vertical direction) of the plurality of pixels 14, the ratio of the off-time of the transmission control signal to the frame period (FP1, SFP1, or SFP2) can be approximately 56.25%. At 2 / 4 and 4 / 4 points, the ratio of the off-time of the transmission control signal to the frame period (FP1, SFP1, or SFP2) can be approximately 50%. Therefore, because the transmission period varies depending on the position of the plurality of pixels 14, the user of the display device 10 may observe flickering.

[0147] In the following text, and later referred to Figures 13 to 16 A driving method for a display device used to prevent flickering is described.

[0148] Figures 13 to 16 This is a diagram illustrating the first and second frame time periods according to embodiments of the present disclosure. (See diagram below.) Figure 2B As shown, it is assumed that the duty cycle (or number of cycles) of the (1-1)th transmit control signal EM11 of the display device 10 is 4. That is, the number of pulses of the (1-1)th transmit control signal EM11 included in one cycle (e.g., FP1, SFP1, or SFP2) is 4.

[0149] exist Figure 13 In the embodiment shown, the brightness waveform and driving method of the first pixel PX1j in the first frame time period FP1 are similar to... Figure 7 Those shown are the same. Furthermore, in Figure 13 In the embodiment shown, the individual luminance waveforms and average luminance waveforms AVG of the first pixel PX1j and the second pixel PX2j in the second frame time period FP2 are compared with... Figure 7 Those shown are essentially the same.

[0150] However, Figure 13 The driving method for the second frame period FP2 in the embodiment shown is similar to Figure 7 The implementation shown differs in that each of the first subframe period SFP1 and the second subframe period SFP2 does not include a data blank period BPC. For example, Figure 13 The length of each of the first subframe period SFP1 and the second subframe period SFP2 shown in the figure can be equal to Figure 7 The length of each of the first subframe period SFP1 and the second subframe period SFP2 shown in the diagram. Figure 13 In the embodiment shown, the data driver 12 can be connected to... Figure 7 The data voltage is supplied during the equal time periods shown.

[0151] Reference Figure 14 This shows the control signals during the first subframe period SFP1 in the second frame period FP2.

[0152] During the first subframe period SFP1, the timing controller 11 can apply the first clock signal CK1 and the third clock signal CK3 at the on level to the first clock line CKL1 and the third clock line CKL3, and keep the second clock signal CK2 and the fourth clock signal CK4 at the off level. In both the first frame period FP1 and the first subframe period SFP1, the periods for applying the first clock signal CK1 and the third clock signal CK3 at the on level to the first clock line CKL1 and the third clock line CKL3 can be the same. For example, the period of each of the first clock signal CK1 and the third clock signal CK3 at the on level can have four horizontal periods.

[0153] Furthermore, the timing controller 11 can apply a pass-through level scan start signal FLM to the scan start line FLML. The length of the pass-through level scan start signal FLM can be set to overlap with the pass-through level first clock signal CK1. For example, as... Figure 14 As shown, the on-level scan start signal FLM can cover two horizontal time periods. However, in Figure 9 In this context, the on-level scan start signal FLM can cover only one horizontal time period.

[0154] During the first subframe period SFP1, the scan driver 13 can apply the first scan signal SS1 and the third scan signal SS3 at the on level to the first scan line SL1 and the third scan line SL3, and keep the second scan signal SS2 and the fourth scan signal SS4 at the off level. The periods for applying the first scan signal SS1 and the third scan signal SS3 at the on level to the first scan line SL1 and the third scan line SL3 can be the same during both the first frame period FP1 and the first subframe period SFP1.

[0155] Data driver 12 can supply data voltage to the data lines synchronously with the on-level first scan signal SS1 and the third scan signal SS3. Since it is not necessary to supply data voltage synchronously with the second scan signal SS2 and the fourth scan signal SS4, the period of the on-level data enable signal DE in the first subframe period SFP1 can be set to be longer than the period of the on-level data enable signal DE in the first frame period FP1. Therefore, due to the increased period of data voltage change by data driver 12, the dynamic power required by data driver 12 is reduced.

[0156] Reference Figure 15 This shows the control signals during the second subframe period SFP2 in the second frame period FP2.

[0157] During the second subframe period SFP2, the timing controller 11 can apply the on-level second clock signal CK2 and the fourth clock signal CK4 to the second clock line CKL2 and the fourth clock line CKL4, and maintain the first clock signal CK1 and the third clock signal CK3, which are applied to the first clock line CKL1 and the third clock line CKL3, at the off level. In the first frame period FP1 and the second subframe period SFP2, the periods for applying the on-level second clock signal CK2 and the fourth clock signal CK4 to the second clock line CKL2 and the fourth clock line CKL4 can be the same. For example, the period of each of the on-level second clock signal CK2 and the fourth clock signal CK4 can have four horizontal periods.

[0158] Furthermore, the timing controller 11 can apply a pass-through level scan start signal FLM to the scan start line FLML. The pass-through level scan start signal FLM can be configured to overlap with a pass-through level second clock signal CK2. For example, as... Figure 15 As shown, the scan start signal FLM with a conduction level can have two horizontal time periods. However, in Figure 11 In this context, the on-level scan start signal FLM can cover only one horizontal time period.

[0159] During the second subframe period SFP2, the scan driver 13 can apply the on-level second scan signal SS2 and the fourth scan signal SS4 to the second scan line SL2 and the fourth scan line SL4, and maintain the first scan signal SS1 and the third scan signal SS3 supplied to the first scan line SL1 and the third scan line SL3 at the off level. During the first frame period FP1 and the second subframe period SFP2, the periods for applying the on-level second scan signal SS2 and the fourth scan signal SS4 to the second scan line SL2 and the fourth scan line SL4 can be the same.

[0160] The data driver 12 can supply data voltage synchronously with the on-level second scan signal SS2 and the fourth scan signal SS4. Since it does not need to supply data voltage synchronously with the first scan signal SS1 and the third scan signal SS3, the period of the on-level data enable signal DE in the second subframe period SFP2 can be longer than the period of the on-level data enable signal DE in the first frame period FP1. Therefore, due to the increased time for the data driver 12 to supply data voltage, the dynamic power required by the data driver 12 can be reduced.

[0161] Reference Figure 16 As mentioned above Figure 2B As described in the description, in the display device 10 according to the embodiments of the present disclosure, the duty cycle (or number of periods) of the transmission control signal can be 4. That is, in each of the first frame period FP1 (e.g., 60Hz) of the first display mode and the first subframe period SFP1 and the second subframe period SFP2 (e.g., 30Hz) of the second display mode, the number of pulses of the transmission control signal can be 4. For the convenience of description, Figure 16 In the diagram, the off period EM_OFF of the transmit control signal is indicated by a black square, and the on period EM_ON of the transmit control signal is indicated by a blank area.

[0162] In the first display mode, feed is supplied to all scan lines SL1, SL2, SL3, ... and SLm (see... Figure 1 The scan signals (e.g., first scan signal SS1 to fourth scan signal SS4, see...) Figure 8 (This can be supplied sequentially during the first frame time period FP1. For ease of description, in...) Figure 16 In the middle, this is indicated by the first slash SS_all.

[0163] During the time period between the first diagonal line SS_all, multiple pixels 14 (see...) Figure 1 The device can emit no light during the off period EM_OFF of the (1-1) transmission control signal EM11, and emit light during the on period EM_ON of the (1-1) transmission control signal EM11. Therefore, when the interval between the first diagonal lines SS_all in the first display mode is constant, the emission time of the plurality of pixels 14 is also constant. Therefore, the user of the display device 10 does not observe flickering.

[0164] In the second display mode, supplies are provided to odd-numbered scan lines SL1, SL3, ... and SLm-1 (see... Figure 1 The scan signals (e.g., first scan signal SS1 and third scan signal SS3, see...) Figure 9 (This can be supplied sequentially during the first subframe SFP1 period. For ease of description, in...) Figure 16 In this context, this is indicated by the second slash SS_odd. Similarly, this is supplied to even-numbered scan lines SL2, SL4, ... and SLm (see...). Figure 1 The scan signals (e.g., the second scan signal SS2 and the fourth scan signal SS4, see...) Figure 11 (This can be sequentially supplied during the second subframe SFP2 period. For ease of description, in...) Figure 16 In this context, it is indicated by the third slash SS_even. See above for reference. Figure 8 , Figure 14 and Figure 15 As described, the total time required to supply odd-numbered scan signals during the first subframe period SFP1 and the total time required to supply even-numbered scan signals during the second subframe period SFP2 can each be equal to the total time required to supply all scan signals during the first frame period FP1. In other words, the slopes of the second slash SS_odd and the third slash SS_even can be equal to the slope of the first slash SS_all.

[0165] During the time period between the second slash SS_odd and the third slash SS_even, multiple pixels 14 (see...) Figure 1 The device can emit no light during the off period EM_OFF of the first (1-1) transmission control signal EM11, and emit light during the on period EM_ON of the first (1-1) transmission control signal EM11. Therefore, when the interval between the second diagonal line SS_odd and the third diagonal line SS_even is constant in the second display mode, the emission time of the multiple pixels 14 is also constant. Therefore, the user of the display device 10 does not observe flickering.

[0166] At the same time, with Figures 7 to 12 The implementation methods shown are different, in Figures 13 to 16 In the illustrated embodiment, the boundary time for the display device 10 to change from a first display mode to a second display mode will be described. Since the slopes of the first slant SS_all and the second slant SS_odd are the same, the interval between the first slant SS_all and the second slant SS_odd can be maintained constant. Therefore, at each location of the plurality of pixels 14, the ratio of the off-time of the transmission control signal to the frame time (FP1, SFP1, or SFP2) can be the same. For example, at all points of the plurality of pixels 14, the ratio of the off-time of the transmission control signal to the frame time (FP1, SFP1, or SFP2) can be approximately 50%. Therefore, the transmission time is the same at each location of the plurality of pixels 14, and thus, the user of the display device 10 does not observe flickering.

[0167] Similarly, the boundary time for the display device 10 to change from the second display mode to the first mode will be described. Since the slopes of the first slant SS_all and the third slant SS_even are the same, the interval between the first slant SS_all and the third slant SS_even can be maintained constant. Therefore, at each location of the plurality of pixels 14, the ratio of the off-time of the transmission control signal to the frame time (FP1, SFP1, or SFP2) can be the same. For example, at all points of the plurality of pixels 14, the ratio of the off-time of the transmission control signal to the frame time (FP1, SFP1, or SFP2) can be approximately 50%. Therefore, the transmission time is the same at each location of the plurality of pixels 14, and thus, the user of the display device 10 does not observe flickering.

[0168] Other embodiments will be described below. In the embodiments described below, the description of components that are the same as those in the embodiments described above will be omitted and simplified, and the description will mainly focus on the parts that are different from those in the embodiments described above.

[0169] Figure 17A and Figure 17B This is a diagram illustrating the first and third frame time periods according to another embodiment of the present disclosure. (See diagram below.) Figure 2B As described herein, it is assumed that the duty cycle (or number of periods) of the transmission control signal in the display device 10 is 4. That is, the number of pulses of the transmission control signal included in one period (e.g., FP1, SFP1_1, SFP2_1, or SFP3_1) is 4 (or the duty cycle included in the first frame period FP1 is 4, and the duty cycle included in the third frame period FP3 is 12). However, the duty cycle (or number of periods) of the transmission control signal is merely illustrative, and this disclosure is not limited thereto.

[0170] Figure 17A The implementation method with carry level 3 shown is similar to... Figure 13 The implementation shown has a different carry level of 2. The interval (or unit) between stages that transmit carry signals can be specified as the carry level. Although not shown in the figure, the scan driver 13 (see Figure 1 It may include six clock signal lines, and the period of the clock signal may have six horizontal time intervals. For example, refer to Figure 4 When the first input terminal 1001 of the fourth stage ST4 receives the carry signal transmitted from the output terminal 1004 of the second stage ST2, the carry level is 2.

[0171] At the same time, Figure 17A In the first frame time period FP1, the brightness waveform and driving method of the first pixel PX1j are compared with... Figure 7 Those shown are the same. Furthermore, Figure 17AThe driving method for the third frame period FP3 in the embodiment shown is similar to Figure 13 The driving method for the second frame period FP2 in the illustrated embodiment is essentially the same, except that each of the (1_1) subframe periods SFP1_1, (2_1) subframe periods SFP2_1, and (3_1) subframe periods SFP3_1 in the third frame period FP3 does not include a data blank period BPC. Specifically, the period of the clock signal for the (1_1) subframe periods SFP1_1, (2_1) subframe periods SFP2_1, and (3_1) subframe periods SFP3_1 can be maintained to be the same as the period of the clock signal for the first frame period FP1. For example, the period of the clock signal can have six horizontal periods in both the first frame period FP1 and the third frame period FP3.

[0172] Each third frame period FP3 may include subframe period (1_1) SFP1_1, subframe period (2_1) SFP2_1, and subframe period (3_1) SFP3_1. The lengths of subframe period (1_1) SFP1_1, subframe period (2_1) SFP2_1, and subframe period (3_1) SFP3_1 may be equal to each other. For example, when assuming the third frame period FP3 is 1 / 20 second, each of subframe period (1_1) SFP1_1, subframe period (2_1) SFP2_1, and subframe period (3_1) SFP3_1 may be 1 / 60 second.

[0173] In each subframe period (1_1) SFP1_1, the data driver 12 can sequentially apply data voltages corresponding to the (3k-2)th pixel row (k is an integer greater than 0) to the data lines. For example, the data driver 12 can sequentially apply data voltages DT1, DT4, ..., and DT(3n-2) to the j-th data line DLj. Similarly, in each subframe period (2_1) SFP2_1, the data driver 12 can sequentially apply data voltages corresponding to the (3k-1)th pixel row to the data lines. For example, the data driver 12 can sequentially apply data voltages DT2, DT5, ..., and DT(3n-1) to the j-th data line DLj. Likewise, in each subframe period (3_1) SFP3_1, the data driver 12 can sequentially apply data voltages corresponding to the 3kth pixel row to the data lines. For example, the data driver 12 can sequentially apply data voltages DT3, DT6, ..., and DT3n to the j-th data line DLj.

[0174] Therefore, the first data voltage DT1 can be supplied to the first pixel PX1j at a frequency of 20Hz. Consequently, the first pixel PX1j emits light with the highest brightness during the time the first data voltage DT1 is applied, and then the brightness may gradually decrease due to leakage current. (Refer to...) Figure 17AThe diagram shows the brightness waveform of the first pixel PX1j corresponding to multiple third frame periods FP3. A second data voltage DT2 can be applied to the second pixel PX2j at 20Hz. Therefore, the second pixel PX2j emits light with the highest brightness at the time the second data voltage DT2 is applied, and then the brightness may gradually decrease due to leakage current. (Refer to...) Figure 17A The diagram shows the brightness waveform of the second pixel PX2j corresponding to multiple third frame periods FP3. A third data voltage DT3 can be applied to the third pixel PX3j at 20Hz. Therefore, the third pixel PX3j emits light with the highest brightness during the time the third data voltage DT3 is applied, and then the brightness can gradually decrease due to leakage current. (Refer to...) Figure 17A The figure shows the brightness waveform of the third pixel PX3j corresponding to multiple third frame time periods FP3.

[0175] The first pixel PX1j, the second pixel PX2j, and the third pixel PX3j are positioned adjacent to each other, and therefore, the first data voltage DT1, the second data voltage DT2, and the third data voltage DT3 in a normal input image are usually equal to or similar to each other.

[0176] The times when the first pixel PX1j, the second pixel PX2j, and the third pixel PX3j have the highest brightness are continuously located and repeated for each frame. Therefore, the user can recognize the image as 60Hz and identify the average brightness waveform (AVG) of the first pixel PX1j, the second pixel PX2j, and the third pixel PX3j as brightness. In this case, even when the image is displayed at 20Hz, the user can recognize the image as if it were displayed at 60Hz. Therefore, when the image is displayed in the second display mode, and the display device 10 is driven at a lower frequency than in the first display mode, flickering due to differences in the brightness waveform can be prevented.

[0177] In addition, refer to Figure 17B As mentioned above Figure 2B As described in the description, in the display device 10 according to the embodiments of the present disclosure, the duty cycle (or number of periods) of the transmission control signal can be 4. That is, the number of pulses of the transmission control signal in each of the first frame period FP1 of the first display mode (e.g., 60Hz) and the (1_1) subframe period SFP1_1, the (2_1) subframe period SFP2_1 and the (3_1) subframe period SFP3_1 of the second display mode (e.g., 20Hz) can be 4. Figure 17B In the diagram, the off period EM_OFF of the transmit control signal is indicated by a black square, and the on period EM_ON of the transmit control signal is indicated by a blank area.

[0178] In the first display mode, feed is supplied to all scan lines SL1, SL2, SL3, ... and SLm (see... Figure 1 The scan signals (e.g., first scan signal SS1 to fourth scan signal SS4, see...) Figure 8 (This can be supplied sequentially during the first frame time period FP1. For ease of description, in...) Figure 17B In the middle, this is indicated by the first slash SS_all.

[0179] During the time period between the first diagonal line SS_all, multiple pixels 14 (see...) Figure 1 The device can emit no light during the off period EM_OFF of the (1-1) transmission control signal EM11, and emit light during the on period EM_ON of the (1-1) transmission control signal EM11. Therefore, when the interval between the first diagonal lines SS_all in the first display mode is constant, the emission time of the plurality of pixels 14 is also constant. Therefore, the user of the display device 10 does not observe flickering.

[0180] In the second display mode, supplies are provided to the (3m-2)th scan lines SL1, SL4, ... and SL3m-2 (see... Figure 1 The scan signals (e.g., first scan signal SS1 and fourth scan signal SS4) can be sequentially supplied during the (1_1) subframe time period SFP1_1. For ease of description, in Figure 17B In this context, this is indicated by the (2_1)th slash SS_(3m-2). Furthermore, supplies are provided to the (3m-1)th scan lines SL2, SL5, ... and SL3m-1 (see...). Figure 1 The scan signals (e.g., the second scan signal SS2 and the fifth scan signal) can be sequentially supplied during the (2_1) subframe period SFP2_1. For ease of description, in Figure 17B In this context, this is indicated by the slash SS_(3m-1) of the (3_1)th scan line. Similarly, the slashes supplied to the 3m scan lines SL3, SL6, ... and SL3m (see...) Figure 1 The scan signals (e.g., the third scan signal SS3 and the sixth scan signal) can be sequentially supplied during the (3_1) subframe time period SFP3_1. For ease of description, in Figure 17B In the middle, this is indicated by the slash SS_(3m) of the (4_1)th line.

[0181] The total time required to supply the (3m-2)th scan signal during subframe (1_1) SFP1_1, the total time required to supply the (3m-1)th scan signal during subframe (2_1) SFP2_1, and the total time required to supply the 3mth scan signal during subframe (3_1) SFP3_1 can each be equal to the total time required to supply all scan signals in the first frame period FP1. In other words, the slopes of the (2_1) diagonal SS_(3m-2), the (3_1) diagonal SS_(3m-1), and the (4_1) diagonal SS_(3m) can be equal to the slope of the first diagonal SS_all.

[0182] During the time interval between the (2_1)th diagonal SS_(3m-2), the (3_1)th diagonal SS_(3m-1), and the (4_1)th diagonal SS_(3m), multiple pixels 14 (see Figure 1 The device can emit no light during the off period EM_OFF of the (1-1) transmission control signal EM11, and emit light during the on period EM_ON of the (1-1) transmission control signal EM11. Therefore, when the interval between the (2_1) diagonal line SS_(3m-2), the (3_1) diagonal line SS_(3m-1), and the (4_1) diagonal line SS_(3m) is constant in the second display mode, the emission time of the plurality of pixels 14 is also constant. Therefore, the user of the display device 10 does not observe flickering.

[0183] Simultaneously, the boundary time for the change of the display device 10 from the first display mode to the second display mode will be described. Since the slopes of the first slant SS_all and the (2_1)th slant SS_(3m-2) are the same, the interval between the first slant SS_all and the (2_1)th slant SS_(3m-2) can be maintained constant. Therefore, at each position of the plurality of pixels 14, the ratio of the off-time of the transmission control signal to the frame time period (FP1, SFP1_1, SFP2_1, or SFP3_1) can be the same. For example, at all points of the plurality of pixels 14, the ratio of the off-time of the transmission control signal to the frame time period (FP1, SFP1_1, SFP2_1, or SFP3_1) can be approximately 50%. Therefore, the transmission time period is the same at each position of the plurality of pixels 14, and therefore, the user of the display device 10 does not observe flickering.

[0184] Similarly, the boundary time for the change of the display device 10 from the second display mode to the first mode will be described. Since the slopes of the first slant SS_all and the (4_1)th slant SS_(3m) are the same, the interval between the first slant SS_all and the (4_1)th slant SS_(3m) can be maintained constant. Therefore, at each location of the plurality of pixels 14, the ratio of the off-time of the transmission control signal to the frame time (FP1, SFP1_1, SFP2_1, or SFP3_1) can be the same. For example, at all points of the plurality of pixels 14, the ratio of the off-time of the transmission control signal to the frame time (FP1, SFP1_1, SFP2_1, or SFP3_1) can be approximately 50%. Therefore, the transmission time is the same at each location of the plurality of pixels 14, and therefore, the user of the display device 10 does not observe flickering.

[0185] Figure 18A and Figure 18B This is a diagram illustrating the first and fourth frame time periods according to another embodiment of the present disclosure. (See diagram below.) Figure 2B As described herein, it is assumed that the duty cycle (or number of periods) of the transmission control signal in the display device 10 is 4 (or the duty cycle included in the first frame period FP1 is 4, and the duty cycle included in the fourth frame period FP4 is 16). That is, the number of pulses of the transmission control signal included in one period (e.g., FP1, SFP1_2, SFP2_2, SFP3_2, or SFP4_2) is 4. However, the duty cycle (or number of periods) of the transmission control signal is merely illustrative, and this disclosure is not limited thereto.

[0186] Figure 18A The implementation method with carry level 4 shown is similar to... Figure 13 The implementation with a carry level of 2 shown is different. Although not shown in the figure, the scan driver 13 (see...) Figure 1 It may include eight clock signal lines, and the period of the clock signal may have eight horizontal time intervals. The interval (or unit) between stages that transmit carry signals may be specified as carry levels. For example, when the first input terminal 1001 of the fifth stage ST5 receives a carry signal transmitted from the output terminal 1004 of the first stage ST1, the carry level is 4.

[0187] At the same time, Figure 18A In the first frame time period FP1, the brightness waveform and driving method of the first pixel PX1j are compared with... Figure 7 Those shown are the same. Furthermore, Figure 18A The driving method for the fourth frame period FP4 in the embodiment shown is similar to Figure 13The driving method for the second frame period FP2 in the illustrated embodiment is substantially the same, except that each of the (1_2)th subframe periods SFP1_2, (2_2)th subframe period SFP2_2, (3_2)th subframe period SFP3_2, and (4_2)th subframe period SFP4_2 in the fourth frame period FP4 does not include a data blank period BPC. Specifically, the period of the clock signal for the (1_2)th subframe period SFP1_2, (2_2)th subframe period SFP2_2, (3_2)th subframe period SFP3_2, and (4_2)th subframe period SFP4_2 can be maintained to be the same as the period of the clock signal for the first frame period FP1. For example, the period of the clock signal can have eight horizontal periods in both the first frame period FP1 and the fourth frame period FP4.

[0188] Each fourth frame period FP4 may include subframe period SFP1_2 (1_2), subframe period SFP2_2 (2_2), subframe period SFP3_2 (3_2), and subframe period SFP4_2 (4_2). The lengths of subframe periods SFP1_2 (1_2), SFP2_2 (2_2), SFP3_2 (3_2), and SFP4_2 (4_2) may be equal. For example, when assuming the fourth frame period FP4 is 1 / 15 of a second, each of subframe periods SFP1_2 (1_2), SFP2_2 (2_2), SFP3_2 (3_2), and SFP4_2 (4_2) may be 1 / 60 of a second.

[0189] In each subframe period (1_2) SFP1_2, the data driver 12 can sequentially apply data voltages corresponding to the (4k-3)th pixel row (k is an integer greater than 0) to the data lines. For example, the data driver 12 can sequentially apply data voltages DT1, DT5, ..., and DT(4n-3) to the j-th data line DLj. Furthermore, in each subframe period (2_2) SFP2_2, the data driver 12 can sequentially apply data voltages corresponding to the (4k-2)th pixel row to the data lines. For example, the data driver 12 can sequentially apply data voltages DT2, DT6, ..., and DT(4n-2) to the j-th data line DLj. Furthermore, in each subframe period (3_2) SFP3_2, the data driver 12 can sequentially apply data voltages corresponding to the (4k-1)th pixel row to the data lines. For example, the data driver 12 can sequentially apply data voltages DT3, DT7, ..., and DT(4n-1) to the j-th data line DLj. Similarly, in each (4_2) subframe period SFP4_2, the data driver 12 can sequentially apply data voltages corresponding to the 4k pixel row to the data lines. For example, the data driver 12 can sequentially apply data voltages DT4, DT8, ..., DT4n to the j-th data line DLj.

[0190] Therefore, the first data voltage DT1 can be supplied to the first pixel PX1j at a frequency of 15Hz. Consequently, the first pixel PX1j emits light with the highest brightness during the time the first data voltage DT1 is applied, and then the brightness may gradually decrease due to leakage current. (Refer to...) Figure 18A The diagram shows the brightness waveform of the first pixel PX1j corresponding to multiple fourth frame periods FP4. Furthermore, a second data voltage DT2 can be applied to the second pixel PX2j at a frequency of 15 Hz. Therefore, the second pixel PX2j emits light with the highest brightness during the time the second data voltage DT2 is applied, and then the brightness may gradually decrease due to leakage current. (Refer to...) Figure 18A The diagram shows the brightness waveform of the second pixel PX2j corresponding to multiple fourth frame periods FP4. Furthermore, a third data voltage DT3 can be applied to the third pixel PX3j at a frequency of 15 Hz. Therefore, the third pixel PX3j emits light with the highest brightness during the time the third data voltage DT3 is applied, and then the brightness gradually decreases due to leakage current. (Refer to...) Figure 18A The diagram illustrates the brightness waveform of the third pixel PX3j corresponding to multiple fourth frame periods FP4. Similarly, a fourth data voltage DT4 can be applied to the fourth pixel PX4j at 15Hz. Therefore, the fourth pixel PX4j emits light with the highest brightness during the time the fourth data voltage DT4 is applied, and then the brightness can gradually decrease due to leakage current. (Refer to...) Figure 18AThe figure shows the brightness waveform of the fourth pixel PX4j corresponding to multiple fourth frame time periods FP4.

[0191] The first pixel PX1j, the second pixel PX2j, the third pixel PX3j, and the fourth pixel PX4j are positioned adjacent to each other, and therefore, the first data voltage DT1, the second data voltage DT2, the third data voltage DT3, and the fourth data voltage DT4 in a normal input image can usually be equal to or similar to each other.

[0192] The times when the first pixel PX1j, the second pixel PX2j, the third pixel PX3j, and the fourth pixel PX4j have the highest brightness are continuously located and repeated for each frame. Therefore, the user can recognize the image as 60Hz and identify the average brightness waveform (AVG) of the first pixel PX1j, the second pixel PX2j, the third pixel PX3j, and the fourth pixel PX4j as brightness. In this case, even when the image is displayed at 15Hz, the user can recognize the image as if it were displayed at 60Hz. Therefore, when displaying an image in the second display mode, if the display device 10 is driven at a lower frequency than in the first display mode, flickering due to differences in the brightness waveform can be prevented.

[0193] In addition, refer to Figure 18B As mentioned above Figure 2B As described in the description, in the display device 10 according to the embodiments of the present disclosure, the duty cycle (or number of periods) of the transmission control signal can be 4. That is, the number of pulses of the transmission control signal in each of the first frame period FP1 in the first display mode (e.g., 60Hz) and the (1_2) subframe period SFP1_2, (2_2) subframe period SFP2_2, (3_2) subframe period SFP3_2 and (4_2) subframe period SFP4_2 in the second display mode (e.g., 15Hz) can be 4. For the convenience of description, Figure 18B In the diagram, the off period EM_OFF of the transmit control signal is indicated by a black square, and the on period EM_ON of the transmit control signal is indicated by a blank area.

[0194] In the first display mode, feed is supplied to all scan lines SL1, SL2, SL3, ... and SLm (see... Figure 1 The scan signals (e.g., first scan signal SS1 to fourth scan signal SS4, see...) Figure 8 (This can be supplied sequentially during the first frame time period FP1. For ease of description, in...) Figure 18B In the middle, this is indicated by the first slash SS_all.

[0195] During the time period between the first diagonal line SS_all, multiple pixels 14 (see...) Figure 1 The device can emit no light during the off period EM_OFF of the (1-1) transmission control signal EM11, and emit light during the on period EM_ON of the (1-1) transmission control signal EM11. Therefore, when the interval between the first diagonal lines SS_all in the first display mode is constant, the emission time of the plurality of pixels 14 is also constant. Therefore, the user of the display device 10 does not observe flickering.

[0196] In the second display mode, supplies are provided to the (4m-3)th scan lines SL1, SL5, ... and SL4m-3 (see... Figure 1 The scan signals (e.g., the first scan signal SS1 and the fifth scan signal) can be sequentially supplied during the (1_2) subframe period SFP1_2. For ease of description, in Figure 18B In this context, this is indicated by the (2_2)th slash SS_(4m-3). Furthermore, supplies are provided to the (4m-2)th scan lines SL2, SL6, ... and SL4m-2 (see...). Figure 1 The scan signals (e.g., the second scan signal SS2 and the sixth scan signal) can be sequentially supplied during the (2_2) subframe period SFP2_2. For the sake of description, in Figure 18B In this context, this is indicated by the (3_2)th slash SS_(4m-2). Furthermore, it is supplied to the (4m-1)th scan lines SL3, SL7, ... and SL4m-1 (see...). Figure 1 The scan signals (e.g., the third scan signal SS3 and the seventh scan signal) can be sequentially supplied during the (3_2) subframe period SFP3_2. For ease of description, in Figure 18B In this context, this is indicated by the (4_2)th slash SS_(4m-1). Similarly, the lines supplied to the 4m scan lines SL4, SL8, ... and SL4m (see...) Figure 1 The scan signals (e.g., the fourth scan signal SS4 and the eighth scan signal) can be sequentially supplied during the (4_2) subframe period SFP4_2. For ease of description, in Figure 18B In the middle, this is indicated by the slash SS_(4m) of the (5_2)th line.

[0197] The total time required to supply the (4m-3)th scan signal during subframe (1_2) SFP1_2, the total time required to supply the (4m-2)th scan signal during subframe (2_2) SFP2_2, the total time required to supply the (4m-1)th scan signal during subframe (3_2) SFP3_2, and the total time required to supply the 4mth scan signal during subframe (4_2) SFP4_2 can each be equal to the total time required to supply all scan signals in the first frame period FP1. In other words, the slopes of the (2_2)th slant SS_(4m-3), the (3_2)th slant SS_(4m-2), the (4_2)th slant SS_(4m-1), and the (5_2)th slant SS_(4m) can be equal to the slope of the first slant SS_all.

[0198] During the time interval between the (2_2)th diagonal SS_(4m-3), the (3_2)th diagonal SS_(4m-2), the (4_2)th diagonal SS_(4m-1), and the (5_2)th diagonal SS_(4m), multiple pixels 14 (see Figure 1 The device can emit no light during the off period EM_OFF of the (1-1) transmission control signal EM11, and emit light during the on period EM_ON of the (1-1) transmission control signal EM11. Therefore, when the interval between the (2_2) diagonal line SS_(4m-3), the (3_2) diagonal line SS_(4m-2), the (4_2) diagonal line SS_(4m-1), and the (5_2) diagonal line SS_(4m) is constant in the second display mode, the emission time of the plurality of pixels 14 is also constant. Therefore, the user of the display device 10 does not observe flickering.

[0199] Simultaneously, the boundary time for the change of the display device 10 from the first display mode to the second display mode will be described. Since the slopes of the first slant SS_all and the (2_2)th slant SS_(4m-3) are the same, the interval between the first slant SS_all and the (2_2)th slant SS_(4m-3) can be maintained constant. Therefore, at each position of the plurality of pixels 14, the ratio of the off-time of the transmission control signal to the frame time period (FP1, SFP1_2, SFP2_2, SFP3_2, or SFP4_2) can be the same. For example, at all points of the plurality of pixels 14, the ratio of the off-time of the transmission control signal to the frame time period (FP1, SFP1_2, SFP2_2, SFP3_2, or SFP4_2) can be approximately 50%. Therefore, the transmission time period is the same at each position of the plurality of pixels 14, and therefore, the user of the display device 10 does not observe flickering.

[0200] Similarly, the boundary time for changing the mode of the display device 10 from the second display mode to the first mode will be described. Since the slopes of the first slant SS_all and the (5_2)th slant SS_(4m) are the same, the interval between the first slant SS_all and the (5_2)th slant SS_(4m) can be kept constant. Therefore, at each position of the plurality of pixels 14, the ratio of the off-time of the transmission control signal to the frame time (FP1, SFP1_2, SFP2_2, SFP3_2 or SFP4_2) can be the same. For example, at all points of the plurality of pixels 14, the ratio of the off-time of the transmission control signal to the frame time (FP1, SFP1_2, SFP2_2, SFP3_2 or SFP4_2) can be about 50%. Therefore, the transmission time is the same for each position of the plurality of pixels 14, and therefore, the user of the display device 10 does not observe flickering.

[0201] In the display device according to this disclosure, the waveform of the clock signal (or scan signal) provided to the scan driver is adjusted. Therefore, flickering can be prevented, and mode switching between progressive scan and interlaced scan can be performed.

[0202] Exemplary embodiments have been disclosed herein, and although specific terminology has been used, it is used and interpreted in a general and descriptive sense only and not for limiting purposes. In some instances, as will be apparent to those skilled in the art upon filing this application, unless specifically instructed otherwise, features, characteristics, and / or elements described in connection with particular embodiments may be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments. Accordingly, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit and scope of this disclosure as set forth in the appended claims.

Claims

1. A display device, comprising: Multiple pixels; A transmit control driver configured to provide transmit control signals to the plurality of pixels; A scan driver configured to provide scan signals to a plurality of scan lines connected to the plurality of pixels; as well as A timing controller is configured to select, based on input image data, whether the display device operates in either a first display mode or a second display mode, wherein in the first display mode the display device is driven at a first frequency, and in the second display mode the display device is driven at a second frequency lower than the first frequency. The first display mode includes multiple first frame time periods, and the second display mode includes multiple second frame time periods. Each of the multiple second frame time periods has at least two sub-frame time periods, and each of the at least two sub-frame time periods is equal to a first frame time period. The total time required to supply the scan signal to the plurality of scan lines in the first frame period, the total time required to supply the scan signal to the odd-numbered scan lines in the plurality of scan lines in a subframe period, and the total time required to supply the scan signal to the even-numbered scan lines in the plurality of scan lines in another subframe period are all the same.

2. The display device according to claim 1, wherein, The timing controller receives the input image data and outputs a clock signal, a scan start signal, and image data.

3. The display device according to claim 2, wherein, The scan driver includes multiple stages connected to multiple clock signal lines provided with the clock signal, and the multiple stages generate the scan signal in response to the scan start signal.

4. The display device according to claim 3, wherein, The carry signal is transmitted to the next level after that, and The second frame time period includes a first subframe time period and a second subframe time period. In the first subframe time period, odd-numbered scan signals from among the multiple scan signals are provided to the multiple pixels. In the second subframe time period, even-numbered scan signals from among the multiple scan signals are provided to the multiple pixels.

5. The display device according to claim 4, wherein, The period of the clock signal in the first frame period is equal to each of the period of the clock signal in the first subframe period and the period of the clock signal in the second subframe period.

6. The display device according to claim 5, wherein, The period of the clock signal in the first frame period, the period of the clock signal in the first subframe period, and the period of the clock signal in the second subframe period each have four horizontal periods.

7. The display device according to claim 4, wherein, The plurality of clock signal lines include a first clock line, a second clock line, a third clock line, and a fourth clock line, and The first clock line and the third clock line are alternately connected to the first clock input terminal and the second clock input terminal of the odd-numbered stages among the plurality of stages, and The second clock line and the fourth clock line are alternately connected to the first clock input terminal and the second clock input terminal of the even-numbered level among the plurality of levels.

8. The display device according to claim 7, wherein, During the first frame period, the timing controller sequentially supplies a first clock signal to the first clock line, a second clock signal to the second clock line, a third clock signal to the third clock line, and a fourth clock signal to the fourth clock line.

9. The display device according to claim 8, wherein, During the first subframe period, the timing controller provides the first clock signal and the third clock signal at the on level to the first clock line and the third clock line, respectively, and provides the second clock signal and the fourth clock signal at the off level to the second clock line and the fourth clock line, respectively.

10. The display device according to claim 8, wherein, During the second subframe period, the timing controller provides the first clock signal and the third clock signal at the off level to the first clock line and the third clock line, respectively, and provides the second clock signal and the fourth clock signal at the on level to the second clock line and the fourth clock line, respectively.

11. The display device of claim 2, further comprising a data driver configured to generate a data signal based on the image data. in, Each of the plurality of pixels emits light with a brightness corresponding to the data signal in response to one of the plurality of scan signals.

12. The display device according to claim 1, wherein, The timing controller includes a brightness controller configured to adjust the duty cycle to the number of pulses of the transmit control signal included in a predetermined time period.

13. The display device according to claim 12, wherein, The brightness controller sets the duty cycle of the transmission control signal to 4 during the first frame period of the first display mode and the sub-frame period of the second display mode.

14. The display device according to claim 12, wherein, During the first frame period and the second frame period, the ratio of the off period of the transmit control signal to the frame period is 50% in all areas of the plurality of pixels.

15. The display device according to claim 1, wherein, The timing controller: The first display mode is selected when the grayscale values ​​of the input image data corresponding to each of the consecutive frames are different from each other. as well as The second display mode is selected when the grayscale value is the same as that of the input image data corresponding to each of the consecutive frames.

Images