Bit line sense amplifier and memory device

Abstract

A bit line sense amplifier includes an amplifier connected between a first sense bit line and a second sense bit line and responsive to a first control signal and a second control signal to detect and amplify a voltage difference between the first bit line and the second bit line, and an equalizer connected between a first power supply line through which the first control signal is provided and a second power supply line through which the second control signal is provided and responsive to an equalization control signal to pre-charge the first bit line and the second bit line with a pre-charge voltage, wherein the equalizer includes an equalization enable transistor having a source connected to the first power supply line and is responsive to the equalization control signal to perform equalization.

Description

Technical Field

[0001] The present invention relates to a bit line sense amplifier for a memory device. Background Technology

[0002] Semiconductor memory devices are used to store data. Random Access Memory (RAM) is a volatile memory device that loses data when power is off. RAM is primarily used as the main memory device in computers. Dynamic Random Access Memory (DRAM) is a volatile type of RAM composed of memory cells. For example, DRAM uses transistors and capacitors for each cell. To detect data stored in a DRAM memory cell, bit lines and complementary bit lines are pre-charged with a pre-charge voltage, performing a charge-sharing operation and generating a difference between the voltage levels of the bit lines and the complementary bit lines. A sense amplifier then receives and amplifies this voltage difference to detect the data stored in the memory cell.

[0003] Due to recent advancements in the electronics industry, there is a growing demand for electronic components with more advanced functions, higher speeds, and smaller dimensions. Consequently, to improve the integration of semiconductor memory devices, the area of ​​memory cell regions and peripheral circuit regions has been reduced. Furthermore, efforts have been made to increase the amount of data processed in order to accelerate data processing time. Summary of the Invention

[0004] Embodiments of the present invention provide a semiconductor memory device that reduces the number of upper conductors in the sense amplifier to improve the efficiency of the area occupied by the peripheral circuitry.

[0005] According to an embodiment of the present invention, a bit line sense amplifier is provided, comprising: an amplifier connected between a first sense bit line and a second sense bit line, and responding to a first control signal and a second control signal to detect and amplify a voltage difference between the first and second bit lines; and an equalizer connected between a first power line through which the first control signal is provided and a second power line through which the second control signal is provided, and responding to an equalization control signal to precharge the first and second bit lines with a precharge voltage, wherein the equalizer includes an equalization enable transistor whose source is connected to the first power line, and performs equalization in response to the equalization control signal.

[0006] According to an embodiment of the present invention, a bit line sense amplifier is provided, comprising: an equalization enable transistor having a first terminal connected to a first power supply line to precharge a first bit line and a second bit line with a precharge voltage in response to an equalization control signal; a first power supply transistor to provide a first power supply voltage to the first power supply line in response to a first control signal; and an amplifier connected between the first sense bit line and the second sense bit line, and detecting and amplifying the voltage difference between the first bit line and the second bit line in response to the first control signal and the second control signal, wherein the equalization enable transistor and the first power supply transistor share a single active region.

[0007] According to an embodiment of the present invention, a bit line sense amplifier is provided, comprising: an equalizer connected between a first power line of a first control signal and a second power line of a second control signal, responsive to a first equalization control signal to equalize the first control signal and the second control signal, and responsive to a second equalization control signal to precharge a first bit line and a second bit line with a precharge voltage; an amplifier connected between a first sense bit line and a second sense bit line, and responsive to the first control signal and the second control signal to detect and amplify the voltage difference between the first bit line and the second bit line; a first offset transistor operating in response to an offset control signal and connected between the first bit line and the second sense bit line; and a second offset transistor connected between the second bit line and the first sense bit line and operating in response to the offset control signal, wherein the equalizer includes an equalization enable transistor having one end connected to either the first power line or the second power line, and performs precharging of the first bit line and the second bit line in response to the second equalization control signal, and the second equalization control signal is enabled before precharging based on the offset control signal.

[0008] According to an embodiment of the present invention, a bit line readout amplifier is provided, comprising: an equalizer connected between a first power line of a first control signal and a second power line of a second control signal, and pre-charging a first bit line and a second bit line with a pre-charge voltage according to an equalization control signal; and an amplifier connected between a first readout bit line and a second readout bit line, and detecting and amplifying a voltage difference between the first bit line and the second bit line according to the first control signal and the second control signal, wherein the equalizer includes an equalization enable transistor having one end connected to either the first power line or the second power line to perform pre-charging, and the equalization enable transistor includes: a first active region including a first region arranged in pairs to extend parallel in a first direction, and a second region connected to one end of the pair and having a rectangular shape; a first gate pattern extending in a second direction over the first region and being applied with the equalization control signal; and a first gate pattern pair extending in parallel in the first direction over the second region and being applied with either the first control signal or the second control signal.

[0009] According to an embodiment of the present invention, a bit line readout amplifier is provided, comprising: an equalization enable transistor; and an amplifier that detects and amplifies the voltage difference between a first bit line and a second bit line based on a first control signal and a second control signal, wherein the equalization enable transistor comprises: a P-type shared active region including a first rectangular region, a second rectangular region, and a bridge region connecting the first rectangular region and the second rectangular region on a substrate; a first control signal contact placed on the first rectangular region and subjected to the first control signal; a second control signal contact placed on the second rectangular region and subjected to the second control signal; and a first gate pattern placed on the bridge region and subjected to the equalization control signal. Attached Figure Description

[0010] The above and other features of the present invention will become more apparent from a detailed description of its embodiments with reference to the accompanying drawings, in which:

[0011] Figure 1 These are diagrams illustrating some embodiments of a memory device according to a concept conceived in this invention;

[0012] Figure 2 It is shown Figure 1 A diagram of the memory cells;

[0013] Figure 3 This is a diagram illustrating a memory cell array incorporating a sense amplifier according to some embodiments of the concept of the present invention;

[0014] Figure 4 This is a circuit diagram illustrating some embodiments of a bit line readout amplifier according to the present invention.

[0015] Figure 5 This is a circuit diagram illustrating some embodiments of a bit line readout amplifier according to the present invention.

[0016] Figure 6 Show Figure 4 or Figure 5 The timing diagram of the bit line readout amplifier is shown below;

[0017] Figure 7 This is a diagram illustrating the layout of a bit line readout amplifier according to some embodiments of the concept of the present invention;

[0018] Figure 8 Show connection Figure 7 The bit line layout of the bit line readout amplifier is shown.

[0019] Figure 9 This is a diagram illustrating the layout of a bit line readout amplifier according to some embodiments of the concept of the present invention;

[0020] Figure 10 Show connection Figure 9 The bit line layout of the bit line readout amplifier is shown.

[0021] Figure 11 This is a diagram illustrating the layout of a bit line readout amplifier according to some embodiments of the concept of the present invention;

[0022] Figure 12 This is a diagram illustrating the layout of a bit line readout amplifier according to some embodiments of the concept of the present invention;

[0023] Figure 13 This is a diagram illustrating the layout of a bit line readout amplifier according to some embodiments of the concept of the present invention;

[0024] Figure 14 Show connection Figure 12 or Figure 13 The bit line layout of the bit line readout amplifier is shown.

[0025] Figure 15 This is a diagram illustrating a memory cell array incorporating a sense amplifier according to some embodiments of the concept of the present invention;

[0026] Figure 16 This is a diagram illustrating a memory cell array employing a sense amplifier according to some embodiments of the concept of the present invention; and

[0027] Figure 17 This is a diagram illustrating an electronic device including a memory device according to some embodiments of the concept of the present invention. Detailed Implementation

[0028] In the following description, embodiments of the present invention will be described with reference to the accompanying drawings.

[0029] Figure 1 This is a diagram illustrating some embodiments of a memory device according to a concept conceived in this invention.

[0030] refer to Figure 1 The memory device 100 can be a semiconductor-based memory device. For example, the memory device 100 can be dynamic random access memory (DRAM), such as double data rate static DRAM (DDR SDRAM), single data rate SDRAM (SDR SDRAM), low-power DDR SDRAM (LPDDR SDRAM), low-power SDR SDRAM (LPSDRSDRAM), and Rambus DRAM (Direct RDRAM) or any volatile memory device. Specifically, the memory device 100 can be a device that uses standard protocols (such as DDR4 or DDR5).

[0031] As an example, the number of data pins using the DDR4 or DDR5 standard protocol can be four, eight, or sixteen, and the number of data pins in the semiconductor memory device 100 according to the present invention can be sixteen. In the following description of the number of data pins in the memory system described herein, while applicable to standard protocols used for DRAM, the inventive concept is not necessarily limited thereto.

[0032] The memory device 100 can output data via the data line DQ in response to commands CMD, addresses ADDR, and control signals received from an external device (e.g., a memory controller). The memory device 100 includes a memory cell array 110, a command decoder 112, control logic 114, an address buffer 120, a row decoder 130, a column decoder 140, a sense amplifier array 150, and data input / output circuitry 160.

[0033] The memory cell array 110 includes a plurality of memory cells provided in the form of a matrix arranged in rows and columns. The memory cell array 110 includes a plurality of word lines and a plurality of bit lines BL connected to the memory cells. The plurality of word lines can be connected to rows of memory cells, and the plurality of bit lines BL can be connected to columns of memory cells.

[0034] Command decoder 112 decodes commands received from the memory controller (e.g., write enable signal / WE, row address strobe signal / RAS, column address strobe signal / CAS, chip select signal / CS, etc.). Command CMD may include active commands, read commands, write commands, precharge commands, etc.

[0035] Control logic 114 can generate various control signals in response to decoded commands to perform access operations on memory cell array 110, such as write operations, read operations, precharge operations, etc.

[0036] Address buffer 120 receives address ADDR from the memory controller, which is an external device. Address ADDR includes row address RA for addressing rows of memory cell array 110 and column address CA for addressing columns of memory cell array 110. Address buffer 120 can send row address RA to row decoder 130 and column address CA to column decoder 140.

[0037] Row decoder 130 can select one of multiple word lines connected to memory cell array 110. Row decoder 130 can decode the row address RA received from address buffer 120, select any word line corresponding to row address RA, and activate the selected word line. When activating the word line, a high supply voltage (e.g., VPP) higher than the supply voltage (e.g., VDD) can be applied to the gate of the access transistor of the memory cell; in other words, this is a word line enable operation.

[0038] The column decoder 140 can select a predefined bit line from among the multiple bit lines BL of the memory cell array 110. The column decoder 140 can decode the column address CA received from the address buffer 120 and select the predefined bit line BL corresponding to the column address CA.

[0039] A sense amplifier array (S / A) 150 is connected to the bit lines BL of the memory cell array 110. The sense amplifier array 150 detects a voltage change on a selected bit line among multiple bit lines BL, amplifies it, and outputs the voltage change. The data input / output circuit 160 can output data to the outside via the data line DQ, where the data is based on the voltage detected and amplified by the sense amplifier array 150. Any bit line sense amplifier BLSA can be connected to a bit line pair including the first bit line BL and the second bit line BLB to read and amplify the potential generated on the bit lines. Specific connections between the bit line sense amplifiers and the bit line pairs will be described below. Figure 3 and Figure 4 As described in the text.

[0040] The sense amplifier array 150 can receive an isolation signal ISO and an offset cancellation signal OC from control logic 114. The sense amplifier array 150 can perform an offset cancellation operation based on the isolation signal ISO and the offset cancellation signal OC. As an example, offset refers to the characteristic between the semiconductor elements constituting the sense amplifier array 150, such as the difference in threshold voltage.

[0041] Figure 2 It is shown Figure 1 A diagram of memory cells.

[0042] refer to Figure 1 and Figure 2 The memory cell MC in the memory cell array is connected to each of the word line WL and bit line BL.

[0043] The memory cell MC is composed of a cell transistor MTR and a cell capacitor C. The memory device 100 can perform a read operation or a refresh operation based on the amount of charge stored in the cell capacitor C. In this case, the first bit line BL connected to the memory cell MC is precharged with a precharge voltage Vpre. Subsequently, when the word line WL connected to the memory cell MC is activated, the charge of the first bit line BL, which is precharged with the precharge voltage Vpre, is shared with the charge of the cell capacitor C of the memory cell MC. Due to the charge-sharing operation, the voltage of the first bit line BL can be reduced or increased by a voltage change V from the precharge voltage Vpre. Each sense amplifier in the sense amplifier array 150 can detect and amplify the voltage change V.

[0044] Figure 3 This is a diagram illustrating a memory cell array employing a sense amplifier according to some embodiments of the concept of the present invention.

[0045] refer to Figure 3 The memory device 200 includes multiple memory cell arrays 110_1 to 110_n and multiple sense amplifiers 150_1 to 150_n.

[0046] Each of the multiple sense amplifiers 150_1 to 150_n may include multiple bit line sense amplifiers (BLSAs). The bit line sense amplifiers (BLSAs) can be implemented as follows: Figures 1 to 2 The aforementioned readout amplifier array 150.

[0047] Multiple bit line pairs BL and BLB connected to multiple memory cell arrays 110_1 to 110_n can each be connected to multiple bit line sense amplifiers BLSA. Each bit line sense amplifier BLSA can be a cross-coupled differential sense amplifier implemented by a P-type sense amplifier and an N-type sense amplifier.

[0048] Each bit line amplifier (BLSA) is a circuit element that operates during the operation of the memory device 200, and is distinct from a dummy sense amplifier implemented in a region other than the region in which the bit line sense amplifier (BLSA) is implemented.

[0049] According to some embodiments of the present invention, the odd-numbered bit lines of the memory cell array 110_1 can be connected to the first bit line BL, and the even-numbered bit lines can be connected to the second bit line BLB. The bit line sense amplifier 150-2 can be connected in both directions to each of the bit line pairs BL and BLB. In other words, the left end of the bit line sense amplifier 150-2 is connected to the odd-numbered bit line of the memory cell array 110_1, namely the first bit line BL, and the right end of the bit line sense amplifier 150-2 is connected to the even-numbered bit line of the memory cell array 110_2, namely the second bit line BLB.

[0050] When the potential of the first bit line BL is high during the readout operation of the bit line sense amplifier BLSA, the potential of the second bit line BLB becomes low. Conversely, when the potential of the first bit line BL is low during the readout operation of the bit line sense amplifier BLSA, the potential of the second bit line BLB becomes high.

[0051] Figure 4 This is a circuit diagram illustrating some embodiments of a bit-line readout amplifier according to the present invention.

[0052] refer to Figure 4 The bit line readout amplifier 300 includes amplifiers 310 and 320, as well as an equalizer 360.

[0053] According to some embodiments of the present invention, amplifiers 310 and 320 are connected between a first power line (LA line, N1) providing a first control signal LA and a second power line (LAB line, N2) providing a second control signal LAB, and between a first bit line BL and a second bit line BLB. The bit line readout amplifier 300 includes a P-type amplifier 310 having one end connected to a first node N1 and an N-type amplifier 320 having one end connected to a second node N2. The other end of each of the P-type amplifier 310 and the N-type amplifier 320 can be electrically connected via a third node N3 and a fourth node N4. The third node N3 and the fourth node N4 can also be referred to as a first cross-coupled node and a second cross-coupled node, respectively. The P-type amplifier 310 includes transistors MP1 and MP2, and the N-type amplifier 320 includes transistors MN1 and MN2. Transistors MP1 and MP2 are connected to each other, and transistors MN1 and MN2 are connected to each other via a cross-coupled structure. The N-type amplifier 320 is also connected to the first bit line BL and the second bit line BLB.

[0054] For example, transistor MP1 is connected between the first node N1 and the third node N3, and the gate of transistor MP1 is connected to the fourth node N4. Transistor MP2 is connected between the first node N1 and the fourth node N4, and the gate of transistor MP2 is connected to the third node N3. Transistor MN1 is connected between the second node N2 and the third node N3, and the gate of transistor MN1 is connected to the fifth node N5, wherein the first bit line BL is connected to the fifth node N5. Transistor MN2 is connected between the second node N2 and the fourth node N4, and the gate of transistor MN2 is connected to the sixth node N6, wherein the second bit line BLB is connected to the sixth node N6.

[0055] According to some embodiments of the present invention, the bit line readout amplifier 300 further includes offset cancellation circuit 331 and offset cancellation circuit 332.

[0056] Offset cancellation circuits 331 and 332 perform offset cancellation operations, wherein the offset cancellation operation occurs between the first bit line BL and the second read bit line SBLB, or between the second bit line BLB and the first read bit line SBL. Offset cancellation circuits 331 and 332 may include a first offset transistor MN5 and a second offset transistor MN6. The first offset transistor MN5 is connected between the fifth node N5 and the third node N3 to connect or disconnect the first bit line BL and the second read bit line SBLB according to an offset control signal P1. The second offset transistor MN6 is connected between the sixth node N6 and the fourth node N4 to connect or disconnect the second bit line BLB and the first read bit line SBL according to the offset control signal P1.

[0057] According to some embodiments of the present invention, the bit line sense amplifier 300 further includes an isolation circuit 340. The isolation circuit 340 connects or disconnects the first bit line BL and the first sense bit line SBL, or connects or disconnects the second bit line BLB and the second sense bit line SBLB, according to an isolation control signal P2. The isolation circuit 340 includes isolation transistors MN3 and MN4. Isolation transistor MN3 is connected between a fifth node N5 and a fourth node N4 to connect or disconnect the first bit line BL and the first sense bit line SBL according to the isolation control signal P2. Isolation transistor MN4 is connected between a sixth node N6 and a third node N3 to connect or disconnect the second bit line BLB and the second sense bit line SBLB according to the isolation control signal P2.

[0058] Equalizer 360 is connected between the first power line (LA line) and the second power line (LAB line), that is, between the first node N1 and the second node N2, and precharges the first bit line BL and the second bit line BLB with a precharge voltage VBL according to the second equalization control signal PEQ. Equalizer 360 includes transistor MN21 connected between the first node N1 and the seventh node N7, transistor MN22 connected between the second node N2 and the seventh node N7, and transistor MN23 connected between the first node N1 and the second node N2. Each gate of transistors MN21, MN22, and MN23 is connected to an eighth node N8, the first equalization control signal LAEQ is applied to each gate, and the precharge voltage VBL is provided to the seventh node N7.

[0059] According to some embodiments of the present invention, the equalizer 360 further includes an equalization enable transistor 351. For example, when the equalization enable transistor 351 is an N-type transistor, the equalization enable transistor 351 connects or disconnects the second bit line BLB and the second power line (LAB line) according to a second equalization control signal PEQ to perform equalization operation. Although Figure 4 The diagram shows an equalization enable transistor 351 connected between the second bit line BLB and the second power line (LAB line) to precharge the second bit line. However, according to another example, the equalization enable transistor 351 may also be connected to the first bit line BL to precharge the first bit line.

[0060] Figure 5 This is a circuit diagram illustrating some embodiments of a bit-line readout amplifier according to the present invention. (The symbols and symbols are omitted.) Figure 4 The explanation will be repeated, and the main focus will be on the differences.

[0061] refer to Figure 5 The bit-line readout amplifier 400 also includes amplifiers 410 and 420, as well as an equalizer 460. However, with Figure 4 Unlike other equalizers, the equalization enable transistor 435 included in equalizer 460 can be implemented as a P-type transistor.

[0062] The equalization enable transistor 435 is connected between the fourth node N4 and the first node N1, and connects or disconnects the first power line (LA line) and the first read bit line SBL according to the second equalization control signal PEQ to perform equalization operation.

[0063] Figure 6 Show Figure 4 The timing diagram shown is for the operation of the bit line readout amplifier 400. Figure 6 The X-axis represents time, and the Y-axis represents the voltage level of each signal.

[0064] The bit-line sense amplifier 400 sequentially performs a pre-charge operation, an offset cancellation operation, a charge sharing operation, a pre-readout operation, and a re-store operation. The pre-charge operation will be described primarily in the following description.

[0065] refer to Figure 4 and Figure 6 After the re-storage operation is performed until time t0, the memory cell is deactivated (e.g., WL begins to transition from logic high to logic low). When the first equalization control signal LAEQ changes from logic low to logic high at time t1, transistors MN21, MN22, and MN23 of equalizers 360 and 460 are turned on, and equalization of the first control signal LA and the second control signal LAB begins. At this time, the equalization voltage of the first control signal LA and the second control signal LAB can converge at time t2 to the pre-charge voltage VBL provided through the seventh node N7.

[0066] Between time t3 and time t4, the isolation control signal P2 remains in a logic high state, while the offset control signal P1 transitions from logic low to logic high. Isolation control signal P2 turns on transistors MN3 and MN4, and offset control signal P1 turns on offset transistors MN5 and MN6. The signal at the fifth node N5 of the first bit line BL is input to the gate of transistor MP2 through the third node N3, and the signal at the sixth node N6 of the second bit line BLB is input to the gate of transistor MP1 through the fourth node N4. Furthermore, the third node N3 is connected to the sixth node N6 through transistors MN3 and MN4, and the fourth node N4 is connected to the fifth node N5. Therefore, the voltage levels of the first bit line BL and the second bit line BLB gradually begin to change through the first control signal LA and the second control signal LAB connected to each of the first node N1 and the second node N2.

[0067] When the second equalization signal PEQ goes high at time t5, transistor MN7 turns on, and the second bit line BLB is pre-charged with the equalization voltage of the second power supply line (e.g., the LAB line). Although Figure 6 The diagram shows that the first bit line BL and the second bit line BLB converge to the pre-charge voltage at the same time point, but the transistors MP1 and MP2 that drive the first bit line BL and the second bit line BLB can converge at the same time point or at different time points, depending on their respective current driving capabilities.

[0068] At time t6, after time t5, when the first equalization signal LAEQ first goes low and transistors MN21, MN22, and MN23 are turned off, then when the isolation control signal P2 goes low, transistors MN3 and MN4 are turned off, and when the second equalization signal PEQ also goes low, transistor MN7 is also turned off. Therefore, the first bit line BL and the second bit line BLB are separated in the pre-charge state, and when only the offset control signal P1 is high, transistors MN5 and MN6 are turned on, performing the offset cancellation operation OC.

[0069] When the offset control signal P1 goes low at time t7 and the voltage level of the word line goes high, and the second equalization signal PEQ goes high during the period between time t7 and time t8, the memory cell belonging to that word line undergoes a charge-sharing operation. Afterwards, the memory cell MC can be changed according to the amount of charge stored in the capacitor C.

[0070] Although the above description is mainly based on Figure 4 It is provided, but the assumption is... Figure 5It operates similarly. However, since the equalization enable transistor MP3 is P-type, the second equalization control signal PEQ can be used in conjunction with... Figure 6 The phases shown are opposite to the phases used to operate the equalization enable transistor MP3. Figures 7 to 9 This illustrates the back-end-of-line (BEOL) layout of a bit line sense amplifier according to an embodiment of the present invention. The equalization enable transistor will be described primarily. As an example, the source of the equalization enable transistor is connected to a first power supply line (LA line), and the equalization enable transistor may include an active region shared with the active region (e.g., a P-type active pattern) of the transistor providing the first control signal LA. As another example, the source of the equalization enable transistor may be connected to a second power supply line (LAB line), and the equalization enable transistor may include an active region shared with the active region (e.g., an N-type active pattern) of the transistor providing the second control signal LAB. In the illustrated bit line sense amplifiers 150 and 150', the PEQ region forming the equalization enable transistor and the LAB region formed by the transistor providing the second control signal share the N-type active region. However, since the signals applied to each of the gate patterns 33, 51, and 52 are simply different, the area of ​​the independent active regions used to equalize the source or drain of the enable transistor can be reduced, and the number of line patterns can be reduced accordingly. In other words, the memory cell array and bit line sense amplifier array can be designed using the entire effective area.

[0071] In the following text, Figures 7 to 14 The present invention describes embodiments of the layout of bit line sense amplifiers according to some embodiments of the present invention.

[0072] Figure 7 This is a diagram illustrating the layout of a bit line sense amplifier according to some embodiments of the present invention, and Figure 8 Show connection Figure 7 The bit line layout of the bit line readout amplifier is shown.

[0073] refer to Figure 7 According to some embodiments of the present invention, the bit line sense amplifier 150 includes a first P-type active region 10 and a second N-type active region S.

[0074] The P-type active region 10 can be placed on the substrate in a rectangular active pattern along the X direction. The N-type active region S can be separated from the P-type active region 10 on the substrate along the X direction and can be placed in an active pattern in the form of a fork. For example, the N-type active region S can have a tuning fork shape.

[0075] Contacts BL_C11 and BL_C12 for connecting to a bit line metal pattern including bit line BL or complementary bit line BLB, and contact C_LA for connecting to a first control signal LA metal pattern, can be formed on the P-type active region 10.

[0076] According to some embodiments of the present invention, an N-type active region S includes: a first region 30 having a spacer portion on a substrate and extending parallel in the X direction; a second region 40 having a spacer portion connected to the spacer portion of the first region 30, and being parallel, and having a width narrower than the width of the first region; and a third region 50 connecting the spacer portion of the second region. As an example, the first region 30 may be a pair of active patterns placed at both ends of the spacer portion of the second region 40 in the Y direction. The second region 40 is a pair of active patterns placed at both ends of the spacer portion of the first region 30 in the Y direction, but may have a width narrower than the width of the active pattern in the first region 30. The first region 30, the second region 40, and the third region 50 have different cross-sections in the Z direction, but may be patterns connected to each other as a common region.

[0077] Contacts G12_1, G12_2, G21_1, G21_2, BL_C21, and BL_C22 for connecting to a bit line metal pattern including bit line BL or complementary bit line BLB can be formed on the first region 30. Contacts BL_C31 and BL_C32 for connecting to a bit line metal pattern including bit line BL or complementary bit line BLB can be formed on the third region 50. On the third region 50, contact C_LAB for connecting to a second control signal LAB metal pattern can be formed in the central region in the Y direction (e.g., on the same line as contact C_LAB).

[0078] According to some embodiments of the present invention, a bit line sense amplifier may include a plurality of gate patterns. For example, a bit line sense amplifier includes a first gate pattern pair 12, a second gate pattern pair 51 and 52, a first gate pattern 31, a second gate pattern 32, and a third gate pattern 33.

[0079] The first gate pattern pair 12 is spaced apart from each other in the Y direction and is positioned to extend in the X direction. In the Y direction, the spacing between the first gate pattern pair 12 is wider than the spacing between the first region 30 and the second region 40 (which are active patterns) and narrower than the length of the first region 10 (which is a P-type active region). A first control signal LA is provided to the first gate pattern pair 12.

[0080] Gate contact G11_1 and gate contact G11_2 can be formed on the first gate pattern pair 12, respectively.

[0081] Therefore, the P-type first region 10, the first gate pattern pair 12, and the contacts BL_C11 and BL_C12 can be formed respectively. Figure 4 The MP1 and MP2 transistors. Gate contacts G11_1 and G11_2 can be connected to the third node N3 and the fourth node N4, respectively.

[0082] The second gate pattern pairs 51 and 52 are spaced apart from each other in the Y direction and are positioned to extend in the X direction. In the Y direction, the spacing between the second gate pattern pairs 51 and 52 is the same as the spacing between the first gate pattern pairs 12, and is wider than the spacing between the first region 30 and the second region 40, but narrower than the length of the P-type first region 10.

[0083] The first gate pattern 31, the second gate pattern 32, and the third gate pattern 33 are positioned to extend along the Y direction over the first region 30 of the N-type active region S and to be spaced apart by a predetermined distance in the X direction. The first gate pattern pair 12 and the second gate pattern pairs 51 and 52 can be cut to a predetermined length so as not to connect with other gate patterns (e.g., the first gate pattern 31, the second gate pattern 32, and the third gate pattern 33).

[0084] For example, an isolation control signal P2 can be applied to the first gate pattern 31, an offset control signal P1 can be applied to the second gate pattern 32, and a second equalization control signal PEQ can be applied to the third gate pattern 33. However, according to other examples, the order of the signals applied to each of the first gate pattern 31, the second gate pattern 32, and the third gate pattern 33 can be changed.

[0085] The second gate pattern pair 51 and 52 can be the gate patterns of adjacent bit line sense amplifiers. Gate contacts G22_1 and G22_2 can be formed on the second gate pair 51 and 52, and gate contacts G22_1 and G22_2 can be connected to the third node N3 and the fourth node N4, respectively. In other words, the third region 50, the second gate pattern pair 51 and 52, and the gate contacts G22_1 and G22_2 can form Figure 4 MN1 transistor and MN2 transistor.

[0086] refer to Figure 8 , Figure 7The contacts BL_C11, BL_C12, G11_1, G11_2, G12_1, G12_2, G21_1, G21_2, BL_C21, BL_C22, G22_1, G22_2, BL_C31, and BL_C32, as well as the control signal contacts C_LA and C_LAB shown, can be placed... Figure 8 The same position below the bit line metal pattern shown.

[0087] Therefore, since the second control signal LAB is applied to the active region of the first region 30, and is not related to the equalization enable transistors (PEQ, 150, ... Figure 4 The MN7 region shares another active region, so the number of bit line metal patterns on the PEQ region can be reduced.

[0088] Figure 9 This is a diagram illustrating the layout of a bit line sense amplifier according to some embodiments of the present invention, and Figure 10 Show connection Figure 9 The bit line layout of the bit line readout amplifier is shown.

[0089] refer to Figure 9 In the bit line readout amplifier, with Figure 7 Unlike other transistors, isolation transistors MN3 and MN4, as well as the equalization enable transistor, can have active regions that are independent of each other. Figure 9 The equalization enable transistor shown is an N-type transistor, and can be Figure 4 The equalization enable transistor MN7 is shown.

[0090] For example, the bit line sense amplifier 150' may include a first N-type active region S, a P-type active region 60, a second N-type active region 30, and a third N-type active region 35 on the substrate.

[0091] According to some embodiments of the present invention, the spacing between active regions in the X direction can be the same or different, depending on the shape of the gate pattern. According to some embodiments of the present invention, the spacing between active regions of different types (P-type, N-type) in the X direction can be greater than the spacing between active regions of the same type in the X direction.

[0092] The first N-type active region S can be divided into a first region 50, a second region 80, and a third region 70. The first region 50 is positioned as a rectangle in the X direction, and the second region 80 can be a rectangular pattern with a narrower length (i.e., a narrower width) than the first region 50 in the Y direction. The third region 70 can be placed in a pair of active pattern structures in the Y direction, wherein the pair of active pattern structures extends parallel to the X direction at both ends of its spacer portion. The first region 50, the second region 80, and the third region 70 have different cross-sections in the Z direction, but can be patterns connected to each other as a common region.

[0093] Contacts BL_C11 and BL_C12 can be formed on the first region 50 of the first N-type active region S. Furthermore, a control signal contact C_LA1 is formed on the first region 50, and a control signal LA1 (e.g., a LAB signal) can be applied to the control signal contact C_LA1. Contacts BLB_C21 and BLB_C22 can be formed on the third region 70.

[0094] One side of the P-type active region 60 (the left boundary of the P-type active region) is separated from one side (e.g., the right boundary) of the first N-type active region S in the X direction, and the P-type active region 60 can be arranged in a rectangular structure in the X direction. Contacts BLB_C31 and BLB_C32 can be formed on the P-type active region 60, and control signal contact C_LA2 for applying control signal LA2 (e.g., LA signal) can be formed.

[0095] The second N-type active region 30 is spaced apart from the P-type active region 60 in the X direction, facing one side of the P-type active region 60 in the X direction (e.g., the left boundary of the P-type active region 60), and can be positioned as an active pattern pair 30 extending parallel in the X direction and including two spaced portions in the Y direction. Contacts C31, C32, C21, and BL_Co2 can be formed on the second N-type active region 30. In other words, contacts C21 and BL_Co2 of the second N-type active region 30 are connected to the bit line BL and can form a [missing information - likely a gate pattern 31]. Figure 4 The MN3 transistor.

[0096] One side of the third N-type active region 35 is positioned to be separated from one side (e.g., the right boundary) of the first N-type active region S in the X direction, and the third N-type active region 35 can be positioned as an active pattern pair 35 extending parallel in the X direction and including a spaced portion in the Y direction. In this case, the spaced portion of the second N-type active region 30 and the spaced portion of the third N-type active region 35 can have the same spacing distance in the Y direction. Contacts C61, C62, BLB_C41, and BLB_C42 can be formed on the third N-type active region 35. In other words, contacts BLB_C41 and BLB_C42 of the third N-type active region 35 are connected to the complementary bit line BLB and can form a gate pattern 37 together with the gate pattern 37. Figure 4 The MN4 transistor.

[0097] Bit line sense amplifier 150' may include multiple gate patterns on multiple active regions. For example, bit line sense amplifier 150' may include a first gate pattern 71, a first gate pattern pair 51 and 52, a second gate pattern pair 61 and 62, a second gate pattern 31, and a third gate pattern 37.

[0098] The first gate pattern 71, the second gate pattern 31, and the third gate pattern 37 are single patterns extending in the Y direction, and the first gate pattern pair 51 and 52 and the second gate pattern pair 61 and 62 may be gate pattern pairs extending in the X direction. The first gate pattern pair 51 and 52 and the second gate pattern pair 61 and 62 may be cut to predetermined lengths so as not to connect with other gate patterns (e.g., the second gate pattern 31, the first gate pattern 71, and the third gate pattern 37).

[0099] The first gate pattern pairs 51 and 52 are spaced apart from each other in the Y direction and are positioned to extend in the X direction. In the Y direction, the spacing between the first gate pattern pairs 51 and 52 is wider than the spacing portion of the active pattern 70, but narrower than the length of the first N-type active region S. Gate contacts C11, C12, BLB_C11, and BLB_C12 can be formed on each gate pattern in the first gate pattern pairs 51 and 52.

[0100] The second gate pattern pairs 61 and 62 are spaced apart from each other in the Y direction and are positioned to extend in the X direction. In the Y direction, the spacing between the second gate pattern pairs 61 and 62 is the same as the spacing between the first gate pattern pairs 51 and 52, and is wider than the spacing between the second N-type active region 30 and the third N-type active region 35, but narrower than the length of the second N-type active region 30 and the third N-type active region 35. Gate contacts BL_C21, BL_C22, C41, and C42 can be formed on each gate pattern in the second gate pattern pairs 61 and 62.

[0101] A first gate pattern 71 is placed on a third region 70 extending along the Y-axis, and a second equalization control signal PEQ is applied to the first gate pattern 71. A second gate pattern 31 is placed on a second N-type active region 30 extending along the Y-axis, and an isolation control signal P2 is applied to the second gate pattern 31. A third gate pattern 37 is placed on a third N-type active region 35 extending along the Y-axis, and an isolation control signal P2 is applied to the third gate pattern 37.

[0102] refer to Figure 10 , Figure 9 The contacts C31, C32, C21, BL_Co2, BL_C21, BL_C22, BL_C11, BL_C12, BLB_C21, BLB_C22, BLB_C31, BLB_C32, BLB_C41, BLB_C42, C61, and C62, as well as the control signal contacts C_LA1 and C_LA2 shown, can be placed... Figure 10 The same position below the bit line metal pattern shown.

[0103] Therefore, since the second control signal LAB is applied to the first N-type active region S, and is not related to the equalization enable transistors (PEQ, 150, ... Figure 4 The MN7 region shares another active region, so the number of bit line metal patterns on the PEQ region can be reduced.

[0104] Figure 11 This is a diagram illustrating the layout of a bit line readout amplifier according to some embodiments of the present invention.

[0105] refer to Figure 11 In the bit line readout amplifier 150', with Figure 7 Unlike other transistors, isolation transistors MN3 and MN4, as well as the equalization enable transistor, can have independent active regions. Furthermore, compared to… Figure 9 different, Figure 11The equalization enable transistor shown is a P-type transistor, and can be Figure 5 The equalization enable transistor MP3 is shown.

[0106] For example, the bit line sense amplifier 150' may include a P-type active region S, a first N-type active region 60, a second N-type active region 30, and a third N-type active region 35 on the substrate.

[0107] According to some embodiments of the present invention, the spacing between active regions in the X direction can be the same or different, depending on the shape of the gate pattern. According to some embodiments of the present invention, the spacing between active regions of different types (e.g., P-type and N-type) in the X direction can be greater than the spacing between active regions of the same type in the X direction.

[0108] The P-type active region S can be divided into a first region 50, a second region 80, and a third region 70. The first region 50 is positioned as a rectangle in the X direction, and the second region 80 can be a rectangular pattern with a narrower length (i.e., wider) than the first region 50 in the Y direction. The third region 70 can be placed within a pair of active pattern structures, wherein the pair extends parallel to each other in the X direction and has spaced portions in the Y direction. The first region 50, the second region 80, and the third region 70 have different cross-sections in the Z direction and can be patterns connected to each other as a common region. However, with... Figure 9 The arrangement order of the active regions S in the X direction (where the first region 50, the second region 80, and the third region 70 are placed from left to right) is different, in Figure 11 In the middle, the first area 50, the second area 80, and the third area 70 are arranged from right to left.

[0109] One side of the first N-type active region 60 (the right boundary of the first N-type active region 60) is separated from one side (e.g., the left boundary) of the P-type active region S in the X direction, and the first N-type active region 60 can be placed in a rectangular structure in the X direction.

[0110] The second N-type active region 30 is separated from the P-type active region S in the X direction to face one side of the P-type active region S in the X direction (e.g., the left boundary of the P-type active region S), and can be positioned as an active pattern pair 30 that extends parallel in the X direction and has a spaced portion in the Y direction.

[0111] One side of the third N-type active region 35 is positioned to be separated from the other side (e.g., the right boundary) of the P-type active region S in the X direction, and the third N-type active region 35 can be positioned as an active pattern pair 35 extending parallel in the X direction and having a spaced portion in the Y direction. In this case, the spaced portion of the second N-type active region 30 and the spaced portion of the third N-type active region 35 can have the same spacing distance in the Y direction.

[0112] Bit line sense amplifier 150' may include multiple gate patterns on multiple active regions. For example, bit line sense amplifier 150' may include a first gate pattern 71, a first gate pattern pair 51 and 52, a second gate pattern pair 61 and 62, a second gate pattern 31, and a third gate pattern 37.

[0113] The first gate pattern 71, the second gate pattern 31, and the third gate pattern 37 are single patterns extending in the Y direction, and the first gate pattern pair 51 and 52 and the second gate pattern pair 61 and 62 may be gate pattern pairs extending in the X direction. The first gate pattern pair 51 and 52 and the second gate pattern pair 61 and 62 may be cut to predetermined lengths so as not to connect with other gate patterns (e.g., the second gate pattern 31, the first gate pattern 71, and the third gate pattern 37).

[0114] The first gate pattern pairs 51 and 52 are spaced apart from each other in the Y direction and are positioned to extend along the X direction over the first region 50. In the Y direction, the spacing between the first gate pattern pairs 51 and 52 is wider than the spacing portion of the active pattern 70, but narrower than the length of the active pattern 50. First control signals LA and LA1 are provided to the first gate pattern pairs 51 and 52.

[0115] The second gate pattern pairs 61 and 62 are spaced apart from each other in the Y direction and are placed on the first N-type active region 60 to extend in the X direction. In the Y direction, the spacing between the second gate pattern pairs 61 and 62 is the same as the spacing between the first gate pattern pairs 51 and 52, and is wider than the spacing between the second active pattern 30 and the third active pattern 35, but narrower than the length of the active regions 50 and 60. A second control signal LAB and a second control signal LA2 are provided to the second gate pattern pairs 61 and 62.

[0116] A first gate pattern 71 is placed on a third region 70 extending along the Y-axis, and a second equalization control signal PEQ is applied to the first gate pattern 71. A second gate pattern 31 is placed on a second N-type active region 30 extending along the Y-axis, and an isolation control signal P2 is applied to the second gate pattern 31. A third gate pattern 37 is placed on a third N-type active region 35 extending along the Y-axis, and an isolation control signal P2 is applied to the third gate pattern 37.

[0117] On the other hand, although Figure 11 The contact points are not shown, but Figure 11 The embodiments can be with Figure 9 The same implementation method is used, and the contacts and bit line metal lines can be connected.

[0118] Figure 12 This is a diagram illustrating the layout of a bit line readout amplifier according to some embodiments of the present invention. Figure 13 This is a diagram illustrating the layout of a bit line readout amplifier according to some embodiments of the present invention. Figure 14 Show connection Figure 12 or Figure 13 The bit line layout of the bit line readout amplifier is shown. For ease of explanation, since the second N-type active region 30 and the third N-type active region 35 correspond to... Figure 7 , Figure 9 and Figure 11 The active region will not be described.

[0119] refer to Figure 12 In the bit line readout amplifier 150', with Figure 9 or Figure 11 different, Figure 4 The MP1 and MP2 transistors, as well as MN4 and the equalization enable transistor MP3, can share a single active region.

[0120] The P-type shared active region SU1 can be divided into the LA1 region, the PEQ region, and the LA2 region when viewed from the Z direction, but they have different cross-sections in the Z direction and can be connected to each other as a pattern of common region.

[0121] According to some embodiments of the present invention, regions LA1 and LA2 can be P-type active regions formed in a rectangular shape on a substrate. The PEQ region can be implemented as a bridge shape connecting the rectangular LA1 and rectangular LA2 regions at the center. For example, the PEQ region can be implemented as a bridge pair with a predetermined interval region in the middle of the bridge shape. In this case, the bridge shape can be implemented as tilted diagonally between regions LA1 and LA2, such as... Figure 12As shown. According to another embodiment of the invention, the bridge shape can be implemented as a shape based on the gate pattern 71 that bends (or slants) only in the XY direction between the LA1 and LA2 regions, such as... Figure 13 As shown.

[0122] Contacts BLB_C11, BLB_C12, BL_C21, and BL_C22 connected to bit lines or complementary bit lines can be formed on the P-type shared active region SU1, and control signal contacts C_LA1 and C_LA2 can be formed to apply the first control signal LA1 or the second control signal LA2.

[0123] Bit line sense amplifier 150' may include multiple gate patterns on multiple active regions. For example, bit line sense amplifier 150' may include a first gate pattern 71, a first gate pattern pair 51 and 52, and a second gate pattern pair 61 and 62.

[0124] The first gate pattern 71 is a single pattern extending in the Y direction, and the first gate pattern pair 51 and 52 and the second gate pattern pair 61 and 62 can be gate pattern pairs extending in the X direction. The first gate pattern pair 51 and 52 and the second gate pattern pair 61 and 62 can be cut to a predetermined length so as not to be connected to another gate pattern (e.g., the first gate pattern 71).

[0125] The first gate pattern pairs 51 and 52 are spaced apart from each other in the Y direction and are positioned to extend in the X direction. Gate contacts C21, C23, BL_C11, and BL_C12 may be formed on the first gate pattern pairs 51 and 52.

[0126] The second gate pattern pairs 61 and 62 are spaced apart from each other in the Y direction and are positioned to extend in the X direction. Gate contacts BLB_C21, BLB_C22, C31, and C32 can be formed on the second gate pattern pairs 61 and 62.

[0127] The first gate pattern 71 is placed on the PEQ region of the P-type shared active region SU1 to extend along the Y-axis, and the second equalization control signal PEQ is applied to the first gate pattern 71.

[0128] refer to Figure 14 , Figure 12 or Figure 13The contacts C11, C12, C21, C23, BLB_C11, BLB_C12, BL_C11, BL_C12, BLB_C21, BLB_C22, BL_C21, BL_C22, C31, C32, C41, and C42, as well as the control signal contacts C_LA1 and C_LA2 shown, can be placed... Figure 14 The same position below the bit line metal pattern shown.

[0129] Therefore, since the P-type shared active region SU1 applies the first control signal LA1 or the second control signal LA2, and is not related to the equalization enable transistors (PEQ, 150, ... Figure 5 The MP3 shares another active region, so the number of bit line metal patterns on the PEQ region can be reduced.

[0130] In addition, with Figure 9 or Figure 11 In contrast, since the LA1, PEQ, and LA2 regions are implemented as a single P-type shared active region SU, it is not necessary to Figure 9 The gap between the PEQ region and the LA2 region or Figure 11 The gap between the PEQ region and the LA1 region. Furthermore, separate contacts and separate upper-layer wiring are not required to connect transistors formed in the LA1 region that are different from MP3 transistors (e.g., equalization control transistors) or transistors formed in the LA2 region. In other words, this has the effect of reducing area in memory cell layout and can reduce wiring.

[0131] Figure 15 and Figure 16 This is a schematic diagram illustrating a memory device employing a bit-line sense amplifier according to some embodiments of the concept of the present invention.

[0132] Figure 15 and Figure 16 Is and as above Figure 3 The diagram shows a first memory cell array 110_1, a second memory cell array 110_2, and a bit line sense amplifier 150_2, some of the plurality of memory cell arrays 110_1 to 110_n and plurality of sense amplifiers 150_1 to 150_n. Each bit line sense amplifier 150_2 may include a plurality of bit line sense amplifiers (BLSAs). The bit line sense amplifiers (BLSAs) can be implemented as follows: Figures 4 to 14 The bit line readout amplifier mentioned above.

[0133] and Figure 3 The memory devices 200 are different, in Figure 15In the memory device 600, two bit line sense amplifiers (BLSAs) in the second sense amplifier 150_2a are placed adjacent to each other. The two BLSAs can be connected to the first bit line BL1 and the second bit line BL2, as well as the first complementary bit line BLB1 and the second complementary bit line BLB2. One of the two BLSAs can detect voltage changes in the first bit line pair BL1 and BLB1, and the other can detect voltage changes in the second bit line pair BL2 and BLB2.

[0134] and Figure 3 The memory devices 200 are different, in Figure 16 In the memory device 700, the three bit line sense amplifiers (BLSAs) in the second sense amplifier 150_2b are placed adjacent to each other. The three bit line sense amplifiers (BLSAs) can be connected to the first bit line BL1, the second bit line BL2, and the third bit line BL3, as well as the first complementary bit line BLB1, the second complementary bit line BLB2, and the third complementary bit line BLB3. Each of the three bit line sense amplifiers (BLSAs) can detect a voltage change in each of the first bit line pair (BL1, BLB1), the second bit line pair (BL2, BLB2), and the third bit line pair (BL3, BLB3).

[0135] Figure 15 and Figure 16 Memory devices 600 and 700 can be selectively applied based on the following trend: the size of the unit cell is reduced due to miniaturization according to the design rules of high integration of memory cell elements. According to an embodiment of the present invention, n bit line sense amplifiers (BLSAs) are placed adjacent to each other, and the n bit line sense amplifiers (BLSAs) are connected to the first bit lines BL1 to the nth bit lines BLn and the first complementary bit lines BLB1 to the nth complementary bit lines BLBn, and each of the n bit line sense amplifiers can detect a voltage change in each of the first bit line pairs (BL1, BLB1) to the nth bit line pairs (BLn, BLBn).

[0136] Figure 17 This is a block diagram illustrating an example of a memory device including a readout amplifier according to an embodiment of the present invention being applied to a mobile device. The mobile device may be a mobile phone or a smartphone.

[0137] refer to Figure 17 The mobile device 1000 includes a Global System for Mobile Communications (GSM) block 1010, a Near Field Communication (NFC) transceiver 1020, an input / output block 1030, an application block 1040, a memory 1050, and a display 1060. Figure 17In this embodiment, components / blocks of mobile device 1000 are shown as examples. Mobile device 1000 may include more or fewer components / blocks. Furthermore, although the embodiment is shown to use GSM technology, mobile device 1000 may be implemented using other technologies such as Code Division Multiple Access (CDMA). Figure 17 The blocks will be implemented as integrated circuits. Alternatively, some blocks will be implemented as integrated circuits, while others will be implemented separately.

[0138] The GSM block 1010 is connected to the antenna 1011 and can operate to provide wireless telephone operation. The GSM block 1010 may internally include a receiver and a transmitter to perform corresponding receiving and transmitting operations.

[0139] The NFC transceiver 1020 can be configured to transmit and receive NFC signals wirelessly via inductive coupling. The NFC transceiver 1020 provides NFC signals to the NFC antenna matching network system 1021, and the NFC antenna matching network system 1021 can transmit NFC signals via inductive coupling. The NFC antenna matching network system 1021 can receive NFC signals from other NFC devices and provide the received NFC signals to the NFC transceiver 1020.

[0140] Application block 1040 includes hardware circuitry (e.g., one or more processors) and is operable to provide various user applications provided by mobile device 1000. User applications may include voice call operations, data transmission, data exchange, etc. Application block 1040 may operate in conjunction with GSM block 1010 and / or NFC transceiver 1020 to provide the operational characteristics of GSM block 1010 and / or NFC transceiver 1020. Alternatively, application block 1040 may include a program for mobile point-of-sales (POS). Such a program can provide purchase and payment functionality using a credit card on a mobile phone (i.e., a smartphone).

[0141] Display 1060 can display an image in response to a display signal received from application block 1040. The image may be provided in application block 1040 or generated by a camera built into mobile device 1000. Display 1060 may internally include a frame buffer for temporarily storing pixel values ​​and may be configured by a liquid crystal display screen along with associated control circuitry.

[0142] Input / output block 1030 provides input functionality to the user and provides output received through application block 1040.

[0143] Memory 1050 stores programs (commands) and / or data to be used by application block 1040, and can be implemented as random access memory (RAM), read-only memory (ROM), flash memory, etc. Therefore, memory 1050 may include volatile and non-volatile storage elements. For example, memory 1050 corresponds to... Figures 1 to 16 The memory devices 100, 600 and 700 are mentioned above.

[0144] The memory 1050 may include Figures 1 to 9 The bit line sense amplifier includes an amplifier and an equalizer, and the equalizer may include an equalization enable transistor having one end connected to one of a first power line applying a first control signal LA and a second power line applying a second control signal LAB, and performs equalization operation according to an equalization control signal PEQ.

[0145] In concluding this detailed description, those skilled in the art will understand that many variations and modifications can be made to the embodiments disclosed herein without substantially departing from the scope of the inventive concept. Therefore, the disclosed embodiments are not intended to be limiting.

Claims

1. A bit-line sense amplifier, comprising: An amplifier is connected between the first readout bit line and the second readout bit line, and responds to the first control signal and the second control signal to detect and amplify the voltage difference between the first bit line and the second bit line. and An equalizer is connected between a first power line through which the first control signal is provided and a second power line through which the second control signal is provided, and precharges the first bit line and the second bit line with a precharge voltage in response to the equalization control signal. The equalizer includes an equalization enable transistor whose source is connected to the first power line, and performs equalization in response to the equalization control signal.

2. The bit line sense amplifier according to claim 1, wherein, The amplifier includes: A P-type amplifier includes a first P-type transistor and a second P-type transistor, each connected between the first power line and the first node and the second node. An N-type amplifier, comprising a first N-type transistor and a second N-type transistor respectively connected between the first node and the second node and the second power line; and The offset cancellation circuit includes an offset transistor connected to each of the first bit line and the second bit line and the first node and the second node, and operating in response to an offset control signal.

3. The bit line sense amplifier according to claim 2, wherein, The amplifier includes: An isolation circuit includes a first isolation transistor and a second isolation transistor, wherein the first isolation transistor is connected between the second bit line and the first node and operates in response to an isolation control signal, and the second isolation transistor is connected between the first bit line and the second node and operates in response to the isolation control signal.

4. The bit line sense amplifier according to claim 3, wherein, The equalization enable transistor is an N-type transistor connected between the second power line and the second bit line, wherein the equalization control signal is applied to the gate of the N-type transistor.

5. The bit line sense amplifier according to claim 4, wherein, The bit line sense amplifier includes: The fork-shaped N-type active region includes a first region having a spaced portion on a substrate and extending parallel in a first direction, a second region having a spaced portion parallel to the first region and having a narrower width than the first region, and a third region connected to the spaced portion of the second region. A first gate pattern extends over the first region along a second direction, and the isolation control signal is applied to the first gate pattern; A second gate pattern extends over the first region along a second direction, and the offset control signal is applied to the second gate pattern; and A third gate pattern extends over the first region along a second direction, and the equalization control signal is applied to the third gate pattern.

6. The bit line sense amplifier according to claim 5, further comprising: The fourth gate pattern and the fifth gate pattern extend parallel to each other in the first direction and are placed on a portion of the second region and the third region, and the second control signal is applied to the fourth gate pattern and the fifth gate pattern.

7. The bit line sense amplifier according to claim 6, further comprising: The P-type active region is separated from the N-type active region in the first direction; and A sixth gate pattern is placed parallel to the P-type active region in a first direction, and the first control signal is applied to the sixth gate pattern.

8. The bit line sense amplifier according to claim 3, wherein, The equalization enable transistor is a P-type transistor connected between the second node and the first power line, wherein the equalization control signal is applied to the gate of the P-type transistor.

9. The bit line sense amplifier according to claim 8, wherein, The bit line sense amplifier includes: At least two first N-type active regions have a first spaced portion on the substrate and extend parallel to each other in a first direction; The first P-type active region has a first side spaced apart from the first N-type active region in a first direction, and the first P-type active region has a first region with a rectangular shape placed in the first direction, a second region with a width narrower than the first region, and a third region with a second spacing portion and connected to the second region. A first gate pattern extends over the first region along a first direction, and the first control signal is applied to the first gate pattern; and A second gate pattern, spaced apart from the first gate pattern in a first direction, extends over the third region in a second direction, and the equalization control signal is applied to the second gate pattern.

10. The bit line sense amplifier according to claim 9, further comprising: The second N-type active region has a first side that is spaced apart from the second side of the first P-type active region in a first direction, and has a rectangular shape placed in the first direction. At least two third N-type active regions are positioned to be spaced apart from the second side of the second N-type active region in a first direction, have a third spacing portion, and extend parallel to each other in the first direction; A third gate pattern is placed on the second N-type active region to extend in a first direction, and a second control signal is applied to the third gate pattern. A fourth gate pattern is placed on the at least two third N-type active regions to extend in a second direction, and the isolation control signal is applied to the fourth gate pattern; and A fifth gate pattern is placed on the at least two first N-type active regions to extend in a second direction, and the isolation control signal is applied to the fifth gate pattern.

11. The bit line sense amplifier according to claim 8, wherein, The bit line sense amplifier includes: At least two first N-type active regions have a first isolation portion on the substrate and extend parallel to each other in a first direction; A first P-type active region has a first side separated from the first N-type active region and has a rectangular shape placed in a first direction. The second N-type active region has a first side that is separated from the second side of the first P-type active region in a first direction, and the second N-type active region includes a first region composed of a bifurcated structure, a second region connected to the first region, and a third region having a wider width than the second region and having a rectangular shape placed in the first direction. A first gate pattern extends along a second direction over the first region, and the equalization control signal is applied to the first gate pattern; and A second gate pattern is placed on the third region to extend in a first direction, and the first control signal is applied to the second gate pattern.

12. The bit line sense amplifier according to claim 11, further comprising: The third N-type active region is positioned to be separated from the second side of the first P-type active region in a first direction; A third gate pattern is placed on the first N-type active region to extend in the second direction, and the isolation control signal is applied to the third gate pattern. A fourth gate pattern is placed on the second N-type active region to extend in a first direction, and the second control signal is applied to the fourth gate pattern; and A fifth gate pattern is placed on the third N-type active region to extend in the second direction, and the isolation control signal is applied to the fifth gate pattern.

13. The bit line sense amplifier according to claim 1, wherein, The equalization enable transistor includes: The P-type shared active region includes two rectangular regions and a bridge region connecting the two rectangular regions; A first gate pattern is placed on the bridge region along a direction intersecting the bridge region, and the equalization control signal is applied to the first gate pattern; A first contact is formed on a first rectangular region of the P-type shared active region, and the first control signal is applied to the first contact; and The second contact is formed on the second rectangular region of the P-type shared active region, and the second control signal is applied to the second contact.

14. The bit line sense amplifier according to claim 13, wherein, The bridge region of the P-type shared active region has a spaced area and connects the first rectangular region and the second rectangular region in a diagonally inclined manner.

15. The bit line sense amplifier according to claim 13, wherein, The bridge region of the P-type shared active region has a spaced region surrounding the first gate pattern and connects the first rectangular region and the second rectangular region in a curved manner.

16. The bit line sense amplifier according to claim 13, comprising: The first gate pattern pair is placed on the first rectangular region; and The second gate pattern pair is placed on the second rectangular region.

17. The bit line sense amplifier according to claim 1, wherein, The amplifier includes: A P-type amplifier includes a first P-type transistor and a second P-type transistor, each connected between the first power line and the first cross-coupled node and the second cross-coupled node. An N-type amplifier, comprising a first N-type transistor and a second N-type transistor respectively connected between the first cross-coupled node and the second cross-coupled node and the second power line; and The offset cancellation circuit includes an offset transistor connected to each of the first bit line and the second bit line, as well as the first cross-coupled node and the second cross-coupled node, and operates in response to an offset control signal.

18. The bit line sense amplifier according to claim 13, wherein, The equalization enable transistor is a P-type transistor connected between the cross-coupled node and the first power line, wherein the equalization control signal is applied to the gate of the P-type transistor.

19. The bit line sense amplifier according to claim 1, wherein, The equalization enable transistor includes: The first P-type active region includes a first region placed on a substrate and having a rectangular shape in a first direction, a second region having a width narrower than the first region, and a third region with a bifurcated structure connected to the second region. A first control signal contact is placed on a first region of the first P-type active region, and a first control signal is applied to the first control signal contact; and A first gate pattern is formed on the third region to extend in a second direction, and the equalization control signal is applied to the first gate pattern.

20. The bit line sense amplifier according to claim 19, wherein, The bit line sense amplifier includes: The N-type active region is separated from the first P-type active region; and A second control signal contact is formed on the N-type active region, and the first control signal is applied to the second control signal contact.

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