Data writing method and device, data rollback method and device

Abstract

A data writing method, a data writing device, a data rollback method and a data rollback device. The data writing method comprises obtaining a first data value of old data stored in a memristor; selecting a write operation from a plurality of write operations according to the first data value and a second data value of new data to be written, and performing the selected write operation on the memristor to write the second data value, wherein the memristor has different memory characteristics for the plurality of write operations. The data rollback method comprises: obtaining the memristor after the data writing method is operated; selecting a recovery operation from a plurality of recovery operations according to the second data value currently stored in the memristor, and performing the selected recovery operation on the memristor; obtaining a third data value of the memristor after the selected recovery operation is performed, and obtaining the first data value of the old data based on the third data value. The data writing method and the data rollback method can prevent important data from being lost, quickly recover data and save storage space.

Description

Technical Field

[0001] The embodiments of this disclosure relate to a data writing method, a data writing device, and a data backtracking method and a data backtracking device. Background Technology

[0002] With the rapid development of information technology, a large amount of data is stored in electronic systems. Due to system malfunctions, virus intrusions, hardware damage, and accidental data deletion caused by human error, important data stored in electronic systems often faces the risk of loss, making it impossible for users to directly and quickly retrieve the original data, thus causing a series of economic losses and security risks.

[0003] Currently, there are two main technologies for preventing data loss: data recovery technology and data backup technology. Data recovery technology can "retrieve" the original data based on the address, while data backup technology can "save" the original data based on the replica storage. Although these two technologies can prevent data loss to a certain extent, they still have many limitations and cannot achieve true data recovery. Summary of the Invention

[0004] At least one embodiment of this disclosure provides a data writing method, the data writing method comprising: obtaining a first data value of old data stored in a memristor; selecting a write operation from a plurality of write operations based on the first data value and a second data value of new data to be written, and performing the selected write operation on the memristor to write the second data value, wherein the memristor has different memory characteristics for the plurality of write operations.

[0005] For example, in the data writing method provided in at least one embodiment of this disclosure, the multiple write operations include: a write set operation and a write reset operation, wherein the write set operation causes the data value of the memristor to be 1, and the write set operation includes a first set operation and a second set operation, and according to the memory characteristics of the memristor, the first set voltage of the first set operation is greater than the second set voltage of the second set operation; the write reset operation causes the data value of the memristor to be 0, and the write reset operation includes a first reset operation and a second reset operation, and according to the memory characteristics of the memristor, the first reset voltage of the first reset operation is greater than the second reset voltage of the second reset operation.

[0006] For example, in the data writing method provided in at least one embodiment of this disclosure, the first set operation is used to make the resistance value of the memristor less than a first target resistance value, the second set operation is used to make the resistance value of the memristor less than a second target resistance value, and the first target resistance value is less than the second target resistance value; the first reset operation is used to make the resistance value of the memristor greater than a third target resistance value, and the second reset operation is used to make the resistance value of the memristor greater than a fourth target resistance value, wherein the third target resistance value is greater than the fourth target resistance value.

[0007] For example, in a data writing method provided in at least one embodiment of this disclosure, a write operation is selected from multiple write operations based on the first data value and the second data value of the new data to be written, and the memristor is subjected to the selected write operation to write the second data value. This includes: performing a first set operation on the memristor when the second data value to be written is 1 and the first data value is 1; performing a second set operation on the memristor when the second data value to be written is 1 and the first data value is 0; performing a second reset operation on the memristor when the second data value to be written is 0 and the first data value is 1; and performing a first reset operation on the memristor when the second data value to be written is 0 and the first data value is 0, wherein the resistance value of the memristor when the data value is 1 is less than the resistance value of the memristor when the data value is 0.

[0008] For example, in the data writing method provided in at least one embodiment of this disclosure, the memristor is a non-volatile memristor.

[0009] At least one embodiment of this disclosure also provides a data backtracking method, which includes: obtaining a memristor after the data writing method operation described in at least one embodiment of this disclosure; selecting a recovery operation from a variety of recovery operations based on the second data value currently stored in the memristor, and performing the selected recovery operation on the memristor; obtaining a third data value of the memristor after the selected recovery operation, and obtaining the first data value of the old data based on the third data value.

[0010] For example, in the data backtracking method provided in at least one embodiment of this disclosure, a recovery operation is selected from a variety of recovery operations based on the second data value currently stored in the memristor, and the selected recovery operation is performed on the memristor, including: reading the resistance value of the memristor to obtain the second data value; and performing a third set operation or a third reset operation on the memristor based on the second data value.

[0011] For example, in the data backtracking method provided in at least one embodiment of this disclosure, performing a third set operation or a third reset operation on the memristor according to the second data value includes: performing the third set operation on the memristor N times when the second data value is 0; and performing the third reset operation on the memristor M times when the second data value is 1, wherein M and N are integers greater than or equal to 1.

[0012] For example, in the data backtracking method provided in at least one embodiment of this disclosure, obtaining the third data value of the memristor after the selected recovery operation has been performed, and obtaining the first data value of the old data based on the third data value, includes: when the third data value of the memristor is 0, the first data value of the old data is 0; when the third data value of the memristor is 1, the first data value of the old data is 1.

[0013] At least one embodiment of this disclosure also provides a data writing device, which includes: a data acquisition module configured to acquire a first data value of old data stored in a memristor; and a data writing module configured to select a write operation from a plurality of write operations based on the first data value and a second data value of new data to be written, and perform the selected write operation on the memristor to write the second data value, wherein the memristor has different memory characteristics for the plurality of write operations.

[0014] At least one embodiment of this disclosure also provides a data backtracking device, which includes: a data acquisition module configured to acquire the second data value currently stored in the memristor after the data writing method described in at least one embodiment of this disclosure; a data recovery module configured to select a recovery operation from a variety of recovery operations based on the second data value currently stored in the memristor, and perform the selected recovery operation on the memristor; and a data backtracking module configured to acquire a third data value of the memristor after the selected recovery operation has been performed, and obtain the first data value of the old data based on the third data value. Attached Figure Description

[0015] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure.

[0016] Figure 1 This is a schematic diagram of the structure of a memristor unit;

[0017] Figure 2A A schematic diagram illustrating the cumulative probability of the memristor's resistance value under different set operations;

[0018] Figure 2BA schematic diagram illustrating the cumulative probability of the memristor's resistance value under different reset operations;

[0019] Figure 3A This is a schematic diagram illustrating the memory characteristics of a memristor for different set operations.

[0020] Figure 3B This is a schematic diagram illustrating the memory characteristics of a memristor under different reset operations.

[0021] Figure 4 A schematic diagram illustrating a data writing method provided in at least one embodiment of this disclosure;

[0022] Figure 5 A flowchart illustrating a data writing method provided in at least one embodiment of this disclosure;

[0023] Figure 6 A schematic diagram illustrating another data writing method provided in at least one embodiment of this disclosure;

[0024] Figures 7A-7B A flowchart illustrating another data writing method provided in at least one embodiment of this disclosure;

[0025] Figure 8 A schematic diagram illustrating a data backtracking method provided in at least one embodiment of this disclosure;

[0026] Figure 9 A flowchart illustrating a data backtracking method provided in at least one embodiment of this disclosure;

[0027] Figure 10 A schematic diagram illustrating the backtracking result of a data backtracking method provided in at least one embodiment of this disclosure;

[0028] Figure 11 This is a schematic diagram of the structure of a data writing device provided in an embodiment of the present disclosure;

[0029] Figure 12 This is a schematic diagram of the structure of a data backtracking device provided in an embodiment of the present disclosure. Detailed Implementation

[0030] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0031] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “upper,” “lower,” “left,” and “right” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0032] To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of known functions and known components may be omitted.

[0033] Currently, one technical solution to prevent data loss is data recovery technology. This involves manually repairing partition tables and file allocation tables in storage modules to relocate, link, and restore the data. However, because data recovery technology manually rebuilds the linked lists of data, allowing it to be retrieved again, the data itself never truly "disappears." Rather, the computer loses its storage addresses, making it untraceable. Therefore, data recovery technology relies entirely on the objective condition that the old data itself has not been deleted or overwritten. Once this condition is not met, the data cannot be recovered. For example, if old data is overwritten by new data, data recovery technology will completely fail. Furthermore, in cases of virus attacks, hardware failures, or human error, important data may be permanently lost and unrecoverable.

[0034] Another technical solution to prevent data loss is data backup technology, which involves allocating a separate storage area and periodically copying important data. However, on the one hand, data backup technology requires copying important data to another independent storage medium. When the data volume is large, data backup technology consumes significant hardware resources, resulting in high hardware costs. On the other hand, data backup technology requires periodic updates to the backup data to minimize losses caused by the loss of important data. However, data backup often has a lag; if an unexpected event occurs before or during the backup process, it may also cause permanent loss of important data. Therefore, while data backup technology can solve the problem of data loss caused by data deletion or overwriting to a certain extent, the possibility of data loss still exists, and trade-offs must be made between backup intervals, storage performance, and the degree of data recovery.

[0035] To this end, at least one embodiment of this disclosure provides a data backtracking technique, which allows the memory to recover and retrieve the old data when it is overwritten by new data. For example, if data [A] is written to the memory for the first time, and then data [B] is written to it for the second time, and the second data [B] completely overwrites the original data [A], the data backtracking technique provided by at least one embodiment of this disclosure can directly recover and retrieve the data [A] by backtracking once when it is necessary to recover the data [A].

[0036] Furthermore, the data backtracking technology provided in at least one embodiment of this disclosure is based on a memristor with memory characteristics, a data writing method, and a data backtracking method. The data writing method can write data [A] and data [B] into the same memristor sequentially, and data [B] can be read and used normally. The memristor remembers the data [A] written with different write operations, so that when data recovery is needed, the previous data [A] can be retrieved by backtracking through the data backtracking method.

[0037] At least one embodiment of this disclosure provides a data writing method comprising: acquiring a first data value of old data stored in a memristor; selecting a write operation from a variety of write operations based on the first data value and a second data value of new data to be written, and performing the selected write operation on the memristor to write the second data value, wherein the memristor has different memory characteristics for the various write operations. This data writing method relies on the memory characteristics of the memristor to use a specific write operation to achieve data writing, which can provide a prerequisite for the retrieval and recovery of previous old data, while not affecting the normal reading and use of subsequent new data.

[0038] The data backtracking method provided in at least one embodiment of this disclosure includes: obtaining a memristor after the data writing method operation of at least one embodiment of this disclosure; selecting a recovery operation from a variety of recovery operations based on a second data value currently stored in the memristor, and performing the selected recovery operation on the memristor; obtaining a third data value of the memristor after the selected recovery operation, and obtaining a first data value of the old data based on the third data value. This data backtracking method does not rely on the objective condition that "the old data itself has not been deleted or rewritten," and does not require additional hardware storage space, greatly improving the recoverability of old data, reducing the risk of data loss, and improving the reliability of the computer system.

[0039] Therefore, the memristor-based data backtracking technology provided in at least one embodiment of this disclosure can recover the overwritten old data by utilizing the memristor's own memory characteristics of historical operations when new data is written to the memristor. It has the characteristics of low cost, strong real-time performance, and minimal impact on system performance.

[0040] Figure 1 This is a schematic diagram of a memristor memory cell. Figure 1 As shown in (a) to (c), the memristor storage cell can be a 1T1R structure, that is, it includes a transistor T and a memristor R.

[0041] like Figure 1 As shown in (a), the memristor R may include a resistive switching layer 111, a functional layer 112, and upper electrodes 113 and lower electrodes 114 located on both sides. The functional layer 112 is optional and can be added or not depending on the optimization direction of the memristor's performance, and can be designed accordingly. The resistive switching layer 111 may be, for example, a single layer of a single type of binary metal oxide (e.g., NiO, AlOx, etc.), graphene oxide, multi-component perovskite oxide (e.g., STO, SZO, PCMO, etc.), or a stack of multiple layers of the above materials, such as a stack of TixN and AlOx.

[0042] For example, when transistor T is an N-type transistor, its gate is connected to the word line terminal WL. For example, when the word line terminal WL is high, transistor T is turned on. The first electrode of transistor T can be the source and is configured to be connected to the source line terminal SL. The second electrode of transistor T can be the drain and is configured to be connected to the lower electrode 114 (e.g., the negative electrode) of memristor R. The upper electrode 113 (e.g., the positive electrode) of memristor R is connected to the bit line terminal BL. For example, when transistor T is a P-type transistor (not shown in the figure), its gate is connected to the word line terminal WL. For example, when the word line terminal WL is low, transistor T is turned on. The first electrode of transistor T can be the drain and is configured to be connected to the source line terminal SL. The second electrode of transistor T can be the source and is configured to be connected to the lower electrode 114 (e.g., the negative electrode) of memristor R. The upper electrode 113 (e.g., the positive electrode) of memristor R is connected to the bit line terminal BL. It should be noted that the structure of the memristor storage cell can also be implemented in other ways, such as a structure in which the second terminal of the memristor R is connected to the source line terminal SL, etc. The embodiments disclosed herein do not limit this.

[0043] The word line terminal WL applies a voltage to the gate of transistor T, thereby controlling its on / off state. When operating on memristor R, such as during read or write operations, transistor T must first be turned on; that is, a turn-on voltage must be applied to the gate of transistor T through the word line terminal WL. After transistor T is turned on, voltages can be applied to memristor R through the source line terminal SL and the bit line terminal BL to change its resistance state. For example, voltages can be applied simultaneously to both the word line terminal WL and the bit line terminal BL, causing the resistance of memristor R to decrease, i.e., changing from a high-resistance state to a low-resistance state. This change is called a write-set (SET) operation. Conversely, voltages can be applied simultaneously to both the word line terminal WL and the source line terminal SL, causing the resistance of memristor R to increase, i.e., changing from a low-resistance state to a high-resistance state. This change is called a write-reset (RESET) operation. For example, as... Figure 1 As shown in (b), a pulse voltage can be applied to the word line terminal WL and the bit line terminal BL, while the source line terminal SL is grounded. This performs a write-set operation on the memristor R, causing it to be in a low-resistance state. For example, as shown in (b) Figure 1 As shown in (c), a pulse voltage can be applied to the word line terminal WL and the source line terminal SL, and the bit line terminal BL can be grounded, which means a write reset operation is performed on the memristor R so that the memristor R is in a high impedance state.

[0044] In at least one embodiment of this disclosure, the low-resistance state of the memristor is referred to as the "1 state" and is used to store data 1. That is, performing a write set operation on the memristor can make the corresponding data value of the memristor 1. The high-resistance state of the memristor is referred to as the "0 state" and is used to store data 0. That is, performing a write reset operation on the memristor can make the corresponding data value of the memristor 0.

[0045] In at least one embodiment of this disclosure, a preset target resistance value can be used to distinguish between the low-resistance state and the high-resistance state of the memristor. For example, if the preset target resistance value is 100kΩ, then memristors with a resistance value less than 100kΩ are in a "1 state" with a corresponding data value of 1, and memristors with a resistance value greater than 100kΩ are in a "0 state" with a corresponding data value of 0. The preset target resistance value can be set according to the actual characteristics of the memristor, and the embodiments of this disclosure do not limit this.

[0046] In at least one embodiment of this disclosure, the memristor can be a resistive switching memristor, such as a non-volatile memristor or a threshold-switching memristor. The memristor in at least one embodiment of this disclosure has memory characteristics and good data retention. It can change its conductance state under the action of an external voltage excitation signal and maintain its conductance state without external electrical signal excitation; for example, it is a conductive filament device or a Mott device.

[0047] For memristors with memory characteristics, such as non-volatile memristors, different write operation conditions have different effects on the resistance value of the memristor. For example, a write set operation can put the memristor in a low-resistance state. Furthermore, applying write set voltages with different pulse amplitudes and pulse widths to the word line and bit line can also make the upper limit resistance value of the memristor in the low-resistance state different.

[0048] It should be noted that due to process errors and external factors, even multiple memristors manufactured using the same process may have different resistance values ​​in actual use. Although the resistance values ​​of multiple memristors may not be exactly the same under the same write operation conditions, the distribution of the resistance values ​​of multiple memristors usually falls within a certain range. In the embodiments of this disclosure, the "upper limit resistance value" and "lower limit resistance value" are the endpoints of the resistance value distribution range of multiple memristors of the same specification at a certain voltage. In at least one embodiment of this disclosure, the target resistance value can be determined based on the actual characteristics of the memristor, and different write operation conditions can be set according to the relationship between the upper limit resistance value or lower limit resistance value of the memristor resistance value distribution range and the target resistance value.

[0049] In at least one embodiment of this disclosure, the write-set operation can be divided into a first set operation and a second set operation based on the memory characteristics of the memristor. The first set operation and the second set operation are used to make the upper limit resistance value of the memristor in the low-resistance state different. In at least one embodiment of this disclosure, the first set operation is used to make the resistance value of the memristor less than a first target resistance value, and the second set operation is used to make the resistance value of the memristor less than a second target resistance value, and the first target resistance value is less than the second target resistance value. For example, a memristor with a resistance value of less than 100kΩ is in a low-resistance state. Both the first set operation and the second set operation can make the resistance value of the memristor less than 100kΩ, but the first set operation makes the upper limit resistance value of the memristor not exceed the first target resistance value (e.g., 33kΩ), and the second set operation makes the upper limit resistance value of the memristor not exceed the second target resistance value (e.g., 50kΩ).

[0050] In at least one embodiment of this disclosure, the first set operation can make the resistance value of the memristor in the low-resistance state smaller. Therefore, the first set operation can also be called a "strong SET" operation, and the memristor after the strong SET operation is in a "strong 1 state". The second set operation can make the resistance value of the memristor in the low-resistance state larger. Therefore, the second set operation can also be called a "weak SET" operation, and the memristor after the weak SET operation is in a "weak 1 state".

[0051] In at least one embodiment of this disclosure, the first set voltage of the first set operation is greater than the second set voltage of the second set operation. For example, when the same pulse amplitude and pulse width are applied to the word line terminal WL, the pulse amplitude of the first set voltage applied to the bit line terminal BL is greater than the pulse amplitude of the second set voltage.

[0052] For example, such as Figure 2A As shown, when the first target resistance is 33kΩ, the first set operation in the write set operation is performed on 100 memristors of the same specifications (including size, material, manufacturing process, etc., similar below). The conditions for this first set operation are: a voltage with a pulse width of 50ns and a pulse amplitude of 1.8V is applied to the word line terminal WL, and a voltage with a pulse width of 50ns and a pulse amplitude of 2.2V is applied to the bit line terminal BL. That is, a strong SET operation is performed on the 100 memristors, and the resistance distribution of the 100 memristors is obtained as follows. Figure 2A As shown in curve 1, the resistance values ​​of all 100 memristors are less than the first target resistance value of 33kΩ. At this time, all 100 memristors are in a strong 1 state. When the second target resistance value is 50kΩ, the second set operation in the write set operation is selected for the 100 memristors. The conditions for the second set operation are: a voltage with a pulse width of 50ns and a pulse amplitude of 1.8V is applied to the word line terminal WL, and a voltage with a pulse width of 50ns and a pulse amplitude of 1.8V is applied to the bit line terminal BL. That is, a weak SET operation is performed on the 100 memristors, and the resistance value distribution of the 100 memristors is as follows. Figure 2A As shown in curve 2, the resistance values ​​of all 100 memristors are less than the first target resistance value of 50kΩ. At this time, all 100 memristors are in a weak 1 state. Here, the data value corresponding to the memristor in either a strong 1 state or a weak 1 state is 1.

[0053] For memristors with memory characteristics, such as non-volatile memristors, different write operation conditions have different effects on the resistance value of the memristor. For example, a write reset operation can put the memristor in a high-resistance state. Furthermore, applying write reset voltages with different pulse amplitudes and pulse widths to the word line and bit line can also make the lower limit resistance value of the memristor in the high-resistance state different. In at least one embodiment of this disclosure, the write reset operation can be divided into a first reset operation and a second reset operation according to the memory characteristics of the memristor. The first reset operation and the second reset operation are used to make the lower limit resistance value of the memristor in the high-resistance state different. In at least one embodiment of this disclosure, the first reset operation is used to make the resistance value of the memristor greater than a third target resistance value, the second reset operation is used to make the resistance value of the memristor greater than a fourth target resistance value, and the third target resistance value is greater than the fourth target resistance value. For example, a memristor with a resistance greater than 100kΩ is in a high-resistance state. Both the first reset operation and the second reset operation can make the resistance of the memristor greater than 100kΩ. However, the first reset operation makes the lower limit resistance of the memristor no less than the first target resistance value (e.g., 300kΩ), while the second reset operation makes the lower limit resistance of the memristor no less than the second target resistance value (e.g., 200kΩ).

[0054] In at least one embodiment of this disclosure, the first reset operation can make the resistance value of the memristor in the high-resistivity state larger. Therefore, the first reset operation can also be called a "strong RESET" operation, and the memristor after the strong RESET operation is in a "strong 0 state". The second reset operation can make the resistance value of the memristor in the high-resistivity state smaller. Therefore, the second reset operation can also be called a "weak RESET" operation, and the memristor after the weak RESET operation is in a "weak 0 state".

[0055] In at least one embodiment of this disclosure, the first reset voltage of the first reset operation is greater than the second reset voltage of the second reset operation. For example, when the same pulse amplitude and pulse width are applied to the word line terminal WL, the pulse amplitude of the first reset voltage applied to the bit line terminal BL is greater than the pulse amplitude of the second reset voltage.

[0056] For example, such as Figure 2B As shown, when the third target resistance is 300kΩ, the first reset operation in the write reset operation is selected for 100 memristors of the same specification. The conditions for this first reset operation are: a voltage with a pulse width of 50ns and a pulse amplitude of 5.0V is applied to the word line terminal WL, and a voltage with a pulse width of 50ns and a pulse amplitude of 1.8V is applied to the bit line terminal BL. That is, a strong RESET operation is performed on the 100 memristors, and the resistance distribution of the 100 memristors is obtained as follows. Figure 2BAs shown in curve 4, the resistance values ​​of all 100 memristors are greater than the third target resistance value of 300kΩ. At this point, all 100 memristors are in a strong 0 state. When the fourth target resistance value is 200kΩ, the second reset operation in the write reset operation is selected for the 100 memristors. The conditions for the second reset operation are: a voltage with a pulse width of 50ns and a pulse amplitude of 5.0V is applied to the word line terminal WL, and a voltage with a pulse width of 50ns and a pulse amplitude of 1.6V is applied to the bit line terminal BL. That is, a weak RESET operation is performed on the 100 memristors, and the resistance value distribution of the 100 memristors is as follows. Figure 2B As shown in curve 3, the resistance values ​​of all 100 memristors are less than the fourth target resistance value of 200kΩ. At this point, all 100 memristors are in a weak 0 state. Here, the data value corresponding to the memristors in both strong and weak 0 states is 0.

[0057] In at least one embodiment of this disclosure, the memory characteristic of the memristor refers to its ability to remember different previous write operations. Previous write operations on the memristor can influence the result of the current recovery operation. Therefore, a recovery operation can be performed on the memristor based on this memory characteristic, thereby achieving data backtracking. In at least one embodiment of this disclosure, the recovery operation includes a third set operation and a third reset operation. The operating conditions of the third set operation and the third reset operation in the recovery operation can be set according to the actual characteristics of the memristor. For example, they can be set by adjusting parameters such as pulse width, pulse amplitude, and pulse number (or execution count) so that the memristor can backtrack to the resistance value state before the write operation.

[0058] In at least one embodiment of this disclosure, the recovery operation can be applied to the memristor in the same manner as the write operation; that is, the third set operation and the third reset operation can be applied to the memristor in the same manner as the write set operation and the write reset operation. For example, in Figure 1In the memristor cell shown, the third set or third reset operation can apply a pulse voltage to the memristor through the word line terminal WL and the source line terminal SL. However, the recovery operation is not the same as the write operation; that is, the operating conditions for the third set and third reset operations are not the same as the operating conditions for the write set and write reset operations. For example, the pulse width and pulse amplitude of the third set operation can be the same as those of the first or second set operation, but the number of pulses (or execution count, e.g., 10 times) of the third set operation must be greater than the number of pulses (or execution count, e.g., 1 time) of the first and second set operations. Alternatively, the number of pulses for both the third set and write set operations can be 1 (or the number of executions can be 1), but the pulse amplitude of the third set operation must be greater than the pulse amplitude of the first and second set operations. The setting for the third reset operation is similar and will not be described further here.

[0059] Additionally, it should be noted that for the memristor after data retrieval, it is only necessary to distinguish whether its resistance value state corresponds to the "1 state" of data value 1 or the "0 state" of data value 0, without further distinguishing between "strong" and "weak". That is, it is only necessary to compare the resistance value of the memristor after data retrieval with the preset target resistance value, without comparing it with the first, second, third, and fourth target resistance values. Here and in the following text, "1 state" refers to the memristor being in a low resistance state, that is, the resistance value of the memristor is less than the preset target resistance value; "0 state" refers to the memristor being in a high resistance state, that is, the resistance value of the memristor is greater than the preset target resistance value.

[0060] For memristors that have undergone different write and set operations, applying a third reset operation in the recovery process can restore the memristor to its "1 state" or "0 state" before the write and set operations. For example, for a memristor that has undergone a first set operation and is currently in a "strong 1 state", applying a third reset operation will restore the memristor's resistance value to a "1 state". For a memristor that has undergone a second set operation and is currently in a "weak 1 state", applying a third reset operation will restore the memristor's resistance value to a "0 state".

[0061] For example, such as Figure 3A As shown, the conditions for the third reset operation are: a voltage with a pulse width of 50ns and a pulse amplitude of 5.0V is applied to the word line terminal WL, and a voltage with a pulse width of 50ns and a pulse amplitude of 1.8V is applied to the bit line terminal BL. The number of pulses is 10, that is, the third reset operation is performed 10 times on 100 memristors of the same specification. The result of applying the third reset operation to 100 memristors that have undergone the first set operation (strong SET operation) is as follows. Figure 3AAs shown in curve 5, the resistance values ​​of all 100 memristors are less than the preset target resistance value of 100kΩ, i.e., they are in a low-resistance state, or "state 1". The result of applying a third reset operation to the 100 memristors that have undergone a second set operation (weak SET operation) is as follows: Figure 3A As shown in curve 6, the resistance values ​​of all 100 memristors are greater than the preset target resistance value of 100kΩ, i.e., they are in a high-resistance state, or "0 state". Therefore, according to the memory characteristics of memristors, memristors in a "strong 1 state" due to a strong SET operation will remain in a "1 state" after a reset operation, while memristors in a "weak 1 state" due to a weak SET operation will become a "0 state" after a reset operation. Thus, the resistance value state of the memristor after a reset operation can be used to distinguish whether the historical write operation was a strong SET operation or a weak SET operation.

[0062] For memristors that have undergone different write-reset operations, applying a third set operation in the recovery operation can restore the memristor to its "1 state" or "0 state" before the write-reset operation. For example, for a memristor that has undergone a first reset operation and is currently in a "strong 0 state", applying a third set operation will restore the memristor's resistance value to a "0 state". For a memristor that has undergone a second reset operation and is currently in a "weak 0 state", applying a third set operation will restore the memristor's resistance value to a "1 state".

[0063] For example, such as Figure 3B As shown, the conditions for the third set operation are: a voltage with a pulse width of 50ns and a pulse amplitude of 1.6V is applied to the word line terminal WL, and a voltage with a pulse width of 50ns and a pulse amplitude of 2.0V is applied to the bit line terminal BL. The number of pulses is 10, that is, the third set operation is performed 10 times on 100 memristors of the same specification. For example, as Figure 3B As shown in curve 8, after applying the third set operation to 100 memristors that have undergone the first reset operation (strong RESET operation), the resistance values ​​of all 100 memristors are greater than the preset target resistance value of 100kΩ, that is, they are in a high-resistance state, or "0 state". Figure 3BAs shown in curve 7, after applying the third set operation to 100 memristors that have undergone the second reset operation (weak RESET operation), the resistance values ​​of all 100 memristors are less than the preset target resistance value of 100kΩ, i.e., they are in a low resistance state, or "state 1". Therefore, according to the memory characteristics of memristors, memristors that were in a "strong 0 state" due to a strong RESET operation in the past will remain in a "0 state" after the set recovery operation, while memristors that were in a "weak 0 state" due to a weak RESET operation in the past will become a "state 1" after the set recovery operation. Thus, the resistance value state of the memristor after the set recovery operation can be used to distinguish whether the past write operation was a strong RESET operation or a weak RESET operation.

[0064] It is important to note that in the embodiments of this disclosure, whether a memristor is in a "strong 1 state," "weak 1 state," "strong 0 state," or "weak 0 state" is determined by the write operation applied to it, rather than by the magnitude of its resistance value. For example, in... Figure 2A In the scenario shown, the memristor's resistance value may remain the same even under different write-set operations. For example, as Figure 2A As shown in curve 1, after a strong SET operation, there is a certain probability that the resistance value of the memristor may be 25kΩ, such as... Figure 2A As shown in curve 2, there is a certain probability that the resistance value of the memristor may be 25kΩ after a weak SET operation. However, the state of the memristor is determined only by whether a "strong SET" or "weak SET" operation is performed on it, and not by its resistance value. For example, the resistance value of memristor A is 25kΩ after a strong SET operation, and the resistance value of memristor B is also 25kΩ after a weak SET operation. However, at this time, memristor A is in a "strong 1 state", while memristor B is in a "weak 1 state".

[0065] In other words, in the embodiments of this disclosure, even if the resistance values ​​of two memristors are the same, the operations they remember are not necessarily the same. For example, memristor A and memristor B have the same resistance value, but memristor A is in a "strong 1 state" after a strong SET operation, while memristor B is in a "weak 1 state" after a weak SET operation. Then, after performing the same recovery operation (third reset operation) on memristor A and memristor B, memristor A will become a "1 state", while memristor B will become a "0 state".

[0066] Based on the memory characteristics of the memristor described above, at least one embodiment of this disclosure proposes a data recovery technique. This data recovery technique relies on the data writing method and the data recovery method described above, and can realize data recovery function to prevent the loss of important data.

[0067] Figure 4A schematic diagram of a data writing method provided in at least one embodiment of this disclosure is shown. The data writing method includes the following two steps:

[0068] S100: Retrieve the first data value of the old data stored in the memristor;

[0069] S200: Based on the first data value and the second data value of the new data to be written, select a write operation from a variety of write operations and perform the selected write operation on the memristor to write the second data value.

[0070] For example, in at least one embodiment of this disclosure, during the data writing process, it is necessary not only to obtain the data value to be written (new data value), but also to obtain the data value currently stored in the memristor (old data value), that is, the first data value of the old data stored in the memristor. For example, in step S100, a read operation voltage can be applied to the memristor to read the resistance value of the memristor. The first data value of the old data currently stored in the memristor is obtained according to the relationship between the read resistance value of the memristor and the preset target resistance value. For example, when the resistance value of the memristor is less than the target resistance value, the memristor is in a "1 state", and the first data value is 1; when the resistance value of the memristor is greater than the target resistance value, the memristor is in a "0 state", and the first data value is 0.

[0071] For example, in step S200, the second data value of the new data to be written can be 1 or 0. Before writing the data, the write operation to be selected is determined based on the second data value. For example, when the new data to be written is 1, a write set operation is performed on the memristor, and when the new data to be written is 0, a write reset operation is performed on the memristor.

[0072] For example, the write set operation includes a first set operation and a second set operation. In step S200, it is also necessary to determine which set operation to perform on the memristor based on the first data value of the old data. For example, when the second data value to be written is 1 and the first data value is 1, the memristor is set by a first set operation (strong SET operation) to make the memristor in a "strong 1 state"; when the second data value to be written is 1 and the first data value is 0, the memristor is set by a second set operation (weak SET operation) to make the memristor in a "weak 1 state".

[0073] For example, the write reset operation includes a first reset operation and a second reset operation. In step S200, it is also necessary to determine which type of reset operation to perform on the memristor based on the first data value of the old data. For example, when the second data value to be written is 0 and the first data value is 1, a second reset operation (weak RESET operation) is performed on the memristor to make the memristor in a "weak 0 state"; when the second data value to be written is 0 and the first data value is 0, a first reset operation (strong RESET operation) is performed on the memristor to make the memristor in a "strong 0 state".

[0074] The data writing method provided in at least one embodiment of this disclosure is based on the memory characteristics of memristors for different write operations. Different write operations are selected to implement data writing, which can provide the preconditions for data backtracking and recovery, and does not affect the normal reading and use of the currently stored data.

[0075] Figure 5 A flowchart illustrating a data writing method provided in at least one embodiment of this disclosure is shown. Figure 5 As shown, the data writing method includes the following steps:

[0076] Step S110: Read the resistance value of the memristor to obtain the first data value of the old data stored in the memristor;

[0077] Step S210: Determine whether the first data value of the old data currently stored in the memristor is 1 or 0;

[0078] Step S220: Obtain the second data value of the new data to be written and determine whether the second data value is 1 or 0;

[0079] Steps S221 to S224: Based on the judgment results of steps S210 and S220, select one of the various write operations to perform on the memristor to write the second data value.

[0080] For example, in Figure 5 In the data writing method shown, when step S210 determines that the first data value of the currently stored old data is 1, and step S220 determines that the second data value of the new data to be written is 1, step S221 is executed to perform a strong SET operation on the memristor so that the value of the new data written to the memristor is 1, and at the same time the memristor is in a "strong 1 state".

[0081] For example, when step S210 determines that the first data value of the currently stored old data is 1, and step S220 determines that the second data value of the new data to be written is 0, step S224 is executed to perform a weak RESET operation on the memristor so that the value of the new data written to the memristor is 0, and at the same time the memristor is in a "weak 0 state".

[0082] For example, when step S210 determines that the first data value of the currently stored old data is 0, and step S220 determines that the second data value of the new data to be written is 1, step S222 is executed to perform a weak SET operation on the memristor so that the value of the new data written to the memristor is 1, and at the same time the memristor is in a "weak 1 state".

[0083] For example, when step S210 determines that the first data value of the currently stored old data is 0, and step S220 determines that the second data value of the new data to be written is 0, step S223 is executed to perform a strong RESET operation on the memristor so that the value of the new data written to the memristor is 0, and at the same time the memristor is in a "strong 0 state".

[0084] Figure 6 A schematic diagram illustrating another data writing method provided in at least one embodiment of this disclosure, and... Figure 5 Compared to the embodiments shown, Figure 6 The data writing method also includes step S300: verifying whether the memristor needs to perform the selected write operation again.

[0085] For example, in step S300, it can be verified whether the resistance value of the memristor has reached the preset target resistance value, and whether the data writing result is correct. If the verified data writing result is correct, the current data writing ends. If the verified data writing result is incorrect, the selected write operation is performed on the memristor again. This selected write operation is also known as the historical write operation. The subsequent write operation makes the state of the memristor the same as the state of the previous historical write operation. The states described here include "strong 1 state", "weak 1 state", "strong 0 state", and "weak 0 state".

[0086] The data writing method provided in at least one embodiment of this disclosure can ensure the accuracy of data writing and does not affect the normal reading and use of data. As described below, it can be used to realize data backtracking without affecting the correctness of data backtracking. The data written into the memristor can be used for calculation or storage and has the advantages of long-term storage and not easy to lose.

[0087] Figure 7A and Figure 7B A flowchart illustrating another data writing method provided in at least one embodiment of this disclosure. Figure 5 In comparison, Figure 7A and Figure 7B In the data writing method shown, step S220 (in Figure 7A The middle part is step S2201, in Figure 7BStep S2202 can be performed before step S110. That is, the second data value of the new data to be written can be obtained first, and it can be determined whether the second data value is 1 or 0 before reading the resistance value of the memristor to obtain the first data value of the old data stored in the memristor. The embodiments of this disclosure do not limit the order in which the first data value and the second data value are obtained.

[0088] like Figure 7A As shown, after obtaining the second data value of the new data to be written as 1 in step S2201, step S110 is executed. The data currently stored in the memristor is obtained according to the resistance value of the memristor read in step S110. Then, step S210 is executed: it is determined whether the first data value currently stored in the memristor is 1 or 0.

[0089] If the first data value currently stored in the memristor is 1, then execute step S221: perform a strong SET operation on the memristor. If the first data value currently stored in the memristor is 0, then execute step S222: perform a weak SET operation on the memristor.

[0090] In step S310, the resistance value of the memristor is read again, and then step S321 is executed to determine whether the resistance value of the memristor is less than the preset target resistance value, that is, to determine whether the second data value of the new data written to the memristor is 1. If the determination result is "yes", the data writing ends. If the determination result is "no", then step S331 is executed: the memristor is "strong SET" or "weak SET" again. Steps S310 to S331 are executed repeatedly until the second data value written is 1.

[0091] In step S331, whether a "strong SET" or "weak SET" operation is performed on the memristor depends on whether step S221 or step S222 is executed. For example, in step S210, if the first data value currently stored in the memristor is 1, then step S221 is executed to perform a strong SET operation on the memristor. After executing steps S310 and S321, if the resistance value of the memristor does not reach the preset target resistance value, that is, the memristor fails to be in the "1 state", then in step S331, a strong SET operation is performed on the memristor again to make the memristor in the "strong 1 state". This ensures both the correctness of data writing (writing 1) and that the memristor can be traced back to the correct "strong 1 state" when data is traced back. The process of selecting to perform a "weak SET" operation in step S331 is similar to the process of selecting to perform a "strong SET" operation, and will not be described again here.

[0092] like Figure 7BAs shown, after obtaining the second data value of the new data to be written as 0 in step S2202, step S110 is executed. The data currently stored in the memristor is obtained according to the resistance value of the memristor read in step S110. Then, step S210 is executed: determine whether the first data value currently stored in the memristor is 1 or 0.

[0093] If the first data value currently stored in the memristor is 0, then step S223 is executed: perform a strong RESET operation on the memristor. If the first data value currently stored in the memristor is 1, then step S224 is executed: perform a weak RESET operation on the memristor.

[0094] In step S310, the resistance value of the memristor is read again, and then step S322 is executed to determine whether the resistance value of the memristor is greater than the preset target resistance value, that is, to determine whether the second data value of the new data written to the memristor is 0. If the determination result is "yes", the data writing ends. If the determination result is "no", then step S332 is executed: the memristor is subjected to a "strong RESET" or "weak RESET" operation again. Steps S310 to S332 are executed repeatedly until the second data value written is 0.

[0095] In step S332, whether a "strong RESET" or "weak RESET" operation is performed on the memristor depends on whether step S223 or step S224 is executed. For example, in step S210, if the first data value currently stored in the memristor is 0, then step S223 is executed to perform a strong RESET operation on the memristor. After executing steps S310 and S322, if the resistance value of the memristor does not reach the preset target resistance value, that is, the memristor fails to be in the "0 state", then in step S332, a strong RESET operation is performed on the memristor again to make the memristor in the "strong 0 state". This ensures both the correctness of data writing (writing 0) and that the memristor can be backed to the correct "strong 0 state" when data is traced back. The process of selecting to perform a "weak RESET" operation in step S332 is similar to the process of selecting to perform a "strong RESET" operation, and will not be described again here.

[0096] Figure 8 This diagram illustrates a data backtracking method provided in at least one embodiment of the present disclosure. The data backtracking method includes the following three steps:

[0097] Step S400: Obtain the second data value currently stored in the memristor after the data write method operation;

[0098] Step S500: Based on the second data value currently stored in the memristor, select one recovery operation from a variety of recovery operations and perform the selected recovery operation on the memristor;

[0099] Step S600: Obtain the third data value of the memristor after the selected recovery operation has been performed, and obtain the first data value of the old data based on the third data value.

[0100] For example, in at least one embodiment of this disclosure, the data backtracking method is based on the above-described data writing method. That is, when writing new data to the memristor to replace old data, the above-described data writing operation is performed on the memristor, so that the memristor can be in a special state that remembers the corresponding different write operations. Thus, during data backtracking, different recovery operations can be performed on the memristor according to the special state remembered by the memristor. Based on the different recovery operations and the state of the memristor after the recovery operation, the data value of the old data can be obtained, thereby realizing data recovery.

[0101] For example, in step S500, the second data value currently stored in the memristor is the second data value of the new data. For example, when the currently stored second data value is 0, the memristor is subjected to N third set operations to restore the old data; when the currently stored second data value is 1, the memristor is subjected to M third reset operations to restore the old data.

[0102] The operating conditions for the recovery operation can be set according to the actual situation, and the recovery operation does not need to distinguish between "strong" and "weak" as the write operation. For example, during data rollback, the same recovery operation can be performed on all memristors in the storage device, that is, the same third set operation or third reset operation under the same conditions can be performed on all memristors. For example, M and N can be the same or different. For example, a recovery operation can be performed on a memristor once, or multiple recovery operations can be performed on a memristor, such as 3 times, 5 times, 10 times, etc. The pulse conditions and execution number (or number of pulses) of the third set operation and the fourth set operation are related to the characteristics of the memristor, as long as it can ensure that the data can be rolled back to the correct value. The embodiments of this disclosure do not impose any limitations on this.

[0103] For example, in step S600, when the memristor obtained after data backtracking is in the "0 state", that is, when the third data value corresponding to the memristor is 0, it can be determined that the old data is 0. When the memristor obtained after data backtracking is in the "1 state", that is, when the third data value corresponding to the memristor is 1, it can be determined that the old data is 1.

[0104] The data recovery method provided in at least one embodiment of this disclosure can recover data in real time, quickly and accurately, without occupying additional hardware storage space, greatly improving data recoverability, reducing the risk of data loss, and improving the reliability of computer systems.

[0105] Figure 9 A flowchart of a data backtracking method provided in at least one embodiment of this disclosure, the data backtracking method including the following steps:

[0106] Step S410: Read the memristor resistance value;

[0107] Step S510: Select a recovery operation from a variety of recovery operations based on the second data value currently stored in the memristor;

[0108] If the second data value is 0, then execute step S521: perform N third set operations (SET operations) on the memristor;

[0109] If the second data value is 1, then execute step S522: perform M third reset operations (RESET operations) on the memristor;

[0110] Step S610: Read the resistance value of the memristor again after the recovery operation is completed;

[0111] Step S620: Obtain the third data value currently stored in the memristor after the selected recovery operation has been performed;

[0112] If the third data value is 0, then execute step S621: output data backtracking result 0, that is, the old data is 0;

[0113] If the third data value is 1, then execute step S622: output data backtracking result 1, that is, the old data is 1.

[0114] For example, if the current second data value is determined to be 0 in step S510, then in step S521, the memristor undergoes N=10 third set operations (SET operations). If, after the 10 SET operations, the resistance value of the memristor read in step S610 is less than the preset target resistance value, that is, the memristor is in a low resistance state ("1 state"), it indicates that the memristor has been subjected to a "weak RESET" operation, and thus the old data can be obtained as 1. If, after the 10 SET operations, the resistance value of the memristor read in step S610 is greater than the preset target resistance value, that is, the memristor is in a high resistance state ("0 state"), it indicates that the memristor has been subjected to a "strong RESET" operation, and thus the old data can be obtained as 0.

[0115] For example, if in step S510 the current second data value is determined to be 1, then in step S522 the memristor undergoes a third reset operation (RESET operation) M=10 times. If, after the 10 RESET operations, the resistance value of the memristor read in step S610 is greater than the preset target resistance value, that is, the memristor is in a high resistance state ("0 state"), it indicates that the memristor has been subjected to a "weak SET" operation, and thus the old data can be obtained as 0. If, after the 10 RESET operations, the resistance value of the memristor read in step S610 is less than the preset target resistance value, that is, the memristor is in a low resistance state ("1 state"), it indicates that the memristor has been subjected to a "strong SET" operation, and thus the old data can be obtained as 1.

[0116] Figure 10 This demonstrates the backtracking effect achieved by the data backtracking method provided by at least one embodiment of this disclosure, for example, Figure 10 The diagram illustrates a 10x10 data structure, where each square represents a data value. Black squares represent a value of "0", and white squares represent a value of "1". The data value of each square can be represented by the resistance value of a memristor unit. For example, the memristor unit can include a 1T1R structure or a 2T1R structure. A 1T1R memristor unit includes one switching transistor and one memristor, while a 2T1R memristor unit includes two switching transistors and one memristor. It should be noted that the transistors used in the embodiments of this disclosure can be thin-film transistors, field-effect transistors (e.g., MOS field-effect transistors), or other switching devices with similar characteristics. The source and drain of the transistors used here can be structurally symmetrical, so their structures can be indistinguishable. The embodiments of this disclosure do not limit the type of transistor used.

[0117] For a given that can be represented as Figure 10 The diagram shows a 10×10 data memristor array, comprising at least 100 memristor cells. Each memristor cell in a "1 state" corresponds to a data value of 1. Figure 10 The white squares in the diagram represent the data value 0 when each memristor cell is in the "0 state", which is the black square in Figure 10.

[0118] For example, when writing data, selecting the "weak RESET" operation will overwrite the white square in the first row and first column of the old data (first data value 1) with the black square in the new data (second data value 0); selecting the "strong RESET" operation will overwrite the black square in the first row and second column of the old data (first data value 0) with the black square in the new data (second data value 0); selecting the "weak SET" operation will overwrite the black square in the second row and first column of the old data (first data value 0) with the white square in the new data (second data value 1); selecting the "strong SET" operation will overwrite the white square in the second row and second column of the old data (first data value 1) with the white square in the new data (second data value 1).

[0119] For example, during data backtracking, the third set operation is selected to restore the memristor cells representing data in rows 1, 3, 5, 7, and 9 (currently storing 0 data), and the third reset operation is selected to restore the memristor cells representing data in rows 2, 4, 6, 8, and 10 (currently storing 1 data). The final data backtracking result is consistent with the old data, indicating that the old data has been successfully restored. Therefore, the data backtracking method provided in at least one embodiment of this disclosure, based on the unique memory characteristics of memristors, enables accurate restoration of old data even after it has been completely overwritten by new data. This saves storage space, reduces system energy consumption and the risk of data loss, and improves the security and stability of important data within the system.

[0120] Figure 11 At least one embodiment of the present disclosure provides a data writing device 10, which includes a data acquisition module 11 and a data writing module 12.

[0121] For example, data acquisition module 11 is configured to acquire a first data value of old data stored in the memristor. For example, this data acquisition module 11 can be used to implement... Figure 4 and Figure 6 Step S100 in the process, or can be used to implement Figure 5 Step S110 in the process can also be used to implement Figure 7A and Figure 7B Step S310 in the process.

[0122] For example, the data writing module 12 is configured to select a write operation from a variety of write operations based on a first data value and a second data value of new data to be written, and to perform the selected write operation on the memristor to write the second data value, wherein the memristor has different memory characteristics for the various write operations.

[0123] For example, the data writing device 10 may also include word line driving circuits, bit line driving circuits, source line driving circuits, etc., or be coupled to the memristor array through word line driving circuits, bit line driving circuits, source line driving circuits, etc. For example, the word line driving circuit includes multiple multiplexers (Mux) for switching word line input voltages; the bit line driving circuit includes multiple multiplexers for switching bit line input voltages; the source line driving circuit also includes multiple multiplexers for switching source line input voltages.

[0124] For example, the data acquisition module 11 can read the resistance value of the memristor in the memristor array according to the control signal of the multiplexer, thereby obtaining the current data value corresponding to the memristor. For example, the data writing module 12 can switch the word line input voltage or bit line input voltage to the corresponding voltage range according to the control signal of the multiplexer in the word line or bit line drive circuit. For example, when performing operations on the memristor... Figure 2A During the first set operation shown, the word line input voltage is set to 1.8V and the bit line input voltage is set to 2.2V. Other write operations are executed similarly and will not be described further here.

[0125] The aforementioned components of the data writing device 10 can be configured as software, hardware, firmware, or any combination thereof to perform specific functions. For example, some functions of the aforementioned modules can be implemented by dedicated digital and / or analog circuits, or by software code; the embodiments of this disclosure do not limit this.

[0126] Figure 12 At least one embodiment of the present disclosure provides a data backtracking device 20, which includes a data acquisition module 21, a data recovery module 22, and a data backtracking module 23.

[0127] For example, the data acquisition module 21 is configured to acquire the second data value currently stored in the memristor after the data writing method operation of at least one embodiment of this disclosure. For example, the data acquisition module 21 can be used to implement Figure 8 Step S400 or Figure 9 Step S410 in the process. For example, the data acquisition module 21 and Figure 11 The data acquisition module 11 in the data writing device 10 shown can be the same module or different modules.

[0128] For example, the data recovery module 22 is configured to select one of a variety of recovery operations based on the second data value currently stored in the memristor, and perform the selected recovery operation on the memristor.

[0129] For example, the data backtracking module 23 is configured to obtain the third data value of the memristor after the selected recovery operation has been performed, and obtain the first data value of the old data based on the third data value.

[0130] For example, the data backtracking device 20 may also include word line driving circuits, bit line driving circuits, source line driving circuits, etc., or be coupled to the memristor array through word line driving circuits, bit line driving circuits, source line driving circuits, etc. For example, the word line driving circuit includes multiple multiplexers (Mux) for switching word line input voltages; the bit line driving circuit includes multiple multiplexers for switching bit line input voltages; the source line driving circuit also includes multiple multiplexers for switching source line input voltages.

[0131] For example, data acquisition module 21 can read the resistance value of the memristor in the memristor array according to the control signal of the multiplexer, thereby obtaining the data value currently stored in the memristor after a write operation. For example, data recovery module 22 can switch the word line input voltage or bit line input voltage to the corresponding voltage range according to the control signal of the multiplexer in the word line or bit line drive circuit. For example, when performing a write operation on the memristor... Figure 3A During the third reset operation shown, the word line input voltage is set to 5.0V and the bit line input voltage is set to 1.8V. For example, when performing a reset on a memristor... Figure 3B During the third set operation shown, the word line input voltage is set to 1.6V and the bit line input voltage is set to 2.0V.

[0132] The aforementioned components of the data backtracking device 20 can be configured as software, hardware, firmware, or any combination thereof to perform specific functions. For example, some functions of the aforementioned modules can be implemented by dedicated digital and / or analog circuits, or by software code; the embodiments disclosed herein do not impose any limitations on this.

[0133] It should be noted that although the data writing device 10 or the data backtracking device 20 are divided into modules for performing corresponding processes in the above description, those skilled in the art should understand that the processes performed by each module can also be performed without any specific module division or without clear boundaries between modules.

[0134] Furthermore, in at least one embodiment of this disclosure, the data writing device 10 and the data recovery device 20 can be located in the same storage device, thereby enabling data writing and recovery within a single storage device. Alternatively, the data writing device 10 and the data recovery device 20 can be separately located in different storage devices, peripheral circuits, or other storage media to meet specific needs in different application scenarios. For example, the data recovery device 20 can be located in a peripheral circuit and coupled to multiple storage devices to select the appropriate storage device for data recovery based on actual needs. Or, for example, the data recovery device 20 can be independently located in a computer-readable medium, including but not limited to a portable hard drive, USB storage device, or flash memory, for data recovery of important or private data.

[0135] Although the present disclosure has been described in detail above with general descriptions and specific embodiments, modifications or improvements can be made to the embodiments of the present disclosure, which will be obvious to those skilled in the art. Therefore, all such modifications or improvements made without departing from the spirit of the present disclosure are within the scope of protection claimed by the present disclosure.

[0136] The following points should be noted regarding this disclosure:

[0137] (1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure. Other structures can be referred to the general design.

[0138] (2) For clarity, the thickness of layers or regions in the drawings used to describe embodiments of the present disclosure is enlarged or reduced, i.e., these drawings are not drawn to actual scale.

[0139] (3) Where there is no conflict, the embodiments of this disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

[0140] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. The scope of protection of this disclosure should be determined by the scope of protection of the claims.

Claims

1. A data writing method, comprising: Retrieve the first data value of the old data stored in the memristor; Based on the first data value and the second data value of the new data to be written, a write operation is selected from multiple write operations, and the selected write operation is used to write the second data value to the memristor. The memristor has different memory characteristics for the various write operations, and these different memory characteristics are used to perform recovery operations on the memristor. The various write operations include: write set operation and write reset operation. The write-set operation makes the data value of the memristor 1, and the write-set operation includes a first set operation and a second set operation. According to the memory characteristics of the memristor, the first set voltage of the first set operation is greater than the second set voltage of the second set operation. The write reset operation makes the data value of the memristor 0, and the write reset operation includes a first reset operation and a second reset operation. According to the memory characteristics of the memristor, the first reset voltage of the first reset operation is greater than the second reset voltage of the second reset operation.

2. The data writing method according to claim 1, wherein, The first set operation is used to make the resistance value of the memristor less than the first target resistance value, and the second set operation is used to make the resistance value of the memristor less than the second target resistance value, wherein the first target resistance value is less than the second target resistance value; The first reset operation is used to make the resistance value of the memristor greater than the third target resistance value, and the second reset operation is used to make the resistance value of the memristor greater than the fourth target resistance value, wherein the third target resistance value is greater than the fourth target resistance value.

3. The data writing method according to claim 1, wherein, Based on the first data value and the second data value of the new data to be written, a write operation is selected from multiple write operations, and the memristor is subjected to the selected write operation to write the second data value, including: When the second data value to be written is 1 and the first data value is 1, the first set operation is performed on the memristor; When the second data value to be written is 1 and the first data value is 0, the memristor is set by the second bit operation. When the second data value to be written is 0 and the first data value is 1, the memristor is subjected to the second reset operation; When the second data value to be written is 0 and the first data value is 0, the memristor is subjected to the first reset operation. The resistance of the memristor when the data value is 1 is less than the resistance of the memristor when the data value is 0.

4. The data writing method according to any one of claims 1-3, wherein, The memristor is a non-volatile memristor.

5. A data backtracking method, comprising: Obtain the memristor after the data writing method according to any one of claims 1-4; Based on the second data value currently stored in the memristor, select one recovery operation from a variety of recovery operations and perform the selected recovery operation on the memristor; Obtain the third data value of the memristor after the selected recovery operation has been performed, and obtain the first data value of the old data based on the third data value.

6. The data backtracking method according to claim 5, wherein, Based on the second data value currently stored in the memristor, a recovery operation is selected from multiple recovery operations, and the selected recovery operation is performed on the memristor, including: Read the resistance value of the memristor to obtain the second data value; Perform a third set operation or a third reset operation on the memristor based on the second data value.

7. The data backtracking method according to claim 6, wherein, Performing a third set operation or a third reset operation on the memristor based on the second data value includes: When the second data value is 0, the memristor is subjected to the third set operation N times; When the second data value is 1, the memristor is subjected to the third reset operation M times, where M and N are integers greater than or equal to 1.

8. The data backtracking method according to claim 5, wherein, Obtain the third data value of the memristor after the selected recovery operation, and obtain the first data value of the old data based on the third data value, including: When the third data value of the memristor is 0, the first data value of the old data is 0; When the third data value of the memristor is 1, the first data value of the old data is 1.

9. A data writing device, comprising: The data acquisition module is configured to acquire the first data value of the old data stored in the memristor; The data writing module is configured to select a write operation from multiple write operations based on the first data value and a second data value of new data to be written, and to perform the selected write operation on the memristor to write the second data value. The memristor has different memory characteristics for the various write operations, and these different memory characteristics are used to perform recovery operations on the memristor. The various write operations include: write set operation and write reset operation. The write-set operation makes the data value of the memristor 1, and the write-set operation includes a first set operation and a second set operation. According to the memory characteristics of the memristor, the first set voltage of the first set operation is greater than the second set voltage of the second set operation. The write reset operation makes the data value of the memristor 0, and the write reset operation includes a first reset operation and a second reset operation. According to the memory characteristics of the memristor, the first reset voltage of the first reset operation is greater than the second reset voltage of the second reset operation.

10. A data backtracking device, comprising: The data acquisition module is configured to acquire the second data value currently stored in the memristor after the data writing method operation according to any one of claims 1-4; The data recovery module is configured to select one recovery operation from a variety of recovery operations based on the second data value currently stored in the memristor, and perform the selected recovery operation on the memristor. The data backtracking module is configured to obtain the third data value of the memristor after the selected recovery operation has been performed, and to obtain the first data value of the old data based on the third data value.

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