Non-volatile memory device, method of operating the same, and memory system including the same

Abstract

The present application relates to a non-volatile memory device, an operating method thereof, and a memory system including the same. A memory system includes a non-volatile memory device including a plurality of memory blocks each including a plurality of memory cells coupled to a plurality of word lines, and a controller configured to control the non-volatile memory device to perform a read operation on the plurality of memory blocks, wherein the read operation includes a first operation of providing a first voltage level to the plurality of word lines, a second operation of discharging the plurality of word lines to a second voltage level, a third operation of providing a third voltage level less than the first voltage level to the plurality of word lines, and a fourth operation of discharging the plurality of word lines to a fourth voltage level.

Description

Technical Field

[0001] Various embodiments of this disclosure relate to semiconductor design technology, and more specifically, to a non-volatile memory device supporting read-refresh operations, a method of operating a non-volatile memory device, and a memory system including a non-volatile memory device. Background Technology

[0002] Memory systems are storage devices implemented using semiconductors such as silicon (Si), germanium (Ge), gallium arsenide (GaAs), and indium phosphide (InP). Memory systems are classified into volatile memory devices and non-volatile memory devices. Volatile memory devices are memory devices in which the data stored is lost when power is interrupted. Representative examples of volatile memory devices include static RAM (SRAM), dynamic RAM (DRAM), and synchronous DRAM (SDRAM). Non-volatile memory devices are memory devices in which the data stored is retained even when power is interrupted. Representative examples of non-volatile memory devices include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, phase-change random access memory (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), and ferroelectric RAM (FRAM). Flash memory is mainly divided into NOR type memory and NAND type memory.

[0003] Recently, the computing paradigm has shifted to ubiquitous computing, enabling computer systems to be accessed anytime, anywhere. As a result, the use of portable electronic devices such as mobile phones, digital cameras, and laptops has increased. Such portable electronic devices typically use or include memory systems that use or embed at least one memory device (i.e., a data storage device). The data storage device can serve as either the primary or secondary storage device for the portable electronic device.

[0004] In computing devices, unlike hard drives, data storage devices implemented as non-volatile semiconductor memory devices offer advantages such as superior stability and durability because they lack mechanically driven components (e.g., robotic arms) and feature high data access speeds and low power consumption. Examples of such data storage devices include Universal Serial Bus (USB) memory devices, memory cards with various interfaces, and solid-state drives (SSDs). Summary of the Invention

[0005] Various embodiments of this disclosure are intended to provide a non-volatile memory device capable of efficiently performing read-refresh operations, a method of operating a non-volatile memory device, and a memory system including a non-volatile memory device.

[0006] The technical problems to be solved in this disclosure are not limited to those described above, and those skilled in the art to which this disclosure pertains will clearly understand other unmentioned technical problems through the following description.

[0007] According to an embodiment of the present invention, a memory system may include: a non-volatile memory device including a plurality of memory blocks, each memory block including a plurality of memory cells coupled to a plurality of word lines; and a controller configured to control the non-volatile memory device to perform read operations on the plurality of memory blocks. The read operations may include: a first operation providing a first voltage level to the plurality of word lines, a second operation discharging the plurality of word lines to a second voltage level, a third operation providing a third voltage level less than the first voltage level to the plurality of word lines, and a fourth operation discharging the plurality of word lines to a fourth voltage level.

[0008] Each of the second and fourth voltage levels can be a ground voltage level.

[0009] The second voltage level can be essentially the same as the third voltage level, and the fourth voltage level can be the ground voltage level.

[0010] The first voltage level can be a level that is higher than the highest of the plurality of read voltage levels used for the read operation by a set level. The third voltage level can be any one of the plurality of read voltage levels.

[0011] Each of the plurality of memory blocks may further include a first select line and a second select line, with a plurality of word lines arranged between the first select line and the second select line. The read operation may further include: maintaining the first select line and the second select line substantially at an on-state voltage level during a first operation or a third operation; maintaining the first select line and the second select line substantially at either an on-state voltage level or an off-state voltage level during a second operation; and maintaining the first select line and the second select line substantially at an off-state voltage level during a fourth operation.

[0012] The controller can also be configured to determine when to start a read operation based on the number of accesses to multiple storage blocks.

[0013] The controller can also be configured to select one of the storage blocks as the target storage block for read operations based on the timing of the most recent access to the storage block.

[0014] Multiple memory blocks can be divided into a first block group and a second block group, where memory blocks share bit lines within each of the first and second block groups. The controller can also be configured to determine when to initiate read operations on memory blocks within the first block group based on the number of accesses to the first block group, and to determine when to initiate read operations on memory blocks within the second block group based on the number of accesses to the second block group.

[0015] The controller can also be configured to select a storage block within a first block group as the target storage block for a read operation based on the timing of the most recent access to a storage block within that first block group. The controller can also be configured to select a storage block within a second block group as the target storage block for a read operation based on the timing of the most recent access to a storage block within that second block group.

[0016] According to an embodiment of the present invention, a non-volatile memory device may include: a plurality of memory blocks, each memory block including a plurality of memory cells connected to a plurality of word lines; and control circuitry configured to perform a read operation on a selected memory block among the plurality of memory blocks. The read operation may include: a first operation providing a first voltage level to the plurality of word lines, a second operation discharging the plurality of word lines to a second voltage level, a third operation providing a third voltage level less than the first voltage level to the plurality of word lines, and a fourth operation discharging the plurality of word lines to a fourth voltage level.

[0017] The second and fourth voltage levels can be ground voltage levels.

[0018] The second voltage level can be essentially the same as the third voltage level, and the fourth voltage level can be the ground voltage level.

[0019] The first voltage level can be a level that is higher than the highest of the plurality of read voltage levels used for the read operation by a set level. The third voltage level can be any one of the plurality of read voltage levels.

[0020] Each of the plurality of memory blocks may further include a first select line and a second select line, with a plurality of word lines arranged between the first select line and the second select line. The read operation may further include: maintaining the first select line and the second select line substantially at an on-state voltage level during a first operation or a third operation; maintaining the first select line and the second select line substantially at either an on-state voltage level or an off-state voltage level during a second operation; and maintaining the first select line and the second select line substantially at an off-state voltage level during a fourth operation.

[0021] According to an embodiment of the present invention, an operation method for a non-volatile memory device is provided. The non-volatile memory device includes a plurality of memory blocks, each memory block including a plurality of memory cells connected to a plurality of word lines. The operation method may include: selecting at least one of the plurality of memory blocks as a selected memory block; and performing a read operation on the selected memory block. The read operation may include: a first operation providing a first voltage level to the plurality of word lines; a second operation discharging the plurality of word lines to a second voltage level after the first operation; a third operation providing a third voltage level lower than the first voltage level to the plurality of word lines after the second operation; and a fourth operation discharging the plurality of word lines to a fourth voltage level after the third operation.

[0022] Each of the second and fourth voltage levels can be a ground voltage level.

[0023] The second voltage level can be essentially the same as the third voltage level, and the fourth voltage level can be the ground voltage level.

[0024] The first voltage level can be a level that is a predetermined amount higher than the highest of the plurality of read voltage levels used for the read operation. The third voltage level can be one of the plurality of read voltage levels.

[0025] Each of the plurality of memory blocks may further include a first select line and a second select line, with a plurality of word lines arranged between the first select line and the second select line. The read operation may further include: maintaining the first select line and the second select line substantially at an on-state voltage level during a first operation or a third operation; maintaining the first select line and the second select line substantially at either an on-state voltage level or an off-state voltage level during a second operation; and maintaining the first select line and the second select line substantially at an off-state voltage level during a fourth operation.

[0026] According to an embodiment of the present invention, an operation method for a non-volatile memory device may include: increasing the level of a select line connected to a memory block to an on level while simultaneously increasing the level of a word line connected to the memory block to a first level; discharging the word line while simultaneously decreasing the level of the select line to an off level; increasing the level of the word line to a second level lower than the first level while simultaneously increasing the level of the select line to an on level; and discharging the level of the word line while simultaneously decreasing the level of the select line to an off level.

[0027] According to this technology, in a non-volatile memory device that supports read refresh operations, word lines included in a memory block selected as the target for read refresh operations can be continuously driven at two different voltage levels and then discharged.

[0028] Therefore, the increase in interference between memory cells caused by negative boost due to read refresh operations can be minimized. Attached Figure Description

[0029] Figure 1 This is a diagram illustrating an example of a memory system according to an embodiment of the present disclosure.

[0030] Figure 2 It is used to describe embodiments according to this disclosure. Figure 1 A diagram showing an example of a memory device.

[0031] Figure 3 It is used to describe embodiments according to this disclosure. Figure 1 and Figure 2 A diagram showing an example of a storage block.

[0032] Figure 4 This is a diagram illustrating an example of a read-refresh operation performed by a memory device according to an embodiment of the present disclosure.

[0033] Figure 5 This is for describing in detail the embodiments according to this disclosure. Figure 4 The diagram shows the first segment operation of the read-refresh operation.

[0034] Figure 6 and Figure 7 This is for describing in detail the embodiments according to this disclosure. Figure 4 The diagram shows the second segment operation of the read-refresh operation.

[0035] Figure 8 It is a diagram used to describe the threshold voltage distribution of a multi-stage unit according to an embodiment of the present disclosure. Detailed Implementation

[0036] Various examples of this disclosure are described in more detail below with reference to the accompanying drawings. However, aspects and features of the invention may be implemented in different ways to form other embodiments, including variations of any of the disclosed embodiments. Therefore, the invention is not limited to the embodiments set forth herein. Rather, the described embodiments are provided so that this disclosure is thorough and complete, and will fully convey the contents of this disclosure to those skilled in the art. Throughout this disclosure, similar reference numerals refer to similar parts in the various drawings and examples. It should be noted that references to “implementation,” “another embodiment,” etc., do not necessarily imply only one embodiment, and different references to any such phrases do not necessarily refer to the same embodiment.

[0037] It will be understood that although the terms “first,” “second,” “third,” etc., may be used herein to identify various elements, these elements are not limited by these terms. These terms are used to distinguish one element from another element that would otherwise have the same or similar name. Thus, a first element in one instance may be referred to as a second or third element in another instance without indicating any change in the element itself.

[0038] The accompanying drawings are not necessarily drawn to scale, and in some cases, the scale may be exaggerated to clearly illustrate the features of the embodiments. When an element is referred to as being connected to or coupled to another element, it should be understood that the former may be directly connected to or coupled to the latter, or electrically connected to or coupled to the latter via one or more intermediate elements. Furthermore, it will be understood that when an element is referred to as being “between” two elements, it may be the only element between the two elements, or there may be one or more intermediate elements.

[0039] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used herein, the singular form is intended to include the plural form and vice versa unless the context clearly indicates otherwise. Similarly, the indefinite articles “a” and “an” mean one or more, unless it is clear from the language or context that the intention is only one.

[0040] It will also be understood that, when used in this specification, the terms “comprising,” “including,” “included in,” and “contained in” specify the presence of the said element and do not exclude the presence or addition of one or more other elements. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0041] Unless otherwise defined, all terms used herein, including technical and scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains in light of this disclosure. It will also be understood that terms such as those defined in common dictionaries should be interpreted as having meanings consistent with their meanings in the context of this disclosure and the relevant field, and are not to be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0042] Numerous specific details are set forth in the following description in order to provide a thorough understanding of the invention. The invention may be practiced without some or all of these specific details. In other instances, well-known process structures and / or processes have not been described in detail so as not to unnecessarily obscure the invention.

[0043] It should also be noted that in some cases, as will be apparent to those skilled in the art, a feature or element described in connection with one embodiment may be used alone or in combination with other features or elements of another embodiment, unless otherwise specifically indicated.

[0044] Embodiments of this disclosure will now be described in detail with reference to the accompanying drawings, wherein similar reference numerals denote similar elements.

[0045] Figure 1 This is a diagram illustrating an example of a memory system according to an embodiment of the present disclosure.

[0046] Reference Figure 1 The data processing system 100 may include a host 102 that is coupled to or operatively connected to the memory system 110.

[0047] The host 102 may include any of the following: portable electronic devices such as mobile phones, MP3 players, and laptop computers; and electronic devices such as desktop computers, game consoles, televisions (TVs), and projectors.

[0048] Host 102 also includes at least one operating system (OS) that can generally manage and control the functions and operations performed within host 102. The OS can provide interoperability between host 102, which is coupled to memory system 110, and users using memory system 110. The OS can support functions and operations corresponding to user requests. By way of example, and not limitation, OSes can be categorized into general-purpose operating systems and mobile operating systems based on the mobility of host 102. General-purpose operating systems can be categorized into personal operating systems and enterprise operating systems, depending on system requirements or user environment. Personal operating systems, including Windows and Chrome, can be supported by general-purpose support services. However, enterprise operating systems can be specifically designed for protection and support of high performance, including Windows Server, Linux, Unix, etc. Furthermore, mobile operating systems can include Android, iOS, Windows Mobile, etc. Mobile operating systems can be supported by mobility support services or functions (e.g., power-saving features). Host 102 can include multiple operating systems. Host 102 can run multiple operating systems interlocked with memory system 110 corresponding to user requests. Host 102 can send multiple commands corresponding to user requests to memory system 110, thereby executing operations corresponding to the commands within memory system 110.

[0049] The storage device of memory system 110 may be implemented using volatile memory devices (e.g., dynamic random access memory (DRAM) and static RAM (SRAM)) and / or non-volatile memory devices such as read-only memory (ROM), mask ROM (MROM), programmable ROM (PROM), erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), ferroelectric RAM (FRAM), phase-change RAM (PRAM), magnetoresistive RAM (MRAM), resistive RAM (RRAM or ReRAM) and flash memory.

[0050] The memory system 110 may include a controller 130 and a memory device 150. The memory device 150 may store data to be accessed by the host 102. The controller 130 may control the operation of storing data in the memory device 150.

[0051] The controller 130 and memory device 150 included in memory system 110 can be integrated into a single semiconductor device, which can be included in any of the various types of memory systems discussed above in the examples.

[0052] By way of example, and not limitation, the controller 130 and memory device 150 can be implemented using an SSD. When the memory system 110 is used as an SSD, the operating speed of the host 102 connected to the memory system 110 can be significantly higher than that of a host 102 implemented with a hard disk. Furthermore, the controller 130 and memory device 150 can be integrated into a single semiconductor device to form memory cards such as PC cards (PCMCIA), compact flash memory cards (CF), memory cards such as smart media cards (SM, SMC), memory sticks, multimedia cards (MMC, RS-MMC, MCmicro), SD cards (SD, mini SD, micro SD, SDHC), general-purpose flash memory, etc.

[0053] The memory system 110 can be configured as, for example, a computer, an ultra-mobile PC (UMPC), a workstation, a netbook, a personal digital assistant (PDA), a portable computer, a web tablet, a tablet computer, a cordless phone, a mobile phone, a smartphone, an e-book reader, a portable multimedia player (PMP), a portable game console, a navigation system, a black box, a digital camera, a digital multimedia broadcasting (DMB) player, a three-dimensional (3D) television, a smart television, a digital audio recorder, a digital audio player, a digital image recorder, a digital image player, a digital video recorder, a digital video player, a storage device configured for a data center, a device capable of transmitting and receiving information in a wireless environment, one of various electronic devices configured for a home network, one of various electronic devices configured for a computer network, one of various electronic devices configured for a telematics network, a radio frequency identification (RFID) device, or one of various components configured for a computing system.

[0054] The memory device 150 may be a non-volatile memory device, and the data stored therein can be retained even when power is not supplied. The memory device 150 can store data provided by the host 102 through write operations, and provide the data stored therein to the host 102 through read operations.

[0055] Specifically, the memory device 150 may include a plurality of memory blocks <1:4>. Each of the memory blocks <1:4> (MEMORY BLOCKi, where i is one of 1 to 4) may include a plurality of memory cells and includes a first select line, a second select line, and a plurality of word lines disposed between the first select line and the second select line. The first select line may be a source select line, and the second select line may be a drain select line. For a more detailed configuration of each of the memory blocks <1:4> (MEMORY BLOCKi), refer to the following disclosure. Figure 3 The description.

[0056] Due to repeated access to a specific memory block among the plurality of memory blocks MEMORY BLOCK<1:4> included in the memory device 150, interference may occur, causing the threshold voltage of memory cells included in memory blocks adjacent to that specific memory block to rise. For example, when the first memory block MEMORY BLOCK1 among the plurality of memory blocks MEMORY BLOCK<1:4> is repeatedly accessed, the threshold voltage of memory cells included in each of the second to fourth memory blocks MEMORY BLOCK<2:4> adjacent to the first memory block MEMORY BLOCK1 may rise due to interference.

[0057] As described above, when the threshold voltage of a memory cell included in a specific memory block rises due to interference, a read refresh operation can be performed on the specific memory block to lower the threshold voltage of the memory cell. That is, the read refresh operation is an operation that boosts the channel voltage by driving the word line of the specific memory block at a specific level while the source path of the specific memory block is on, and then lowers the channel potential by discharging the word line of the specific memory block while the source path is off.

[0058] A read refresh operation can be performed on at least one of a plurality of memory blocks <1:4>. Therefore, the controller 130 can control the memory device 150 such that a read refresh operation is performed by selecting a block among the plurality of memory blocks <1:4> included in the memory device 150 that meets the set conditions at a set time point.

[0059] At this time, the controller 130 can determine the set time point based on the number of accesses to all the plurality of memory blocks MEMORYBLOCK<1:4> included in the memory device 150. That is, the controller 130 can determine the "set time point" based on the number of accesses to all the plurality of memory blocks MEMORY BLOCK<1:4>, which is the time point at which the operation of selecting at least one memory block as the target for a read refresh operation is to be performed. For example, the controller 130 can determine the time point when the number of accesses to all the plurality of memory blocks MEMORY BLOCK<1:4> included in the memory device 150 exceeds a set number of accesses as the "set time point". When a read refresh operation is performed in response to the number of accesses to all the plurality of memory blocks MEMORY BLOCK<1:4> exceeding the set number of accesses, the controller 130 can initialize the number of accesses to all the plurality of memory blocks MEMORY BLOCK<1:4> in order to perform subsequent read refresh operations.

[0060] Furthermore, the controller 130 can classify data-storing blocks among the plurality of memory blocks <1:4> included in the memory device 150 as storage blocks, and select at least one storage block as a block that meets a set condition, which is selected based on the amount of time elapsed since the most recent access. That is, the controller 130 can determine the "set condition" based on the amount of time elapsed since the most recent access among the storage blocks containing data; this "set condition" is a condition used to select at least one storage block as the target for a read refresh operation. For example, the controller 130 can classify the first to third memory blocks <1:3> among the plurality of memory blocks <1:4> as storage blocks, and select the third memory block <1:3>, which is the earliest accessed memory block among the first to third memory blocks <1:3>, as a block that meets the "set condition".

[0061] Furthermore, under the control of the controller 130, the memory device 150 may perform the following operations as a read refresh operation: a first operation driving multiple word lines included in a memory block selected as the target for the read refresh operation at a first voltage level, a second operation discharging the multiple word lines to a second voltage level, a third operation driving the multiple word lines at a third voltage level lower than the first voltage level, and a fourth operation discharging the multiple word lines to a fourth voltage level.

[0062] According to one embodiment, each of the second voltage level and the fourth voltage level may be a ground voltage (VSS) level. According to another embodiment, the second voltage level and the third voltage level may be substantially the same level, and the fourth voltage level may be a ground voltage (VSS) level.

[0063] According to the implementation, the first voltage level may be a level that is a predetermined amount higher than the highest level among a plurality of read voltage levels used for read refresh operations on a plurality of memory blocks <1:4>. Furthermore, the third voltage level may be one of a plurality of read voltage levels.

[0064] Furthermore, under the control of the controller 130, the memory device 150 can substantially maintain each of the first and second selection lines at an on-state voltage level in a segment where a first or third operation is performed, driving multiple word lines in a memory block selected as the target for a read refresh operation at a first or third voltage level. According to an embodiment, the on-state voltage level can be equal to or higher than the power supply voltage level. That is, the on-state voltage level can be the power supply voltage level, but it can also be a pump voltage level higher than the power supply voltage level.

[0065] Furthermore, under the control of controller 130, in the segment where a fourth operation is performed—discharging multiple word lines in the memory block selected for a read refresh operation to a fourth voltage level—while multiple word lines are already driven at a third voltage level, the memory device 150 can substantially maintain each of the first and second select lines at a cutoff voltage level. According to an embodiment, the cutoff voltage level can be equal to or lower than the ground voltage level. That is, the cutoff voltage level can be the ground voltage level, but it can also be a negative voltage level lower than the ground voltage level.

[0066] Furthermore, under the control of the controller 130, in the segment where the second operation is performed, in which the multiple word lines included in the memory block to be selected for the read refresh operation are discharged to the second voltage level, the memory device 150 can substantially keep each of the first and second select lines at one of the on-state and off-state voltage levels.

[0067] For reference, the purpose of performing a read refresh operation can be to further reduce the threshold voltage level of the memory cells included in a specific memory block, which has risen due to interference. Therefore, even if a read refresh operation is performed on a specific memory block, data may not be output from that specific memory block. Even if data is output, the data may be meaningless.

[0068] Figure 2 It is used to describe embodiments according to this disclosure. Figure 1 A diagram showing an example of a memory device.

[0069] Reference Figure 2 The memory device 150 according to embodiments of the present disclosure may include a memory cell array 151 in which data is stored. The memory device 150 may include peripheral circuitry 152 to 155, configured to perform programming operations for storing data in the memory cell array 151, reading operations for outputting the stored data, and erasing operations for erasing the stored data. The memory device 150 may be included in a controller (…). Figure 1 The control logic 156 controls the peripheral circuits 152 to 155 under the control of 130. The peripheral circuits 152 to 155 may include a line decoder 152, a page buffer 153, an input / output (I / O) buffer 154, and a voltage generator 155.

[0070] The memory cell array 151 may include multiple memory blocks <1:4>. Local lines and bit lines BL1 or BL2 may be connected to each memory block <1:4> (where i is one of 1 to 4). For example, the local lines may include at least one source select line SSL, at least one drain select line DSL, and multiple word lines WL arranged between the source select line SSL and the drain select line DSL. The local lines may be connected to each of the memory blocks <1:4> (MEMORYBLOCKi), and the bit lines BL1 or BL2 may be connected together to at least two of the memory blocks <1:4>. For example, the first bit line BL1 may be connected together to the first and second memory blocks <1:2>, and the second bit line BL2 may be connected together to the third and fourth memory blocks <3:4>. The first and second memory blocks MEMORY BLOCK<1:2> sharing the first bit line BL1 can be classified as the first block group 1511, and the third and fourth memory blocks MEMORY BLOCK<3:4> sharing the second bit line BL2 can be classified as the second block group 1512. That is, the first and second memory blocks MEMORY BLOCK<1:2> included in the first block group 1511 can be considered physically adjacent to each other. Similarly, the third and fourth memory blocks MEMORY BLOCK<3:4> included in the second block group 1512 can be considered physically adjacent to each other. On the other hand, the first and second memory blocks MEMORY BLOCK<1:2> included in the first block group 1511 and the third and fourth memory blocks MEMORY BLOCK<3:4> included in the second block group 1512 can be considered non-adjacent to each other. For reference, each of the block groups 1511 and 1512 included in the memory device 150 can represent a plane. Furthermore, the fact that two memory blocks are included in a block group 1511 or 1512 is merely an example, and in practice, more memory blocks can be included. Also, unlike the accompanying drawings, all the plurality of memory blocks <1:4> included in the memory device 150 can be commonly connected to a single bit line. That is, as referenced above... Figure 1As described, all memory blocks in the plurality of memory blocks <1:4> included in the memory device 150 can be physically adjacent to each other. The memory blocks <1:4> can be implemented in a two-dimensional or three-dimensional structure. For example, in a memory block <1:4> with a two-dimensional structure, memory cells can be stacked in a direction parallel to the substrate. For example, in a memory block <1:4> with a three-dimensional structure, memory cells can be arranged in a direction intersecting the substrate. This will be disclosed below. Figure 3 The description provides a more detailed configuration of each (MEMORY BLOCKi) in the memory block MEMORY BLOCK<1:4>.

[0071] Due to repeated access to a specific memory block among the multiple memory blocks MEMORY BLOCK<1:4> included in the memory device 150, interference may occur, causing the threshold voltage of memory cells included in memory blocks adjacent to the specific memory block to rise.

[0072] For example, when repeatedly accessing the first memory block MEMORY BLOCK1 of the first block group 1511 within a plurality of memory blocks MEMORY BLOCK<1:4>, the threshold voltage of the memory cells included in the second memory block MEMORY BLOCK2, which is located in the first block group 1511 and adjacent to the first memory block MEMORY BLOCK1, may rise due to interference. In this case, since the third and fourth memory blocks MEMORY BLOCK<3:4> are included in the second block group 1512, which is separate from the first block group 1511, the threshold voltage of the memory cells included therein may not rise.

[0073] As another example, when repeatedly accessing the fourth memory block MEMORY BLOCK4 of the second block group 1512 within multiple memory blocks MEMORY BLOCK<1:4>, the threshold voltage of the memory cells included in the third memory block MEMORY BLOCK3, which is located in the second block group 1512 and adjacent to the fourth memory block MEMORY BLOCK4, may rise due to interference. In this case, since the first and second memory blocks MEMORY BLOCK<1:2> are included in the first block group 1511, which is separate from the second block group 1512, the threshold voltage of the memory cells included therein may not rise.

[0074] As described above, when the threshold voltage of a memory cell included in a specific memory block rises due to interference, a read refresh operation can be performed on the specific memory block to lower the threshold voltage of the memory cell. That is, the read refresh operation is an operation that boosts the channel voltage by driving the word line of the specific memory block at a specific level while the source path of the specific memory block is on, and then lowers the channel potential by discharging the word line of the specific memory block while the source path is off.

[0075] A read refresh operation can be performed on at least one of a plurality of memory blocks <1:4>. Therefore, the controller 130 can control the memory device 150 such that a read refresh operation is performed by selecting a block among the plurality of memory blocks <1:4> included in the memory device 150 that meets the set conditions at a set time point.

[0076] Reference Figure 1 and Figure 2 Based on the number of accesses to all memory blocks <1:2> included in the first block group 1511 of the block groups 1511 and 1512 included in the memory device 150, the controller 130 can determine the set time point of the memory blocks <1:2> included in the first block group 1511 as a first time point. Furthermore, based on the number of accesses to all memory blocks <3:4> included in the second block group 1512 of the block groups 1511 and 1512 included in the memory device 150, the controller 130 can determine the set time point of the memory blocks <3:4> included in the second block group 1512 as a second time point.

[0077] In other words, the controller 130 can independently determine a "set time point" for the first block group 1511 and the second block group 1512. This "set time point" is the time point at which the operation of selecting at least one memory block as the target for a read refresh operation is to be performed. Specifically, based on the number of accesses to all first and second memory blocks (MEMORY BLOCK<1:2>) included in the first block group 1511, the controller 130 can determine the set time point of the memory blocks (MEMORY BLOCK<1:2>) included in the first block group 1511 as the first time point. Similarly, based on the number of accesses to all third and fourth memory blocks (MEMORY BLOCK<3:4>) included in the second block group 1512, the controller 130 can determine the set time point of the memory blocks (MEMORY BLOCK<3:4>) included in the second block group 1512 as the second time point.

[0078] For example, controller 130 can determine the point in time when the number of accesses to all first and second memory blocks <1:2> included in the first block group 1511 exceeds a first set of access counts, as the "set time point" for the first block group 1511. When a read refresh operation is performed in response to the number of accesses to all first and second memory blocks <1:2> included in the first block group 1511 exceeding the first set of access counts, controller 130 can initialize the value of the first set of access counts to perform subsequent read refresh operations for the first block group 1511. As another example, controller 130 can determine the point in time when the number of accesses to all third and fourth memory blocks <3:4> included in the second block group 1512 exceeds a second set of access counts, as the "set time point" for the second block group 1512. When a read refresh operation is performed in response to a situation where the number of accesses to all third and fourth memory blocks MEMORYBLOCK<3:4> included in the second block group 1512 exceeds the number of accesses in the second group, the controller 130 can initialize the value of the second group of access counts to enable subsequent read refresh operations for the second block group 1512. Here, the first group of access counts and the second group of access counts can be substantially the same, but they can also be different from each other.

[0079] Furthermore, the controller 130 can classify blocks containing stored data, including the first storage block and the second storage block MEMORY BLOCK<1:2> in the first block group 1511, as first storage blocks, and select at least one of the first storage blocks as a first target block that meets set conditions, wherein the at least one first storage block is selected based on the amount of time elapsed since the most recent access. Additionally, the controller 130 can classify blocks containing stored data, including the third storage block and the fourth storage block MEMORY BLOCK<3:4> in the second block group 1512, as second storage blocks, and select at least one of the second storage blocks as a second target block that meets set conditions, wherein the at least one second storage block is selected based on the amount of time elapsed since the most recent access.

[0080] In other words, the controller 130 can independently determine "setting conditions" for the first block group 1511 and the second block group 1512, which are conditions for selecting at least one storage block as the target for a read refresh operation.

[0081] For example, data can be stored in each of the first and second storage blocks MEMORYBLOCK<1:2> included in the first block group 1511, and both the first and second storage blocks MEMORYBLOCK<1:2> can be classified as first storage blocks. The second storage block MEMORYBLOCK2, being the earliest accessed storage block between the first and second storage blocks MEMORYBLOCK<1:2> classified as first storage blocks, can be selected as the first target block satisfying set conditions. As another example, data can be stored in each of the third and fourth storage blocks MEMORYBLOCK<3:4> included in the second block group 1512, and both the third and fourth storage blocks MEMORYBLOCK<3:4> can be classified as second storage blocks. The third storage block MEMORYBLOCK3, being the earliest accessed storage block between the third and fourth storage blocks MEMORYBLOCK<3:4> classified as second storage blocks, can be selected as the second target block satisfying set conditions.

[0082] Return to reference Figure 2 Voltage generator 155 can be connected to line decoder 152 and control logic 156. Voltage generator 155 can be configured to generate various voltages required for programming, reading, and erasing operations in response to voltage control signal VCON from control logic 156. The voltage generated by voltage generator 155 can be transmitted via line decoder 152 to multiple lines DSL, WL, and SSL connected to memory cell array 151.

[0083] Furthermore, control logic 156 can be connected to row decoder 152, page buffer 153, I / O buffer 154, and voltage generator 155. Control logic 156 can output a voltage control signal VCON to generate the voltage required for the operation of memory device 150 in response to the command CMD input through I / O buffer 154. Control logic 156 can also output a row address signal RADD and a column address signal CADD in response to the address signal ADD input through I / O buffer 154.

[0084] The row decoder 152 can be electrically connected to the memory cell array 151 via the word line WL and the select lines SSL and DSL. The page buffer 153 can be electrically connected to the memory cell array 151 via the bit line BL1 or BL2. For example, the first page buffer PAGE BUFFER1 included in the page buffer 153 can be electrically connected to the first block group 1511, i.e., the first memory block and the second memory block MEMORY BLOCK<1:2>, via the first bit line BL1. Furthermore, the second page buffer PAGE BUFFER2 included in the page buffer 153 can be electrically connected to the second block group 1512, i.e., the third memory block and the fourth memory block MEMORY BLOCK<3:4>, via the second bit line BL2.

[0085] The row decoder 152 can be configured to operate in response to control of control logic 156. The row decoder 152 can receive a row address signal RADD from control logic 156. The row decoder 152 can be configured to decode the received row address signal RADD. The row decoder 152 can select one of a plurality of memory blocks <1:4> included in the memory cell array 151 in response to the decoded row address signal RADD. The row decoder 152 can transmit various operating voltages VOP (e.g., voltages for programming, reading, and erasing operations) generated by voltage generator 155 to the word line WL and selection lines SSL and DSL of the selected memory block.

[0086] Under the control of control logic 156, the line decoder 152 and voltage generator 155 can perform the following operations as read refresh operations: a first operation driving multiple word lines WL included in the selected memory block at a first voltage level, a second operation discharging multiple word lines WL to a second voltage level, a third operation driving multiple word lines WL at a third voltage level lower than the first voltage level, and a fourth operation discharging multiple word lines WL to a fourth voltage level.

[0087] According to one embodiment, each of the second and fourth voltage levels may be a ground voltage (VSS) level. According to another embodiment, the second and third voltage levels may be substantially the same level, and the fourth voltage level may be a ground voltage (VSS) level.

[0088] According to the implementation, the first voltage level may be a level that is a predetermined amount higher than the highest level among a plurality of read voltage levels used for read refresh operations on a plurality of memory blocks <1:4>. Furthermore, the third voltage level may be one of a plurality of read voltage levels.

[0089] Under the control of control logic 156, the line decoder 152 and voltage generator 155 can substantially maintain each of the drain select line DSL and source select line SSL at an on-state voltage level during a segment of a first or third operation that drives multiple word lines WL included in the selected memory block at a first or third voltage level. According to an embodiment, the on-state voltage level can be equal to or higher than the power supply voltage level. That is, the on-state voltage level can be the power supply voltage level, but it can also be a pump voltage level higher than the power supply voltage level.

[0090] Under the control of control logic 156, in the segment where a fourth operation is performed to discharge the multiple word lines WL included in the selected memory block to a fourth voltage level while the multiple word lines WL have already been driven at a third voltage level, the line decoder 152 and voltage generator 155 can substantially maintain each of the drain select line DSL and the source select line SSL at a cutoff voltage level. According to an embodiment, the cutoff voltage level can be equal to or lower than the ground voltage level. That is, the cutoff voltage level can be the ground voltage level, but it can also be a negative voltage level lower than the ground voltage level.

[0091] Under the control of control logic 156, in the segment where a second operation is performed to discharge the multiple word lines WL included in the selected memory block to a second voltage level while the multiple word lines WL have been driven at a first voltage level, the line decoder 152 and the voltage generator 155 can substantially keep each of the drain select line DSL and the source select line SSL at one of the on-state and off-state voltage levels.

[0092] Page buffer 153 can operate as a write driver or a sense amplifier depending on the operating mode. During programming operations, page buffer 153 can transmit a voltage corresponding to the data to be programmed to bit line BL1 or BL2 of memory cell array 151. During read operations, page buffer 153 can sense data stored in the selected memory cell via bit line BL1 or BL2 and transmit the sensed data to I / O buffer 154. For example, the first page buffer PAGE BUFFER1 included in page buffer 153 can transmit a voltage corresponding to the data to be programmed to the first block group 1511, i.e., the first memory block and the second memory block MEMORY BLOCK<1:2>, via the first bit line BL1, or sense data stored in the first memory block and the second memory block MEMORY BLOCK<1:2> via the first bit line BL1 and transmit the sensed data to I / O buffer 154. Furthermore, the second page buffer PAGE BUFFER2 included in page buffer 153 can transmit a voltage corresponding to the data to be programmed to the second block group 1512, i.e., the third and fourth memory blocks MEMORY BLOCK<3:4>, via the second bit line BL2, or sense the data stored in the third and fourth memory blocks MEMORY BLOCK<3:4> via the second bit line BL2 and transmit the sensed data to I / O buffer 154. During an erase operation, page buffer 153 can float either bit line BL1 or BL2 of memory cell array 151. For example, when an erase operation is performed on any block included in the first block group 1511 (i.e., one of the first and second memory blocks MEMORY BLOCK<1:2>), the first page buffer PAGE BUFFER1 included in page buffer 153 can float the first bit line BL1. Furthermore, when an erase operation is performed on any block included in the second block group 1512 (i.e., one of the third memory block and the fourth memory block MEMORY BLOCK<3:4>), the second page buffer PAGE BUFFER2 included in the page buffer 153 can float the second bit line BL2.

[0093] I / O buffer 154 can transfer write data from external input to page buffer 153 during programming operations. I / O buffer 154 can output data provided from page buffer 153 to the outside during read operations. I / O buffer 154 can transmit address signal ADD or command CMD from external input to control logic 156.

[0094] For reference, the purpose of performing a read refresh operation may be to further reduce the threshold voltage level of the memory cells included in a specific memory block, which has risen due to interference. Therefore, even if a read refresh operation is performed on a specific memory block, the data may not be stored in the page buffer 153 corresponding to that specific memory block. Even if the data is stored in the page buffer 153, the data may not be output through the I / O buffer 154. Even if the data stored in the page buffer 153 is output through the I / O buffer 154, the data may be meaningless.

[0095] Figure 3 It is used to describe embodiments according to this disclosure. Figure 1 and Figure 2 A diagram showing an example of a storage block.

[0096] Reference Figure 3 , Figure 1 and Figure 2 Each of the plurality of memory blocks MEMORY BLOCK<1:4> (MEMORYBLOCKi) shown may include a plurality of cell strings CS11 to CS1m and CS21 to CS2M. Each of the plurality of cell strings CS11 to CS1m and CS21 to CS2m may extend along the +Z direction. Each of the plurality of cell strings CS11 to CS1m and CS21 to CS2M may include at least one source selection transistor SST, at least one source-side dummy memory cell SDC, a first normal memory cell MC1 to the Nth normal memory cell MCN, at least one drain-side dummy memory cell DDC, and at least one drain selection transistor DST, stacked on a substrate (not shown) beneath the memory block BLKi.

[0097] The source select transistor SST of each cell string can be connected between the common source line CSL and the source-side dummy memory cell SDC. The source select transistors of cell strings arranged in substantially the same row (e.g., CS11 to CS1m) can be connected to substantially the same source select line (e.g., SSL1). The source select transistors of cell strings CS11 to CS1m arranged in the first row can be connected to the first source select line SSL1. The source select transistors of cell strings CS21 to CS2M arranged in the second row can be connected to the second source select line SSL2.

[0098] The source-side dummy memory cell SDC of each cell string can be connected in series between the source select transistor SST and the normal memory cells MC1 to MCN. Source-side dummy memory cells with substantially the same height can be connected to substantially the same source-side dummy word line. The gate of the source-side dummy memory cell SDC can be connected to the source-side dummy word line SPWL.

[0099] The first normal memory cell MC1 to the Nth normal memory cell MCN in each cell string can be connected in series between the source-side dummy memory cell SDC and the drain-side dummy memory cell DDC. The gates of the first normal memory cell MC1 to the Nth normal memory cell MCN can be connected to the first normal word line WL1 to the Nth normal word line WLN, respectively.

[0100] The drain-side dummy memory cell (DDC) of each cell string can be connected in series between the drain select transistor (DST) and the normal memory cells MC1 to MCN. Drain-side dummy memory cells with substantially the same height can be connected to substantially the same source-side dummy word line. The drain-side dummy memory cell (DDC) can be connected to the drain-side dummy word line (DPWL).

[0101] The drain select transistor (DST) of each cell string can be connected between the corresponding bit line and the drain-side dummy memory cell (DDC). The drain select transistors of cell strings arranged in the row direction can be connected to drain select lines extending in the row direction. The drain select transistors of cell strings CS11 to CS1m in the first row can be connected to the first drain select line DSL1. The drain select transistors of cell strings CS21 to CS2M in the second row can be connected to the second drain select line DSL2.

[0102] Each of the first normal memory cells MC1 to the Nth normal memory cell MCN can store 1 bit of data or 2 or more bits of data. Typically, a memory cell storing 1 bit of data is called a single-level cell (SLC), a memory cell storing 2 bits of data is called a multi-level cell (MLC), a memory cell storing 3 bits of data is called a three-level cell (TLC), a memory cell storing 4 bits of data is called a four-level cell (QLC), and a memory cell storing 5 or more bits of data is called a multilevel cell. A single-level cell can have erase and program states depending on a threshold voltage, and each of the multi-level, three-level, four-level, and multilevel cells can have an erase state and multiple program states depending on a threshold voltage.

[0103] In embodiments of this disclosure, each of the first normal memory cell MC1 to the Nth normal memory cell MCN is a three-level cell (TLC) storing 3 bits of data. Therefore, as... Figure 8 As shown, each of the first normal memory cell MC1 to the Nth normal memory cell MCN can have an erase state ERASE and seven programming states PG1 to PG7.

[0104] Here, the threshold voltage level of the memory cell in the ERASE state can be lower than the first voltage PV1 level; the threshold voltage level of the memory cell in the first programming state PG1 can be higher than the first voltage (PV1) level and lower than the second voltage (PV2) level; the threshold voltage level of the memory cell in the second programming state PG2 can be higher than the second voltage (PV2) level and lower than the third voltage (PV3) level; the threshold voltage level of the memory cell in the third programming state PG3 can be higher than the third voltage (PV3) level and lower than the fourth voltage (PV4) level; the threshold voltage level of the memory cell in the fourth programming state PG4 can be higher than the fourth voltage (PV4) level and lower than the fifth voltage (PV5) level; the threshold voltage level of the memory cell in the fifth programming state PG5 can be higher than the fifth voltage (PV5) level and lower than the sixth voltage (PV6) level; the threshold voltage level of the memory cell in the sixth programming state PG6 can be higher than the sixth voltage (PV6) level and lower than the seventh voltage (PV7) level; and the threshold voltage level of the memory cell in the seventh programming state PG7 can be higher than the seventh voltage (PV7) level. Here, the erase state ERASE and the first programming states PG1 to the seventh programming states PG7 indicate the states in which data with different values ​​are stored in the memory cell.

[0105] Here, the first voltage PV1 to the seventh voltage PV7 can be reference voltages used to distinguish whether a memory cell is in the erase state ERASE, the first programming state PG1, the second programming state PG2, the third programming state PG3, the fourth programming state PG4, the fifth programming state PG5, the sixth programming state PG6, or the seventh programming state PG7. Therefore, when verifying whether a memory cell has been correctly programmed, or when reading data stored in a memory cell, a sensing operation using the first voltage PV1 to the seventh voltage PV7 can be performed.

[0106] Figure 4 This is a diagram illustrating an example of a read-refresh operation performed by a memory device according to an embodiment of the present disclosure.

[0107] Reference Figures 1 to 4 According to the embodiments of this disclosure, the read refresh operation can be broadly classified into a first section operation first SECTION and a second section operation second SECTION. That is, when a read refresh operation on a selected memory block is started in response to a read refresh command READREFRESH CMD, after performing the first section operation first SECTION on the selected memory block, the second section operation second SECTION can be performed on it.

[0108] The first section of the first operation may include a first operation, a first DRV, and a second operation, a first DSC. The second section of the second operation may include a third operation, a second DRV, and a fourth operation, a second DSC.

[0109] The first operation, first DRV, may include driving all word lines ALL WL in the memory block selected as the target for a read refresh operation at a first voltage level V1. Furthermore, the first operation, first DRV, may include maintaining all select lines (i.e., drain select line DSL and source select line SSL) in the memory block selected as the target for a read refresh operation substantially at the on-state voltage level TON.

[0110] The second operation, first DSC, can be an operation that discharges all word lines ALL and WL, which have been driven at a first voltage level V1 by the first operation, first DRV, to a second voltage level. Furthermore, the second operation, first DSC, can include an operation that substantially maintains all select lines (i.e., drain select line DSL and source select line SSL) included in the memory block selected as the target for a read refresh operation at one of the on-state voltage level TON and the off-state voltage level TOFF.

[0111] Here, when the second voltage level is set to a relatively low level (solid line) in the first DSC of the second operation, the drain select line DSL and the source select line SSL can be substantially maintained at the cutoff voltage level TOFF (solid line) during the segment of the first DSC of the second operation. Furthermore, when the second voltage level is set to a relatively high level (dashed line) in the first DSC of the second operation, the drain select line DSL and the source select line SSL can be substantially maintained at the on-voltage level TON (dashed line) during the segment of the first DSC of the second operation.

[0112] The third operation, second DRV, can be executed following the second operation, first DSC, and can be an operation that drives all word lines (ALL WL) in the memory block selected as the target for the read refresh operation at a third voltage level V2. Furthermore, the third operation, second DRV, can include an operation in which all select lines (i.e., drain select line DSL and source select line SSL) in the memory block selected as the target for the read refresh operation are substantially maintained at the on-state voltage level TON.

[0113] The fourth operation, second DSC, can be an operation that discharges all word lines ALL WL, which have been driven to the third voltage level V2 by the third operation, second DRV, to the fourth voltage level. Furthermore, the fourth operation, second DSC, can include an operation that substantially maintains all select lines (i.e., drain select line DSL and source select line SSL) included in the memory block selected as the target for the read refresh operation at the cutoff voltage level TOFF.

[0114] According to an implementation, the first voltage level V1 may be a level that is higher than the highest of a plurality of read voltage levels used for a read-refresh operation on a memory block selected as the target for a read-refresh operation by a set level. For example, see also... Figure 8 The first voltage level V1 can be a level higher than the highest level (i.e., the seventh voltage (PV7) level among the first to seventh voltages (PV1 to PV7) levels used for read refresh operations of a three-level cell (TLC) with an erase state ERASE and seven programming states PG1 to PG7). Specifically, the first voltage level V1 can be a voltage level sufficient to turn on all memory cells in the seventh programming state PG7.

[0115] According to the implementation, the third voltage level V2 can be one of a plurality of read voltage levels used for a read refresh operation on the selected target memory block. For example, see also... Figure 4 and Figure 8 The third voltage level V2 can be one of the first voltage level PV1 to the seventh voltage level PV7 used for read refresh operations on a three-level cell (TLC) having an erase state ERASE and seven programming states PG1 to PG7. Specifically, the third voltage level V2 can be the fifth voltage (PV5) level used to distinguish between the fourth programming state PG4 and the fifth programming state PG5. That is, the third voltage level V2 can be a level that enables the conduction of memory cells corresponding to almost half of the seven programming states PG1 to PG7 and disables the conduction of memory cells corresponding to the other half.

[0116] According to the implementation, the second voltage level and the fourth voltage level can be the ground voltage (VSS) level indicated by the solid line in the figure.

[0117] According to the implementation method, as indicated by the dashed line in the figure, the second voltage level can be a voltage level that is substantially the same as the third voltage level V2.

[0118] According to the implementation method, the turn-on voltage level can be equal to or higher than the power supply voltage level. That is, the turn-on voltage level can be the power supply voltage level, but it can also be a pumping voltage level higher than the power supply voltage level.

[0119] According to the implementation method, the cutoff voltage level can be equal to or lower than the ground voltage level. That is, the cutoff voltage level can be the ground voltage level, but it can also be a negative voltage level lower than the ground voltage level.

[0120] Figure 5 This is for describing in detail the embodiments according to this disclosure. Figure 4 The diagram shows the first segment operation of the read-refresh operation.

[0121] Reference Figures 1 to 5 In the first section of the read refresh operation according to the embodiments of the present disclosure, the phenomena occurring in the storage block selected as the target for the read refresh operation can be understood in detail.

[0122] First, the seventh voltage (PV7), the highest of the first to seventh voltage (PV1 to PV7) levels used to determine the data of the multiple memory cells MC1 to MCN included in the memory block selected as the target for reading the refresh operation, is higher than 2V and lower than 5V. Furthermore, the threshold voltage level DSL Vt of the drain select transistor DST and the threshold voltage level SSL Vt of the source select transistor SST are equal to or less than 2V, and the drain select transistor DST and the source select transistor SST are included in the memory block selected as the target for reading the refresh operation. Additionally, the first voltage level V1 is 7V, which is higher than the seventh voltage PV7. Furthermore, the second voltage level is the ground voltage (VSS, 0V) level. Furthermore, the data in the seventh programming state PG7 is stored in both the memory cell MCN closest to the drain select transistor DST and the memory cell MC1 closest to the source select transistor SST among the multiple memory cells MC1 to MCN included in the memory block selected as the target for reading the refresh operation, and the on / off state is selected based on the seventh voltage PV7. In addition, the dummy memory cells DDC and SDC, which exist between multiple memory cells MC1 to MCN and the drain select transistor DST / source select transistor SST, are all in an erased state E.

[0123] In the first operation, first DRV of the first SECTION of the first segment operation, each of the drain select line DSL and source select line SSL included in the memory block selected as the target for the read refresh operation is at the on-state voltage level TON, and the on-state voltage level TON can be a level higher than 2V. Therefore, the drain select transistor DST and the source select transistor SST can be in the on state.

[0124] In the first operation, first DRV, the level of all word lines ALL WL in the memory block selected as the target for the read refresh operation can rise from the ground voltage (VSS) level to 7V, which is the first voltage level V1. At this time, since the level of all word lines ALL WL is higher than the seventh voltage PV7, all memory cells MC1 to MCN included in all word lines ALL WL can be turned on. In this way, the level of all word lines ALL WL rises, but the drain select transistor DST and the source select transistor SST are turned on. Therefore, the channel can be essentially kept at the ground voltage (VSS) level of 0V.

[0125] In state "A" of the first DSC of the second operation in the first SECTION of the first segment operation, each of the drain select line DSL and the source select line SSL included in the memory block selected as the target for the read refresh operation is at the cutoff voltage level TOFF, and the cutoff voltage level TOFF can be the ground voltage (VSS) level of 0V. Therefore, in state "A" of the first DSC of the second operation, the drain select transistor DST and the source select transistor SST can be in the cutoff state.

[0126] The state "A" of the second operation, first DSC, indicates the time point immediately following the start of the second operation, first DSC, after the first operation, first DRV. Therefore, in state "A" of the second operation, first DSC, the level of all word lines ALL WL in the memory block selected as the target for the refresh operation can rise to 7V (the first voltage level V1) through the first operation, first DRV, and then drop to 5V as the second operation, first DSC, begins. At this time, since the level of all word lines ALL WL is higher than the seventh voltage PV7, all memory cells MC1 to MCN included in all word lines ALL WL can be in the ON state. In this way, since both the drain select transistor DST and the source select transistor SST are in the OFF state during the section where the level of all word lines ALL WL drops from 7V to 5V, the channel voltage level can drop to -2V, which is lower than the ground voltage (VSS) level of 0V.

[0127] In state "B" of the second operation, which follows state "A" of the first DSC in the first SECTION of the first operation, each of the drain select line DSL and source select line SSL included in the memory block selected as the target for the read refresh operation is at the cutoff voltage level TOFF, and the cutoff voltage level TOFF can be the ground voltage (VSS) level of 0V. However, since the channel voltage level has dropped to -2V in state "A" of the second operation, the drain select transistor DST and the source select transistor SST can be switched to the on state.

[0128] The voltage levels of all word lines ALL WL, which had already dropped to 5V in state "A" of the second operation of the first DSC, can further drop to 2V in state "B" of the second operation of the first DSC. In this way, during the transition from state "A" to state "B" of the second operation of the first DSC, some of the memory cells MC1 to MCN in all word lines ALL WL can switch from the on state to the off state, but most memory cells can remain essentially on. Although the voltage levels of all word lines ALL WL drop from 5V to 2V, both the drain select transistor DST and the source select transistor SST remain on. Therefore, until state "B" of the second operation of the first DSC, the channel can continuously maintain its voltage level, which had dropped to -2V in state "A" of the second operation of the first DSC.

[0129] In state "C" of the second operation, which follows state "B" of the first DSC in the first SECTION of the first operation, each of the drain select line DSL and source select line SSL in the memory block selected as the target for the read refresh operation is at the cutoff voltage level TOFF, and the cutoff voltage level TOFF can be the ground voltage (VSS) level of 0V. Furthermore, since the channel voltage level has already dropped to -2V in state "A" of the second operation, both the drain select transistor DST and the source select transistor SST can remain continuously on, as in state "B" of the second operation.

[0130] In the second operation, the level of all word lines ALL WL, which has dropped to 2V in state "B" of the first DSC, can be further dropped to the ground voltage (VSS) level of 0V in state "C" of the first DSC. In this way, during the transition from state "B" to state "C" in the second operation, most of the memory cells MC1 to MCN in all word lines ALL WL can be in the off state. Specifically, both the memory cell MCN, which is closest to the drain select transistor DST, and the memory cell MC1, which is closest to the source select transistor SST, which is turned on or off based on a seventh voltage PV7 having a value greater than 2V, can be in the off state. In this way, since the memory cell MCN closest to the drain select transistor DST and the memory cell MC1 closest to the source select transistor SST are reliably in the off state during the section where the level of all word lines ALL WL drops from 2V to the ground voltage (VSS) level of 0V, the channel voltage level between the memory cell MCN closest to the drain select transistor DST and the memory cell MC1 closest to the source select transistor SST can drop to -4V, which is below -2V.

[0131] As described above, the threshold voltages of memory cells MC1 to MCN can appropriately decrease to a point that aligns with the purpose of the read / refresh operation, caused by the channel voltage level dropping to -2V during the second operation of the first DSC in the first SECTION of the first segment operation. However, an excessive decrease in the threshold voltages of memory cells MC1 to MCN due to the channel voltage level dropping to -4V during the second operation of the first DSC in the first SECTION of the first segment operation may not align with the purpose of the read / refresh operation.

[0132] Therefore, according to the embodiments of this disclosure, by performing the second segment operation second SECTION, the threshold voltages of memory cells MC1 to MCN that have excessively decreased due to the state "C" of the second operation first DSC of the first segment operation first SECTION can be compensated to a certain extent.

[0133] Figure 6 and Figure 7 This is for describing in detail the embodiments according to this disclosure. Figure 4 The diagram shows the second segment operation of the read refresh operation.

[0134] first, Figure 6 and Figure 7 An example is illustrated of a phenomenon occurring in a storage block selected as the target of a read refresh operation in the second section of a second segment operation according to an embodiment of the present disclosure. Figure 6The example illustrates that the data in the fifth programming state PG5 is stored in the memory cell MCN, which is closest to the drain selection transistor DST, and the memory cell MC1, which is closest to the source selection transistor SST, among the multiple memory cells MC1 to MCN included in the memory block selected as the target for the read refresh operation, and the on / off state is selected based on the fifth voltage PV5. Figure 7 This illustrates the case where data in the seventh programming state PG7 is stored in one of the memory cells MC1 to MCN, which are among the multiple memory cells selected as the target for the read refresh operation. The memory cell MCN is closest to the drain selection transistor DST, and the memory cell MC1 is closest to the source selection transistor SST. The on / off state is selected based on the seventh voltage PV7.

[0135] Specifically, refer to Figures 1 to 6 The fifth voltage PV5, which is close to the middle of the first to seventh voltages (PV1 to PV7) levels among the multiple memory cells MC1 to MCN included in the memory block selected as the target for reading the refresh operation, is less than or equal to 2.3V. Furthermore, the threshold voltage level DSL Vt of the drain select transistor DST and the threshold voltage level SSL Vt of the source select transistor SST are equal to or less than 2V, and the drain select transistor SST and the source select transistor SST are included in the memory block selected as the target for reading the refresh operation. Additionally, the third voltage level V2 is 2.3V. Furthermore, the dummy memory cells DDC and SDC existing between the multiple memory cells MC1 to MCN and the drain select transistor DST / source select transistor SST are both in an erase state E.

[0136] In the third operation, second DRV, of the second section of the second operation, each of the drain select line DSL and the source select line SSL included in the memory block selected as the target for the read refresh operation is at the on-state voltage level TON, and the on-state voltage level TON can be a level higher than 2V. Therefore, the drain select transistor DST and the source select transistor SST can be in the on state.

[0137] In the third operation, second DRV, the level of all word lines ALL WL included in the memory block selected as the target for the read refresh operation can rise from the ground voltage (VSS) level to 2.3V as the third voltage level V2. In this way, in the third operation, second DRV, almost half of the memory cells MC1 to MCN included in all word lines ALL WL can be in the ON state. Specifically, both the memory cell MCN closest to the drain select transistor DST and the memory cell MC1 closest to the source select transistor SST, which are turned on or off based on a fifth voltage PV5 having a value less than or equal to 2.3V, can be in the ON state. The level of all word lines ALL WL rises, but the drain select transistor DST and the source select transistor SST remain in the ON state. Therefore, the channel can essentially maintain a ground voltage (VSS) level of 0V.

[0138] In the fourth operation, second DSC of the second section of the second operation, each of the drain select line DSL and the source select line SSL included in the memory block selected as the target for the read refresh operation is at the cutoff voltage level TOFF, and the cutoff voltage level TOFF can be the ground voltage (VSS) level of 0V. Therefore, in the fourth operation, second DSC, the drain select transistor DST and the source select transistor SST can be in the off state.

[0139] The level of all word lines ALL WL, which has risen to 2.3V as the third voltage level V2 in the third operation second DRV, can drop to the ground voltage (VSS) level of 0V in the fourth operation second DSC.

[0140] In this manner, during the execution of the fourth operation, the second DSC, following the third operation, most of the memory cells MC1 to MCN in all word lines ALL WL can be in a cutoff state. Specifically, the memory cell MCN closest to the drain select transistor DST and the memory cell MC1 closest to the source select transistor SST, which are turned on or off based on a fifth voltage PV5 having a value of less than or equal to 2.3V, can both be in a cutoff state at the initial stage of the fourth operation, the second DSC.

[0141] In this way, since both the drain select transistor (DST) and the source select transistor (SST) are in the off state in the fourth operation second DSC when the levels of all word lines ALL WL drop from 2.3V to the ground voltage (VSS) level of 0V, the channel voltage level should drop to -2V, which is lower than the ground voltage (VSS) level of 0V. However, since the memory cell MCN, which is closest to the drain select transistor DST, and the memory cell MC1, which is closest to the source select transistor SST, are already turned off in the initial stage of the fourth operation second DSC, the channel voltage level between the memory cell MCN, which is closest to the drain select transistor DST, and the memory cell MC1, which is closest to the source select transistor SST, can drop to -2.3V, which is lower than -2V.

[0142] exist Figure 6 In the second DSC operation of the second section of the second SECTION shown, the channel voltage level drops to -2.3V, but the width of this voltage drop is less than that in the second DSC operation of the second SECTION. Figure 5 The second operation is shown in the case where the channel voltage level in state "C" of the first DSC drops to -4V. Therefore, when in Figure 5 The second operation shown is executed after the first DSC is in state "C". Figure 6 When operating the second section as shown, the threshold voltages of memory cells MC1 to MCN can be appropriately reduced. That is, Figure 5 The state where the threshold voltage of memory cells MC1 to MCN in the first SECTION of the first segment operation shown can be changed to: Figure 6 The state shown is where the threshold voltages of memory cells MC1 to MCN in the second SECTION of the second segment operation are appropriately reduced.

[0143] Reference Figures 1 to 7 The highest of the first to seventh voltage (PV1 to PV7) levels among the multiple memory cells MC1 to MCN included in the memory block selected as the target for the refresh operation, is a seventh voltage PV7, which is higher than 2.3V. Furthermore, the threshold voltage level DSL Vt of the drain select transistor DST and the threshold voltage level SSL Vt of the source select transistor SST are equal to or less than 2V, and the drain select transistor SST and the source select transistor SST are included in the memory block selected as the target for the refresh operation. Additionally, the third voltage level V2 is 2.3V. Furthermore, the dummy memory cells DDC and SDC existing between the multiple memory cells MC1 to MCN and the drain select transistor DST / source select transistor SST are both in an erase state E.

[0144] In the third operation, second DRV, of the second section of the second operation, each of the drain select line DSL and the source select line SSL included in the memory block selected as the target for the read refresh operation is at the on-state voltage level TON, and the on-state voltage level TON can be a level higher than 2V. Therefore, the drain select transistor DST and the source select transistor SST can be in the on state.

[0145] In the third operation, second DRV, the level of all word lines ALL WL included in the memory block selected as the target for the read refresh operation can rise from the ground voltage (VSS) level to 2.3V as the third voltage level V2. In this way, in the third operation, second DRV, almost half of the memory cells MC1 to MCN included in all word lines ALL WL can be in the on state. Specifically, the memory cell MCN closest to the drain select transistor DST and the memory cell MC1 closest to the source select transistor SST, which are turned on or off based on a seventh voltage PV7 having a value greater than 2.3V, can both be in the off state. Since the drain select transistor DST and the source select transistor SST are in the on state, the channel should essentially maintain a ground voltage (VSS) level of 0V. However, since both the memory cell MCN, which is closest to the drain select transistor DST, and the memory cell MC1, which is closest to the source select transistor SST, are in the off state, the voltage level of the channel between the memory cell MCN, which is closest to the drain select transistor DST, and the memory cell MC1, which is closest to the source select transistor SST, can rise to 2.3V in response to the rise of all word lines ALL WL from the ground voltage (VSS) level of 0V to 2.3V, which is the third voltage level V2.

[0146] In the fourth operation, second DSC of the second section of the second operation, each of the drain select line DSL and the source select line SSL included in the memory block selected as the target for the read refresh operation is at the cutoff voltage level TOFF, and the cutoff voltage level TOFF can be the ground voltage (VSS) level of 0V. Therefore, in the fourth operation, second DSC, the drain select transistor DST and the source select transistor SST can be in the off state.

[0147] The level of all word lines ALL WL, which has risen to 2.3V as the third voltage level V2 in the third operation second DRV, can drop to the ground voltage (VSS) level of 0V in the fourth operation second DSC.

[0148] In this way, during the execution of the fourth operation, the second DSC, following the third operation, most of the memory cells MC1 to MCN in all word lines ALL WL can be in the off state. Specifically, the memory cell MCN closest to the drain selection transistor DST and the memory cell MC1 closest to the source selection transistor SST, which are turned on or off based on a seventh voltage PV7 having a value greater than 2.3V, can both remain in the off state even during the fourth operation, the second DSC, following the third operation, the second DRV.

[0149] In this manner, since both the drain select transistor (DST) and the source select transistor (SST) are in the off state in the fourth operation, second DSC, where the levels of all word lines ALL WL drop from 2.3V to the ground voltage (VSS) level of 0V, the channel voltage level should drop to -2V, which is lower than the ground voltage (VSS) level of 0V. However, the channel voltage level between the memory cell MCN, which is closest to the drain select transistor DST, and the memory cell MC1, which is closest to the source select transistor SST, has already risen to 2.3V in the third operation, second DRV. Therefore, the channel between the memory cell MCN, which is closest to the drain select transistor DST, and the memory cell MC1, which is closest to the source select transistor SST, can have a ground voltage (VSS) level of 0V.

[0150] exist Figure 7 In the second section of operation, second SECTION, second DSC, the channel is essentially maintained at ground voltage (VSS) level 0V. Therefore, when in Figure 5 The second operation shown is executed after the first DSC is in state "C". Figure 6 When operating the second section as shown, the threshold voltages of memory cells MC1 to MCN can be appropriately reduced. That is, Figure 5 The state where the threshold voltage of memory cells MC1 to MCN in the first SECTION of the first segment operation shown can be changed to: Figure 6 The state shown is where the threshold voltages of memory cells MC1 to MCN in the second SECTION of the second segment operation are appropriately reduced.

[0151] The present disclosure described above is not limited to the above embodiments and drawings, and it will be apparent to those skilled in the art to which this disclosure pertains that various substitutions, modifications and alterations can be made without departing from the technical spirit of this disclosure and the appended claims.

[0152] For example, the location and type of the logic gates and transistors shown in the above embodiments should be implemented differently depending on the polarity of the input signal. Furthermore, these embodiments can be combined to form additional embodiments.

[0153] Cross-references to related applications

[0154] This application claims priority to Korean Patent Application No. 10-2021-0045115, filed on April 7, 2021, the entire contents of which are incorporated herein by reference.

Claims

1. A memory system, the memory system comprising: A non-volatile memory device, the non-volatile memory device comprising a plurality of memory blocks, each memory block comprising a plurality of memory cells connected to a plurality of word lines; as well as A controller that controls the non-volatile memory device to perform read-refresh operations on the plurality of memory blocks. The read refresh operation includes: A first operation of providing a first voltage level to each of the plurality of word lines; The second operation is to discharge each of the plurality of word lines to the second voltage level; A third operation is performed to provide each of the plurality of word lines with a third voltage level lower than the first voltage level; and The fourth operation involves discharging each of the multiple word lines to the fourth voltage level. Wherein, the first voltage level is a level that is higher than the highest level among a plurality of read voltage levels used to distinguish data stored in the plurality of memory cells by a set level, and The third voltage level is any one of the plurality of read voltage levels.

2. The memory system according to claim 1, wherein, Each of the second voltage level and the fourth voltage level is a ground voltage level.

3. The memory system according to claim 1, wherein, The second voltage level is the same as the third voltage level, and the fourth voltage level is a ground voltage level.

4. The memory system according to claim 1, in, Each of the plurality of memory blocks further includes a first select line and a second select line, and the plurality of word lines are arranged between the first select line and the second select line, and The read-refresh operation further includes: During the first operation or the third operation, the first selection line and the second selection line are maintained at the on-voltage level; During the second operation, the first selection line and the second selection line are maintained at one of the on-voltage level and the off-voltage level; and During the fourth operation, the first selection line and the second selection line are maintained at the cutoff voltage level.

5. The memory system according to claim 1, wherein, The controller also determines when to initiate the read refresh operation based on the number of accesses to the plurality of storage blocks.

6. The memory system according to claim 5, wherein, The controller also selects one of the storage blocks as the target storage block for the read refresh operation based on the timing of the most recent access to the storage block.

7. The memory system according to claim 1, in, The plurality of memory blocks are divided into a first block group and a second block group, wherein the memory blocks within each of the first block group and the second block group share a bit line, and The controller also includes: The timing of the read-refresh operation on the storage blocks within the first block group is determined based on the number of accesses to the first block group, and The timing of the read refresh operation on the storage blocks within the second block group is determined based on the number of accesses to the second block group.

8. The memory system according to claim 7, in, The controller further selects a storage block within the first block group as the target storage block for the read-refresh operation based on the timing of the most recent access to the storage block within the first block group. The controller further selects a storage block within the second block group as the target storage block for the read refresh operation based on the timing of the most recent access to the storage block within the second block group.

9. A non-volatile memory device, the non-volatile memory device comprising: Multiple memory blocks, each memory block comprising multiple memory cells connected to multiple word lines; as well as The control circuit performs a read-refresh operation on the selected memory block among the plurality of memory blocks. The read refresh operation includes: A first operation of providing a first voltage level to each of the plurality of word lines; The second operation is to discharge each of the plurality of word lines to the second voltage level; A third operation is performed to provide each of the plurality of word lines with a third voltage level lower than the first voltage level; and The fourth operation involves discharging each of the multiple word lines to the fourth voltage level. Wherein, the first voltage level is a level that is higher than the highest level among a plurality of read voltage levels used to distinguish data stored in the plurality of memory cells by a set level, and The third voltage level is any one of the plurality of read voltage levels.

10. The non-volatile memory device according to claim 9, wherein, Each of the second voltage level and the fourth voltage level is a ground voltage level.

11. The non-volatile memory device according to claim 9, wherein, The second voltage level is the same as the third voltage level, and the fourth voltage level is a ground voltage level.

12. The non-volatile memory device according to claim 9, in, Each of the plurality of memory blocks further includes a first select line and a second select line, and the plurality of word lines are arranged between the first select line and the second select line, and The read-refresh operation further includes: During the first operation or the third operation, the first selection line and the second selection line are maintained at the on-voltage level; During the second operation, the first selection line and the second selection line are maintained at one of the on-voltage level and the off-voltage level; and During the fourth operation, the first selection line and the second selection line are maintained at the cutoff voltage level.

13. A method of operating a non-volatile memory device, the non-volatile memory device comprising a plurality of memory blocks, each memory block comprising a plurality of memory cells connected to a plurality of word lines, the method comprising the following steps: Select at least one of the plurality of storage blocks as the selected storage block; as well as Perform a read-refresh operation on the selected storage block. The read refresh operation includes: A first operation of providing a first voltage level to each of the plurality of word lines; A second operation following the first operation is to discharge each of the plurality of word lines to a second voltage level; Following the second operation, a third operation is performed to each of the plurality of word lines, providing a third voltage level lower than the first voltage level; and A fourth operation following the third operation involves discharging each of the plurality of word lines to a fourth voltage level. Wherein, the first voltage level is a level that is higher than the highest level among a plurality of read voltage levels used to distinguish data stored in the plurality of memory cells by a set level, and The third voltage level is any one of the plurality of read voltage levels.

14. The operating method according to claim 13, wherein, Each of the second voltage level and the fourth voltage level is a ground voltage level.

15. The operating method according to claim 13, wherein, The second voltage level is the same as the third voltage level, and the fourth voltage level is a ground voltage level.

16. The operating method according to claim 13, in, Each of the plurality of memory blocks further includes a first select line and a second select line, and the plurality of word lines are arranged between the first select line and the second select line, and The read-refresh operation further includes: During the first operation or the third operation, the first selection line and the second selection line are maintained at the on-voltage level; During the second operation, the first selection line and the second selection line are maintained at one of the on-voltage level and the off-voltage level; and During the fourth operation, the first selection line and the second selection line are maintained at the cutoff voltage level.

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