Page buffer, semiconductor memory having the same, and operating method thereof

Abstract

The present application relates to a page buffer, a semiconductor memory having the same and an operating method thereof. A page buffer includes a bit line controller connected between a bit line and a sensing node, wherein the bit line controller is capable of adjusting a potential level of the sensing node based on a current amount of a cell of the bit line by performing an evaluation operation. The page buffer further includes a first latch unit connected to the sensing node, wherein the first latch unit is capable of adjusting an operation period of the evaluation operation. The page buffer further includes a second latch unit for latching verification data based on the potential level of the sensing node.

Description

Technical Field

[0001] This disclosure generally relates to electronic devices, and more specifically, to page buffers, semiconductor memories having the page buffers, and methods of operating the semiconductor memories. Background Technology

[0002] Semiconductor memory devices are memory devices implemented using semiconductors such as silicon (Si), germanium (Ge), gallium arsenide (GaAs), or indium phosphide (InP). Semiconductor memory devices can generally be classified into volatile memory devices or non-volatile memory devices.

[0003] Volatile memory devices are memory devices that lose stored data when power is interrupted. Examples of volatile memory devices include Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), and Synchronous DRAM (SDRAM). Non-volatile memory devices are memory devices that retain stored data even when power is interrupted. Examples of non-volatile memory devices include Read-Only Memory (ROM), Programmable ROM (PROM), Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), Flash Memory, Phase-Change RAM (PRAM), Magnetic RAM (MRAM), Resistive RAM (RRAM), and Ferroelectric RAM (FRAM). Flash memory is generally classified as either NOR flash memory or NAND flash memory. Summary of the Invention

[0004] Some implementations relate to page buffers capable of improving the threshold voltage distribution and programming time of memory cells, semiconductor memories having such page buffers, and methods of operating such semiconductor memories.

[0005] According to an embodiment of the present disclosure, a page buffer includes: a bit line controller connected between a bit line and a sensing node, the bit line controller being able to adjust the potential level of the sensing node based on the cell current of the bit line by performing an evaluation operation; a first latch unit connected to the sensing node, the first latch unit being able to adjust the operation period of the evaluation operation; and a second latch unit configured to latch verification data based on the potential level of the sensing node.

[0006] According to another embodiment of this disclosure, a page buffer includes: a bit line controller connected between a bit line and a sensing node, the bit line controller being capable of adjusting the potential level of the sensing node based on the cell current of the bit line by performing an evaluation operation; a first latch unit connected to the sensing node, the first latch unit being capable of latching specific data for adjusting the operation period of the evaluation operation; and a second latch unit configured to latch verification data based on the potential level of the sensing node. The bit line controller is capable of adjusting the operation period of the evaluation operation based on the specific data latched by the first latch unit.

[0007] According to another embodiment of this disclosure, a semiconductor memory includes: a memory block comprising a plurality of pages; and read / write circuitry including a plurality of page buffers connected to bit lines of the memory block. The plurality of page buffers are capable of storing previously programmed data or specific data of pages programmed in a subsequent previous programming operation, and adjusting the evaluation period in a programming verification operation of the currently selected page based on the previously programmed data or specific data.

[0008] A method for operating a semiconductor memory according to the present disclosure includes: storing previously programmed data or specific data stored in a previous page in a first latch cell of a page buffer, the previous page being adjacent to a selected page among a plurality of pages and having been programmed in a subsequent previous programming operation; storing data to be programmed into the selected page in a second latch cell of the page buffer; adjusting the potential of a bit line connected to the selected page based on the data stored in the second latch cell, and then performing a programming voltage application operation; and performing an evaluation operation to adjust the potential level of a sensing node of the page buffer based on the current of the bit line, and then performing a programming verification operation to latch verification data corresponding to the potential level of the sensing node, wherein the evaluation operation is performed during an evaluation period set to a first evaluation period or a second evaluation period shorter than the first evaluation period, based on the previously programmed data or specific data stored in the first latch cell.

[0009] Another method for operating a semiconductor memory according to this disclosure includes: performing a fuzzy programming operation on a first page, wherein an evaluation operation is performed during a programming verification operation of the fuzzy programming operation to adjust the potential level of a sensing node of a page buffer based on the current of a bit line during the first evaluation period; performing a fuzzy programming operation on a second page adjacent to the first page; and performing a fine programming operation on the first page, wherein an evaluation operation is performed during a programming verification operation of the fine programming operation during a second evaluation period longer than the first evaluation period.

[0010] Another method for operating a semiconductor memory according to this disclosure includes: storing programming data to be programmed in a selected page in a page buffer; adjusting the potential of a bit line based on the programming data; applying a programming voltage to a word line corresponding to the selected page; performing a pre-verification operation at a pre-threshold voltage level lower than a target threshold voltage level, wherein an evaluation operation of the pre-verification operation is performed during a first evaluation period; and performing a primary verification operation at the target threshold voltage level, wherein an evaluation operation of the primary verification operation is performed during a second evaluation period longer than the first evaluation period.

[0011] Another method for operating a semiconductor memory according to this disclosure includes: storing specific data in a first latch cell of a page buffer and storing programming data to be programmed into a memory cell in a second latch cell of the page buffer; applying a programming enable voltage or a programming disable voltage to a bit line connected to the memory cell based on the programming data; applying a programming voltage to a word line connected to the memory cell; and, while a programming verification voltage is applied to the word line, sequentially performing a verification operation corresponding to a first programming state and a verification operation corresponding to a second programming state. Attached Figure Description

[0012] Example embodiments will now be described more fully with reference to the accompanying drawings; however, example embodiments may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to enable those skilled in the art to implement the present disclosure.

[0013] In the accompanying drawings, dimensions may be exaggerated for clarity. It will be understood that when an element is referred to as being "between" two elements, it can be the only element between the two elements, or there may be one or more intermediate elements. Similar reference numerals always refer to similar elements.

[0014] Figure 1 This is a block diagram illustrating a memory system including a memory device according to an embodiment of the present disclosure.

[0015] Figure 2 This is an example Figure 1 A diagram of the semiconductor memory included in the memory device shown.

[0016] Figure 3 This is a diagram illustrating a three-dimensional configuration of storage blocks.

[0017] Figure 4 It provides a detailed example. Figure 3 The circuit diagram of any of the memory blocks shown.

[0018] Figure 5 This is an example Figure 4 The circuit diagram of the memory string shown is shown.

[0019] Figure 6 This is a threshold voltage distribution diagram illustrating the erase state and multiple programming states of a memory cell.

[0020] Figure 7 This is a circuit diagram illustrating a page buffer according to an embodiment of the present disclosure.

[0021] Figure 8 This is a waveform diagram illustrating a method for adjusting the evaluation period in a programming verification operation of the page buffer.

[0022] Figure 9 This is a flowchart illustrating the programming operation of a semiconductor memory according to an embodiment of the present disclosure.

[0023] Figure 10 It provides a more detailed example. Figure 9 The flowchart shown illustrates the steps involved in performing the programming verification operation.

[0024] Figure 11 This is a flowchart illustrating the programming operation of a semiconductor memory according to another embodiment of the present disclosure.

[0025] Figure 12 This is an example Figure 11 The threshold voltage distribution diagram shows the threshold voltage distribution of memory cells in fuzzy programming and fine programming operations.

[0026] Figure 13 This is a flowchart illustrating the programming operation of a semiconductor memory according to yet another embodiment of the present disclosure.

[0027] Figure 14 This is a flowchart illustrating the programming operation of a semiconductor memory according to yet another embodiment of the present disclosure.

[0028] Figure 15 The waveforms of the programming voltage and verification voltage for a multi-sensor operation illustrating the programming voltage application operation and the programming verification operation are shown.

[0029] Figure 16 This is a circuit diagram illustrating a page buffer according to another embodiment of the present disclosure.

[0030] Figure 17 This is a circuit diagram illustrating a page buffer according to yet another embodiment of the present disclosure.

[0031] Figure 18 This is a diagram illustrating another implementation of the memory system.

[0032] Figure 19 This is a diagram illustrating another implementation of the memory system.

[0033] Figure 20 This is a diagram illustrating another implementation of the memory system.

[0034] Figure 21 This is a diagram illustrating another implementation of the memory system. Detailed Implementation

[0035] The specific structural or functional descriptions disclosed herein are merely illustrative for the purpose of describing embodiments based on the concept of this disclosure. Embodiments based on the concept of this disclosure can be implemented in various forms and should not be construed as limited to the embodiments set forth herein.

[0036] In the following description, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings in order to enable those skilled in the art to implement the technical spirit of the present disclosure.

[0037] Figure 1 This is a block diagram illustrating a memory system including a memory device according to an embodiment of the present disclosure.

[0038] Reference Figure 1 The memory system 1000 includes a memory device 1100, a controller 1200, and a host 1300. The memory device 1100 includes a plurality of semiconductor memories 100. The plurality of semiconductor memories 100 may be divided into a plurality of groups GR1 to GRn. Although embodiments of this disclosure illustrate and describe a case where the host 1300 is included in the memory system 1000, the memory system 1000 may include only the controller 1200 and the memory device 1100, and the host 1300 may be located external to the memory system 1000.

[0039] exist Figure 1 In the illustration, multiple groups GR1 to GRn of the memory device 1100 are shown communicating with the controller 1200 via first channel CH1 to nth channel CHn, respectively. (See below for further details.) Figure 2 Describe each semiconductor memory 100.

[0040] Each of the multiple groups GR1 to GRn communicates with the controller 1200 through a common channel. The controller 1200 controls the multiple semiconductor memories 100 of the memory device 1100 through multiple channels CH to CHn.

[0041] Controller 1200 is connected between host 1300 and memory device 1100. Controller 1200 accesses memory device 1100 in response to requests from host 1300. For example, controller 1200 controls read operations, programming operations, erase operations, and background operations of memory device 1100 in response to a host command Host_CMD received from host 1300. In a programming operation, host 1300 can send address ADD and data to be programmed DATA along with host command Host_CMD. In a read operation, host 1300 can send address ADD along with host command Host_CMD. In a programming operation, controller 1200 can send a command corresponding to the programming operation and data to be programmed DATA to memory device 1100. In a read operation, controller 1200 can send a command corresponding to the read operation to memory device 1100, receive read data DATA from memory device 1100, and send the received data DATA to host 1300. Controller 1200 provides an interface between memory device 1100 and host 1300. Controller 1200 drives firmware for controlling memory device 1100.

[0042] The host 1300 includes portable electronic devices such as computers, PDAs, PMPs, MP3 players, cameras, portable video cameras, and mobile phones. The host 1300 can request programming, reading, and erasing operations from the memory system 1000 via the host command Host_CMD. For programming operations, the host 1300 can send the host command Host_CMD, data DATA, and address ADD corresponding to the programming operation to the controller 1200. For reading operations, the host can send the host command Host_CMD and address ADD corresponding to the reading operation to the controller 1200. The address ADD can be a logical address block of data.

[0043] The controller 1200 and the memory device 1100 can be integrated into a single semiconductor memory. In one embodiment, the controller 1200 and the memory device 1100 can be integrated into a single semiconductor memory to form a memory card. For example, the controller 1200 and the memory device 1100 can be integrated into a single semiconductor memory to form a memory card such as a PC card (Personal Computer Memory Card International Association (PCMCIA)), a compact flash memory (CF) card, a smart media card (SM or SMC), a memory stick, a multimedia card (MMC, RS-MMC, or micro MMC), an SD card (SD, mini SD, micro SD, or SDHC), or a universal flash memory (UFS).

[0044] In another example, the memory system 1000 may be one of various components of an electronic device such as: a computer, an ultra-mobile PC (UMPC), a workstation, a netbook, a personal digital assistant (PDA), a portable computer, a network tablet computer, a cordless phone, a mobile phone, a smartphone, an e-book reader, a portable multimedia player (PMP), a portable game console, a navigation system, a black box, a digital camera, a 3D television, a digital audio recorder, a digital audio player, a digital picture recorder, a digital picture player, a digital video recorder, a digital video player, a device capable of transmitting / receiving information in a wireless environment, one of various electronic devices constituting a home network, one of various electronic devices constituting a computer network, one of various electronic devices constituting a telematics network, an RFID device, or one of various components constituting a computing system.

[0045] In implementations, the memory device 1100 or memory system 1000 can be packaged in various forms. For example, the memory device 1100 or memory system 1000 can be packaged as a package stack (PoP), ball grid array (BGA), chip-scale package (CSP), plastic leaded chip carrier (PLCC), plastic dual in-line package (PDIP), wafer-in-package, wafer-in-chip, chip-on-board (COB), ceramic dual in-line package (CERDIP), plastic metric quad flat package (MQFP), thin quad flat package (TQFP), small outline integrated circuit (SOIC), shrink small outline package (SSOP), thin small outline package (TSOP), system-in-package (SIP), multi-chip package (MCP), wafer-level fabrication package (WFP), or wafer-level fabrication stack-up package (WSP).

[0046] Figure 2 This is an example Figure 1 A diagram of the semiconductor memory included in the memory device 1100 shown.

[0047] Reference Figure 2 The semiconductor memory 100 includes a memory cell array 110, an address decoder 120, a read / write circuit 130, control logic 140, and a voltage generation circuit 150. The address decoder 120, the read / write circuit 130, and the voltage generation circuit 150 can be defined as peripheral circuits 160 that perform read operations on the memory cell array 110.

[0048] The memory cell array 110 includes multiple memory blocks BLK1 to BLKz. The multiple memory blocks BLK1 to BLKz are connected to the address decoder 120 via word lines WL. The multiple memory blocks BLK1 to BLKz are connected to the read / write circuitry 130 via bit lines BL1 to BLm. Each of the multiple memory blocks BLK1 to BLKz includes multiple memory cells. In this embodiment, the multiple memory cells may be non-volatile memory cells. Multiple memory cells connected to a word line can be defined as a page. That is, the memory cell array 110 may be configured with multiple pages.

[0049] Each of the plurality of memory blocks BLK1 to BLKz in the memory cell array 110 includes a plurality of memory strings. Each of the plurality of memory strings includes a drain selection transistor, a plurality of memory cells, and a source selection transistor connected in series between a bit line and a source line. Furthermore, each of the plurality of memory strings may include a transfer transistor between the source selection transistor and the memory cell, and a transfer transistor between the drain selection transistor and the memory cell, and also includes a pipe gate transistor between the memory cells. The memory cell array 110 will be described in detail later.

[0050] Address decoder 120 is connected to memory cell array 110 via word line WL. Address decoder 120 operates in response to address decoder control signal AD_signals generated by control logic 140. Address decoder 120 receives address ADDR through input / output buffer (not shown) in semiconductor memory 100.

[0051] Address decoder 120 can decode the row address in the received address ADD, and apply multiple operating voltages, including programming voltage Vpgm, read voltage Vread, pass voltage Vpass, and verification voltage Vverify generated by voltage generation circuit 150 during programming or read operations, to multiple memory cells of memory cell array 110 based on the decoded row address.

[0052] Address decoder 120 decodes the column address in the received address ADDR. Address decoder 120 sends the decoded column address Yi to read / write circuit 130.

[0053] The address ADDR received during programming or read operations includes the block address, row address, and column address. Address decoder 120 selects a memory block and a word line based on the block address and row address. The column address is decoded by address decoder 120 to provide to read / write circuitry 130.

[0054] Address decoder 120 may include block decoder, row decoder, column decoder, address buffer, etc.

[0055] The read / write circuit 130 includes multiple page buffers PB1 to PBm. The multiple page buffers PB1 to PBm are connected to the memory cell array 110 via bit lines BL1 to BLm. The multiple page buffers PB1 to PBm can perform data sensing operations during read operations or program verification operations to sense the programming state of the memory cells connected to the bit lines BL1 to BLm. During data sensing operations, each of the multiple page buffers PB1 to PBm can latch data based on the current amount of the corresponding bit line among the bit lines BL1 to BLm. The multiple page buffers PB1 to PBm can perform data transfer operations to receive data to be programmed during programming operations and temporarily store the received data, and adjust the potential level of the corresponding bit line among the bit lines BL1 to BLm based on the temporarily stored data.

[0056] Each of the multiple page buffers PB1 to PBm can control the amount of cell current flowing through the bit line by adjusting the evaluation period during a data sensing operation. Therefore, a programming verification operation corresponding to multiple programming states or multiple threshold voltage levels can be performed by applying a read voltage or a verification voltage to the word line to which the memory cell is connected. In other words, each of the multiple page buffers PB1 to PBm can adjust the amount of cell current by adjusting the evaluation period during a data sensing operation. Therefore, each of the multiple page buffers PB1 to PBm can perform data sensing operations, such as adjusting the read voltage or verification voltage applied to the word line.

[0057] Each of the multiple page buffers PB1 to PBm can temporarily store data programmed in a page that has completed programming operations and is adjacent to the selected page in the programming operation, and set the evaluation period in the programming verification operation of the selected page.

[0058] In addition, each of the multiple page buffers PB1 to PBm can receive and temporarily store specific data for setting the evaluation period, and set the evaluation period in the programming verification operation of the selected page based on the temporarily stored specific data.

[0059] The read / write circuit 130 operates in response to the page buffer control signal PB_signals output from the control logic 140.

[0060] In an implementation, the read / write circuit 130 may include a page buffer (or page register), a column select circuit, etc.

[0061] Control logic 140 is connected to address decoder 120, read / write circuit 130, and voltage generation circuit 150. Control logic 140 receives commands (CMD) through input / output buffers (not shown) of semiconductor memory 100. Control logic 140 controls the overall operation of semiconductor memory 100 in response to commands (CMD). For example, control logic 140 receives commands (CMD) corresponding to programming commands, and in response to the received commands (CMD), generates and outputs address decoder control signals AD_signals for controlling address decoder 120, page buffer control signals PB_signals for controlling read / write circuit 130, and voltage generation circuit control signals VG_signals for controlling voltage generation circuit 150. Additionally, control logic 140 receives commands corresponding to read operations, and in response to the received commands (CMD), generates and outputs address decoder control signals AD_signals for controlling address decoder 120, page buffer control signals PB_signals for controlling read / write circuit 130, and voltage generation circuit control signals VG_signals for controlling voltage generation circuit 150. Control logic 140 can be implemented as hardware, software, or a combination of hardware and software. For example, control logic 140 can be a control logic circuit that operates according to an algorithm and / or a processor that executes control logic code.

[0062] During programming operations, the voltage generation circuit 150, under the control of the voltage generation circuit control signal VG_signals output from the control logic 140, generates a programming voltage Vpgm, a pass voltage Vpass, and a verification voltage Vverify, and outputs the generated voltages to the address decoder 120. Conversely, during reading operations, the voltage generation circuit 150, under the control of the voltage generation circuit control signal VG_signals output from the control logic 140, generates a read voltage Vread and a pass voltage Vpass, and outputs the generated voltages to the address decoder 120.

[0063] Figure 3 This is a diagram illustrating a three-dimensional configuration of storage blocks.

[0064] Reference Figure 3 The three-dimensionally configured memory blocks BLK1 to BLKz can be spaced apart from each other along the direction Y extending from bit lines BL1 to BLm. For example, the first memory block BLK1 to the z-th memory block BLKz can be spaced apart from each other along the second direction Y and include multiple memory cells stacked along the third direction Z. (See reference...) Figure 4 and Figure 5 Describe in detail the construction of any one of the storage blocks from the first storage block BLK1 to the z-th storage block BLKz.

[0065] Figure 4 It provides a detailed example. Figure 3 The circuit diagram of any of the memory blocks shown.

[0066] Figure 5 This is an example Figure 4 The circuit diagram of the memory string shown is shown.

[0067] Reference Figure 4 and Figure 5 Each memory string ST can be connected between the corresponding bit line BL1 to BLm and the source line SL. An example is given describing a memory string ST connected between the first bit line BL1 and the source line SL.

[0068] A memory string ST may include source select transistors SST connected in series between source line SL and first bit line BL1, memory cells F1 to Fn (n is a positive integer), and drain select transistors DST. The gates of the source select transistors SST included in different memory strings ST connected to different bit lines BL1 to BLm may be connected to a first source select line SSL0 and a second source select line SSL1. In the example, source select transistors SST that are adjacent to each other in the second direction Y may be connected to the same source select line. For example, assuming that the source select transistors SST are arranged sequentially along the second direction Y, the gates of source select transistors SST arranged in the first direction X starting from the first source select transistor SST and included in different strings ST, and the gates of source select transistors SST arranged in the first direction X starting from the second source select transistor SST and included in different strings ST, may be connected to the first source select line SSL0. Additionally, the gates of source selection transistors SST arranged in the first direction X and included in different strings ST starting from the third source selection transistor SST, and the gates of source selection transistors SST arranged in the first direction X and included in different strings starting from the fourth source selection transistor SST, can be connected to the second source selection line SSL1.

[0069] The gates of memory cells F1 to Fn can be connected to word lines WL1 to WLn, and the gate of drain select transistor DST can be connected to any one of the first drain select line DSL0 to the fourth drain select line DSL3.

[0070] In a drain-select transistor (DST), the gates of transistors arranged in the first direction X are connected to the same drain-select line (e.g., DSL0), but transistors arranged in the second direction Y can be connected to different drain-select lines DSL1 to DSL3. For example, assuming that the drain-select transistors DST are arranged sequentially along the second direction Y, the gates of drain-select transistors DST arranged in the first direction X starting from the first drain-select transistor DST and included in different strings ST can be connected to the first drain-select line DSL0. Drain-select transistors DST arranged in the second direction Y starting from the drain-select transistor DST connected to the first drain-select line DSL0 can be sequentially connected to the second drain-select lines DSL1 to the fourth drain-select line DSL3. Therefore, in a selected memory block, the memory string ST connected to the selected drain-select line can be selected, and the memory string ST connected to other unselected drain-select lines can be left unselected.

[0071] Memory cells connected to the same word line can constitute a page PG. A page can represent a physical page. For example, a group of memory cells connected to the same word line in the string ST connected to the first bit line BL1 to the m-th bit line BLm in the first direction X is called a page PG. For example, memory cells arranged in the first direction X in the first memory cell F1 connected to the first word line WL1 can constitute a page PG. Memory cells arranged in the second direction Y in the first memory cell F1 that are commonly connected to the first word line WL1 can constitute another page. Therefore, when the first drain selection line DSL0 is the selected drain line and the first word line WL1 is the selected word line, the page connected to the first drain selection line DSL0 among the multiple page PGs connected to the first word line WL1 becomes the selected page. Pages that are commonly connected to the first word line WL1 but connected to the unselected second drain selection line DSL1 to the unselected fourth drain selection line DSL3 become unselected pages.

[0072] Although the accompanying drawings illustrate a case where a string ST includes one source-select transistor (SST) and one drain-select transistor (DST), depending on the semiconductor memory, a string ST may include multiple source-select transistors (SST) and multiple drain-select transistors (DST). Furthermore, depending on the semiconductor memory, dummy cells may be included between the source-select transistors (SST), memory cells F1 to Fn, and drain-select transistors (DST). These dummy cells do not store user data like ordinary memory cells F1 to Fn, but can be used to improve the electrical characteristics of each string ST. However, dummy cells are not essential components in this embodiment, and therefore their detailed description will be omitted.

[0073] Figure 6 This is a threshold voltage distribution diagram illustrating the erase state and multiple programming states of a memory cell.

[0074] Each memory cell can be a single-level cell (SLC) storing one data bit, a multi-level cell (MLC) storing two data bits, a three-level cell (TLC) storing three data bits, or a four-level cell (QLC) storing four data bits. In embodiments of this disclosure, the programming states of a TLC will be described as an example.

[0075] Multiple memory cells contained in a single page can be programmed to have threshold voltages corresponding to erase state E and multiple programming states PV1 to PV7. PV1 To V PV7 This distinguishes it from adjacent programming states. For example, the threshold voltage distribution of the memory cell corresponding to the first programming state PV1 is equal to or higher than the verification voltage V. PV1 And below the verification voltage V PV2 The threshold voltage distribution of the memory cell corresponding to the second programming state PV2 is equal to or higher than the verification voltage V. PV2 And below the verification voltage V PV3 .

[0076] Figure 7 This is a circuit diagram illustrating a page buffer according to an embodiment of the present disclosure.

[0077] Including Figure 2 The page buffers PB1 to PBm in the illustrated read / write circuit 130 may have similar structures to each other. In the embodiments of this disclosure, page buffer 131A will be described as an example for ease of description.

[0078] Reference Figure 7 The page buffer 131A may include a bit line controller 231, a bit line discharge unit 232, a sensing node precharge unit 233, a first latch unit 235, and a second latch unit 234. The first latch unit 235 may be defined as the master latch unit, and the second latch unit 234 may be defined as the sub-latch unit.

[0079] During a data sensing operation in a read operation or a programming verification operation, the bit line controller 231 controls the potential level of the sensing node SO based on the amount of current (i.e., cell current) of the bit line BL1, which changes according to the programming state or threshold voltage of the memory cell connected to the bit line BL1.

[0080] Bit line controller 231 may include multiple NMOS transistors N1 and N3 to N6 and multiple PMOS transistors P1 and P2.

[0081] The NMOS transistor N1 is connected between bit line BL1 and node ND1, and electrically connects the first bit line BL1 and node ND1 to each other in response to the page buffer select signal PBSEL.

[0082] NMOS transistor N3 is connected between node ND1 and common node CSO, and electrically connects node ND1 and common node CSO to each other in response to the page buffer sensing signal PB_SENSE.

[0083] PMOS transistors P1 and PMOS transistor P2 are connected in series between the power supply voltage VDD and the sensing node SO, and are turned on in response to node QS of sub-latch unit 234 and the precharge signal SA_PRECH_N, respectively.

[0084] NMOS transistor N4 is connected between the common node CSO and the node located between PMOS transistors P1 and PMOS transistor P2, and in response to the control signal SA_CSOC, it provides the power supply voltage VDD supplied through PMOS transistor P1 to the common node CSO.

[0085] The NMOS transistor N5 is connected between the sensing node SO and the common node CSO, and electrically connects the sensing node SO and the common node CSO to each other in response to the transmission signal TRANSO.

[0086] NMOS transistor N6 is connected between common node CSO and node ND2 of sub-latch unit 234, and electrically connects common node CSO and node ND2 to each other in response to discharge signal SA_DISCH.

[0087] The operation of the bitline controller 231 in data sensing operations will be described below.

[0088] PMOS transistors P1 and P2 precharge the sensing node SO to the supply voltage VDD level in response to the node QS set to logic low in the second latch unit 234 and the precharge signal SA_PRECH_N with logic low. NMOS transistor N5 turns on in response to the transmission signal TRANSO with logic high, and the common node CSO is precharged to a specific level VDD-Vth.

[0089] Next, an evaluation operation is performed from the time the precharge signal SA_PRECH_N is changed to a logic high level until the transfer signal TRANSO is changed to a logic low level. PMOS transistor P2 is turned off in response to the precharge signal SA_PRECH_N changing to a logic high level, and the power supply voltage VDD applied to the sensing node SO is interrupted. The potential levels of the sensing node SO and the common node CSO change according to the programming state of the memory cell connected to bit line BL1. For example, when a memory cell has a programming state where its threshold voltage is higher than the read voltage or verification voltage applied to the word line of the memory cell during a read or verification operation, no current flows through bit line BL1. Therefore, the potentials of the common node CSO and the sensing node SO remain at the precharge level. On the other hand, when a memory cell has a state where its threshold voltage is lower than the read voltage or verification voltage applied to the word line of the memory cell during a read or verification operation, current flows through bit line BL1. Therefore, when the common node CSO and the sensing node SO are discharging, their potentials decrease to the discharge level, and the slope of this potential decrease varies depending on the cell current. For example, when the cell current is relatively large, the sensing node SO discharges at a high speed, resulting in a relatively large slope. When the cell current is relatively small, the sensing node SO discharges at a low speed, resulting in a relatively small slope.

[0090] Bit line discharge unit 232 is connected to node ND1 of bit line controller 231 to discharge the potential level of bit line BL1.

[0091] Bit line discharge unit 232 may include an NMOS transistor N2 connected between node ND1 and ground power supply VSS, and the NMOS transistor N2 applies the ground power supply VSS to node ND1 in response to the bit line discharge signal ND1BL_DIS.

[0092] The sensing node pre-charge unit 233 is connected between the sensing node SO and the power supply voltage VDD to pre-charge the sensing node SO to the level of the power supply voltage VDD.

[0093] The sensing node precharge unit 233 may include a PMOS transistor P3, and the PMOS transistor P3 applies a power supply voltage VDD to the sensing node SO in response to the sensing node precharge signal PRECHSO_N.

[0094] The second latch unit 234 may include multiple NMOS transistors N7 to N11 and inverters IV1 and IV2.

[0095] Inverters IV1 and IV2 are connected in anti-parallel between nodes QS and QS_N to form a latch. Inverters IV1 and IV2 can be defined as a second latch.

[0096] NMOS transistors N7 and NMOS transistor N8 are connected in series between the sensing node SO and the ground power supply VSS. NMOS transistor N7 turns on in response to the transmission signal TRANS, and NMOS transistor N8 turns on or off depending on the potential level of node QS.

[0097] NMOS transistor N9 is connected between node QS and node ND3 to electrically connect nodes QS and ND3 in response to the reset signal SRST. NMOS transistor N10 is connected between node QS_N and node ND3 to electrically connect nodes QS_N and ND3 in response to the set signal SSET. NMOS transistor N11 is connected between node ND3 and the ground supply VSS, and is turned on according to the potential of the sense node SO to electrically connect nodes ND3 and the ground supply VSS. For example, when the sense node SO is precharged to a high level, and the reset signal SRST is applied to NMOS transistor N9 at a logic high level, nodes QS and QS_N are initialized to logic low and logic high levels, respectively. Conversely, when the sense node SO is precharged to a high level, and the set signal SSET is applied to NMOS transistor N10 at a logic high level, nodes QS and QS_N are set to logic high and logic low levels, respectively. During the bit line precharge operation and data sensing operation in the evaluation period, the node QS can be set to logic low.

[0098] During the data latching period following the evaluation period, the second latch unit 234 can latch read data or verify data based on the potential level of the sensing node SO. For example, the second latch unit 234 can latch read data or verify data in response to the potential of the sensing node SO evaluated based on the cell current after the end of the evaluation period and the set signal SSET that flips to a high level for a specific time, by keeping the potential of node QS_N at a high level or discharging the potential of node QS_N to a low level.

[0099] The first latch unit 235 may include multiple NMOS transistors N12 to N16, multiple PMOS transistors P4 and P5, and inverters IV3 and IV4.

[0100] Inverters IV3 and IV4 are connected in anti-parallel between node QM and node QM_N to form a latch. Inverters IV3 and IV4 can be defined as the first latch.

[0101] NMOS transistors N12 and NMOS transistor N13 are connected in series between the sensing node SO and the ground power supply VSS. NMOS transistor N12 turns on in response to the first transmission signal TRANM, and NMOS transistor N13 turns on or off according to the potential level of node QM.

[0102] NMOS transistor N14 is connected between node QM and node ND4. NMOS transistor N14 is turned on or off in response to the reset signal MRST. NMOS transistor N15 is connected between node QM_N and node ND4 to electrically connect nodes QM_N and ND4 to each other in response to the set signal MSET. NMOS transistor N16 is connected between node ND4 and the ground power supply VSS, and connects node ND4 and the ground power supply VSS to each other according to the potential of the sensed node SO.

[0103] The first latch unit 235 can store previously programmed data that was programmed in a programming operation immediately preceding the currently executing programming operation. For example, the first latch unit 235 can store previously programmed data that has been programmed in a page adjacent to the selected page and has already been programmed. The page buffer 131A can transfer to the first latch unit 235, after the programming operation immediately preceding the current programming operation is completed, the data to be programmed that was received from an external source and temporarily stored in the programming operation immediately preceding the current programming operation, and then store the data, or during the current programming operation, the data can be transferred from the page buffer 131A. Figure 2 The control logic 140 shown receives previously programmed data and then stores it. For example, when the previously programmed data is data with a relatively high programming state, the first latch unit 235 can set node QM_N to a logic low level to store the previously programmed data. When the previously programmed data is data with a relatively low programming state, the first latch unit 235 can set node QM_N to a logic high level.

[0104] Furthermore, the first latch unit 235 can receive specific data from the control logic 140 and then store that specific data. For example, the first latch unit 235 can set node QM_N to a logic low level to store specific data.

[0105] When node QM_N is set to logic low, the first latch unit 235 can reduce the evaluation period. For example, the bit line controller 231 can adjust the evaluation period, which is the period for performing the evaluation operation, based on the data stored in the first latch unit 235. The bit line controller 231 can define the period from the time when the precharge signal SA_PRECH_N changes to logic high to the time when the transmission signal TRANSO changes to logic low as the first evaluation period. The first latch unit 235 applies the power supply voltage VDD to the sensing node SO based on the second transmission signal TRANM_N, which was applied at a logic low level before the precharge signal SA_PRECH_N changes to logic high, and the logic low potential of node QM_N. Therefore, although the precharge signal SA_PRECH_N changes to logic high, the power supply voltage VDD is continuously applied to the sensing node SO, so that no evaluation operation is performed. Subsequently, the bit line controller 231 can define the period from the time when the second transmission signal TRANM_N changes to logic high to the time when the transmission signal TRANSO changes to logic low as the second evaluation period. The second assessment period can be set shorter than the first assessment period.

[0106] As described above, the page buffer 131A according to this disclosure can set the evaluation period in a read operation or a programming verification operation to a first evaluation period or a second evaluation period shorter than the first evaluation period based on the data stored in the first latch unit 235.

[0107] The page buffer 131A according to this disclosure may include an additional latch unit (not shown) connected to the sensing node SO. The additional latch unit may receive data to be programmed during a programming operation, temporarily store the received data, and then send the temporarily stored data to the second latch unit 234. Additionally, the temporarily stored data in the additional latch unit may be sent to the first latch unit 235 for storage after the programming operation is completed.

[0108] Figure 8 The diagram illustrates a signal waveform of a method for adjusting the evaluation period in a programming verification operation of the page buffer.

[0109] The following will refer to Figure 7 and Figure 8 This describes a method for adjusting the evaluation period in a data sensing operation during a read operation or a programmable verification operation.

[0110] 1) Method for setting the evaluation period as the first period, Eval1

[0111] The first latch unit 235 of the page buffer 131A sets the logic level of node QM_N to logic high (QM_N = 1).

[0112] For example, during initialization, the first latch unit 235 is initialized to make the logic level of node QM_N logic high. For example, when a reset signal MRST is applied at a logic high level while the sensing node SO is precharged to a logic high level, the first latch unit 235 is initialized to make node QM logic low and node QM_N logic high.

[0113] Subsequently, the first latch unit 235 stores previously programmed data or specific data used in the immediate preceding programming operation. When the previously programmed data corresponds to a relatively low programming state (e.g., Figure 6 When any of E and PV1 to PV5 are shown, or when specific data is used to set the evaluation period to the first period Eval1, the first latch unit 235 holds the logic level of node QM_N at logic high. For example, based on previously programmed data or specific data, the sensing node SO is controlled to have a logic low level, causing the NMOS transistor N16 to be turned off. Therefore, although the set signal MSET is applied at a logic high level, node QM_N remains in the initialized state, i.e., at a logic high level.

[0114] PMOS transistors P1 and P2 of page buffer 131A precharge the sensing node SO to the power supply voltage VDD level in response to the node QS of the second latch unit 234 being set to logic low and the precharge signal SA_PRECH_N having a logic low level. NMOS transistor N5 turns on in response to the transfer signal TRANSO having a logic high level, and the common node CSO is precharged to a specific level VDD-Vth.

[0115] Subsequently, an evaluation operation is performed during the first evaluation period Eval1, which is the time from when the precharge signal SA_PRECH_N changes to a logic high level to when the transmission signal TRANSO changes to a logic low level. The PMOS transistor P2 is turned off in response to the precharge signal SA_PRECH_N changing to a logic high level, and the power supply voltage VDD applied to the sensing node SO is interrupted. The potential levels of the sensing node SO and the common node CSO change according to the programming state of the memory cell connected to the bit line BL1. For example, depending on the programming state of the memory cell or the read voltage or verification voltage applied to the memory cell, a cell current Icell occurs, and the discharge slope of the sensing node SO based on the cell current Icell is changed. Therefore, after the first evaluation period Eval1 ends, the potential level of the sensing node SO can be determined based on the cell current Icell. Subsequently, the second latch unit 234 can latch data corresponding to the potential of the sensing node SO in response to the reset signal SRST. For example, when the potential of the sensing node SO is higher than the reference voltage Vtrip, the second latch unit 234 can latch data with a first data value. When the potential of the sensing node SO is lower than the reference voltage Vtrip, the second latch unit 234 can latch the data with the second data value.

[0116] 2) Method for setting the evaluation period as the second period, Eval2.

[0117] The first latch unit 235 of the page buffer 131A sets the logic level of node QM_N to logic low (QM_N = 0).

[0118] For example, during initialization, the first latch unit 235 is initialized to make the logic level of node QN_N logic high. For example, when a reset signal MRST is applied at a logic high level while the sensing node SO is precharged to a logic high level, the first latch unit 235 is initialized to make node QM logic low and node QM_N logic high.

[0119] Subsequently, the first latch unit 235 stores previously programmed data or specific data used in the immediate preceding programming operation. When the previously programmed data corresponds to a relatively high programming state (e.g., Figure 6When either PV6 or PV7 is shown, or when the specific data is used to set the evaluation period to the second period Eval2, the first latch unit 235 sets the logic level of node QM_N to logic low. For example, based on previously programmed data or specific data, the sensing node SO is controlled to have a logic high level, causing the NMOS transistor N16 to turn on. Therefore, when the set signal MSET is applied at a logic high level, node QM_N is set to change from a logic high level to a logic low level.

[0120] PMOS transistors P1 and P2 of page buffer 131A precharge the sensing node SO to the level of the power supply voltage VDD in response to the node QS of the second latch unit 234 being set to logic low and the precharge signal SA_PRECH_N having logic low. NMOS transistor N5 turns on in response to the transfer signal TRANSO having logic high, and the common node CSO is precharged to a specific level VDD-Vth.

[0121] The first latch unit 235 applies a power supply voltage VDD to the sensing node SO based on the second transmission signal TRANM_N, which was applied at a logic low level before the precharge signal SA_PRECH_N changes to a logic high level, and the potential of the node QM_N, which has a logic low level. Therefore, even though the precharge signal SA_PRECH_N changes to a logic high level, the power supply voltage VDD is continuously applied to the sensing node SO, preventing the evaluation operation from being performed. Subsequently, the evaluation operation is performed during a second evaluation period Eval2, which is the time from when the second transmission signal TRANM_N changes to a logic high level to when the transmission signal TRANSO changes to a logic low level. PMOS transistor P2 is turned off in response to the precharge signal SA_PRECH_N changing to a logic high level, and PMOS transistor P4 is turned off when the transmission signal TRANSO changes to a logic low level. Therefore, the power supply voltage VDD applied to the sensing node SO is interrupted. The potential levels of the sensing node SO and the common node CSO change according to the programming state of the memory cell connected to bit line BL1. For example, a cell current Icell occurs based on the programming state of the memory cell or the read or verify voltage applied to the memory cell, and the discharge slope of the sensing node SO based on the cell current Icell is changed. Therefore, after the second evaluation period Eval2 ends, the potential level of the sensing node SO can be determined based on the cell current Icell. The second evaluation period Eval2 is shorter than the first evaluation period Eval1. Therefore, after the second evaluation period Eval2 ends, the potential of the sensing node SO can be relatively higher than the potential of the sensing node SO after the first evaluation period Eval1 ends. That is, as the evaluation period becomes shorter, the time for the potential level of the sensing node SO to be discharged becomes shorter. Therefore, the potential of the sensing node SO can be evaluated at the same level as when the read or verify voltage applied to the memory cell becomes relatively low.

[0122] Subsequently, the second latch unit 234 can latch data corresponding to the potential of the sensing node SO in response to the reset signal SRST. For example, when the potential of the sensing node SO is higher than the reference voltage Vtrip, the second latch unit 234 can latch data with a first data value. When the potential of the sensing node SO is lower than the reference voltage Vtrip, the second latch unit 234 can latch data with a second data value.

[0123] Figure 9 This is a flowchart illustrating the programming operation of a semiconductor memory according to an embodiment of the present disclosure.

[0124] Figure 10 It provides a more detailed example. Figure 9 The flowchart shown illustrates step S940 of performing the programming verification operation.

[0125] The following will refer to Figures 2 to 10 The programming operation of a semiconductor memory according to embodiments of the present disclosure is described.

[0126] In the programming operation of the semiconductor memory according to the embodiments of the present disclosure, pages corresponding to multiple word lines WL1 to WLn are programmed sequentially. For example, after programming the page corresponding to word line WL1, programming the page corresponding to word line WL2 can be performed. Subsequently, programming the page corresponding to word line WL3 can be performed.

[0127] In this embodiment, as an example, the programming operation of the memory unit F2 included in the page corresponding to the word line WL2 adjacent to word line WL1 will be described after the programming operation of the memory unit F1 included in the page corresponding to word line WL1 is completed.

[0128] In step S910, the page buffers PB1 to PBm of the read / write circuit 130 store previously programmed data (i.e., data stored in the previous page) programmed in the page corresponding to the programmed word line WL1 in the first latch of the first latch unit 235. The page corresponding to the programmed word line WL1 is adjacent to the page corresponding to the selected word line WL2 in the source line direction and was programmed in the previous programming operation.

[0129] The previously programmed data stored in the previous page can be data that was temporarily stored in page buffers PB1 to PBm during the programming operation of the previous page. That is, the data that was temporarily stored in page buffers PB1 to PBm during the programming operation of the previous page can be stored as previously programmed data in the first latch of the first latch unit 235.

[0130] The logic level of node QM_N of the first latch can be controlled based on the previously stored data. For example, when the previously programmed data stored in the first latch corresponds to... Figure 6 When the erase state E and at least one of the programming states PV1 to PV7 (e.g., PV6 and PV7) with a relatively high threshold voltage distribution are shown, the node QM_N of the first latch can be controlled to have a logic low level. This is when the previously programmed data stored in the first latch corresponds to... Figure 6 When the erase state E and at least one of the multiple programming states PV1 to PV7 with a relatively low threshold voltage distribution (e.g., PV1 to PV5) are shown, the node QM_N of the first latch can be controlled to have a logic high level.

[0131] In other words, when previously programmed data corresponding to at least one programming state PV6 and PV7 with a relatively high threshold voltage distribution is stored in the first latch, the time for performing the evaluation operation in the programming verification operation is set to a second evaluation period Eval2 in the page buffer. Conversely, when previously programmed data corresponding to an erase state E with a relatively low threshold voltage distribution and at least one programming state PV1 to PV5 is stored in the first latch, the time for performing the evaluation operation in the programming verification operation is set to a first evaluation period Eval1 in the page buffer, which is longer than the second evaluation period Eval2.

[0132] In step S920, data to be stored in the page corresponding to the word line WL2 selected in the current programming operation is received, and then stored in the second latch of the second latch unit 234 of each of the plurality of page buffers PB1 to PBm. Based on the data stored in the second latch unit 234, each of the plurality of page buffers PB1 to PBm can control a corresponding bit line among the bit lines BL1 to BLm to have a programming enable voltage level or a programming disable voltage level.

[0133] In step S930, a programming voltage application operation is performed by applying a programming voltage Vpgm to the selected word line WL2.

[0134] The voltage generation circuit 150 generates a programming voltage Vpgm and a pass voltage Vpass under the control of the voltage generation circuit control signal VG_signals output from the control logic 140. The address decoder 120 applies the programming voltage Vpgm generated by the voltage generation circuit 150 to the selected word line WL2, and applies the pass voltage Vpass generated by the voltage generation circuit 150 to the other unselected word lines WL1 and WL3 to WLn.

[0135] In step S940, a programming verification operation is performed on the selected page corresponding to the selected word line WL2.

[0136] The voltage generation circuit 150 generates a verification voltage Vverify and a pass voltage Vpass under the control of the voltage generation circuit control signal VG_signals output from the control logic 140. The address decoder 120 applies the verification voltage Vverify generated by the voltage generation circuit 150 to the selected word line WL2, and applies the pass voltage Vpass generated by the voltage generation circuit 150 to the other unselected word lines WL1 and WL3 to WLn. Multiple page buffers PB1 to PBm perform programming verification operations by sensing the current of bit lines BL1 to BLm. During the programming verification operation, multiple verification voltages V, corresponding to multiple programming states PV1 to PV7, can be applied sequentially. PV1 To V PV7And whenever multiple verification voltages V are applied PV1 To V PV7 Each of the multiple page buffers PB1 to PBm in the middle can sense the current of bit lines BL1 to BLm.

[0137] The following will refer to Figure 10 Step S940 is described in more detail.

[0138] In step S941, multiple page buffers PB1 to PBm precharge bit lines BL1 to BLm to a set level.

[0139] In step S942, the address decoder 120 applies a verification voltage (e.g., V) generated by the voltage generation circuit 150 to the selected word line WL2. PV1 It applies the pass voltage Vpass generated by the voltage generation circuit 150 to the other unselected word lines WL1 and WL3 to WLn.

[0140] In step S943, each of the plurality of page buffers PB1 to PBm can perform an evaluation operation on the potential level of the sensing node SO based on the amount of current in the corresponding bit line during a set evaluation period, according to the previously programmed data stored in the first latch.

[0141] In step S944, each of the multiple page buffers PB1 to PBm latches the verification data corresponding to the potential level of the sensing node SO into the second latch.

[0142] Subsequently, the next programming verification voltage (e.g., V) is used. PV2 Repeat steps S941 to S944 above.

[0143] As described above, according to embodiments of this disclosure, the evaluation period of multiple page buffers PB1 to PBm can be adjusted based on previously programmed data in a programming verification operation. When a previously programmed adjacent memory cell is programmed to a relatively high programming state during the programming operation of the selected memory cell, the selected memory cell can be programmed to have a threshold voltage higher than the target threshold voltage level based on the interference effects of adjacent memory cells. According to embodiments of this disclosure, when the previously programmed data corresponds to a relatively high programming state, by adjusting the evaluation period to be relatively short, it is possible to achieve the effect of reducing the verification voltage level in the programming verification operation. Therefore, the phenomenon that memory cells are programmed to a programming state higher than the target threshold voltage based on the interference effects of adjacent memory cells can be improved.

[0144] Figure 11 This is a flowchart illustrating the programming operation of a semiconductor memory according to another embodiment of the present disclosure.

[0145] Figure 12 This is an example Figure 11 The threshold voltage distribution diagram shows the threshold voltage distribution of memory cells in fuzzy programming and fine programming operations.

[0146] The following will refer to Figures 2 to 8 , Figure 11 and Figure 12 The programming operation of a semiconductor memory according to another embodiment of the present disclosure is described.

[0147] The programming operation of a semiconductor memory according to another embodiment of this disclosure may include fuzzy programming and fine programming. Fuzzy programming is the operation of programming memory cells included in a selected page to have a pre-threshold voltage level lower than a target threshold voltage level, while fine programming is the operation of programming fuzzily programmed memory cells included in a selected page to have a target threshold voltage level.

[0148] The fuzzy-fine programming operation can be performed in the following order: fuzzy programming operation on the first page, fuzzy programming operation on the second page adjacent to the first page, fine programming operation on the first page, fuzzy programming operation on the third page adjacent to the second page, and fine programming operation on the second page.

[0149] In another embodiment of this disclosure, fuzzy-fine programming operations on a first page corresponding to word line WL1 and a second page corresponding to word line WL2 will be described as an example, with the first and second pages being adjacent to each other.

[0150] In step S1110, fuzzy programming of the first page is performed. For example, the first latch unit 235 of each of the multiple page buffers PB1 to PBm sets the logic level of node QM_N to logic low (QM_N = 0). For example, in an initialization operation, the first latch unit 235 is initialized to make the logic level of node QN_N logic high. For example, when a reset signal MRST is applied at a logic high level while the sensing node SO is precharged to a logic high level, the first latch unit 235 is initialized to make node QM have a logic low level and node QM_N have a logic high level. Subsequently, the first latch unit 235 stores specific data, which may be data used to set the evaluation period to the second period Eval2. For example, the sensing node SO is controlled to have a logic high level based on the specific data, causing the NMOS transistor N16 to be turned on. Therefore, when a set signal MSET is applied at a logic high level, node QM_N is set to change from a logic high level to a logic low level.

[0151] The data to be stored in the first page is received and then stored in the second latch of the second latch unit 234 of each of the multiple page buffers PB1 to PBm. Based on the data stored in the second latch unit 234, each of the multiple page buffers PB1 to PBm can control a corresponding bit line among the bit lines BL1 to BLm to have a programmable enable voltage level or a programmable disable voltage level.

[0152] The programming voltage application operation is performed by applying a programming voltage Vpgm to the word line WL1 corresponding to the first page. The voltage generation circuit 150 generates the programming voltage Vpgm and the pass voltage Vpass under the control of the voltage generation circuit control signal VG_signals output from the control logic 140. The address decoder 120 applies the programming voltage Vpgm generated by the voltage generation circuit 150 to the selected word line WL1, and applies the pass voltage Vpass generated by the voltage generation circuit 150 to the other unselected word lines WL2 to WLn.

[0153] A programming verification operation is performed on the first page. Under the control of the voltage generation circuit control signal VG_signals output from the control logic 140, the voltage generation circuit 150 generates a verification voltage Vverify and a pass voltage Vpass. The address decoder 120 applies the verification voltage Vverify generated by the voltage generation circuit 150 to the selected word line WL1, and applies the pass voltage Vpass generated by the voltage generation circuit 150 to the other unselected word lines WL2 to WLn. Multiple page buffers PB1 to PBm perform the programming verification operation by sensing the current in bit lines BL1 to BLm. During the programming verification operation, multiple verification voltages V, corresponding to multiple programming states PV1 to PV7, can be applied sequentially. PV1 To V PV7 And whenever multiple verification voltages V are applied PV1 To V PV7 Each of the multiple page buffers PB1 to PBm can sense the current amount of bit lines BL1 to BLm. During the programming verification operation, each of the multiple page buffers PB1 to PBm performs an evaluation operation in the second evaluation period Eval2 based on specific data stored in the first latch. Therefore, the programming verification operation is performed with a voltage level V below the target threshold voltage level in the programming verification operation. PV1 To V PV7 Pre-threshold voltage level V PV1' To V PV7' The memory cells included on the first page are programmed to an erase state E and multiple programming states PV1 to PV7, and each of the multiple programming states PV1 to PV7 has a pre-threshold voltage level V equal to or higher than V. PV1' To V PV7' Threshold voltage distribution.

[0154] After the fuzzy programming operation on the first page is completed, the data stored in the second latch unit 234 can be moved to the additional latch unit for storage in the additional latch unit.

[0155] In step S1120, fuzzy programming is performed on the second page, which is adjacent to the first page. The fuzzy programming operation on the second page is similar to that on the first page, and therefore a detailed description will be omitted.

[0156] In step S1130, a fine-tuning operation is performed on the first page. For example, the first latch unit 235 of each of the plurality of page buffers PB1 to PBm sets the logic level of node QM_N to logic high (QM_N = 1). For example, in an initialization operation, the first latch unit 235 is initialized such that the logic level of node QM_N becomes logic high. For example, when a reset signal MRST is applied at a logic high level while the sensing node SO is pre-charged to a logic high level, the first latch unit 235 is initialized such that node QM has a logic low level and node QM_N has a logic high level.

[0157] Each of the multiple page buffers PB1 to PBm can store data to be stored in the first page, which is stored in the additional latch unit, in the second latch of the second latch unit 234. In another embodiment, each of the multiple page buffers PB1 to PBm can be accessed from an external source (e.g., control logic 140 or...). Figure 1 The controller 1200 shown receives new data to be stored in the first page and stores the newly received data in the second memory of the second latch unit 234. Each of the plurality of page buffers PB1 to PBm can control a corresponding bit line among the bit lines BL1 to BLm to have a programmable enable voltage level or a programmable disable voltage level based on the data stored in the second latch unit 234.

[0158] The programming voltage application operation is performed by applying a programming voltage Vpgm to the word line WL1 corresponding to the first page. The voltage generation circuit 150 generates the programming voltage Vpgm and the pass voltage Vpass under the control of the voltage generation circuit control signal VG_signals output from the control logic 140. The address decoder 120 applies the programming voltage Vpgm generated by the voltage generation circuit 150 to the selected word line WL1, and applies the pass voltage Vpass generated by the voltage generation circuit 150 to the other unselected word lines WL2 to WLn.

[0159] The first page undergoes a programming verification operation. Under the control of the voltage generation circuit control signal VG_signals output from the control logic 140, the voltage generation circuit 150 generates a verification voltage Vverify and a pass voltage Vpass. The address decoder 120 applies the verification voltage Vverify generated by the voltage generation circuit 150 to the selected word line WL1, and applies the pass voltage Vpass generated by the voltage generation circuit 150 to the other unselected word lines WL2 to WLn. Multiple page buffers PB1 to PBm perform the programming verification operation by sensing the current in bit lines BL1 to BLm. During the programming verification operation, multiple verification voltages V, corresponding to multiple programming states PV1 to PV7, can be applied sequentially. PV1 To V PV7 And whenever multiple verification voltages V are applied PV1 To V PV7 At each time, multiple page buffers PB1 to PBm can sense the current amount of bit lines BL1 to BLm. During the programming verification operation, based on the potential of the initialization node QM_N of the first latch, each of the multiple page buffers PB1 to PBm performs an evaluation operation during the first evaluation period Eval1. Therefore, a programming verification operation can be performed to achieve the target threshold voltage V during the programming verification operation. PV1 To V PV7 .

[0160] In the fine-tuning of the first page, the threshold voltage distribution of the memory cells included in the second page adjacent to the first page can be partially increased. However, the memory cells included in the second page are programmed to be below the target threshold voltage V. PV1 To V PV7 Pre-threshold voltage level V PV1' To V PV7' Therefore, it is possible to minimize the problem of excessive increase in threshold voltage distribution compared to the target threshold voltage level.

[0161] In step S1140, fine-tuning is performed on the second page. The fine-tuning of the second page is performed similarly to the fine-tuning of the first page described above, and therefore a detailed description will be omitted.

[0162] As described above, in a programming operation according to another embodiment of this disclosure, multiple page buffers perform an evaluation operation during a second evaluation period in a fuzzy programming operation, enabling programming operations to be performed at a pre-threshold voltage level below the target threshold voltage level. Additionally, multiple page buffers perform an evaluation operation during a first evaluation period in a fine programming operation, enabling programming operations to be performed at the target threshold voltage level.

[0163] Figure 13This is a flowchart illustrating the programming operation of a semiconductor memory according to yet another embodiment of the present disclosure.

[0164] The following will refer to Figures 2 to 8 and Figure 13 The programming operation of a semiconductor memory according to yet another embodiment of the present disclosure is described.

[0165] In a programming operation of a semiconductor memory according to another embodiment of the present disclosure, a pre-verification operation is performed on the memory cells included in the selected page to have a pre-threshold voltage level, and the page buffer corresponding to the memory cell determined to be passed based on the result of the pre-verification operation increases the potential level of the bit line by a specific level to the programming allow voltage level in a subsequent programming voltage application operation.

[0166] In step S1310, multiple page buffers PB1 to PBm receive data to be stored in the selected page, and then store the received data in the second latch of the second latch unit 234.

[0167] Additionally, the first latch unit 235 of each of the multiple page buffers PB1 to PBm sets the logic level of node QM_N to logic low (QM_N = 0). For example, during an initialization operation, the first latch unit 235 is initialized to make the logic level of node QN_N logic high. For example, when a reset signal MRST is applied at a logic high level while the sensing node SO is pre-charged to a logic high level, the first latch unit 235 is initialized to make node QM logic low and node QM_N logic high. Subsequently, the first latch unit 235 stores specific data, which may be data used to set the evaluation period to the second period Eval2. For example, the sensing node SO is controlled to have a logic high level based on the specific data, causing the NMOS transistor N16 to be turned on. Therefore, when a set signal MSET is applied at a logic high level, node QM_N is set to change from logic high to logic low.

[0168] In step S1320, each of the plurality of page buffers PB1 to PBm can control a corresponding bit line among the bit lines BL1 to BLm to have a programming enable voltage level or a programming disable voltage level based on the data stored in the second latch unit 234. For example, the programming enable voltage level can be the level of the ground power supply VSS, and the programming disable voltage level can be the level of the power supply voltage VDD.

[0169] In step S1330, a programming voltage Vpgm is applied to the selected word line. For example, the voltage generation circuit 150 generates the programming voltage Vpgm and the pass voltage Vpass under the control of the voltage generation circuit control signal VG_signals output from the control logic 140. The address decoder 120 applies the programming voltage Vpgm generated by the voltage generation circuit 150 to the selected word line WL1, and applies the pass voltage Vpass generated by the voltage generation circuit 150 to the other unselected word lines WL2 to WLn.

[0170] In step S1340, a pre-verification operation is performed on the selected page. The pre-verification operation is performed at a pre-threshold voltage level lower than the target threshold voltage level. For example, the voltage generation circuit 150 generates a programming voltage Vpgm and a pass voltage Vpass under the control of the voltage generation circuit control signal VG_signals output from the control logic 140. The address decoder 120 applies the programming voltage Vpgm generated by the voltage generation circuit 150 to the selected word line WL1, and applies the pass voltage Vpass generated by the voltage generation circuit 150 to the other unselected word lines WL2 to WLn. Multiple page buffers PB1 to PBm perform a programming verification operation by sensing the current of bit lines BL1 to BLm. During the programming verification operation, multiple verification voltages V corresponding to multiple programming states PV1 to PV7 can be applied sequentially. PV1 To V PV7 And whenever multiple verification voltages V are applied PV1 To V PV7 During each of the multiple page buffers PB1 to PBm, the current in bit lines BL1 to BLm can be sensed. In the programming verification operation, each of the multiple page buffers PB1 to PBm performs an evaluation operation in the second evaluation period Eval2 based on specific data stored in the first latch. Therefore, in the pre-verification operation, a voltage level higher than the target threshold voltage level V can be achieved. PV1 To V PV7 A low pre-threshold voltage level is used to perform the programming verification operation.

[0171] In step S1350, a primary verification operation is performed on the selected page. The primary verification operation is performed at a target threshold voltage level. For example, whenever multiple verification voltages V are applied... PV1 To V PV7At each time, multiple page buffers PB1 to PBm can sense the current amount on bit lines BL1 to BLm. During the programming verification operation, each of the multiple page buffers PB1 to PBm performs an evaluation operation during the first evaluation period Eval1. For example, control logic 140 controls each of the multiple page buffers PB1 to PBm to perform an evaluation operation during the first evaluation period Eval1 by applying a second transfer signal TRANM_N with a logic high level during the main verification operation. Therefore, the target threshold voltage level V can be used during the main verification operation. PV1 To V PV7 Perform programming verification.

[0172] The page buffer corresponding to the memory cell determined to be passed based on the pre-programming operation applies a voltage higher than the programming enable voltage to the corresponding bit line, and the page buffer corresponding to the memory cell determined to be passed based on the main programming operation applies a programming disable voltage to the corresponding bit line. Then, steps S1330 to S1350 are repeated.

[0173] As described above, in the programming operation of a semiconductor memory according to another embodiment of the present disclosure, multiple page buffers can perform pre-verification operations by setting the evaluation operation to a second evaluation period, and can perform main verification operations by setting the evaluation operation to a first evaluation period.

[0174] Figure 14 This is a flowchart illustrating the programming operation of a semiconductor memory according to yet another embodiment of the present disclosure.

[0175] Figure 15 The waveforms of the programming voltage and verification voltage for a multi-sensor operation illustrating the programming voltage application operation and the programming verification operation are shown.

[0176] The following will refer to Figures 2 to 8 , Figure 14 and Figure 15 The programming operation of a semiconductor memory according to yet another embodiment of the present disclosure is described.

[0177] As an example, a method for verifying two adjacent programming states by using a verification voltage in a programming operation of a semiconductor memory, according to another embodiment of the present disclosure, will be described.

[0178] In step S1410, the data to be programmed into the selected page is stored in the second latch of the second latch unit 234 of the plurality of page buffers PB1 to PBm. Based on the data stored in the second latch unit 234, each of the plurality of page buffers PB1 to PBm can control a corresponding bit line among the bit lines BL1 to BLm to have a programming enable voltage level or a programming disable voltage level.

[0179] In step S1420, the first latch unit 235 of each of the plurality of page buffers PB1 to PBm stores specific data in the first latch, causing the logic level of node QM_N to become logic low. For example, in an initialization operation, the first latch unit 235 is initialized to cause the logic level of node QN_N to become logic high. For example, when a reset signal MRST is applied at a logic high level while the sensing node SO is precharged to a logic high level, the first latch unit 235 is initialized to cause node QM to have a logic low level and node QM_N to have a logic high level. Subsequently, the first latch unit 235 stores specific data, which may be data used to set the evaluation period to the second period Eval2. For example, based on the specific data, the sensing node SO is controlled to have a logic high level, causing the NMOS transistor N16 to be turned on. Therefore, when the set signal MSET is applied at a logic high level, node QM_N is set to change from a logic high level to a logic low level.

[0180] In step S1430, a programming voltage Vpgm is applied to the word line WL corresponding to the selected page. For example, the voltage generation circuit 150 generates the programming voltage Vpgm and the pass voltage Vpass under the control of the voltage generation circuit control signal VG_signals output from the control logic 140. The address decoder 120 applies the programming voltage Vpgm generated by the voltage generation circuit 150 to the selected word line WL, and applies the pass voltage Vpass generated by the voltage generation circuit 150 to the other unselected word lines.

[0181] In step S1440, a verification operation for the two programming states is performed using a verification voltage.

[0182] In the programming verification operation, verification operations can be performed sequentially on multiple programming states PV1 to PV7.

[0183] First, a verification operation is performed on the programming state PV1. Under the control of the voltage generation circuit control signal VG_signals output from the control logic 140, the voltage generation circuit 150 generates a verification voltage V corresponding to the programming state PV1. PV1 And through voltage Vpass. The address decoder 120 applies the verification voltage V generated by the voltage generation circuit 150 to the selected word line. PV1 And apply the pass voltage Vpass generated by the voltage generation circuit 150 to other unselected word lines.

[0184] Each of the multiple page buffers PB1 to PBm performs an evaluation operation during the first evaluation period Eval1. For example, control logic 140 controls each of the multiple page buffers PB1 to PBm to perform an evaluation operation during the first evaluation period Eval1 by applying a second transmission signal TRANM_N with a logic high level during the main verification operation. Therefore, in the verification operation of the programming state PV1, the verification voltage V can be used. PV1 To perform the verification operation.

[0185] Verification operations are performed on the adjacent programming states PV2 and PV3. Under the control of the voltage generation circuit control signal VG_signals output from the control logic 140, the voltage generation circuit 150 generates the verification voltage V corresponding to the programming state PV3. PV3 And through voltage Vpass. The address decoder 120 applies the verification voltage V generated by the voltage generation circuit 150 to the selected word line. PV3 And apply the pass voltage Vpass generated by the voltage generation circuit 150 to other unselected word lines.

[0186] Each of the multiple page buffers PB1 to PBm performs an evaluation operation during the second evaluation period Eval2. Based on specific data stored in the first latch, each of the multiple page buffers PB1 to PBm performs an evaluation operation during the second evaluation period Eval2. Therefore, a verification voltage V can be applied to the word line WL of the memory cell. PV3 The verification operation for programming state PV2 is performed under the specified state. Subsequently, each of the multiple page buffers PB1 to PBm can perform the verification operation for programming state PV3 by performing an evaluation operation during the first evaluation period Eval1. Therefore, it is possible to perform verification operations for at least two adjacent programming states using a single verification voltage.

[0187] Subsequently, the verification operation methods described above can be used to perform verification operations on programming states PV4 and PV5, as well as programming states PV6 and PV7.

[0188] After completing the verification operation on the final programming state PV7, the above-mentioned programming application operation and programming verification operation can be re-executed on the memory cell that was determined to have failed to program.

[0189] To perform verification operations on two programmed states using a single verification voltage, at least two latch units are used to latch the verification data. For example, different latch units are used to latch the verification data corresponding to each of the programmed states PV2 and PV3. Verification data for the verification operation on programmed state PV2 in the second evaluation period Eval2 can be latched using the first latch unit 235, and verification data for the verification operation on programmed state PV3 in the first evaluation period Eval1 can be latched using the second latch unit 234.

[0190] As described above, according to another embodiment of this disclosure, verification operations for adjacent programming states can be performed using a single verification voltage. Therefore, the operation of changing the verification voltage is skipped, thereby reducing or minimizing the time required to perform the programming operation.

[0191] Figure 16 This is a circuit diagram illustrating a page buffer according to another embodiment of the present disclosure.

[0192] Figure 16 The bit line controller 231, bit line discharge unit 232, sense node precharge unit 233, and second latch unit 234 shown in another embodiment of the page buffer 131B are... Figure 7 The corresponding components of the page buffer 131A shown are constructed in the same manner.

[0193] In the following text, for ease of description, the terms "and" will be omitted. Figure 7 The description of the same bit line controller 231, bit line discharge unit 232, sense node precharge unit 233, and second latch unit 234 as the page buffer 131A in the description will be detailed. Figure 7 The page buffer 131A shown has different components: a first latch unit 235 and a third latch unit 236.

[0194] The first latch unit 235 may include multiple NMOS transistors N12 to N16 and inverters IV3 and IV4.

[0195] Inverters IV3 and IV4 can be connected in parallel in reverse between node QM and node QM_N to form a latch.

[0196] NMOS transistors N12 and NMOS transistor N13 are connected in series between the sensing node SO and the ground power supply VSS. NMOS transistor N12 turns on in response to the first transmission signal TRANM, and NMOS transistor N13 turns on or off according to the potential of node QM.

[0197] NMOS transistor N14 is connected between node QM and node ND4. NMOS transistor N14 is turned on or off in response to the reset signal MRST. NMOS transistor N15 is connected between node QM_N and node ND4 to electrically connect nodes QM_N and ND4 to each other in response to the set signal MSET. NMOS transistor N16 is connected between node ND4 and the ground supply VSS to connect nodes ND4 and the ground supply VSS to each other according to the potential of the sensed node SO.

[0198] The first latch unit 235 can be related to the reference. Figure 7 The components corresponding to the described additional latch unit. For example, the first latch unit 235 can receive programming data received from an external source and temporarily store the received programming data. The first latch unit 235 can latch verification data or read data during programming verification or read operations.

[0199] The third latch unit 236 may include multiple NMOS transistors N21 to N24, a PMOS transistor P6, and inverters IV5 and IV6.

[0200] Inverters IV5 and IV6 can be connected in parallel in reverse between nodes QX and QX_N to form a latch.

[0201] NMOS transistor N21 and PMOS transistor P6 are connected between sensing node SO and power supply voltage VDD. NMOS transistor N21 turns on in response to the third transmission signal TRANX, and PMOS transistor P6 turns on or off according to the potential of node QX.

[0202] NMOS transistor N22 is connected between node QX and node ND5. NMOS transistor N22 turns on or off in response to the reset signal XRST. NMOS transistor N23 is connected between node QX_N and node ND5 to electrically connect nodes QX_N and ND5 to each other in response to the set signal XSET. NMOS transistor N24 is connected between node ND5 and the ground power supply VSS, and connects node ND5 and the ground power supply VSS to each other according to the potential of the sensed node SO.

[0203] The third latch unit 236 can be related to the reference. Figure 7The components corresponding to the first latch unit described. For example, the third latch unit 236 can store previously programmed data that was programmed in a programming operation immediately preceding the currently executing programming operation. For example, the third latch unit 236 can store previously programmed data that has been programmed in a page adjacent to the selected page and has already been fully programmed. The page buffer 131B can send to the third latch unit 236 the data to be programmed that was received from outside and temporarily stored in the programming operation immediately preceding the current programming operation after the programming operation immediately preceding the current programming operation is completed, and then store the data, or during the current programming operation from... Figure 2 The control logic 140 shown receives previously programmed data and then stores it. For example, when the previously programmed data is data with a relatively high programming state, the third latch unit 236 can set node QX to a logic low level to store the previously programmed data. When the previously programmed data is data with a relatively low programming state, the third latch unit 236 can set node QX to a logic high level. Additionally, the third latch unit 236 can receive specific data from the control logic 140 and store that specific data. For example, the third latch unit 236 can set node QX to a logic low level to store that specific data.

[0204] When node QX is set to logic low, the third latch unit 236 can reduce the evaluation period. For example, the bit line controller 231 can adjust the evaluation period, which is the period for performing the evaluation operation, based on the data stored in the third latch unit 236. The bit line controller 231 can define the period from the time when the precharge signal SA_PRECH_N changes to logic high to the time when the transmission signal TRANSO changes to logic low as the first evaluation period. The third latch unit 236 applies the power supply voltage VDD to the sensing node SO based on the third transmission signal TRANX, which is applied at logic low before the precharge signal SA_PRECH_N changes to logic high, and the potential of node QX, which is at logic low. Therefore, although the precharge signal SA_PRECH_N changes to logic high, the power supply voltage VDD is continuously applied to the sensing node SO, so that no evaluation operation is performed. Subsequently, the bit line controller 231 can define the period from the time when the third transmission signal TRANX changes to logic high to the time when the transmission signal TRANSO changes to logic low as the second evaluation period. The second assessment period can be set shorter than the first assessment period.

[0205] As described above, the page buffer 131B according to this disclosure can set the evaluation period in a read operation or a programming verification operation to a first evaluation period or a second evaluation period shorter than the first evaluation period based on the data stored in the third latch unit 236.

[0206] Figure 17 This is a circuit diagram illustrating a page buffer according to yet another embodiment of the present disclosure.

[0207] Figure 17 The bit line discharge unit 232, the sensing node precharge unit 233, the second latch unit 234, and the first latch unit 235 shown in another embodiment of the page buffer 131C are... Figure 16 The corresponding components of the page buffer 131B shown are constructed in the same manner.

[0208] In the following text, for ease of description, the terms "and" will be omitted. Figure 16 The page buffer 131B in the description includes the same bit line discharge unit 232, sensing node precharge unit 233, second latch unit 234, and first latch unit 235, and will be described in detail with... Figure 16 The page buffer 131B shown consists of different bit line controller 231' and third latch unit 236'.

[0209] Apart from Figure 16 In addition to the configuration of the bit line controller 231 shown, the bit line controller 231' may also include an evaluation time period adjustment circuit 231_A.

[0210] During data sensing operations in read or programming verification operations, bit line controller 231 controls the potential level of sensing node SO based on the amount of current (i.e., cell current) in bit line BL1, which changes according to the programming state or threshold voltage of the memory cell connected to bit line BL1. Additionally, bit line controller 231' can adjust the length of the evaluation period of page buffer 131C in response to the potential of node QX_N of the third latch cell 236' and the fourth transfer signal TRANX_N, by applying a power supply voltage VDD to the common node CSO or by interrupting the application of the power supply voltage VDD to the common node CSO.

[0211] Bit line controller 231' may include multiple NMOS transistors N1 and N3 to N6, multiple PMOS transistors P1 and P2, and evaluation period adjustment circuit 231_A.

[0212] NMOS transistor N1 is connected between bit line BL1 and node ND1, and electrically connects bit line BL1 and node ND1 to each other in response to the page buffer select signal PBSEL.

[0213] NMOS transistor N3 is connected between node ND1 and common node CSO, and electrically connects node ND1 and common node CSO in response to the page buffer sensing signal PB_SENSE.

[0214] PMOS transistors P1 and P2 are connected in series between the power supply voltage VDD and the sensing node SO. PMOS transistors P1 and P2 are turned on in response to node QS of sub-latch cell 234 and the precharge signal SA_PRECH_N.

[0215] NMOS transistor N4 is connected between the common node CSO and the node located between PMOS transistors P1 and PMOS transistor P2, and in response to the control signal SA_CSOC, it supplies the power supply voltage VDD provided by PMOS transistor P1 to the common node CSO.

[0216] The NMOS transistor N5 is connected between the sensing node SO and the common node CSO, and electrically connects the sensing node SO and the common node CSO to each other in response to the transmission signal TRANSO.

[0217] NMOS transistor N6 is connected between common node CSO and node ND2 of sub-latch unit 234, and electrically connects common node CSO and node ND2 in response to discharge signal SA_DISCH.

[0218] The evaluation period adjustment circuit 231_A may include PMOS transistors P7 and P8 connected in series between the power supply voltage VDD and the NMOS transistor N4. In another embodiment, PMOS transistors P7 and P8 may be connected in series between the power supply voltage VDD and the common node CSO. PMOS transistor P7 turns on or off in response to the fourth transmission signal TRANX_N, while PMOS transistor P8 turns on or off in response to the potential of QX_N of the third latch cell 236', to apply the power supply voltage VDD to the common node CSO.

[0219] During the evaluation operation, the evaluation period adjustment circuit 231_A can respond to the potential of QX_N of the third latch unit 236′ and the fourth transmission signal TRANX_N to set the evaluation operation to the first evaluation period or the evaluation operation to the second evaluation period.

[0220] The third latch unit 236' may include multiple NMOS transistors N21 to N25 and inverters IV5 and IV6.

[0221] Inverters IV5 and IV6 can be connected in parallel in reverse between node QX and node QX_N to form a latch.

[0222] NMOS transistors N21 and NMOS transistor N25 are connected in series between the sensing node SO and the ground power supply VSS. NMOS transistor N21 turns on in response to the third transmission signal TRANX, and NMOS transistor N25 turns on or off depending on the potential of node QX.

[0223] NMOS transistor N22 is connected between node QX and node ND5. NMOS transistor N22 turns on or off in response to the reset signal XRST. NMOS transistor N23 is connected between node QX_N and node ND5 to electrically connect nodes QX_N and ND5 to each other in response to the set signal XSET. NMOS transistor N24 is connected between node ND5 and the ground power supply VSS, and connects node ND5 and the ground power supply VSS according to the potential of the sensed node SO.

[0224] The third latch unit 236' can be related to the reference. Figure 16 The components corresponding to the described third latch unit. For example, the third latch unit 236' can store previously programmed data that was programmed in a programming operation immediately preceding the current programming operation. For example, the third latch unit 236' can store previously programmed data that has been programmed in a page adjacent to the selected page and has already been fully programmed. The page buffer 131C can send the data to be programmed, which was received from an external source and temporarily stored in the programming operation immediately preceding the current programming operation, to the third latch unit 236' after the programming operation immediately preceding the current programming operation is completed, and then store the data, or during the current programming operation... Figure 2 The control logic 140 shown receives previously programmed data and then stores it. For example, when the previously programmed data is data with a relatively high programming state, the third latch unit 236' can set node QX_N to a logic low level to store the previously programmed data. When the previously programmed data is data with a relatively low programming state, the third latch unit 236' can set node QX_N to a logic high level. Additionally, the third latch unit 236' can receive specific data from the control logic 140 and store that specific data. For example, the third latch unit 236' can set node QX_N to a logic low level to store that specific data.

[0225] When node QX is set to logic low, the third latch unit 236' can reduce the evaluation period. For example, the bit line controller 231' can adjust the evaluation period, which is the period for performing the evaluation operation, based on the data stored in the third latch unit 236'. The bit line controller 231' can define the period from the time when the precharge signal SA_PRECH_N changes to logic high to the time when the transmission signal TRANSO changes to logic low as the first evaluation period. The third latch unit 236' applies the power supply voltage VDD to the sensing node SO based on the third transmission signal TRANX, which is applied at logic low before the precharge signal SA_PRECH_N changes to logic high, and the potential of node QX, which is at logic low. Therefore, although the precharge signal SA_PRECH_N changes to logic high, the power supply voltage VDD is continuously applied to the sensing node SO, so that no evaluation operation is performed. Subsequently, the bit line controller 231' can define the period from the time when the third transmission signal TRANX changes to logic high to the time when the transmission signal TRANSO changes to logic low as the second evaluation period. The second assessment period can be set shorter than the first assessment period.

[0226] As described above, the page buffer 131C according to this disclosure can set the evaluation period in a read operation or a programming verification operation to a first evaluation period or a second evaluation period shorter than the first evaluation period based on the data stored in the third latch unit 236'.

[0227] Figure 18 This is a diagram illustrating another implementation of the memory system.

[0228] Reference Figure 18 The memory system 30000 can be implemented as a cellular phone, smartphone, tablet PC, personal digital assistant (PDA), or wireless communication device. The memory system 30000 may include a memory device 1100 and a memory controller 1200 capable of controlling the operation of the memory device 1100. The memory controller 1200, under the control of the processor 3100, can control the data access operations of the memory device 1100, such as programming operations, erasing operations, and reading operations.

[0229] Under the control of the memory controller 1200, the data programmed in the memory device 1100 can be output through the display 3200.

[0230] The radio transceiver 3300 can transmit / receive radio signals via the antenna ANT. For example, the radio transceiver 3300 can convert the radio signals received via the antenna ANT into signals that can be processed by the processor 3100. Therefore, the processor 3100 can process the signals output from the radio transceiver 3300 and send the processed signals to the memory controller 1200 or the display 3200. The memory controller 1200 can send the signals processed by the processor 3100 to the memory device 1100. Alternatively, the radio transceiver 3300 can convert the signals output from the processor 3100 into radio signals and output the converted radio signals to an external device via the antenna ANT. The input device 3400 is a device capable of inputting control signals for controlling the operation of the processor 3100 or data to be processed by the processor 3100, and can be implemented as a pointing device such as a touchpad or computer mouse, a keypad, or a keyboard. The processor 3100 can control the operation of the display 3200, so that data output from the memory controller 1200, data output from the radio transceiver 3300, or data output from the input device 3400 can be output through the display 3200.

[0231] In some embodiments, the memory controller 1200, which controls the operation of the memory device 1100, can be implemented as part of the processor 3100 or as a separate chip from the processor 3100. Alternatively, the memory controller 1200 can be... Figure 1 The controller 1200 shown is used to implement this.

[0232] Figure 19 This is a diagram illustrating another implementation of the memory system.

[0233] Reference Figure 19 The memory system 40000 can be implemented as a personal computer (PC), tablet PC, netbook, e-reader, personal digital assistant (PDA), portable multimedia player (PMP), MP3 player or MP4 player.

[0234] The memory system 40000 may include a memory device 1100 and a memory controller 1200 capable of controlling the data processing operations of the memory device 1100.

[0235] The processor 4100 can output data stored in the memory device 1100 via the display 4300 based on data input through the input device 4200. For example, the input device 4200 can be implemented as a pointing device such as a touchpad or computer mouse, a keypad, or a keyboard.

[0236] The processor 4100 can control the overall operation of the memory system 40000 and the operation of the memory controller 1200. In some embodiments, the memory controller 1200, which controls the operation of the memory device 1100, can be implemented as part of the processor 4100 or as a separate chip from the processor 4100. Alternatively, the memory controller 1200 can be... Figure 1 The controller 1200 shown is used to implement this.

[0237] Figure 20 This is a diagram illustrating another implementation of the memory system.

[0238] Reference Figure 20 The memory system 50000 can be implemented as an image processing device, such as a digital camera, a mobile terminal with a digital camera, a smartphone with a digital camera, or a tablet PC with a digital camera.

[0239] The memory system 50000 may include a memory device 1100 and a memory controller 1200 capable of controlling data processing operations (e.g., programming operations, erasing operations, or reading operations) of the memory device 1100.

[0240] The image sensor 5200 of the memory system 50000 can convert optical images into digital signals, and the converted digital signals can be sent to the processor 5100 or the memory controller 1200. Under the control of the processor 5100, the converted digital signals can be output through the display 5300 or stored in the memory device 1100 through the memory controller 1200. Furthermore, under the control of the processor 5100 or the memory controller 1200, data stored in the memory device 1100 can be output through the display 5300.

[0241] In some embodiments, the memory controller 1200, which controls the operation of the memory device 1100, can be implemented as part of the processor 5100, or as a separate chip from the processor 5100. Alternatively, the memory controller 1200 can be... Figure 1 The controller shown is used to implement this.

[0242] Figure 21 This is a diagram illustrating another implementation of the memory system.

[0243] Reference Figure 21 The memory system 70000 can be implemented as a memory card or a smart card. The memory system 70000 may include a memory device 1100, a memory controller 1200, and a card interface 7100.

[0244] The memory controller 1200 can control the data exchanged between the memory device 1100 and the card interface 7100. In some embodiments, the card interface 7100 may be a Secure Digital (SD) card interface or a Multimedia Card (MMC) interface, but this disclosure is not limited thereto. Additionally, the memory controller 1200 can use... Figure 1 The controller 1200 shown is used to implement this.

[0245] Card interface 7100 can interface with the data exchanged between host 60000 and memory controller 1200 according to the protocol of host 60000. In some embodiments, card interface 7100 can support Universal Serial Bus (USB) protocol and chip-to-chip (IC) USB protocol. Card interface 7100 can refer to hardware capable of supporting the protocol used by host 60000, software embedded in the hardware, or signal transmission scheme.

[0246] When the memory system 70000 is connected to the host interface 6200 of a host 60000, such as a PC, tablet PC, digital camera, digital audio player, cellular phone, console video game hardware, or digital set-top box, the host interface 6200 can perform data communication with the memory device 1100 through the card interface 7100 and the memory controller 1200 under the control of the microprocessor 6100.

[0247] According to this disclosure, the evaluation period in the programming verification operation of the selected page can be set based on the data already programmed in the page adjacent to the selected page. Therefore, the threshold voltage distribution can be improved by adjusting the verification level of the memory cells included in the selected page, and multiple programming states can be verified while a single verification voltage is applied. Thus, the time required to perform the programming operation can be reduced.

[0248] While this disclosure has been shown and described with reference to certain embodiments thereof, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit and scope of this disclosure as defined by the appended claims and their equivalents. Therefore, the scope of this disclosure should not be limited to the described embodiments, but should be determined not only by the appended claims but also by their equivalents.

[0249] In the above embodiments, all steps may be selectively performed and / or some steps may be omitted. In each embodiment, the steps are not necessarily performed in the described order and may be rearranged. The embodiments disclosed in this specification and drawings are merely examples to facilitate understanding of this disclosure, and this disclosure is not limited thereto. That is, it will be apparent to those skilled in the art that various modifications can be made based on the technical scope of this disclosure.

[0250] Furthermore, embodiments of this disclosure have been described in the accompanying drawings and specification. While specific terminology is used herein, it is for the purpose of explaining embodiments of this disclosure only. Therefore, this disclosure is not limited to the described embodiments, and many variations are possible within the spirit and scope of this disclosure. Those skilled in the art will understand that various modifications can be made beyond the embodiments disclosed herein, based on the technical scope of this disclosure.

[0251] Cross-references to related applications

[0252] This application claims priority to Korean Patent Application No. 10-2021-0045960, filed with the Korean Intellectual Property Office on April 8, 2021, the entire disclosure of which is incorporated herein by reference.

Claims

1. A page buffer, the page buffer comprising: A bitline controller is connected between a bitline and a sensing node, and the bitline controller is capable of adjusting the potential level of the sensing node based on the cell current of the bitline by performing an evaluation operation; A first latch unit is connected to the sensing node. The first latch unit is capable of adjusting the operation period of the evaluation operation and includes a latch connected between the first node and the second node capable of latching data. as well as The second latch unit latches the verification data based on the potential level of the sensing node. The bitline controller is capable of performing the evaluation operation based on the potential level of the first node during the evaluation operation, either during a first evaluation period or a second evaluation period shorter than the first evaluation period.

2. The page buffer according to claim 1, wherein, The first latch unit can adjust the operation period of the evaluation operation by applying a power supply voltage to the sensing node or interrupting the application of the power supply voltage to the sensing node during the evaluation operation.

3. The page buffer according to claim 1, wherein, The first latch unit further includes: A first transistor and a second transistor are connected in series between the power supply voltage and the sensing node, and The first transistor is capable of turning on or off in response to a transmission signal, and the second transistor is capable of turning on or off in response to the potential of the first node.

4. The page buffer according to claim 3, wherein, When the first node is controlled to have a logic low level as the data is latched into the latch, the first latch unit can set the operation period of the evaluation operation as a first evaluation period by applying the power supply voltage to the sensing node during the evaluation operation.

5. A page buffer, the page buffer comprising: A bitline controller is connected between a bitline and a sensing node, and the bitline controller is capable of adjusting the potential level of the sensing node based on the cell current of the bitline by performing an evaluation operation; A first latch unit, connected to the sensing node, is capable of latching specific data for adjusting the operation period of the evaluation operation; as well as The second latch unit latches the verification data based on the potential level of the sensing node. The bitline controller can adjust the operation period of the evaluation operation based on the specific data latched by the first latch unit. The bitline controller is capable of performing the evaluation operation based on the specific data during a first evaluation period or a second evaluation period shorter than the first evaluation period.

6. The page buffer according to claim 5, wherein, The first latch unit includes a latch connected between the first node and the second node, which is capable of latching the specific data.

7. The page buffer according to claim 6, wherein, The bitline controller is capable of electrically connecting the bitline and the common node to each other during the evaluation operation, and electrically connecting the common node and the sensing node.

8. The page buffer according to claim 6, wherein, The bitline controller includes an evaluation time period adjustment circuit that applies a power supply voltage to the common node based on the potential level of the first node.

9. A semiconductor memory, the semiconductor memory comprising: A storage block, which comprises multiple pages; as well as The read / write circuitry includes multiple page buffers connected to the bit lines of the memory block. The multiple page buffers can store previously programmed data or specific data of pages programmed in the immediate preceding programming operation, and adjust the evaluation period in the programming verification operation of the currently selected page based on the previously programmed data or the specific data. Each of the plurality of page buffers includes a first latch unit connected to the sensing node, the first latch unit being capable of storing the previously programmed data or the specific data, and The first latch unit can set the operation period of the evaluation operation to a first evaluation period or a second evaluation period that is shorter than the first evaluation period.

10. The semiconductor memory according to claim 9, wherein, Each of the plurality of page buffers also includes: A bitline controller, connected between any of the bitlines and a sensing node, is capable of adjusting the potential level of the sensing node based on the cell current of the bitline by performing an evaluation operation; and The second latch unit latches the verification data based on the potential level of the sensing node.

11. The semiconductor memory according to claim 10, wherein, The first latch unit can adjust the evaluation period by applying a power supply voltage to the sensing node during the evaluation operation or interrupting the application of the power supply voltage to the sensing node.

12. The semiconductor memory according to claim 10, wherein, The first latch unit includes: A latch, connected between a first node and a second node, capable of latching the previously programmed data or the specific data; and A first transistor and a second transistor are connected in series between the power supply voltage and the sensing node, and The first transistor is capable of turning on or off in response to a transmission signal, and the second transistor is capable of turning on or off in response to the potential of the first node.

13. The semiconductor memory according to claim 12, wherein, When the first node is controlled to have a logic low level as the previously programmed data or the specific data is latched by the latch, the first latch unit can set the operation period of the evaluation operation to the second evaluation period by applying the power supply voltage to the sensing node during the evaluation operation.

14. A method for operating a semiconductor memory, the method comprising the steps of: The first latch unit of the page buffer stores previously programmed data or specific data stored in a previous page, which is adjacent to the selected page among a plurality of pages and has been programmed in the immediate previous programming operation; The data to be programmed into the selected page is stored in the second latch unit of the page buffer; The potential level of the bit line connected to the selected page is adjusted based on the data stored in the second latch unit, and then the programming voltage application operation is performed; as well as An evaluation operation is performed based on the current quantity of the bit line to adjust the potential level of the sensing node of the page buffer, and then a programming verification operation is performed to latch the verification data corresponding to the potential level of the sensing node. The evaluation operation is performed during an evaluation period that is set to a first evaluation period or a second evaluation period that is shorter than the first evaluation period, based on the previously programmed data or the specific data stored in the first latch unit.

15. The method according to claim 14, wherein, In the evaluation operation, the first latch unit sets the evaluation period to the second evaluation period by applying a power supply voltage to the sensing node based on the previously programmed data or the specific data.

16. The method of claim 14, wherein, The first latch unit sets the evaluation period to the second evaluation period when the previous programming data corresponds to a programming state with a relatively high threshold voltage distribution, and sets the evaluation period to the first evaluation period when the previous programming data corresponds to a programming state with a relatively low threshold voltage distribution.

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