Semiconductor device and readout method

Abstract

The present application provides a semiconductor device and a readout method, which can achieve high-speed readout. The NAND-type flash memory of the present application includes a bit line selection circuit for selecting an even bit line or an odd bit line, and a page buffer / readout circuit connected to the bit line selection circuit. The readout method of the flash memory includes: a step (step #1) of pre-charging a selected bit line by a virtual power source (VIRPWR) connected to the bit line selection circuit; and a step (step #1_2) of initializing a latch circuit (L1) by a voltage supply node (V1) in parallel with the pre-charging of the selected bit line, and a step (step #1_3) of initializing a page buffer / readout circuit (170) by the voltage supply node (V1).

Description

Technical Field

[0001] This invention relates to a semiconductor device including NAND flash memory, and more particularly to a method for reading flash memory. Background Technology

[0002] NAND flash memory is equipped with a read function (burst read function) that reads multiple pages in response to external commands. The page buffer / read circuit includes, for example, two latches, which can output the data held in the other latch while holding the data read from the array in one latch during a read operation. Summary of the Invention

[0003] Figure 1 This is a circuit diagram showing the structure of a page buffer circuit and a bit line select circuit connected thereto in a NAND flash memory. Here, a page buffer / read circuit 10 shared by even-numbered bit lines GBLe and odd-numbered bit lines GBLo is shown. For convenience, the transistors are represented by the signals applied to their gates.

[0004] The page buffer / read circuit 10 includes two latches L1 and L2. Transmission transistors TR1 and TR2 are connected between latches L1 and L2, enabling bidirectional data transmission between them. Node SLR1 of latch L1 is connected to the shared S / D converter of transistors BLCD1 and DTG, while node SLR2 of latch L2 is connected to transistor BLCD2. During program verification, transistor DTG selectively charges node SLR1 with the voltage VDD from voltage supply node V2, or selectively discharges node SLR1 to ground (GND). Furthermore, latch L2 is connected to the input / output circuit via data lines DL (not shown) and data line / DL (not shown).

[0005] Transistors VG and REG are connected in series between the voltage supply node V2 and the readout node SNS. The gate of transistor VG is connected to the S / D converter of transistor DTG. Voltage supply node V1 is connected to the readout node SNS via transistor BLPRE. Voltage supply node V1 supplies voltage VDD during bit line pre-charging and GND during latch L1 reset. Transistors BLCN and BLCLAMP are connected in series between the readout node SNS and node BLS.

[0006] Bit line selection circuit 20 includes transistor BLSe for selecting even-numbered bit lines GBLe, transistor BLSo for selecting odd-numbered bit lines GBLo, transistor YBLe for connecting the virtual power supply VIRPWR to even-numbered bit lines GBLe, and transistor YBLo for connecting the virtual power supply VIRPWR to odd-numbered bit lines GBLo. A NAND string is connected between even-numbered bit lines GBLe / odd-numbered bit lines GBLo and the source line SL. During read operation, when an even-numbered bit line GBLe is selected, an odd-numbered bit line GBLo is not selected, and when an odd-numbered bit line GBLo is selected, an even-numbered bit line GBLe is not selected. A pre-charge voltage is supplied to the selected bit lines, and GND is supplied to the unselected bit lines.

[0007] Previous page reading Figure 2 as well as Figure 3 As shown by the dashed lines, the following initialization steps must be performed: bit line initialization (S10), latch L1 initialization (S20), page buffer circuit initialization (S30), and select bit line pre-charge (S40). (Refer to...) Figure 4 The timing diagram is used to illustrate the actions of these steps S10 to S40. Here, it is assumed that the even-numbered bit line GBLe is selected.

[0008] At time t1, the virtual power supply VIRPWR is set to GND level, transistors YBLe and YBLo are turned on (H level), and bit lines GBLe and GBLo are set to GND, thus initializing bit lines GBLe and GBLo (S10). The initialization of the bit lines is performed to stabilize the read data.

[0009] In parallel with the initialization of the bit lines, during the period from time t1 to time t2, the voltage supply node V1 is set to GND level, transistors BLPRE and BLCD1 are turned on (H level), node SLR1 is set (L1 SET L) to L level (GND), and latch L1 is initialized (S20). The initialization of latch L1 is performed for the stabilization of read data.

[0010] During the period from time t3 to time t4, the voltage supply node V1 is set to VDD (internal supply voltage: e.g., 2.0V), transistors BLPRE, BLCLAMP, and BLCN are sequentially turned on (high level), transistor YBLe is turned off, the readout node SNS is charged to VDD, and nodes TOBL and BLS are charged to VCLMP1 (VCLMP1 < VDD), thus initializing the page buffer / readout circuit (S30). At this time, a voltage VCLMP1 + Vth (Vth is the threshold voltage of transistor BLCLAMP1) is applied to the gate of transistor BLCLAMP, and a sufficiently high voltage is applied to the gates of transistors BLPRE and BLCN to allow VDD to pass through nodes SNS and BLS.

[0011] Next, at time t4, transistor BLSe is turned on, supplying voltage VCLMP1 to the even-numbered bit line GBLe, pre-charging the select bit line GBLe (S40) to prepare for reading the selected memory cell. Meanwhile, during the pre-charging period of the select bit line GBLe, the non-select bit line GBLo is electrically connected to the GND level of the virtual power supply VIRPWR via transistor YBLo. By forcing the non-select bit line GBLo to GND, bit line shielding is created, reducing noise caused by coupling, stabilizing the read data, and ensuring the data retention characteristics of the NAND string connected to the non-select bit line.

[0012] For example, the processing time for steps S10 to S20 is approximately 1 μs, the processing time for step S30 is approximately 1 μs, the processing time for step S40 is approximately 5 μs to 6 μs, and the setup time for the page buffer / read circuit and bit lines is approximately 7 μs to 8 μs. Moreover, when error checking and correction (ECC) is implemented in the flash memory, the read time may be further increased.

[0013] The purpose of this invention is to solve the previous problems and provide a semiconductor device and readout method capable of high-speed readout.

[0014] The readout method of the present invention is a readout method for NAND flash memory. The NAND flash memory includes a bit line selection circuit for selecting even-numbered or odd-numbered bit lines, and a page buffer / readout circuit connected to the bit line selection circuit. The readout method includes: a first step of pre-charging the selected bit lines by supplying a voltage from a first voltage supply source connected to the bit line selection circuit; and a second step of initializing the latch of the page buffer / readout circuit by supplying a voltage from a second voltage supply source connected to the page buffer / readout circuit, in parallel with the pre-charging of the selected bit lines.

[0015] In one embodiment, the readout method further includes a third step, which is performed in parallel with the pre-charging of the select bit line, after the latch is initialized, by initializing the read node of the page buffer / readout circuit with the supply voltage of the second voltage supply source. In one embodiment, the second and third steps are performed during the pre-charging of the select bit line. In one embodiment, the second voltage supply source supplies GND level for the second step and VDD for the third step. In one embodiment, the readout method further includes a fourth step, which initializes the select bit line with the supply voltage of the first voltage supply source before the pre-charging of the select bit line. In one embodiment, the readout method further includes a fifth step, which performs bit line shielding on the non-select bit line with the supply voltage of the second voltage supply source. In one embodiment, the fifth step further includes: electrically connecting the supply voltage of the first voltage supply source to the non-select bit line; and connecting the bit line selection circuit to the page buffer / readout circuit. In one embodiment, the fifth step is performed simultaneously with the second step. In one embodiment, when the pre-charging of the select bit line begins, the transistor connected between the first voltage supply source and the select bit line is turned on. In one embodiment, a first voltage supply source supplies a voltage at the pre-charge level, and the transistor is turned on so that the pre-charge level does not drop.

[0016] The semiconductor device of the present invention includes: a NAND-type memory cell array; a readout unit for reading data from a selected page of the memory cell array; and an output unit for outputting the data read by the readout unit to an external location. The readout unit includes a bit line selection circuit for selecting an even number of bit lines or an odd number of bit lines, and a page buffer / readout circuit connected to the bit line selection circuit. The readout unit precharges the selected bit lines with a supply voltage from a first voltage supply source connected to the bit line selection circuit, and initializes the latch of the page buffer / readout circuit in parallel with the precharging of the selected bit lines with a supply voltage from a second voltage supply source connected to the page buffer / readout circuit.

[0017] In one embodiment, the readout unit initializes the read node of the page buffer / readout circuit using the supply voltage of the second voltage supply source, in parallel with the precharging of the select bit line, after the latch initialization. In another embodiment, the readout unit initializes the select bit line using the supply voltage of the first voltage supply source before the precharging of the select bit line. In another embodiment, the readout unit performs bit line masking on the non-select bit line using the supply voltage of the second voltage supply source. In yet another embodiment, the readout unit simultaneously performs bit line masking on the non-select bit line and latch initialization. In one embodiment, when the precharging of the select bit line begins, the transistor connected between the first voltage supply source and the select bit line is turned on. In one embodiment, the readout unit includes a detection unit that detects the voltage of the bit line, turns on the transistor to prevent the supply voltage of the first supply source from dropping, and turns off the transistor when the detection unit detects the precharging voltage. In one embodiment, the readout unit outputs a precharging level voltage from the first voltage supply source and turns on the transistor to prevent the precharging level voltage from dropping. In one embodiment, the readout unit includes a unity gain buffer that outputs a voltage at the precharge level.

[0018] According to the present invention, the initialization of the latch of the page buffer / read circuit is performed in parallel with the pre-charging of the select bit line, thus enabling high-speed reading compared to the conventional method. Furthermore, since the select bit line is pre-charged from the first voltage supply source of the bit line selection circuit, compared to the case where the select bit line is pre-charged from the second voltage supply source of the page buffer / read circuit, charging of the read node, etc., is not required, enabling rapid pre-charging. Attached Figure Description

[0019] Figure 1 A circuit diagram showing the structure of the page buffer / read circuit and bit line selection circuit of a NAND flash memory;

[0020] Figure 2 Explain the process of each step in the previous reading action;

[0021] Figure 3 A flow diagram illustrating the signals for each step of a previous readout operation;

[0022] Figure 4 A timeline showing past readout actions;

[0023] Figure 5 A structural block diagram illustrating an embodiment of the NAND flash memory of the present invention;

[0024] Figure 6 This describes the process flow of each step of the readout operation in an embodiment of the present invention;

[0025] Figure 7 This is a signal flow diagram illustrating each step of the readout operation in an embodiment of the present invention;

[0026] Figure 8 This is a timing diagram of the readout action according to an embodiment of the present invention;

[0027] Figure 9 (A) and Figure 9 (B) represents a structural diagram of the voltage generation circuit of the second embodiment of the present invention;

[0028] Figure 10 This is a structural diagram showing the voltage generation circuit of the third embodiment of the present invention;

[0029] Figure 11 (A) and Figure 11 (B) represents a structural diagram of the voltage generation circuit of the virtual power supply according to the fourth embodiment of the present invention.

[0030] Explanation of icon numbers:

[0031] 10: Page buffer / read circuit

[0032] 20: Bit line selection circuit

[0033] 100: Flash memory

[0034] 110: Memory cell array

[0035] 120: Input / Output Circuit

[0036] 130: ECC circuit

[0037] 140: Address Register

[0038] 150: Controller

[0039] 160: Word line selection circuit

[0040] 170: Page buffer / read circuit

[0041] 180: Column Selection Circuit

[0042] 190: Internal voltage generation circuit

[0043] 200: PB Replication Circuit

[0044] 210: Comparator

[0045] 300: Voltage generation circuit

[0046] 310: VDD drive circuit

[0047] 320: VCLMPx driver circuit

[0048] #0, #1, #1_1, #1_2, #1_3, S10~S40: Steps

[0049] OP: Operational amplifier

[0050] Ax: Row address information

[0051] Ay: Column address information

[0052] BLCD1, BLCD2, BLCLAMP, BLCN, BLPRE, BLSe, BLSo, DTG, E_BLCLAMP, E_YBL, REG, VG, YBLe, YBLo: transistors

[0053] BLS, SLR1, SLR2, TOBL: Nodes

[0054] DET: Detection signal

[0055] GBLe, R_GBLe: Even bit lines

[0056] GBLo: Odd Bit Line

[0057] L1, L2: Latches

[0058] SEL: Control signal

[0059] SNS: Readout Node

[0060] SW1, SW2, SW3: Switches

[0061] t1~t8: Time points

[0062] TR1, TR2: Transmission transistors

[0063] UGB: Unity Gain Buffer

[0064] V1, V2: Voltage supply nodes

[0065] VCLMP1, VCLMPx: Voltage

[0066] Vers: Erasure voltage

[0067] VIRPWR: Virtual Power Supply

[0068] Vpass: Through voltage

[0069] Vpgm: Write voltage

[0070] Vread: Reads the voltage passing through.

[0071] Vth, Vth_BL, Vth_YBL: Thresholds Detailed Implementation

[0072] The embodiments of the present invention will be described in detail with reference to the accompanying drawings. Figure 5 This is a structural diagram illustrating a NAND flash memory according to an embodiment of the present invention. The flash memory 100 of this embodiment is configured with the following components: a memory array 110, which has multiple memory cells arranged in a matrix; an input / output circuit 120, which outputs read data to the outside or imports data input from the outside; an ECC circuit 130, which generates code for the data to be programmed or performs error detection / correction on the read data; an address register 140, which receives address data via the input / output circuit 120; a controller 150, which controls each part by receiving command data via the input / output circuit 120 or by applying control signals to the terminals; and a word line selection circuit 160, which receives row address information Ax from the address register 140, decodes the row address information Ax, and... The decoding results are used to select blocks or word lines, etc.; the page buffer / read circuit 170 holds data read from the page selected by the word line selection circuit 160, or holds data to be programmed to the selected page; the column selection circuit 180 receives column address information Ay from the address register 140, decodes the column address information Ay, and selects columns in the page buffer / read circuit 170 based on the decoding results, etc.; and the internal voltage generation circuit 190 generates various voltages required for data reading, programming, and erasing (write voltage Vpgm, pass voltage Vpass, read pass voltage Vread, erase voltage Vers, internal supply voltage VDD, etc.).

[0073] Memory array 110, for example, has m memory blocks BLK arranged along the column direction. Within each memory block, multiple NAND strings are formed, consisting of multiple memory cells connected in series. A NAND string includes multiple memory cells connected in series, bit-line selected transistors (BSSTs), and source-line selected transistors (SSTs). The drain of the BSST is connected to a corresponding bit line, and the source of the SST is connected to a common source line. The control gate of the memory cell is connected to a word line, and the gates of the BSSTs and SSTs are respectively connected to select gate lines. NAND strings can be formed two-dimensionally or three-dimensionally on the substrate surface.

[0074] The word line select circuit 160 selects a block or word line by driving the bit line-side select transistor and the source line-side select transistor via the select gate line, based on the row address Ax. The column select circuit 180 selects the bit line based on the column address Ay, for example, selecting the start position for reading data within a page. Furthermore, both the word line select circuit 160 and the column select circuit 180 may include row address counters and column address counters that increment the row and column addresses in response to a clock signal.

[0075] Page buffer / read circuit 170 is with Figure 1 The page buffer / read circuit 10 shown is similarly configured and is connected to the even bit line GBLe and the odd bit line GBLo via the bit line selection circuit 20.

[0076] The controller 150, configured using a microcontroller or state machine, controls the operation of the flash memory 100. During the read operation, a positive voltage is applied to the bit lines, a voltage (e.g., 0V) is applied to the select word lines, and a pass voltage Vpass (e.g., 4.5V) is applied to the non-select word lines, turning on the bit line-side select transistors and the source line-side select transistors, while applying 0V to the common source line. During the programming operation, a high programming voltage Vpgm (15V–20V) is applied to the select word lines, and an intermediate potential (e.g., 10V) is applied to the non-select word lines, turning on the bit line-side select transistors and turning off the source line-side select transistors, supplying the potential corresponding to the data "0" or "1" to the bit lines. During the erase operation, 0V is applied to the select word lines within the block, and a high voltage (e.g., 20V) is applied to the P-well, extracting electrons from the floating gate to the substrate, thereby erasing data block by block.

[0077] Next, the read operation of the flash memory 100 in this embodiment will be described. In order to achieve a higher read speed than before, the flash memory 100 in this embodiment does not perform reads sequentially. Figure 2 Instead of the "initialization of bit lines", "initialization of latch L1", "initialization of page buffer / read circuit", and "pre-charging of select bit lines", it is equipped with a high-speed page read mode for performing these actions in parallel.

[0078] Figure 6 This is a diagram illustrating the operation flow of the high-speed readout mode in this embodiment. Figure 7This is a flow diagram illustrating the signals in high-speed readout mode. The high-speed page readout mode of this embodiment includes: step #0, initializing the select bit lines using the virtual power supply VIRPWR; and after step #0, step #1, pre-charging the select bit lines using the virtual power supply VIRPWR, step #1_1, bit-line shielding of the non-select bit lines using the voltage supply node V1, step #1_2, resetting the latch L1 using the voltage supply node V1, and step #1_3, initializing the page buffer / readout circuit using the voltage supply node V1. These steps are controlled by the controller 150. In step #0, the initialization of the select bit lines may include not only initialization using VIRPWR but also initialization of the non-select bit lines to GND. However, in step #1_1, as long as the non-select bit lines are bit-line shielded using the voltage supply node V1, the non-select bit lines will eventually also be initialized to GND.

[0079] During step #1, which precharges the select bit lines using the virtual power supply VIRPWR, steps #1_2, which initializes the latch L1 using the voltage supply node V1, and step #1_3, which initializes the page buffer / read circuit using the voltage supply node V1, are performed in parallel at least. Alternatively, step #1_1, which performs bit line masking on the non-select bit lines using the voltage supply node V1, can also be included in the parallel operation. Since steps #1_1 and #1_2 use the GND of the voltage supply node V1, they can be executed simultaneously.

[0080] By performing steps #1, #1_2, and #1_3 in parallel, the initialization of latch L1 and page buffer / read circuit 170 is omitted during the pre-charging of the selected bit lines, thus shortening the read time. Furthermore, the pre-charging of the selected bit lines via the virtual power supply VIRPWR differs from the pre-charging from the voltage supply node V1; it does not charge the capacitors of read nodes SNS, TOBL, and BLS, and bypasses transistors BLCLAMP, BLCN, and BLSe / BLSo, thereby achieving rapid pre-charging with shortened pre-charging time. In addition, by running steps #1_1 in parallel with step #1 and simultaneously with step #1_2, bit line shielding of non-selected bit lines can be performed without time penalty, reducing noise caused by coupling.

[0081] Next, refer to Figure 8 The timing diagram will be used to illustrate the detailed operation of the high-speed readout mode in this embodiment. Furthermore, it is assumed that even-numbered bit lines GBLe are selected, and odd-numbered bit lines GBLo are not selected.

[0082] At time t1, the virtual power supply VIRPWR is set to GND, and a high-level voltage (H) is applied to the gate of transistor YBLe, turning it on. The select bit line GBLe is then electrically connected to GND, initializing GBLe (step #0). At this time, transistor YBLo can also be turned on, and the non-select bit line GBLo is electrically connected to GND. At time t1, transistors BLSe / BLSo are off, and even-numbered bit lines GBLe and odd-numbered bit lines GBLo are disconnected from the slave node BLS.

[0083] Furthermore, by setting the voltage supply node V1 to GND, transistors BLCN, BLCLAMP, and BLPRE are turned on, thereby connecting the readout nodes SNS, TOBL, and BLS to the GND level.

[0084] At time t2, the gate of transistor YBLe is shifted from H level (e.g., VDD or VCLMP1+Vth) to VCLMP1+Vth. VCLMP1 < VDD, and Vth is the threshold of transistor YBLe. Furthermore, the gate of transistor YBLo is shifted to GND, turning off transistor YBLo, and the gate of transistor BLSo is shifted from GND to H level, turning on transistor BLSo. This disconnects the non-select bit line GBLo from the virtual power supply VIRPWR. The non-select bit line GBLo is electrically connected to the GND of the voltage supply node V1 via transistors BLS, BLCN, BLCLAMP, and BLPRE, and is thus bit-line shielded (step #1_1).

[0085] At time t3, the virtual power supply VIRPWR is migrated to VDD, and the pre-charge of the select bit line GBLe begins (step #1). Transistor BLSe is off, and the select bit line GBLe is disconnected from node BLS. A voltage VCLMP1+Vth is applied to the gate of transistor YBLe, and the voltage for the select bit line GBLe is supplied via transistor YBLe. The pre-charge period is from time t3 to time t8.

[0086] During the pre-charging period of the select bit line GBLe, the non-select bit line GBLo is disconnected from the virtual power supply VIRPWR, but is electrically connected to the GND of the voltage supply node V1 via transistors BLSo, BLCN, BLCLAMP, and BLPRE. However, the voltage of the non-select bit line GBLo rises slightly due to capacitive coupling with the select bit line GBLe. Accompanying this, the voltages of nodes BLS, TOBL, SNS, and V1 also rise slightly. However, if the select bit line is fully charged, the driving effect of the voltage supply node V1 in forcing the non-select bit line GBLo, BLS, and TOBL to GND is greater than the voltage rise caused by capacitive coupling. As a result, the non-select bit line GBLo, BLS, TOBL, SNS, and V1 return to GND.

[0087] During the period from time t4 to time t5, transistor BLCD1 is switched from GND to H level, turning on transistor BLCD1 and electrically connecting node SLR1 of latch L1 to the GND level of voltage supply node V1, thereby resetting latch L1 (step #1_2). Additionally, due to the voltage rise effect of capacitive coupling, the voltages of voltage supply node V1 and read node SNS will rise slightly, but since the driving capability of voltage supply node V1 to force read node SNS to GND is strong enough, it will not affect step #1_2.

[0088] At time t6, after ensuring sufficient pre-charge time for the bit line, the gate of transistor BLSo transitions from H level to L level, turning off transistor BLSo. As a result, the non-select bit line GBLo disconnects from node BLS, changing from a shielded state to a floating state. Transistor BLSo is on from time t2 until t6. During this period, the non-select bit line GBLo is electrically connected to GND level, and the select bit line GBLe is fully charged, thus preventing the voltage of the non-select bit line GBLo from rising significantly due to capacitive coupling.

[0089] At time t7, the voltage supply node V1 is moved from GND to VDD. During the period from time t7 to time t8, the read node SNS is charged to VDD, and nodes TOBL and BLS are charged to voltage VCLMP1 or VDD, thus initializing the page buffer / read circuit 170 (step #1_3). The initialization of the page buffer / read circuit 170 is performed during the pre-charging period of the select bit line, so the time required for the initialization of the page buffer / read circuit 170 is actually hidden by the pre-charging period. Moreover, since the initialization of the page buffer / read circuit 170 is performed at the end of the pre-charging period, the voltage rise of the floating non-select bit line due to capacitive coupling can be prevented. In addition, at time t7, transistor YBLe can also be turned off, and at time t8, transistor BLSe can be turned on to electrically connect node BLS and select bit line GBLe, thereby aligning the small potential difference generated by nodes TOBL, BLS, and GBLe. At this time, between time t7 and time t8, nodes TOBL and BLS are charged to VCLMP1. When the pre-charging of the selected bit line GBLe ends, the cell is discharged, and the read data is read out. The read data is held in latch L1 at the read node SNS.

[0090] According to the high-speed readout mode of this embodiment, the initialization of latch L1 and the initialization of the page buffer / readout circuit are performed in parallel with the pre-charging of the selection bit line. Therefore, compared with the conventional method of performing these operations sequentially, high-speed readout is possible. For example, in the conventional readout method, the setup time for the page buffer / readout circuit and the bit line is about 7μs to 8μs, but in the high-speed readout mode of this embodiment, it can be shortened to 2μs to 3μs.

[0091] Furthermore, in this embodiment, the latch L1 and the page buffer / read circuit 170 are initialized during the pre-charge period of the select bit line. However, the read time can also be shortened by initializing the latch L1 at least during the pre-charge period of the select bit line. Moreover, although the embodiment illustrates a single-page read operation, the high-speed read mode of this embodiment can of course also be applied to multi-page read operations.

[0092] Next, a second embodiment of the present invention will be described. The second embodiment relates to a pre-charging method for the select bit line. In conventional flash memory, when pre-charging the select bit line, a voltage VCLMP1 + Vth_BL (Vth_BL is the threshold of the transistor BLCLAMP) is applied to the gate of the transistor BLCLAMP, generating a VCLMP1 level on the select bit line. Furthermore, during cell discharge, a voltage VCLMP2 + Vth_BL (VCLMP2 < VCLMP1) is applied to the gate of the transistor BLCLAMP. In contrast, in this embodiment, a voltage VCLMP1 + Vth_YBL (Vth_YBL is the threshold of the transistor YBLe / YBLo) is applied to the gate of the transistor YBLe / YBLo, generating a VCLMP1 level on the select bit line.

[0093] Figure 9 (A) represents a conventional voltage generation circuit. The voltage generation circuit includes an operational amplifier (OP) and a transistor E_BLCLAMP. A voltage VCLMPx is supplied to the non-inverting input terminal (+) of the OP, and a constant current source is supplied to the inverting input terminal (-). A diode connection is used to connect the transistor E_BLCLAMP to create negative feedback between the output of the OP and the inverting input terminal. The transistor E_BLCLAMP is used for emulation of the transistor BLCLAMP, generating VCLMPx + Vth at the output of the OP (Vth is the threshold voltage of the transistor E_BLCLAMP, and Vth ≒ the threshold voltage Vth of the transistor BLCLAMP). Furthermore, during pre-charging of the select bit line, VCLMPx = VCLMP1; during cell discharge, VCLMPx = VCLMP2. VCLMPx is the sum of VCLMP1 and VCLMP2.

[0094] Figure 9 (B) represents the voltage generation circuit of this embodiment. The voltage generation circuit of this embodiment, besides... Figure 9 In addition to the structure of (A), it also includes transistor E_YBL connected in parallel to transistor E_BLCLAMP, switch SW1 connected between transistor E_BLCLAMP and the output, and switch SW2 connected between transistor E_YBL and the output. Transistor E_YBL is a simulation transistor for transistors YBLe / YBLo. Transistor BLCLAMP is a transistor capable of operating at low voltage, while transistors YBLe / YBLo are transistors with withstand voltages up to the bit line; their threshold values ​​are different. Therefore, transistors E_BLCLAMP and E_YBL are required.

[0095] Switches SW1 and SW2 open and close the path in response to the control signal SEL from controller 150. Specifically, when pre-charging the select bit line, switch SW1 is open and switch SW2 is closed. Consequently, the voltage generation circuit outputs a voltage VCLMPx+Vth_YBL, which is applied to the gate of the transistor connected to the select bit line in transistors YBLe / YBLo (corresponding to...). Figure 8 The gate voltage of transistor YBLe is VCLMP1+Vth. On the other hand, during cell discharge, switch SW1 is closed and switch SW2 is open. As a result, the voltage generation circuit outputs voltage VCLMPx+Vth_BL, which is applied to the gate of transistor BLCLAMP.

[0096] According to the voltage generation circuit of this embodiment, it is possible to selectively generate the gate voltage VCLMPx+Vth_BL for the transistor BLCLAMP, or the gate voltage VCLMPx+Vth_YBL for the transistors YBLe / YBLo. Furthermore, for the negative feedback of the operational amplifier, a high-precision voltage can be generated by using a constant current source and a diode-connected transistor E_YBL. Additionally, the voltage generation circuit of this embodiment can be included in the virtual power supply VIRPWR or set up independently of it.

[0097] Next, the third embodiment of the present invention will be described. Figure 10 This is a structural diagram illustrating the voltage generation circuit of the third embodiment. As shown in this figure, the voltage generation circuit includes: a PB replication circuit 200, and a page buffer / readout circuit 170 (e.g., a page buffer / readout circuit). Figure 1 (Structure shown); the even bit line R_GBLe and the odd bit line R_GBLo for copying are connected to the PB copying circuit 200; switch SW1 is connected to the even bit line R_GBLe; switch SW2 is connected to the odd bit line R_GBLo; and comparator 210 connects the common node of switches SW1 and SW2 to the inverting input terminal (-) and connects the voltage VCLMPx to the non-inverting input terminal (+).

[0098] Switches SW1 and SW2 open and close the path in response to the control signal SEL from controller 150. When precharging even-numbered bit lines GBLe, switch SW1 is closed and switch SW2 is open; when precharging odd-numbered bit lines GBLo, switch SW1 is open and switch SW2 is closed.

[0099] During pre-charging of the select bit line, both the page buffer / readout circuit 170 and the PB copy circuit 200 are supplied with VDD by the virtual power supply VIRPWR. A sufficiently large voltage (e.g., the gate voltage that boosts VDD through bootstrapping, etc.) is applied to the gate of the transistor connected to the select bit line in the transistors YBLe / YBLo, thus supplying a voltage at the VDD level for the select bit line. As a result, the select bit line is pre-charged more rapidly than in the second embodiment. The comparator 210 compares the copy voltage of the even bit line R_GBLe or the odd bit line R_GBLo for copying with VCLMPx. When the copy voltage < VCLMPx, it outputs a detection signal DET at level H; when the copy voltage ≥ VCLMPx, it outputs a detection signal DET at level L. When the detection signal DET transitions to level L, the controller 150 disconnects the transistors connected to the select bit line in the transistors YBLe / YBLo in response, ending the pre-charging of the select bit line.

[0100] According to this embodiment, until the select bit line reaches the pre-charge level, the transistor connected to the select bit line in the transistor YBLe / YBLo is strongly turned on, supplying a large drain current to the select bit line, thereby shortening the pre-charge time of the select bit line.

[0101] Next, the fourth embodiment of the present invention will be described. Figure 11 (A) and Figure 11 (B) is a structural diagram showing the voltage generation circuit of the virtual power supply according to the fourth embodiment. The voltage generation circuit 300 of the virtual power supply includes a VDD drive circuit 310, a VCLMPx drive circuit 320, a switch SW1 connected between the VDD drive circuit 310 and the output VIRPWR, a switch SW2 connected between the VCLMPx drive circuit 320 and the output VIRPWR, and a switch SW3 connected between GND and the output VIRPWR. However, it should be noted that the voltage generation circuit 300 can generate other voltages besides the voltage itself.

[0102] Switches SW1, SW2, and SW3 open and close the path according to the control signal SEL from controller 150. During pre-charging of the select bit line, switch SW2 is closed, and switches SW1 and SW3 are open, generating voltage VCLMPx at output VIRPWR. At this time, a sufficiently large voltage (e.g., a voltage that boosts voltage VCLMPx or VDD) is applied to the gate of the transistor connected to the select bit line in transistors YBLe / YBLo, and voltage VCLMPx is supplied to the select bit line. On the other hand, during initialization of the select bit line (… Figure 6In step #0), switches SW1 and SW2 are open, and switch SW3 is closed, supplying GND to the output VIRPWR. Furthermore, when VDD is supplied from the output VIRPWR, switch SW1 is closed, and switches SW2 and SW3 are open.

[0103] Figure 11 (B) is a structural diagram showing the VCLMPx driver circuit 320. The driver circuit 320 includes a unity-gain buffer UGB. The non-inverting input terminal (+) of the unity-gain buffer UGB is supplied with a voltage VCLMPx, and the inverting input terminal (-) provides negative feedback and has an output. The output of the unity-gain buffer UGB is a voltage equal to the input voltage VCLMPx.

[0104] By using a unity-gain buffer UGB as in this embodiment, a high-precision voltage VCLMPx can be generated. Furthermore, by forcefully turning on the transistors connected to the select bit line in the YBLe / YBLo transistors, a large drain current is supplied to the select bit line, thereby shortening the pre-charge time of the select bit line.

[0105] Preferred embodiments of the present invention have been described in detail, but the present invention is not limited to specific embodiments and various modifications and alterations can be made within the scope of the spirit of the present invention as described in the claims.

Claims

1. A readout method, which is a readout method for a NAND flash memory, the NAND flash memory including a bit line selection circuit for selecting an even number of bit lines or an odd number of bit lines and a page buffer / readout circuit connected to the bit line selection circuit, the readout method comprising: The first step is to precharge the selected bit line by using the supply voltage of the first voltage supply source connected to the bit line selection circuit. The second step, in parallel with the pre-charging of the select bit line, is to initialize the latch of the page buffer / read circuit by supplying the voltage of the second voltage supply source connected to the page buffer / read circuit. as well as The third step, in parallel with the pre-charging of the select bit line, is to initialize the read node of the page buffer / read circuit using the supply voltage of the second voltage supply source after the initialization of the latch.

2. The readout method according to claim 1, wherein The second and third steps are performed during the pre-charging period of the selected bit line, with the second voltage supply source supplying a ground level for the second step and an internal supply voltage for the third step.

3. The readout method according to claim 1, wherein, The readout method further includes a fourth step, which is to initialize the select bit line with the supply voltage of the first voltage supply source before the pre-charging of the select bit line.

4. The readout method according to claim 1, wherein The readout method further includes a fifth step, which involves using the supply voltage of the second voltage supply source to shield the non-selected bit lines.

5. The readout method according to claim 4, wherein, The fifth step further includes: electrically connecting the supply voltage of the first voltage supply source to the non-select bit line; and connecting the bit line selection circuit to the page buffer / readout circuit. The fifth step is performed simultaneously with the second step.

6. The readout method according to claim 1, wherein, When the pre-charging of the select bit line begins, a transistor connected between the first voltage supply source and the select bit line is turned on. The first voltage supply source supplies a pre-charging level voltage, and the transistor is turned on so that the pre-charging level does not drop.

7. A semiconductor device, comprising: NAND-type memory cell array; The readout component reads data from the selected page of the storage cell array; as well as The output component outputs the data read by the readout component to the outside. The readout unit includes a bit line selection circuit for selecting either an even number of bit lines or an odd number of bit lines, and a page buffer / readout circuit connected to the bit line selection circuit. The readout unit precharges the selected bit line using a supply voltage from a first voltage supply source connected to the bit line selection circuit, and in parallel with the precharging of the selected bit line, initializes the latch of the page buffer / readout circuit using a supply voltage from a second voltage supply source connected to the page buffer / readout circuit. The readout component, in parallel with the pre-charging of the select bit line, initializes the readout node of the page buffer / readout circuit using the supply voltage of the second voltage supply source after the initialization of the latch.

8. The semiconductor device according to claim 7, wherein The readout unit then initializes the select bit line using the supply voltage of the first voltage supply source before the select bit line is pre-charged.

9. The semiconductor device according to claim 7, wherein, The readout unit then performs bit line shielding on the non-selectable bit lines using the supply voltage of the second voltage supply source, and the readout unit simultaneously performs bit line shielding on the non-selectable bit lines and initialization of the latch.

10. The semiconductor device according to claim 7, wherein, When the pre-charging of the select bit line begins, the transistor connected between the first voltage supply source and the select bit line is turned on.

11. The semiconductor device according to claim 10, wherein, The readout component includes a detection component for detecting the voltage of the bit line, the readout component turning on the transistor to prevent the supply voltage of the first voltage supply source from dropping, and turning the transistor off when the detection component detects a pre-charge voltage.

12. The semiconductor device according to claim 10, wherein, The readout unit outputs a pre-charge level voltage from the first voltage supply source and turns on the transistor to prevent the pre-charge level voltage from dropping.

13. The semiconductor device according to claim 7, wherein, The readout unit includes a unity-gain buffer that outputs a voltage at the pre-charge level.

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