Semiconductor memory device and method of operating a semiconductor memory device

Abstract

The present application relates to semiconductor memory devices and methods of operating semiconductor memory devices. The present technology provides a method of operating a semiconductor memory device that detects a threshold voltage distribution of memory cells included in a page selected from among a plurality of memory cells. The method of operating a semiconductor memory device includes selecting a target state whose threshold voltage distribution is to be detected, determining a plurality of read voltages for dividing a voltage range in which threshold voltages of the selected target state are distributed, and performing a plurality of sensing operations using the plurality of read voltages on the selected page. A mask to the target state is applied in each of the plurality of sensing operations.

Description

Technical Field

[0001] This disclosure relates to electronic devices, and more specifically, to semiconductor memory devices and methods of operating the semiconductor memory devices. Background Technology

[0002] Semiconductor memory devices can be formed as a two-dimensional structure in which strings are horizontally arranged on a semiconductor substrate, or as a three-dimensional structure in which strings are vertically stacked on a semiconductor substrate. Three-dimensional semiconductor memory devices are designed to overcome the integration limitations of two-dimensional memory devices and can include multiple memory cells vertically stacked on a semiconductor substrate. Furthermore, a controller can control the operation of the semiconductor memory device. Summary of the Invention

[0003] According to embodiments of this disclosure, a method for operating a semiconductor memory device detects the threshold voltage distribution of memory cells included in a page selected from a plurality of memory cells. This method for operating a semiconductor memory device may include: selecting a target state to be detected by means of the threshold voltage distribution; determining a plurality of read voltages for dividing the voltage range to which the threshold voltage of the selected target state is distributed; and performing a plurality of sensing operations on the selected page using the plurality of read voltages. Masking of the target state may be applied in each of the plurality of sensing operations.

[0004] According to embodiments of this disclosure, a semiconductor memory device may include: a plurality of memory cells connected to selected word lines; a plurality of page buffers configured to perform a sensing operation on each of the plurality of memory cells; and control logic configured to control the operation of the plurality of page buffers. Each of the plurality of page buffers may include: at least one data latch connected to a sensing output node and storing bit data; and a sensing latch connected to the sensing output node and storing bit data during the sensing operation indicating whether a threshold voltage of a corresponding memory cell among the plurality of memory cells is greater than a selected read voltage. The at least one data latch may store bit data programmed into the corresponding memory cell. The control logic may, based on the bit data stored in the at least one data latch, control each of the plurality of page buffers to apply a masking of a target state of a detection target selected as a threshold voltage distribution to the bit data stored in the sensing latch. Attached Figure Description

[0005] Figure 1 This is a block diagram illustrating a memory system including a semiconductor memory device and a controller according to an embodiment of the present disclosure.

[0006] Figure 2 This is an example Figure 1A block diagram of a semiconductor memory device.

[0007] Figure 3 This is an example Figure 2 A diagram illustrating an implementation of a memory cell array.

[0008] Figure 4 This is an example Figure 3 The circuit diagram of any one of the memory blocks BLKa from BLK1 to BLKz.

[0009] Figure 5 This is an example Figure 3 A circuit diagram of another embodiment of any one of the storage blocks BLK1 to BLKz, BLKb.

[0010] Figure 6 This is an example Figure 2 A circuit diagram illustrating an implementation of any one of the multiple memory blocks BLK1 to BLKz included in the memory cell array, BLKc.

[0011] Figure 7 This is a diagram illustrating pages and strings of cells formed by memory cells included in a memory cell array.

[0012] Figure 8 This is a graph illustrating the threshold voltage distribution of a multilevel cell (MLC).

[0013] Figure 9A This is a graph illustrating the changing state of the threshold voltage distribution of an MLC. Figure 9B It is a table that lists the threshold voltage of the memory cell corresponding to each column of the selected page.

[0014] Figure 10A This is a graph illustrating the threshold voltage distribution corresponding to the erase state E′ among the detected threshold voltage distributions. Figure 10B This is a graph illustrating the threshold voltage distribution corresponding to the first programming state PV1′ among the detected threshold voltage distributions. Figure 10C This is a graph illustrating the threshold voltage distribution corresponding to the second programming state PV2′ among the detected threshold voltage distributions. Figure 10D This is a graph illustrating the threshold voltage distribution corresponding to the third programming state PV3′ among the detected threshold voltage distributions.

[0015] Figure 11A This is a graph illustrating the detection operation of the threshold voltage distribution when the first programming state PV1′ is the target state. Figure 11B This is a table illustrating methods for deriving the threshold voltage distribution within each voltage range based on the results of multiple sensing operations.

[0016] Figure 12A This is a circuit diagram illustrating a page buffer according to an embodiment of the present disclosure, capable of detecting the threshold voltage distribution of an MLC by masking for each target state. Figure 12B It is a table that represents the bit data in the latches to be stored in the page buffer for each target state. Figure 12C This is a table that illustrates the transmission control signals used to mask the corresponding target state for each target state.

[0017] Figure 13A This is a graph illustrating the threshold voltage distribution of the memory cells detected when the first programming state PV1′ is masked as the target state. Figure 13B This is a graph illustrating the threshold voltage distribution of the memory cells detected in a state where the third programming state PV3′ is masked as the target state.

[0018] Figure 14 This is a flowchart illustrating a method of operating a semiconductor memory device according to an embodiment of the present disclosure.

[0019] Figure 15 This is an example Figure 14 A flowchart illustrating an example implementation of step S150.

[0020] Figure 16 This is a circuit diagram illustrating a page buffer according to another embodiment of the present disclosure, capable of detecting the threshold voltage distribution of an MLC by masking for each target state.

[0021] Figure 17 This is an example Figure 14 A flowchart of another example of an implementation of step S150.

[0022] Figures 18A to 18D This is an example based on Figure 17 The diagram illustrates a method for counting memory cells with a threshold voltage between a first read voltage and a second read voltage by masking the memory cells to a target state.

[0023] Figure 19 This is an example Figure 1 The block diagram shown is an example of a controller.

[0024] Figure 20 This is an example Figure 19 A block diagram illustrating an application example of a memory system.

[0025] Figure 21 This example includes references. Figure 20 A block diagram of the computing system describing the memory system. Detailed Implementation

[0026] The specific structural or functional descriptions of embodiments based on the concepts disclosed in this specification or application are merely illustrative for the purpose of describing embodiments based on the concepts disclosed herein. Embodiments based on the concepts disclosed may be implemented in various forms and should not be construed as limited to the embodiments described in this specification or application.

[0027] Embodiments of this disclosure provide a semiconductor memory device capable of rapidly detecting the threshold voltage distribution of each state, and a method for operating the semiconductor memory device.

[0028] This technology can provide a semiconductor memory device capable of rapidly detecting the threshold voltage distribution of each state, as well as a method for operating the semiconductor memory device.

[0029] Figure 1 This is a block diagram illustrating a memory system including a semiconductor memory device and a controller according to an embodiment of the present disclosure.

[0030] Reference Figure 1 The memory system 1000 includes a semiconductor memory device 100 and a controller 200. The memory system 1000 communicates with a host 300. The controller 200 controls the overall operation of the semiconductor memory device 100. Furthermore, the controller 200 controls the operation of the semiconductor memory device 100 based on commands received from the host 300.

[0031] Figure 2 This is an example Figure 1 A block diagram of a semiconductor memory device.

[0032] Reference Figure 2 The semiconductor memory device 100 includes a memory cell array 110, an address decoder 120, a read / write circuit 130, control logic 140, and a voltage generator 150. The control logic 140 can be implemented in hardware, software, or a combination of both. For example, the control logic 140 can be a control logic circuit operating according to an algorithm and / or a processor executing control logic code.

[0033] The memory cell array 110 includes multiple memory blocks BLK1 to BLKz. The multiple memory blocks BLK1 to BLKz are connected to the address decoder 120 via word lines WL. The multiple memory blocks BLK1 to BLKz are connected to the read / write circuitry 130 via bit lines BL1 to BLm. Each of the multiple memory blocks BLK1 to BLKz includes multiple memory cells. In one embodiment, the multiple memory cells are non-volatile memory cells and may be composed of non-volatile memory cells with a vertical channel structure. The memory cell array 110 can be configured as a two-dimensional memory cell array. In another embodiment, the memory cell array 110 can be configured as a three-dimensional memory cell array. Furthermore, each of the multiple memory cells included in the memory cell array can store at least one bit of data. In one embodiment, each of the multiple memory cells included in the memory cell array 110 may be a single-level cell (SLC) storing one bit of data. In another embodiment, each of the multiple memory cells included in the memory cell array 110 may be a multi-level cell (MLC) storing two bits of data. In another embodiment, each of the plurality of memory cells included in the memory cell array 110 may be a tertiary cell storing three bits of data. In yet another embodiment, each of the plurality of memory cells included in the memory cell array 110 may be a quadrilateral cell storing four bits of data. According to embodiments, the memory cell array 110 may include a plurality of memory cells each storing five or more bits of data.

[0034] Address decoder 120, read / write circuitry 130, and voltage generator 150 operate as peripheral circuitry driving memory cell array 110. Address decoder 120 is connected to memory cell array 110 via word line WL. Address decoder 120 is configured to operate in response to control logic 140. Address decoder 120 receives addresses via input / output buffers (not shown) within semiconductor memory device 100.

[0035] Address decoder 120 is configured to decode block addresses from received addresses. Address decoder 120 selects at least one memory block based on the decoded block address. Additionally, during a read operation, address decoder 120 applies a read voltage Vread generated by voltage generator 150 to the selected word lines in the selected memory block and applies a pass voltage Vpass to the remaining unselected word lines. Furthermore, during a program verification operation, address decoder 120 applies a verification voltage generated by voltage generator 150 to the selected word lines in the selected memory block and applies a pass voltage Vpass to the remaining unselected word lines.

[0036] Address decoder 120 is configured to decode the column address in the received address. Address decoder 120 sends the decoded column address to read / write circuit 130.

[0037] Read and programming operations on the semiconductor memory device 100 are performed on a page-by-page basis. The address received when requesting a read or program operation includes a block address, a row address, and a column address. The address decoder 120 selects a memory block and a word line based on the block and row addresses. The column address is decoded by the address decoder 120 and provided to the read / write circuitry 130.

[0038] Address decoder 120 may include block decoder, row decoder, column decoder, address buffer, etc.

[0039] The read / write circuit 130 includes multiple page buffers PB1 to PBm. The read / write circuit 130 can operate as a "read circuit" during read operations of the memory cell array 110 and as a "write circuit" during write operations of the memory cell array 110. The multiple page buffers PB1 to PBm are connected to the memory cell array 110 via bit lines BL1 to BLm. During read and program verification operations, in order to sense the threshold voltage of the memory cells, the multiple page buffers PB1 to PBm continuously provide sensing current to the bit lines connected to the memory cells, sense changes in the amount of current flowing according to the programming state of the corresponding memory cells through sensing nodes, and latch the sensed changes as sensed data. The read / write circuit 130 operates in response to a page buffer control signal output from control logic 140.

[0040] During a read operation, the read / write circuit 130 senses the data in the memory cell, temporarily stores the read data, and outputs the data DATA to the input / output buffer (not shown) of the semiconductor memory device 100. As an example of an implementation, in addition to a page buffer (or page register), the read / write circuit 130 may also include a column select circuit, etc.

[0041] Control logic 140 is connected to address decoder 120, read / write circuitry 130, and voltage generator 150. Control logic 140 receives commands CMD and control signals CTRL via input / output buffers (not shown) of semiconductor memory device 100. Control logic 140 is configured to control the overall operation of semiconductor memory device 100 in response to control signal CTRL. Furthermore, control logic 140 outputs control signals for adjusting the precharge potential levels of sensing nodes in multiple page buffers PB1 to PBm. Control logic 140 can control read / write circuitry 130 to perform read operations on memory cell array 110.

[0042] Voltage generator 150, in response to a control signal output from control logic 140, generates a read voltage Vread and a pass voltage Vpass during a read operation. To generate multiple voltages with various voltage levels, voltage generator 150 may include multiple pumping capacitors that receive an internal power supply voltage, and generate multiple voltages by selectively activating the multiple pumping capacitors in response to control by control logic 140. As described above, voltage generator 150 may include a charge pump, and the charge pump may include the aforementioned multiple pumping capacitors. The specific configuration of the charge pump included in voltage generator 150 can be designed in various ways as needed.

[0043] The address decoder 120, read / write circuit 130, and voltage generator 150 can be used as "peripheral circuitry" to perform read, write, and erase operations on the memory cell array 110. The peripheral circuitry performs these operations based on the control logic 140.

[0044] Figure 3 This is an example Figure 2 A diagram illustrating an implementation of a memory cell array.

[0045] Reference Figure 3 The memory cell array 110 includes multiple memory blocks BLK1 to BLKz. Each memory block may have a three-dimensional structure. Each memory block includes multiple memory cells stacked on a substrate. These multiple memory cells are arranged along the +X, +Y, and +Z directions. (Refer to...) Figure 4 and Figure 5 Describe the structure of each storage block.

[0046] Figure 4 This is an example Figure 3 The circuit diagram of any one of the memory blocks BLKa from BLK1 to BLKz.

[0047] Reference Figure 4 The storage block BLKa comprises multiple cell strings CS11 to CS1m and CS21 to CS2m. In one implementation, each of the multiple cell strings CS11 to CS1m and CS21 to CS2m can be formed in a "U" shape. In the storage block BLKa, m cell strings are arranged along the row direction (i.e., the +X direction). Figure 4 In this example, two unit strings are arranged along the column direction (i.e., the +Y direction). However, this is for ease of description, and it is understood that three or more unit strings can be arranged along the column direction.

[0048] Each of the multiple cell strings CS11 to CS1m and CS21 to CS2m includes at least one source selection transistor SST, a first memory cell MC1 to the nth memory cell MCn, a tube transistor PT, and at least one drain selection transistor DST.

[0049] The selected transistors SST and DST, and each of the memory cells MC1 to MCn, can have similar structures. As an embodiment, each of the selected transistors SST and DST, and each of the memory cells MC1 to MCn, may include a channel layer, a tunneling insulating film, a charge storage film, and a barrier insulating film. As an embodiment, pillars for providing the channel layer may be provided in each cell string. As an embodiment, pillars for providing at least one of the channel layer, tunneling insulating film, charge storage film, and barrier insulating film may be provided in each cell string.

[0050] The source selection transistor SST of each cell string is connected between the common source line CSL and memory cells MC1 to MCp.

[0051] As an implementation, source selection transistors of cell strings arranged in the same row are connected to source selection lines extending in the row direction, and source selection transistors of cell strings arranged in different rows are connected to different source selection lines. Figure 4 In the first row, the source selection transistors CS11 to CS1m are connected to the first source selection line SSL1. The source selection transistors CS21 to CS2m in the second row are connected to the second source selection line SSL2.

[0052] In another implementation, the source selection transistors of cell strings CS11 to CS1m and CS21 to CS2m can be connected together to a single source selection line.

[0053] The first memory cell MC1 to the nth memory cell MCn of each cell string are connected between the source selection transistor SST and the drain selection transistor DST.

[0054] The first memory cells MC1 to the nth memory cell MCn can be divided into first memory cells MC1 to the pth memory cells MCp and (p+1)th memory cells MCp+1 to the nth memory cells MCn. The first memory cells MC1 to the pth memory cells MCp are arranged sequentially in the direction opposite to the +Z direction and connected in series between the source selection transistor SST and the transistor PT. The (p+1)th memory cells MCp+1 to the nth memory cells MCn are arranged sequentially in the +Z direction and connected in series between the transistor PT and the drain selection transistor DST. The first memory cells MC1 to the pth memory cells MCp and the (p+1)th memory cells MCp+1 to the nth memory cells MCn are connected to each other via the transistor PT. The gates of the first memory cells MC1 to the nth memory cells MCn in each cell string are respectively connected to the first word line WL1 to the nth word line WLn.

[0055] The gate of the tubular transistor PT in each cell string is connected to the pipeline PL.

[0056] The drain select transistor (DST) of each cell string is connected between the corresponding bit line and memory cells MCp+1 to MCn. The DSTs of cell strings arranged along the row direction are connected to drain select lines extending in the row direction. The drain select transistors of cell strings CS11 to CS1m in the first row are connected to the first drain select line DSL1. The drain select transistors of cell strings CS21 to CS2m in the second row are connected to the second drain select line DSL2.

[0057] A string of cells arranged along the column direction is connected to a bit line extending along the column direction. Figure 4 In the diagram, the cell strings CS11 and CS21 of the first column are connected to the first bit line BL1. The cell strings CS1m and CS2m of the m-th column are connected to the m-th bit line BLm.

[0058] Memory cells connected to the same word line in a cell string arranged in a row direction constitute a page. For example, memory cells connected to the first word line WL1 in cell strings CS11 to CS1m in the first row constitute one page. Memory cells connected to the first word line WL1 in cell strings CS21 to CS2m in the second row constitute another page. A cell string arranged in a row direction can be selected by selecting either drain select line DSL1 or DSL2. A page in the selected cell string can be selected by selecting any of the word lines WL1 to WLn.

[0059] As another implementation, even-numbered bit lines and odd-numbered bit lines can be provided to replace the first bit line BL1 to the m-th bit line BLm. Additionally, the even-numbered cell strings CS11 to CS1m or CS21 to CS2m arranged in the row direction can be connected to the even-numbered bit lines, and the odd-numbered cell strings CS11 to CS1m or CS21 to CS2m arranged in the row direction can be connected to the odd-numbered bit lines.

[0060] As an implementation, at least one of the first memory cells MC1 to the nth memory cell MCn can be used as a dummy memory cell. For example, at least one dummy memory cell is provided to reduce the electric field between the source selection transistor SST and the memory cells MC1 to MCp. Alternatively, at least one dummy memory cell is provided to reduce the electric field between the drain selection transistor DST and the memory cells MCp+1 to MCn. Providing more dummy memory cells improves the operational reliability of the memory block BLKa; however, it increases the size of the memory block BLKa. Conversely, providing fewer dummy memory cells reduces the size of the memory block BLKa; however, it may decrease the operational reliability of the memory block BLKa.

[0061] To efficiently control at least one dummy memory cell, each dummy memory cell can have a desired threshold voltage. Programming operations can be performed on all or some of the dummy memory cells before or after the erase operation of the memory block BLKa. When an erase operation is performed after programming, the dummy memory cells can have the desired threshold voltage by controlling the voltage applied to the dummy word line connected to the corresponding dummy memory cell.

[0062] Figure 5 This is an example Figure 3 A circuit diagram of another embodiment of any one of the storage blocks BLK1 to BLKz, BLKb.

[0063] Reference Figure 5 The memory block BLKb includes multiple cell strings CS11′ to CS1m′ and CS21′ to CS2m′. Each of the multiple cell strings CS11′ to CS1m′ and CS21′ to CS2m′ extends along the +Z direction. Each of the multiple cell strings CS11′ to CS1m′ and CS21′ to CS2m′ includes at least one source selection transistor SST, a first memory cell MC1 to the nth memory cell MCn, and at least one drain selection transistor DST stacked on a substrate (not shown) beneath the memory block BLK1′.

[0064] The source select transistor SST of each cell string is connected between the common source line CSL and memory cells MC1 to MCn. The source select transistors of cell strings arranged in the same row are connected to the same source select line. The source select transistors of cell strings CS11' to CS1m' arranged in the first row are connected to the first source select line SSL1. The source select transistors of cell strings CS21' to CS2m' arranged in the second row are connected to the second source select line SSL2. Alternatively, the source select transistors of cell strings CS11' to CS1m' and CS21' to CS2m' can be connected to a single source select line.

[0065] The first memory cell MC1 to the nth memory cell MCn in each cell string are connected in series between the source select transistor SST and the drain select transistor DST. The gates of the first memory cell MC1 to the nth memory cell MCn are respectively connected to the first word line WL1 to the nth word line WLn.

[0066] The drain select transistor (DST) of each cell string is connected between the corresponding bit line and memory cells MC1 to MCn. The drain select transistors of cell strings arranged along the row direction are connected to drain select lines extending in the row direction. The drain select transistors of cell strings CS11' to CS1m' in the first row are connected to the first drain select line DSL1. The drain select transistors of cell strings CS21' to CS2m' in the second row are connected to the second drain select line DSL2.

[0067] As a result, in addition to excluding the tubular transistor PT from each cell string, Figure 5 The storage block BLKb has the same characteristics as Figure 4 The equivalent circuit of the storage block BLKa is similar to the equivalent circuit.

[0068] As another implementation, even-numbered bit lines and odd-numbered bit lines can be provided to replace the first bit line BL1 to the m-th bit line BLm. Additionally, the even-numbered cell strings among the cell strings CS11′ to CS1m′ or CS21′ to CS2m′ arranged in the row direction can be connected to the even-numbered bit lines, and the odd-numbered cell strings among the cell strings CS11′ to CS1m′ or CS21′ to CS2m′ arranged in the row direction can be connected to the odd-numbered bit lines.

[0069] As an implementation, at least one of the first memory cells MC1 to the nth memory cell MCn can be used as a dummy memory cell. For example, at least one dummy memory cell is provided to reduce the electric field between the source selection transistor SST and the memory cells MC1 to MCn. Alternatively, at least one dummy memory cell is provided to reduce the electric field between the drain selection transistor DST and the memory cells MC1 to MCn. Providing more dummy memory cells improves the operational reliability of the memory block BLKb; however, it increases the size of the memory block BLKb. Providing fewer memory cells reduces the size of the memory block BLKb; however, it may reduce the operational reliability of the memory block BLKb.

[0070] To efficiently control at least one dummy memory cell, each dummy memory cell can have a desired threshold voltage. Programming operations can be performed on all or some of the dummy memory cells before or after the erase operation of memory block BLKb. When an erase operation is performed after programming, the dummy memory cells can have the desired threshold voltage by controlling the voltage applied to the dummy word line connected to the corresponding dummy memory cell.

[0071] Figure 6 This is an example Figure 2 A circuit diagram illustrating an implementation of any one of the multiple memory blocks BLK1 to BLKz, BLKc, included in the memory cell array 110.

[0072] Reference Figure 6 The memory block BLKc includes multiple cell strings CS1 to CSm. The multiple cell strings CS1 to CSm can be connected to multiple bit lines BL1 to BLm respectively. Each of the cell strings CS1 to CSm includes at least one source selection transistor SST, a first memory cell MC1 to an nth memory cell MCn, and at least one drain selection transistor DST.

[0073] The selected transistors SST and DST, and each of the memory cells MC1 to MCn, can have similar structures. As an embodiment, each of the selected transistors SST and DST, and each of the memory cells MC1 to MCn, may include a channel layer, a tunneling insulating film, a charge storage film, and a barrier insulating film. As an embodiment, pillars for providing the channel layer may be provided in each cell string. As an embodiment, pillars for providing at least one of the channel layer, tunneling insulating film, charge storage film, and barrier insulating film may be provided in each cell string.

[0074] The source selection transistor SST of each cell string is connected between the common source line CSL and memory cells MC1 to MCn.

[0075] The first memory cell MC1 to the nth memory cell MCn of each cell string are connected between the source selection transistor SST and the drain selection transistor DST.

[0076] The drain selection transistor (DST) of each cell string is connected between the corresponding bit line and memory cells MC1 to MCn.

[0077] Memory cells connected to the same word line constitute a page. Cell strings CS1 to CSm can be selected by choosing the drain select line DSL. A page within the selected cell string can be selected by choosing any one of the word lines WL1 to WLn.

[0078] As another implementation, even-numbered bit lines and odd-numbered bit lines can be provided to replace the first bit line BL1 to the m-th bit line BLm. The even-numbered cell strings among the cell strings CS1 to CSm can be connected to the even-numbered bit lines respectively, and the odd-numbered cell strings can be connected to the odd-numbered bit lines respectively.

[0079] Figure 7 This is a diagram illustrating pages and strings of cells formed by memory cells included in a memory cell array.

[0080] Reference Figure 7 The storage block comprises the first unit string CS1 to the m-th unit string CSm. The first unit string CS1 comprises n memory units MC. 11 To MC n1 The second unit string CS2 also includes n memory units MC. 12 To MC n2 Following this method, the m-th unit string CSm can include n memory units MC. 1m To MC nm .

[0081] In addition, the first page PG1 includes m memory cells MC. 11 To MC 1m Page 2, PG2, also includes m memory cells MC. 21 To MC 2m Following this method, page n, PGn, includes m memory units MC. n1 To MC nm .

[0082] Read operations on the semiconductor memory device 100 can be performed on a page-by-page basis. Therefore, any page from the first to the nth page can be selected as the read target. Figure 7 In the example, page i, PGe, can be the selected page PG that is the target of the read. Page i, PGe, includes the first memory cell MC. i1 Up to the m-th memory cell MC im .

[0083] Figure 8 This is a graph illustrating the threshold voltage distribution Vth of an MLC. Specifically, Figure 8 The threshold voltage distribution is shown immediately after programming the selected page PG. Each memory cell in an MLC storing two bits of data can be programmed into any of four states, depending on the bit data to be stored.

[0084] Figure 8 An implementation of an example mapping of four states based on logic code is shown. (Refer to...) Figure 8 Memory cells with both the least significant bit (LSB) and most significant bit (MSB) set to 1 remain in the erase state E. Memory cells with LSB set to 1 and MSB set to 0 are programmed into the first programming state PV1. Memory cells with LSB set to 0 and MSB set to 0 are programmed into the second programming state PV2. Memory cells with LSB set to 0 and MSB set to 1 are programmed into the third programming state PV3. That is, in Figure 8 In the logic code shown, based on the LSB-MSB order, data "11" is mapped to the erase state E, data "10" is mapped to the first programming state PV1, data "00" is mapped to the second programming state PV2, and data "01" is mapped to the third programming state PV3. However, this is exemplary and can be used with... Figure 8 The various logic codes shown are different.

[0085] Typical read operations can be performed to read data stored in memory cells. In this case, data programmed into the memory cells included in the selected page can be read using a first read voltage R1, a second read voltage R2, and a third read voltage R3.

[0086] As another example, a read operation can be performed to detect the threshold voltage distribution of memory cells included in the selected page. As described above, Figure 8 The threshold voltage distribution of a memory cell immediately following a programming operation is shown. However, after a programming operation is performed on the selected page PG, the threshold voltage distribution of the memory cell may change for various reasons. In many cases, it is necessary to detect this changed threshold voltage distribution. For example, in a test operation of the semiconductor memory device 100, the changed threshold voltage distribution of the memory cell can be detected and analyzed. For this purpose, it is necessary to repeatedly perform sensing operations using voltages of various amplitudes on the selected page.

[0087] In this specification, a read operation is defined as an operation to read data stored in a memory cell. Conversely, a sensing operation is defined as an operation to determine whether a threshold voltage of a memory cell is greater than a specific sensing voltage. However, since there is no significant difference between read and sensing operations in actual operation, they can be used interchangeably in this specification. More specifically, in the case of SLC, the data read operation can consist of a single sensing operation. In the case of MLC, to read both LSB and MSB data, three sensing operations—a first read voltage R1, a second read voltage R2, and a third read voltage R3—may be required. That is, according to an embodiment, a read operation on a selected page may include at least one sensing operation.

[0088] Figure 9A This is a graph illustrating the changing state of the threshold voltage distribution of an MLC. Figure 9B It is a table that lists the threshold voltages of the memory cells corresponding to each column of the selected page.

[0089] exist Figure 8 The diagram shows the threshold voltage distribution immediately following the programming operation, including the erase state E and the first programming states P1 through P3. (Refer to...) Figure 9A ,and Figure 8 In comparison, it can be seen that the threshold voltage distribution has been altered. Figure 9A The threshold voltage distribution is illustrated, including the altered erase state E′ and the first programming state PV1′ to the third programming state PV3′.

[0090] Figure 9A The selected page is shown (e.g., Figure 7 The altered threshold voltage distribution of the memory cells included in the selected page (PG) is shown. That is, Figure 9A It shows Figure 7 The selected page PG includes the threshold voltage distribution of the first memory cell MCi1 to the m-th memory cell MCim. For example, the position indicating the threshold voltage of the first memory cell MCi1 is indicated as ①. Additionally, the position indicating the threshold voltage of the second memory cell MCi2 is indicated as ②. Following this method, the positions indicating the threshold voltages of the third memory cell MCi3, the fourth memory cell MCi4, and the fifth memory cell MCi5 can be indicated as ③, ④, and ⑤, respectively. Following this method, the position indicating the threshold voltage of the m-th memory cell MCim can also be determined by… instruct.

[0091] For the selected page PG, the threshold voltage distribution of the memory cell can be detected by using multiple sensing operations with multiple different sensing voltages. For example... Figure 9AAs shown, the form of the threshold voltage distribution of the memory cell belonging to the selected page PG can be detected through multiple sensing operations via multiple sensing voltages Va, Vb, Vc, ... and Vz.

[0092] However, in this case, it is impossible to distinguish which state the threshold voltage of a memory cell located near the boundary of multiple states belongs to. For example, according to Figure 9A The contents shown may not be clear whether the first memory cell MCI1 located in ① belongs to the memory cell in the erase state E′ or the memory cell in the first programming state PV1′.

[0093] As described above, in order to understand the changes in the threshold voltage distribution for each state, after detecting the threshold voltage distribution of the memory cells belonging to the selected page, it is necessary to match the threshold voltage distribution with the data originally stored in the memory cells. Typically, the test device or controller 200 programs data into the selected page of the semiconductor memory device 100. The test device or controller 200 retains the data. Subsequently, the test device or controller 200 controls the semiconductor memory device 100 to perform multiple sensing operations using multiple sensing voltages Va, Vb, Vc, ..., and Vz. Based on the multiple sensing operations, the test device or controller 200 can obtain data regarding the entire threshold voltage distribution for the undivided states. The test device or controller 200 can extract the threshold voltage distribution for each state by matching the obtained data regarding the threshold voltage distribution with the data retained within it.

[0094] In other words, the test device or controller 200 can maintain the following: Figure 9B The data shown. Referring to 9B, the LSB and MSB data corresponding to each of the first memory cells MCi1 to m-th memory cells MCim of the selected page are shown. Figure 9A The threshold voltage of the memory cell corresponding to column ① is detected at position ①. Furthermore, the original test data stored in the memory cell corresponding to column ① has an LSB of 1 and an MSB of 0 corresponding to the first programming state PV1′. As described above, the test device or controller 200 can distinguish the data stored therein from the target state PV1′. Figure 9A The threshold voltage of the first memory cell MCI1 corresponding to position ① shown is the first programming state PV1′ instead of the erase state E′.

[0095] Figure 10A This is a graph illustrating the threshold voltage distribution corresponding to the erase state E′ among the detected threshold voltage distributions. Figure 10B This is a graph illustrating the threshold voltage distribution corresponding to the first programming state PV1′ among the detected threshold voltage distributions. Figure 10CThis is a graph illustrating the threshold voltage distribution corresponding to the second programming state PV2′ among the detected threshold voltage distributions. Figure 10D This is a graph illustrating the threshold voltage distribution corresponding to the third programming state PV3′ among the detected threshold voltage distributions.

[0096] As mentioned above, it can be achieved by using, for example Figure 9B The table shown matches the raw data to threshold voltage distribution data obtained by performing multiple sensing operations via multiple sensing voltages Va, Vb, Vc, ..., Vz, to extract the threshold voltage distribution for each state. For example, in the obtained threshold voltage distribution data, when from... Figure 9B When only the data corresponding to the columns where LSB is 1 and MSB is 1 (including ②) are extracted from the columns shown in the table, threshold voltage distribution data indicating only the erase state E′ can be obtained, such as... Figure 10A As shown. Using a similar method, in the obtained threshold voltage distribution data, when from... Figure 9B The table shown extracts only the columns where LSB is 1 and MSB is 0 (including ① and ②). When the corresponding data is obtained, threshold voltage distribution data indicating only the first programming state PV1′ can be obtained, such as Figure 10B As shown. Additionally, in the obtained threshold voltage distribution data, when from... Figure 9B When only the data corresponding to the columns where LSB is 0 and MSB is 0 (including ③) is extracted from the columns shown in the table, threshold voltage distribution data indicating only the second programming state PV2′ can be obtained, such as... Figure 10C As shown. Finally, in the obtained threshold voltage distribution data, when from Figure 9B When only the data corresponding to the columns where LSB is 0 and MSB is 1 (including ④ and ⑤) are extracted from the columns shown in the table, threshold voltage distribution data indicating only the third programming state PV3′ can be obtained, such as... Figure 10D As shown.

[0097] However, according to the above method, all sensing results obtained by performing multiple sensing operations via multiple sensing voltages Va, Vb, Vc, ..., Vz need to be output to the controller 200 or the testing device. With this method, a significant amount of time is spent outputting the data generated as a result of the multiple sensing operations to the controller 200 or the testing device and comparing the data with the original data. Specifically, when outputting the result data of multiple sensing operations to a testing device that may not output high-speed data, calculating the threshold voltage distribution for each programmed state takes a long time.

[0098] According to embodiments of the present disclosure, a semiconductor memory device outputs a sensing result by storing raw data in latch circuitry included in a plurality of page buffers and masking the target state for each of a plurality of sensing operations. Therefore, the operation of detecting the threshold voltage distribution of each of the plurality of states can be performed quickly.

[0099] Figure 11A This is a graph illustrating the detection operation of the threshold voltage distribution when the first programming state PV1′ is the target state. Figure 11B This is a table illustrating methods for deriving the threshold voltage distribution within each voltage range based on the results of multiple sensing operations.

[0100] Reference Figure 11A When the first programming state PV1′ is the target state, approximately the first voltage V1 to the Pth voltage VP can be determined as the sensed voltage. However, this is an example, and the distribution of the first programming state PV1′ is expected to be... Figure 11A When the distribution is wider, the amplitude of the first voltage V1 can be further reduced and the amplitude of the Pth voltage VP can be further increased. Conversely, when the distribution of the first programming state PV1′ is wider than expected... Figure 11A When the distribution is narrower, the first voltage V1 can be further increased and the P-th voltage VP can be further decreased.

[0101] Alternatively, when the distribution of the first programming state PV1′ is expected to be higher than... Figure 11A When the distribution deviates to the right, the amplitudes of the first voltage V1 and the Pth voltage VP can be further increased.

[0102] Sensing operations using P sensing voltages can be performed. The number P can be determined in various ways as needed. When the size of P is large, the threshold voltage distribution can be detected at a higher resolution, but the detection time increases. When the size of P is small, the detection time can be reduced, but the resolution of the threshold voltage distribution decreases.

[0103] Reference Figure 11B First, a method for detecting a memory cell having a threshold voltage between V1 and V2 as a result of a sensing operation via a first voltage V1 and a second voltage V2 is described.

[0104] When the first sensing operation (SEN) is performed using the first voltage V1, the detection value of memory cells with a threshold voltage lower than the first voltage V1 becomes 1, while the detection value of memory cells with a threshold voltage higher than the first voltage V1 becomes 0. Figure 11B In the example, because the threshold voltage of the memory cell corresponding to column ② is lower than the first voltage V1, the result value of the first sensing SEN corresponding to column ② becomes 1. Furthermore, because the threshold voltage of columns ①, ③, ④, ⑤, and ⑥ is lower than the first voltage V1, the result value of the first sensing SEN corresponding to column ② becomes 1. The threshold voltage of the corresponding memory cell is higher than the first voltage V1, so it is related to columns ①, ③, ④, ⑤ and ⑥. The corresponding result value of the first sensor, the first SEN, becomes 0.

[0105] Furthermore, when the second sensing operation (SEN) is performed using the second voltage V2, the detection value of memory cells with a threshold voltage lower than the second voltage V2 becomes 1, while the detection value of memory cells with a threshold voltage higher than the second voltage V2 becomes 0. Figure 11B For example, since the threshold voltage of the memory cells corresponding to columns ① and ② is lower than the second voltage V2, the result value of the second sensing 2SEN corresponding to columns ① and ② becomes 1. Furthermore, since the threshold voltage of the memory cells corresponding to columns ③, ④, ⑤, and ② is lower than the second voltage V2, the result value of the second sensing 2SEN becomes 1. The threshold voltage of the corresponding memory cell is higher than the second voltage V2, therefore it is related to columns ③, ④, ⑤, and ⑥. The corresponding result value of the second sensor, the second SEN, becomes 0.

[0106] The threshold voltage of the memory cell between intervals V1 and V2 is greater than the first voltage V1 and less than the second voltage V2. That is, when the result values ​​of the first sensing first SEN using the first voltage V1 and the second sensing second SEN using the second voltage V2 are subjected to an XOR operation, the value of the column corresponding to the memory cell with the threshold voltage between intervals V1 and V2 becomes 1, and the value of the column corresponding to the memory cell with the threshold voltage of the remaining intervals becomes 0.

[0107] In order to detect memory cells whose threshold voltage belongs to the interval V2 to V3, a sensing operation using a third voltage V3 is performed, and an XOR operation is performed on the result of the sensing operation and the second sensing 2 SEN.

[0108] When a sensing operation using a first voltage V1 and a second voltage V2 is performed, the number of memory cells with threshold voltages between V1 and V2 among all memory cells belonging to the selected page can be detected. However, in this case, memory cells belonging to the erase state E′ may also be included among memory cells with threshold voltages between V1 and V2. Therefore, in order to detect only the distribution of memory cells corresponding to the first programming state PV1′, a masked sensing operation needs to be applied to the first programming state PV1′. In the following text, reference will be made to... Figure 12A , Figure 12B and Figure 12C Describes the sensing operation that applies masking to the target state.

[0109] Figure 12AThis is a circuit diagram illustrating a page buffer according to an embodiment of the present disclosure, capable of detecting the threshold voltage distribution of an MLC by masking for each target state. Figure 12B It is a table that represents the bit data stored in the latches in the page buffer for each target state. Figure 12C This is a table that illustrates the transmission control signals used to mask the corresponding target state for each target state.

[0110] Reference Figure 12A The circuit diagram shown is an example of a page buffer. Figure 2 The first page buffer PB1 to the m-th page buffer PBm shown can be implemented as follows: Figure 12A The circuit shown. Figure 2 The first page buffer PB1 to the m-th page buffer PBm shown may also include, in addition to Figure 12A Other components besides the circuit shown. In the following description, based on the page buffer PB1 connected to the first bit line BL1.

[0111] The page buffer may include a first latch circuit LC1, a second latch circuit LC2, and a sensing latch circuit LCS. The first latch circuit LC1 may include a first latch L1 and first transistors T1 through T6. The second latch circuit LC2 may include a second latch L2 and seventh transistors T7 through Twelfth transistors T12. The sensing latch circuit LCS may include a sensing latch LS and thirteenth transistors T13 through sixteenth transistors T16. The first latch circuit LC1, the second latch circuit LC2, and the sensing latch circuit LCS may be connected to a sensing output node SO. Furthermore, the page buffer may also include a seventeenth transistor T17 connected between the sensing output node SO and the bit line BL1. The seventeenth transistor T17 may be controlled by the page buffer sensing signal PBSENSE. In this specification, the seventeenth transistor T17 may be referred to as the "page buffer sensing transistor".

[0112] Referring to the first latch circuit LC1, the first transistor T1 is connected between node Q1 of the first latch L1 and ground, and the second transistor T2 is connected between node Q1 of the first latch L1. N Between the ground node and the sensor output node SO, the first transistor T1 is controlled by the first reset signal RST1, and the second transistor T2 is controlled by the first set signal SET1. Furthermore, the third transistor T3 and the fourth transistor T4 are connected sequentially between the ground node and the sensor output node SO. The third transistor T3 is controlled by the voltage at node Q1 of the first latch L1, while the fourth transistor T4 is controlled by the first transmission control signal TRAN. AControl. Additionally, the fifth transistor T5 and the sixth transistor T6 are connected sequentially between the ground node and the sensing output node SO. The fifth transistor T5 is connected to node Q1 of the first latch L1. N The voltage control of the fourth transistor T4 is controlled by the second transmission control signal TRAN. B control.

[0113] Referring to the second latch circuit LC2, the seventh transistor T7 is connected between node Q2 of the second latch L2 and ground, while the eighth transistor T8 is connected between node Q2 of the second latch L2. N Between the ground node and the sensor output node SO, the seventh transistor T7 is controlled by the second reset signal RST2, while the eighth transistor T8 is controlled by the second set signal SET2. Furthermore, the ninth transistor T9 and the tenth transistor T10 are connected sequentially between the ground node and the sensor output node SO. The ninth transistor T9 is controlled by the voltage at node Q2 of the second latch L2, while the tenth transistor T10 is controlled by the third transmission control signal TRAN. C Control. Additionally, the eleventh transistor T11 and the twelfth transistor T12 are connected sequentially between the ground node and the sensing output node SO. The eleventh transistor T11 is connected to node Q2 of the second latch L2. N The voltage control of the twelfth transistor T12 is controlled by the fourth transmission control signal TRAN. D control.

[0114] Referring to the sense latch circuit LCS, the thirteenth transistor T13 is connected between nodes QS and QR of the sense latch LS, while the fourteenth transistor T14 is connected at node QS. N The thirteenth transistor T13 is controlled by the third reset signal RST3, while the fourteenth transistor T14 is controlled by the third set signal SET3. Furthermore, the fifteenth transistor T15 is connected between node QS and the sense output node SO. The fifteenth transistor T15 is controlled by the sense transmission control signal TRAN. S Control. Additionally, the sixteenth transistor T16 is connected between node QR and the ground node. The sixteenth transistor T16 is controlled by sensing the voltage at output node SO.

[0115] All control signals applied to the page buffer can be received from control logic 140.

[0116] First, for each state of masking, the controller 200 or the test device can send the raw data stored in the selected page PG to the semiconductor memory device 100. The semiconductor memory device 100 stores the received raw data in multiple page buffers.

[0117] More specifically, in the original data, the data stored in the first memory cell MCI1 is stored in the first latch L1 and the second latch L2 of the page buffer connected to the first bit line BL1. The first latch L1 and the second latch L2 can be referred to as "data latches". In the case of MLC, since two bits of data are stored in a memory cell, the corresponding page buffer also needs to store two bits of data. In the implementation, the LSB can be stored in the first latch L1 of the page buffer, and the MSB can be stored in the second latch L2.

[0118] exist Figure 9A , Figure 9B , Figure 11A and Figure 11B In the above example, in the column corresponding to the first memory cell MCI1 In this case, the LSB is 1 and the MSB is 0. Therefore, the bit data that is 1 can be stored in... Figure 12A In the first latch L1, bits that are 0 can be stored in the second latch L2. Since bits that are 1 are stored in the first latch L1, node Q1... N The voltage of node Q1 can be a logic high voltage corresponding to a bit value of "1", while the voltage of node Q2 can be a logic low voltage corresponding to a bit value of "0". Since the bit data of value 0 is stored in the second latch L2, node Q2... N The voltage of node Q1 can be a logic low voltage corresponding to a bit value of "0", and the voltage of node Q2 can be a logic high voltage corresponding to a bit value of "1".

[0119] Reference Figure 12B The bit data values ​​to be stored in the first latch L1 and the second latch L2, corresponding to the states E′ and PV1′ to PV3′ of the memory cells, are shown in the table. That is, node Q1 of the first latch L1... N The voltage indicator LSB, and the node Q2 of the second latch L2. N The voltage indicator MSB.

[0120] For each of the first page buffer PB1 to the m-th page buffer PBm, a first reset control signal RST1 and a second reset control signal RST2, as well as a first set control signal SET1 and a second set control signal SET2, can be appropriately applied to store the raw data received from the controller 200 or the test device.

[0121] First, the unmasked sensing results are stored in the sensing latch LS of each page buffer. For example, this can be achieved by applying a word line connected to the selected page PG. Figure 11AThe first voltage V1 shown is used to perform threshold voltage sensing operations on memory cells MCi1 to MCim.

[0122] For example, due to the column The threshold voltage of the corresponding first memory cell MCi1 is greater than the first voltage V1, so the node QS of the sense latch LS connected to the first page buffer PB1 of the first bit line BL1... N The voltage can be a logic low voltage corresponding to a bit value of "0", and the voltage of node QS can be a logic high voltage corresponding to a bit value of "1".

[0123] Furthermore, since the threshold voltage of the second memory cell MCI2 corresponding to column ② is less than the first voltage V1, the node QS of the sensing latch LS connected to the second page buffer PB2 of the second bit line BL2 is... N The voltage can be a logic high voltage corresponding to a bit value of "1", and the voltage of node QS can be a logic low voltage corresponding to a bit value of "0".

[0124] Therefore, the sensing data of the target state that is not masked is stored in the sensing latches LS of the first page buffer PB1 to the m-th page buffer PBm.

[0125] Subsequently, the value of the sense latch LS in each page buffer is sent to the sense output node SO for masking the target state. The fifteenth transistor T15 included in each page buffer is turned on to send the voltage of node QS to the sense output node SO. When the voltage of the sense output node SO is logic high as a result of this transmission, it means that node QS... N The voltage of the sensor is logic low, therefore the threshold voltage of the memory cell is greater than the first voltage V1. Conversely, when the voltage of the sensing output node SO is logic low, this means that node QS... N The voltage is logic high, therefore the threshold voltage of the memory cell is less than the first voltage V1.

[0126] With the value of the sense latch LS sent to the sense output node SO, target state masking can be performed. Assume the target state is the first programming state PV1′. In this case, it is necessary to remove the values ​​of the sense output node SO of the page buffers corresponding to the erase state E′, the second programming state PV2′, and the third programming state PV3′. Furthermore, it is necessary to maintain the value of the sense output node SO of the page buffer corresponding to the first programming state PV1′.

[0127] Therefore, the first transmission control signal TRAN A and the fourth transmission control signal TRAN D It is activated, and the second transmission control signal TRANB and the third transmission control signal TRAN C The transistors are deactivated. Therefore, the fourth transistor T4 and the twelfth transistor T12 in all page buffers are turned on, while the sixth transistor T6 and the tenth transistor T10 are turned off.

[0128] In the case of the first page buffer, as described above, node Q1 N The voltage of node Q1 can be a logic high voltage, while the voltage of node Q2 can be a logic low voltage. Furthermore, node Q2... N The voltage at node SO can be a logic low voltage, while the voltage at node Q2 can be a logic high voltage. Therefore, transistors T3 and T11 are off, while transistors T5 and T9 are on. Thus, all paths between the sensing output node SO and the ground node remain blocked, thereby maintaining the voltage at the sensing output node SO.

[0129] Furthermore, in the case of the second page cache, the original data stored in the memory cell corresponding to column ② is "11". Therefore, node Q1 N The voltage of node Q1 can be a logic high voltage, and the voltage of node Q2 can be a logic low voltage. Additionally, node Q2... N The voltage at node Q1 can be a logic high voltage, and the voltage at node Q2 can be a logic low voltage. Therefore, the third transistor T3 and the ninth transistor T9 are off, while the fifth transistor T5 and the eleventh transistor T11 are on. Due to the fourth transmission control signal TRAN... D When activated and the twelfth transistor T12 is turned on, the sensing output node SO of the second page buffer is electrically connected to the ground node. Therefore, regardless of the value stored in the sensing latch LS of the second page buffer, the voltage of the sensing output node SO becomes a logic low voltage indicating 0.

[0130] When comparing the first page buffer and the second page buffer, the first page buffer stores the LSB and MSB data corresponding to the first programming state PV1′ in the first latch L1 and the second latch L2, respectively. Therefore, by masking the first transmission control signal TRAN of the first programming state PV1′... A To the fourth transmission control signal TRAN D In this combination, the sensing output node SO is not connected to the ground node. Therefore, the voltage of the sensing output node SO is maintained.

[0131] On the other hand, the second page buffer stores the LSB and MSB data corresponding to the erase state E′ in the first latch L1 and the second latch L2, respectively. Therefore, by masking the first transmission control signal TRAN of the first programming state PV1′... A To the fourth transmission control signal TRAN DWith this combination, the eleventh transistor T11 and the twelfth transistor T12 are turned on, and the sensing output node SO is connected to the ground node. Therefore, regardless of the value stored in the sensing latch LS of the second page buffer, the voltage of the sensing output node SO becomes a logic low voltage indicating 0.

[0132] By analogy with the above description, in the case of the third page buffer, since the LSB and MSB data corresponding to the second programming state PV2′ are stored in the first latch L1 and the second latch L2 respectively, the first transmission control signal TRAN of the first programming state PV1′ is masked. A To the fourth transmission control signal TRAN D In this combination, the third transistor T3 and the fourth transistor T4 can be turned on and the sensing output node SO can be connected to the ground node.

[0133] Furthermore, in the case of the fourth page buffer, since the LSB and MSB data corresponding to the third programming state PV3′ are stored in the first latch L1 and the second latch L2 respectively, the first transmission control signal TRAN of the first programming state PV1′ is masked. A To the fourth transmission control signal TRAN D The combination of transistors T3 and T4, as well as transistors T11 and T12, allows the third transistor T3 and the fourth transistor T4, along with the eleventh transistor T11 and the twelfth transistor T12, to conduct and the sensing output node SO to be connected to the ground node.

[0134] In summary, the first transmission control signal TRAN of the first programming state PV1′ is masked. A To the fourth transmission control signal TRAN D The combination maintains the voltage of the sensing output node SO of the page buffer connected to the memory cell corresponding to the first programming state PV1′. On the other hand, the first transfer control signal TRAN of the first programming state PV1′ is masked. A To the fourth transmission control signal TRAN D The combination connects the sensing output node SO of the page buffer, which is connected to the memory cell corresponding to the erase state E′, the second programming state PV2′, and the third programming state PV3′, to the ground node. Therefore, the sensing results corresponding to the erase state E′, the second programming state PV2′, and the third programming state PV3′ are removed.

[0135] While performing masking for the first programming state PV1′, the number of page buffers from the first page buffer PB1 to the m-th page buffer PBm where the voltage of the sensed output node SO is in a logic high state is counted. More specifically, the bit data corresponding to the voltage of the sensed output node SO can be stored in a sense latch LS, and the masked bit data can be counted among the bit data of the sense latch LS included in the multiple page buffers. Therefore, the number of memory cells belonging to the first programming state PV1′ can be counted among memory cells having a threshold voltage greater than the read voltage used in the sensing operation.

[0136] although Figure 12A Not shown, but such a counting operation can be performed by any counting circuit. The counting result can be sent to the controller 200. Thus, from the sensing result using the first voltage V1, the sensing result of the memory cell corresponding only to the first programming state PV1′ can be extracted.

[0137] The above description pertains to the case where the target state is the first programming state PV1′. Masking is also feasible when the target state is the erase state E′, the second programming state PV2′, or the third programming state PV3′. (See also...) Figure 12C The first transmission control signal TRAN is applied to each of the erase state E′, the first programming state PV1′, the second programming state PV2′, and the third programming state PV3′. A To the fourth transmission control signal TRAN D The combinations are shown in the table. For example, when the target state is the erase state E′, the first transmission control signal TRAN... A and the third transmission control signal TRAN C Activated by the on-state voltage, while the second transmission control signal TRAN B and the fourth transmission control signal TRAN D Keep it off using the cutoff voltage.

[0138] When the target state is the second programming state PV2′, the second transmission control signal TRAN B and the fourth transmission control signal TRAN D Activated by the on-state voltage, while the first transmission control signal TRAN A and the third transmission control signal TRAN C Keep it off using the cutoff voltage.

[0139] When the target state is the third programming state PV3′, the second transmission control signal TRAN B and the third transmission control signal TRAN C Activated by the on-state voltage, while the first transmission control signal TRANA and the fourth transmission control signal TRAN D Keep it off using the cutoff voltage.

[0140] Figure 13A This is a graph illustrating the threshold voltage distribution of the memory cells detected when the first programming state PV1′ is masked as the target state. Figure 13B This is a graph illustrating the threshold voltage distribution of the memory cells detected in a state where the third programming state PV3′ is masked as the target state.

[0141] Reference Figure 13A The diagram illustrates the threshold voltage distribution of memory cells detected in a state where the first programming state PV1′ is masked as a target state. As described above, when the first programming state PV1′ is masked as a target state, only the threshold voltage distribution of memory cells corresponding to the first programming state PV1′ can be detected, in addition to the threshold voltage sensing results of memory cells corresponding to the erase state E′ and the second programming states PV2′ and the third programming state PV3′.

[0142] Reference Figure 13B The diagram illustrates the threshold voltage distribution of memory cells detected in a state where the third programming state PV3′ is masked as a target state. As described above, when the third programming state PV3′ is masked as a target state, in addition to the threshold voltage sensing results of memory cells corresponding to the erase state E′, the first programming state PV1′, and the second programming state PV2′, only the threshold voltage distribution results of memory cells corresponding to the third programming state PV3′ can be detected.

[0143] Figure 14 This is a flowchart illustrating a method of operating a semiconductor memory device according to an embodiment of the present disclosure.

[0144] Reference Figure 14 A method for operating a semiconductor memory device according to an embodiment of the present disclosure includes selecting a target state to detect a threshold voltage distribution (S110), determining a plurality of read voltages for dividing the voltage range to which the threshold voltage of the selected target state is distributed (S130), and performing a plurality of sensing operations using the plurality of read voltages on the selected page (S150).

[0145] In step S110, the target state to be extracted by masking can be selected. The target state can be selected internally within the semiconductor memory device 100 or by commands received from the controller 200 or the testing device. For example, as shown in reference... Figures 11A to 13AAs described, the first programming state PV1′ can be selected as the target state. However, in step S110, any one of the erase state E′, the second programming state PV2′, or the third programming state PV3 can be selected as the target state.

[0146] In step S130, firstly, the voltage range to which the threshold voltage is distributed can be determined, and multiple read voltages for dividing the determined voltage range can be determined. (See reference...) Figure 11A As described, when the target state is the first programming state P1′, the voltage range can be determined first, and the P voltages V1 to VP used to divide the voltage range can be determined as multiple read voltages.

[0147] In step S150, multiple sensing operations based on the determined voltages V1 to VP are performed. When the number of determined read voltages is P, the sensing operations can also be performed P times.

[0148] Figure 15 This is an example Figure 14 A flowchart illustrating an example implementation of step S150. More specifically, Figure 15 This is an example in Figure 14 The flowchart shows one of the P sensing operations performed in step S150. Furthermore, Figure 15 Each step can be made by Figure 12A The page buffer shown is executed.

[0149] Reference Figure 15 ,exist Figure 14 The sensing operation performed in step S150 includes: storing the MSB and LSB data stored in each memory cell in a first latch and a second latch included in each of the multiple page buffers (S210); performing a threshold voltage sensing operation on the memory cell included in the selected page using a selected read voltage and storing the bit data generated as a result of sensing in a sensing latch included in each of the multiple page buffers (S230); sending the bit data stored in the sensing latch to the sensing output node of the corresponding page buffer (S250); performing a masking operation on the bit data for the target state by applying a control signal corresponding to the target state to the multiple page buffers (S270); and outputting the bit data masked to the target state (S290).

[0150] In step S210, the MSB and LSB data stored in each memory cell are stored in the first latch L1 and the second latch L2 of the corresponding page buffer. For example, in the above... Figure 9A , Figure 9B , Figure 11A and Figure 11BIn the example, in the column corresponding to the first memory cell MCI1 In this case, LSB is 1 and MSB is 0. Therefore, in step S210, the bit data that is 1 can be stored in the column. The corresponding page buffer's first latch L1 stores the data, while bits that are 0 can be stored in the second latch L2.

[0151] In step S230, the result of the sensing operation using the selected read voltage is stored in the sensing latch of each page buffer. For example, this can be achieved by applying a voltage to the word line connected to the selected page PG. Figure 11A The first voltage V1 shown is used to perform a threshold voltage sensing operation on memory cells MCi1 to MCim. At this time, due to the column... The threshold voltage of the corresponding first memory cell MCi1 is greater than the first voltage V1, therefore the node QS of the sense latch LS connected to the first page buffer PB1 of the first bit line BL1 is... N The voltage can be changed to a logic low voltage corresponding to a bit value of "0". Therefore, the voltage of node QS becomes a logic high voltage corresponding to a bit value of "1".

[0152] In step S250, the bit data stored in the sensing latch is sent to the sensing output node SO of the corresponding page buffer. More specifically, the voltage value corresponding to the bit data stored in the sensing latch LS can be sent to the sensing output node SO. Figure 12A In the example, the voltage of node QS can be sent to the sensing output node SO by turning on the fifteenth transistor T15 included in each page buffer. When the voltage of the sensing output node SO is logic high as a result of executing step S250, this means that the threshold voltage of the memory cell is greater than the first voltage V1 because node QS N The voltage of the sensor output node SO is logic low. Conversely, when the voltage of the sensor output node SO is logic low, this means that the threshold voltage of the memory cell is less than the first voltage V1, because node QS N The voltage is logic high.

[0153] In step S270, control signals corresponding to the target state are applied to multiple page buffers to perform a masking operation on the bit data for the target state. That is, the bit data corresponding to states other than the target state is removed.

[0154] For example, when the target state is the first programming state PV1′, the first transmission control signal TRAN can be activated. A and the fourth transmission control signal TRAN D And the second transmission control signal TRAN can be disabled. Band the third transmission control signal TRAN C Therefore, the voltage of the sensing output node SO of the page buffers in which the bit data stored in the first latch L1 and the second latch L2 is "1" and "0" is maintained, while the voltage of the sensing output node SO of the other page buffers is discharged.

[0155] When the target state is erase state E′, the first transmission control signal TRAN A and the third transmission control signal TRAN C It can be activated by the on-state voltage, and the second transmission control signal TRAN B and the fourth transmission control signal TRAN D It can be disabled using a cutoff voltage. When the target state is the second programmed state PV2′, the second transmission control signal TRAN B and the fourth transmission control signal TRAN D It can be activated by the on-state voltage, and the first transmission control signal TRAN A and the third transmission control signal TRAN C It can be disabled using a cutoff voltage. When the target state is the third programmed state PV3', the second transmission control signal TRAN... B and the third transmission control signal TRAN C It can be activated by the on-state voltage, and the first transmission control signal TRAN A and the fourth transmission control signal TRAN D It can be deactivated using the cutoff voltage.

[0156] In step S290, the bit data masked to the target state can be output. More specifically, the bit data corresponding to the voltage of the sensing output node SO can be stored in the sensing latch LS, and the masked bit data can be counted among the bit data of the sensing latch LS included in multiple page buffers. The counting result can be sent to the controller 200.

[0157] Figure 16 This is a circuit diagram illustrating a page buffer according to another embodiment of the present disclosure, capable of detecting the threshold voltage distribution of an MLC by masking for each target state.

[0158] Reference Figure 16 It shows the relationship with Figure 12A Circuit diagrams showing examples of different page buffers. Figure 2 The first page buffer PB1 to the m-th page buffer PBm shown can be implemented as follows: Figure 16 The circuit shown. Figure 2 The first page buffer PB1 to the m-th page buffer PBm shown may also include, in addition to Figure 16Other components besides the circuit shown. In the following description, based on the page buffer PB1 connected to the first bit line BL1.

[0159] and Figure 12A similar, Figure 16 The page buffer shown may include a first latch circuit LC1, a second latch circuit LC2, and a sensing latch circuit LCS. The first latch circuit LC1 may include a first latch L1 and first transistors T1 through T6. The second latch circuit LC2 may include a second latch L2 and seventh transistors T7 through Twelfth transistors T12. The sensing latch circuit LCS may include a sensing latch LS and thirteenth transistors T13 through sixteenth transistors T16. The first latch circuit LC1, the second latch circuit LC2, and the sensing latch circuit LCS may be connected to a sensing output node SO. Furthermore, the page buffer may also include a seventeenth transistor T17 connected between the sensing output node SO and the bit line BL1. The seventeenth transistor T17 may be controlled by the page buffer sensing signal PBSENSE.

[0160] also, Figure 16 The page buffer may also include a third latch circuit LC3 in addition to the first latch circuit LC1, the second latch circuit LC2, and the sensing latch circuit LCS. The third latch circuit LC3 may include a third latch L3 and transistors eighteen through twenty-one (T18 through T21). The third latch L3 may be referred to as a "buffer latch". Referring to the third latch circuit LC3, the eighteenth transistor T18 is connected between nodes Q3 and QX of the third latch L3, while the nineteenth transistor T19 is connected to node Q3 of the third latch L3. N Between node QX and node SO. The eighteenth transistor T18 is controlled by the reset signal RSTx, and the nineteenth transistor T19 is controlled by the set signal SETx. Furthermore, the twentieth transistor T20 is connected between node Q3 and the sensing output node SO. The twentieth transistor T20 is controlled by the transmission control signal TRANx. Furthermore, the twenty-first transistor T21 is connected between node QX and the ground node. The twenty-first transistor T21 is controlled by the voltage of the sensing output node SO. The third latch circuit LC3 can be used to temporarily store the sensing result masked to the target state after the sensing operation via the first voltage V1. Furthermore, the third latch circuit LC3 can perform an XOR operation on the result of the sensing operation masked to the target state via the second voltage V2 and the bit data stored in the third latch circuit LC3. Then, the third latch circuit LC3 can store the result of the XOR operation.

[0161] Refer to later Figure 17 and Figures 18A to 18D describe Figure 16The operation of the page buffer is shown.

[0162] Figure 17 This is an example Figure 14 A flowchart illustrating another example of an implementation of step S150. More specifically, Figure 17 This is an example in Figure 14 The flowchart shows two of the P sensing operations performed in step S150. Furthermore, Figure 17 Each step can be made by Figure 16 The page buffer shown is executed.

[0163] Figures 18A to 18D This is an example based on Figure 17 The diagram illustrates a method for counting memory cells between a first read voltage and a second read voltage by masking memory cells to a target state.

[0164] In the following text, reference will be made to Figure 17 and Figures 18A to 18D Describe together Figure 16 The operation of the page buffer is shown.

[0165] Reference Figure 17 ,exist Figure 14The sensing operation performed in step S150 includes: storing the MSB and LSB data stored in each memory cell in a first latch and a second latch included in each of the plurality of page buffers (S300); performing a threshold voltage sensing operation on the memory cells included in the selected page using a first read voltage and storing the first bit data generated as a result of sensing in a sensing latch included in each of the plurality of page buffers (S310); sending the first bit data stored in the sensing latch to the sensing output node of the corresponding page buffer (S320); generating first target bit data from the first bit data by applying a control signal corresponding to the target state to the plurality of page buffers (S330); storing the first target bit data of the sensing output node in each of the plurality of cache latches by applying a first control signal to the plurality of cache latches (S340); and using the second... The threshold voltage sensing operation of the memory cells included in the selected page is performed by reading the voltage and the second bit data generated as a result of the sensing is stored in the sensing latch included in each of the plurality of page buffers (S350). The second bit data stored in the sensing latch is sent to the sensing output node of the corresponding page buffer (S360). The second target bit data is generated from the second bit data by applying a control signal corresponding to the target state to the plurality of page buffers (S370). The XOR operation data for the first target bit data and the second target bit data is stored in each of the plurality of cache latches by applying a second control signal to the plurality of cache latches (S380). The number of memory cells in the target state where the threshold voltage is between the first read voltage and the second read voltage is detected by counting the number of bits that are "1" stored in the plurality of cache latches (S390).

[0166] Reference Figure 18A The diagram illustrates the state where the target state is the second programming state PV2′. Below, as an example, the case where the target state is the second programming state PV2′ is described. That is, as an example, a method for counting the number of memory cells belonging to the second programming state PV2′ among the memory cells whose threshold voltage is between the first read voltage V1 and the second read voltage V2 is described.

[0167] In step S300, the MSB and LSB data stored in each memory cell are stored in the first latch L1 and the second latch L2 of the corresponding page buffer. For example, in the above... Figure 9A , Figure 9B , Figure 11A and Figure 11B In the example, in the column corresponding to the first memory cell MCI1 In this case, LSB is 1 and MSB is 0. Therefore, in step S300, the bit data that is 1 can be stored in the column. In the corresponding page buffer, bits that are 0 in the first latch L1 can be stored in the second latch L2. Figure 15 Step S210 is performed in essentially the same way as step S300.

[0168] In step S310, the result of the sensing operation using the first read voltage is stored in the sensing latch of each page buffer. For example, this can be achieved by applying a voltage to the word line connected to the selected page PG. Figure 18A The first voltage V1 shown is used to perform threshold voltage sensing operations on memory cells MCi1 to MCim. This can be used in conjunction with... Figure 15 Step S230 is performed in essentially the same way. Figure 17 Step S310.

[0169] In step S320, the first bit of data stored in the sensing latch is sent to the sensing output node SO of the corresponding page buffer. More specifically, the voltage value corresponding to the first bit of data stored in the sensing latch LS can be sent to the sensing output node SO. Figure 16 In the example, the voltage of node QS can be sent to the sensing output node SO by turning on the fifteenth transistor T15 included in each page buffer. When the voltage of the sensing output node SO is logic high as a result of the execution of step S320, this means that the threshold voltage of the memory cell is greater than the first voltage V1 because node QS N The voltage of the sensor output node SO is logic low. Conversely, when the voltage of the sensor output node SO is logic low, this means that the threshold voltage of the memory cell is less than the first voltage V1, because node QS N The voltage is logic high.

[0170] In step S330, first target bit data is generated from the first bit data by applying control signals corresponding to the target state to multiple page buffers. The first target bit data can be generated by performing a masking operation on the first bit data to achieve the target state. That is, bit data corresponding to states other than the target state are removed.

[0171] Since the target state is the second programmed state PV2′, therefore in Figure 16 In the middle, the second transmission control signal TRAN B and the fourth transmission control signal TRAN D It can be activated by the on-state voltage, and the first transmission control signal TRAN A and the third transmission control signal TRAN CIt can be disabled using a cutoff voltage. Therefore, in the sensing output node SO with a logic high voltage, the voltage of the sensing output node SO of the page buffer corresponding to the second programming state PV2′ is maintained, and the voltage of the sensing output node SO of the page buffer corresponding to other states E′, PV1′ and PV3′ is discharged.

[0172] As step S330 is executed, among the page buffers connected to memory cells with a threshold voltage greater than the first voltage V1, only the sensing output node SO of the page buffer corresponding to the second programming state PV2′ has a logic high state. That is, only Figure 18B The sense output node SO of the page buffer shown in the shaded memory cell is in a logic high state. The first target bit data is obtained by masking the first bit data to the second programming state PV2′.

[0173] In step S340, the first target bit data of the sensing output node is stored in each of the multiple cache latches by applying a first control signal to the multiple cache latches. Figure 17 The "cache latch" shown can represent Figure 16 The third latch L3 is shown.

[0174] Specifically, in Figure 16 The third latch L3 is initialized to the state where the voltage of node Q3 is logic high and node Q3 is in the initial state. N When the voltage at node SO is logic low, the eighteenth transistor T18 is turned on by activating the reset signal RSTx of the third latch circuit LC3. In this case, since the twenty-first transistor T21 is also turned on when the voltage at the sensed output node SO is logic high, node Q3 is connected to the ground node. Therefore, the voltage at node Q3 is changed to logic low, and node Q3... N The voltage is changed to logic high.

[0175] On the other hand, when the voltage of the sensing output node SO is logic low, the twenty-first transistor T21 is turned off, so even if the reset signal RSTx is activated, the third latch L3 remains in its initial state.

[0176] Therefore, the first bit data (i.e., the first target bit data) masked to the second programming state PV2′ is stored in the buffer latch (i.e., in the third latch L3). That is, with the corresponding Figure 18B The third latch L3 of the page buffer corresponding to the memory cell in the shaded area is stored as a "1" bit, while the third latch L3 of the page buffer corresponding to the other memory cells is stored as a "0" bit.

[0177] Subsequently, in step S350, the result of the sensing operation using the second read voltage is stored in the sensing latch of each page buffer. For example, this can be achieved by applying a voltage to the word line connected to the selected page PG. Figure 18A The second voltage V2 shown is used to perform a threshold voltage sensing operation on memory cells MCi1 to MCim. Step S350 can be performed similarly to step S310.

[0178] In step S360, the second bit of data stored in the sensing latch is sent to the sensing output node SO of the corresponding page buffer. More specifically, the voltage value corresponding to the second bit of data stored in the sensing latch LS can be sent to the sensing output node SO. Figure 16 In the example, the voltage of node QS can be sent to the sensing output node SO by turning on the fifteenth transistor T15 included in each page buffer. When the voltage of the sensing output node SO is logic high as a result of the execution of step S360, this means that the threshold voltage of the memory cell is greater than the second voltage V2 because node QS N The voltage of the sensor output node SO is logic low. Conversely, when the voltage of the sensor output node SO is logic low, this means that the threshold voltage of the memory cell is less than the second voltage V2, because node QS N The voltage is logic high.

[0179] In step S370, second target bit data is generated from second bit data by applying control signals corresponding to the target state to multiple page buffers. The second target bit data can be generated by performing a masking operation on the second bit data to achieve the target state. That is, bit data corresponding to states other than the target state are removed.

[0180] Since the target state is the second programmed state PV2′, therefore in Figure 16 In the middle, the second transmission control signal TRAN B and the fourth transmission control signal TRAN D It can be activated by the on-state voltage, and the first transmission control signal TRAN A and the third transmission control signal TRAN C It can be disabled using a cutoff voltage. Therefore, in the sensing output node SO with a logic high voltage, the voltage of the sensing output node SO of the page buffer corresponding to the second programming state PV2′ is maintained, and the voltage of the sensing output node SO of the page buffer corresponding to other states E′, PV1′ and PV3′ is discharged.

[0181] As step S370 is executed, in the page buffers connected to memory cells with a threshold voltage greater than the second voltage V2, only the sensing output node SO of the page buffer corresponding to the second programming state PV2′ has a logic high state. That is, only Figure 18C The sense output node SO of the page buffer shown in the shaded memory cell is in a logic high state. The second target bit data is obtained by masking the second bit data to the second programming state PV2′.

[0182] In step S380, a second control signal is applied to multiple cache latches to store the XOR operation data for the first target bit data and the second target bit data in each of the multiple cache latches. As described above, Figure 17 The "cache latch" shown can represent Figure 16 The third latch L3 is shown.

[0183] Specifically, the first target bit data is stored in Figure 16 In the state of the third latch L3, the nineteenth transistor T19 is turned on by activating the set signal SETx of the third latch circuit LC3. In this case, since the twenty-first transistor T21 is also turned on when the voltage of the sensed output node SO is logic high, node Q3... N Connect to the grounding node. Therefore, node Q3 N The voltage of node Q1 changes to logic low, and the voltage of node Q3 changes to logic high.

[0184] On the other hand, when the voltage of the sensing output node SO is logic low, the twenty-first transistor T21 is turned off, and therefore even if the set signal SETx is activated, the third latch L3 retains the state in which the first target bit data is stored.

[0185] In other words, when connected to Figure 18B The third latch L3 of the page buffer of the memory cell corresponding to the shaded area is connected to... Figure 18C The shaded area corresponds to the node Q3 of the third latch L3 of the page buffer of the memory cell. N The voltage changes from logic high to logic low. Finally, as step S380 is executed, only the voltage corresponding to... Figure 18D The third latch L3 corresponding to the memory cell in the shaded area is stored as a "1" bit, and the third latch L3 corresponding to the other memory cells is stored as a "0" bit.

[0186] With the execution of step S380, the bit data finally stored in the cache latch becomes the result of the XOR operation of the first target bit data and the second target bit data.

[0187] Subsequently, in step S390, the number of bits that are "1" among the bits stored in the multiple cache latches can be counted. Therefore, with Figure 18D The number of memory cells corresponding to the shaded area shown can be sent to the controller 200.

[0188] Figure 19 This is an example Figure 1 The block diagram shown is an example of a controller.

[0189] Reference Figure 19 The controller 200 is connected to the semiconductor memory device 100 and the host computer. The semiconductor memory device 100 can be a reference... Figure 2 The semiconductor memory device described.

[0190] Controller 200 is configured to access semiconductor memory device 100 in response to a request from host. For example, controller 200 is configured to control read operations, write operations, erase operations, and background operations of semiconductor memory device 100. Controller 200 is configured to provide an interface between semiconductor memory device 100 and host. Controller 200 is configured to drive firmware for controlling semiconductor memory device 100.

[0191] The controller 200 includes random access memory (RAM) 210, a processing unit 220, a host interface 230, a memory interface 240, and an error correction block 250. The RAM 210 serves as at least one of the following: operating memory of the processing unit 220, cache memory between the semiconductor memory device 100 and the host, and buffer memory between the semiconductor memory device 100 and the host.

[0192] The processing unit 220 controls the overall operation of the controller 200.

[0193] The host interface 230 includes protocols for performing data exchange between the host and the controller 200. As an example of an implementation, the controller 200 is configured to communicate with the host via at least one of various interface protocols such as: Universal Serial Bus (USB) protocol, Multimedia Card (MMC) protocol, Peripheral Component Interconnect (PCI) protocol, PCI-Fast (PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer System Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronics (IDE) protocol, and proprietary protocols.

[0194] The memory interface 240 is interfaced with the semiconductor memory device 100. For example, the memory interface 240 includes a NAND interface or a NOR interface.

[0195] Error correction block 250 is configured to detect and correct errors in data received from semiconductor memory device 100 using error correction codes (ECC). Processing unit 220 can control semiconductor memory device 100 to adjust read voltage and perform reread based on the error detection results of error correction block 250.

[0196] The controller 200 and the semiconductor memory device 100 can be integrated into a single semiconductor device. As an example of implementation, the controller 200 and the semiconductor memory device 100 can be integrated into a single semiconductor device to form a memory card. For example, the controller 200 and the semiconductor memory device 100 can be integrated into a single semiconductor device to form a memory card such as a PC card (Personal Computer Memory Card International Association (PCMCIA)), a compact flash memory card (CF), a smart media card (SM or SMC), a memory stick, a multimedia card (MMC, RS-MMC, or micro MMC), an SD card (SD, mini SD, micro SD, or SDHC), and a universal flash memory (UFS).

[0197] The controller 200 and the semiconductor memory device 100 can be integrated into a single semiconductor device to form a semiconductor drive (solid-state drive (SSD)). The semiconductor drive (SSD) includes a memory system 1000 configured to store data in the semiconductor memory. When the memory system 1000, including the controller 200 and the semiconductor memory device 100, is used as a semiconductor drive (SSD), the operating speed of a host connected to the memory system 1000 is dramatically increased.

[0198] As another example, the memory system 1000, including the controller 200 and the semiconductor memory device 100, is provided as one of a variety of components in electronic devices such as: computers, ultra-mobile PCs (UMPCs), workstations, netbooks, personal digital assistants (PDAs), portable computers, network tablets, cordless phones, mobile phones, smartphones, e-books, portable multimedia players (PMPs), portable game consoles, navigation devices, black boxes, digital cameras, 3D televisions, digital audio recorders, digital audio players, digital picture recorders, digital picture players, digital video recorders, and digital video players; devices capable of transmitting and receiving information in a wireless environment; one of a variety of electronic devices constituting a home network; one of a variety of electronic devices constituting a computer network; one of a variety of electronic devices constituting a telematics network; an RFID device; or one of a variety of components constituting a computing system.

[0199] As an example of implementation, the semiconductor memory device 100 and the memory system including the semiconductor memory device 100 can be mounted as various types of packages. For example, the semiconductor memory device 100 or the memory system can be packaged or mounted in ways such as PoP, Ball Grid Array (BGA), Chip Scale Package (CSP), Plastic Leaded Chip Carrier (PLCC), Plastic Dual In-line Package (PDIP), Wafer in-package, Wafer in-circuit, Chip on Board (COB), Ceramic Dual In-line Package (CERDIP), Plastic Metric Quad Flat Package (MQFP), Thin Quad Flat Package (TQFP), Small Outline Integrated Circuit Package (SOIC), Shrink Small Outline Package (SSOP), Thin Small Outline Package (TSOP), System-in-Package (SIP), Multi-Chip Package (MCP), Wafer-Scale Fabrication Package (WFP), or Wafer-Scale Fabrication Stacked Package (WSP).

[0200] Figure 20 This is an example Figure 19 A block diagram illustrating an application example of a memory system.

[0201] Reference Figure 20 The memory system 2000 includes a semiconductor memory device 2100 and a controller 2200. The semiconductor memory device 2100 includes a plurality of semiconductor memory chips. The plurality of semiconductor memory chips are divided into a plurality of groups.

[0202] exist Figure 20 In this process, multiple groups communicate with the controller 2200 via channels CH1 to CHk, respectively. Each semiconductor memory chip communicates with a reference... Figure 2 The semiconductor memory device 100 described is similarly configured and operated.

[0203] Each group is configured to communicate with controller 2200 via a common channel. Controller 2200 and reference Figure 19 The controller 200 described is similarly configured and is configured to control multiple memory chips of the semiconductor memory device 2100 via multiple channels CH1 to CHk.

[0204] Figure 21 This example includes references. Figure 20 A block diagram of the computing system describing the memory system.

[0205] The computing system 3000 includes a central processing unit 3100, random access memory (RAM) 3200, a user interface 3300, a power supply 3400, a system bus 3500, and a memory system 2000.

[0206] The memory system 2000 is electrically connected to the central processing unit 3100, RAM 3200, user interface 3300, and power supply 3400 via the system bus 3500. Data provided through the user interface 3300 or processed by the central processing unit 3100 is stored in the memory system 2000.

[0207] exist Figure 21 In this configuration, the semiconductor memory device 2100 is connected to the system bus 3500 via the controller 2200. However, the semiconductor memory device 2100 can also be configured to be directly connected to the system bus 3500. In this case, the functions of the controller 2200 are performed by the central processing unit 3100 and the RAM 3200.

[0208] exist Figure 21 The reference is provided in the middle. Figure 20 The memory system described is 2000. However, it can be referenced... Figure 19 The memory system 1000, which includes a controller 200 and a semiconductor memory device 100, is described in place of the memory system 2000.

[0209] The embodiments of this disclosure disclosed in this specification and accompanying drawings are provided only by way of specific examples to describe the technical content of this disclosure and to aid in understanding it, and are not intended to limit the scope of this disclosure.

[0210] Cross-references to related applications

[0211] This application claims priority to Korean Patent Application No. 10-2021-0045947, filed on April 8, 2021, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference.

Claims

1. A method of operating a semiconductor memory device, the method comprising detecting a threshold voltage distribution of memory cells included in a page selected from a plurality of memory cells, the method comprising the steps of: Select the target state whose threshold voltage distribution is to be detected; Determine multiple read voltages within the voltage range to which the threshold voltage used to classify the selected target state is distributed; as well as Perform multiple sensing operations using the multiple read voltages on the selected page. In each of the plurality of sensing operations, a masking of the target state is applied such that sensing results corresponding to the other states besides the target state are removed.

2. The method according to claim 1, wherein, Each of the plurality of memory units stores N bits of data, and The steps for selecting the target state to be detected by the threshold voltage distribution include the following steps: from the erase state and the first programming state to the (2) N -1) Select the target state in the programming state, and Where N is a natural number.

3. The method according to claim 2, wherein, The steps of performing the plurality of sensing operations using the plurality of read voltages on the selected page include the following steps: The data stored in the memory cells included in the selected page are respectively stored in the data latches of the corresponding page buffer; A threshold voltage sensing operation is performed on the memory cells included in the selected page using a selected read voltage from the plurality of read voltages, and the bit data generated as a result of the sensing is stored in a sensing latch included in each of the plurality of page buffers. Send the bit data stored in the sensing latch to the corresponding sensing output node; and The sensing results corresponding to states other than the target state are removed by applying control signals corresponding to the target state to the plurality of page buffers.

4. The method according to claim 3, wherein, In the step of removing the sensing results corresponding to states other than the target state by applying a control signal corresponding to the target state to the plurality of page buffers, the voltage of the sensing output node of the page buffer storing bit data corresponding to the target state is maintained by the control signal corresponding to the target state.

5. The method according to claim 3, wherein, In the step of removing the sensing results corresponding to states other than the target state by applying a control signal corresponding to the target state to the plurality of page buffers, the sensing output node of the page buffer storing bit data corresponding to the states other than the target state is connected to a ground node through the control signal corresponding to the target state.

6. The method according to claim 3, further comprising the following step: Output the bit data that is masked to the target state.

7. The method according to claim 2, wherein, The steps of performing the plurality of sensing operations using the plurality of read voltages on the selected page include the following steps: The data stored in the memory cells included in the selected page are respectively stored in the data latches of the corresponding page buffer; The threshold voltage sensing operation of the memory cells included in the selected page is performed using the first read voltage, and the first bit data generated as a result of the sensing is stored in the sensing latches included in the corresponding page buffers. The first bit of data stored in the sensing latch is sent to the corresponding sensing output node; First target bit data is generated from the first bit data by applying control signals corresponding to the target state to multiple page buffers; The first target bit data is stored in the cache latches included in the corresponding page buffers; The threshold voltage sensing operation of the memory cell included in the selected page is performed using the second read voltage, and the second bit data generated as a result of the sensing is stored in the sensing latch included in the corresponding page buffer. The second bit of data stored in the sensing latch is sent to the corresponding sensing output node; Second target bit data is generated from the second bit data by applying the control signal corresponding to the target state to the plurality of page buffers; and The result of the XOR operation on the first target bit data and the second target bit data stored in the cache latch is stored in the cache latch.

8. The method according to claim 7, wherein, In the step of generating the first target bit data from the first bit data by applying a control signal corresponding to the target state to the plurality of page buffers, the voltage of the sensing output node of the page buffer storing the bit data corresponding to the target state in the data latch is maintained by the control signal corresponding to the target state.

9. The method according to claim 7, wherein, In the step of generating the first target bit data from the first bit data by applying a control signal corresponding to the target state to the plurality of page buffers, the sensing output node of the page buffer storing bit data corresponding to states other than the target state in the data latch is connected to a ground node via the control signal corresponding to the target state.

10. The method of claim 7, further comprising the step of: The number of memory cells belonging to the target state whose threshold voltage is between the first read voltage and the second read voltage is detected based on the data stored in the cache latch.

11. A semiconductor memory device, the semiconductor memory device comprising: Multiple memory cells connected to the selected word line; Multiple page buffers, wherein the multiple page buffers perform a sensing operation on each of the multiple memory cells; as well as Control logic that controls the operation of the plurality of page buffers. Each of the plurality of page buffers includes: At least one data latch, the at least one data latch being connected to a sensing output node and storing bit data; and A sensing latch, connected to the sensing output node, stores bit data during sensing operations indicating whether a threshold voltage of a corresponding memory cell among the plurality of memory cells is greater than a selected read voltage. The at least one data latch stores bit data programmed into the corresponding memory cell, and The control logic controls each of the plurality of page buffers to apply a target state mask, selected as a threshold voltage distribution, to the bit data stored in the sensing latch based on the bit data stored in the at least one data latch, such that sensing results corresponding to states other than the target state are removed.

12. The semiconductor memory device according to claim 11, wherein, In order to apply the masking of the target state, the control logic controls each of the plurality of page buffers to send a voltage corresponding to the bit data generated based on the selected read voltage to the sensing output node, and controls each of the plurality of page buffers such that the voltage of the sensing output node of the page buffer storing the bit data corresponding to the target state is maintained and the sensing output node of the page buffer storing the bit data corresponding to the states other than the target state is connected to a ground node.

13. The semiconductor memory device according to claim 12, wherein, The control logic controls each of the plurality of page buffers to store the target bit data generated as a result of masking to the target state in the corresponding sense latch.

14. The semiconductor memory device of claim 11, wherein, Each of the plurality of page buffers further includes: a cache latch connected to the sensing output node, and the control logic performs a sensing operation on each of the plurality of memory cells using a first read voltage, stores the first bit data generated as a result of the sensing operation in the corresponding sensing latch, generates first target bit data by applying the target state mask to the first bit data, stores the first target bit data in the corresponding cache latches, performs a sensing operation on each of the plurality of memory cells using a second read voltage different from the first read voltage, stores the second bit data generated as a result of the sensing operation in the corresponding sensing latch, generates second target bit data by applying the target state mask to the second bit data, and controls each of the plurality of page buffers to store the result of the XOR operation of the first target bit data and the second target bit data in the cache latches.

15. The semiconductor memory device of claim 14, further comprising: A counting circuit, based on data stored in the cache latch, counts the number of memory cells belonging to the target state whose threshold voltage is between the first read voltage and the second read voltage.

16. The semiconductor memory device of claim 11, wherein, Each of the plurality of page buffers further includes a page buffer sensing transistor connected between a bit line connected to the corresponding memory cell and the sensing output node.

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