Semiconductor device and erase method

Abstract

The present invention provides a semiconductor device and an erase method, which can control the number of times of applying an erase pulse. The erase method of the flash memory of the present invention is to program a plurality of sacrificial memory cells in a block with different write levels, to apply a monitoring erase pulse (R1) to a well when erasing a selected block in response to an erase command, and then to perform a test (S_EV) on the plurality of sacrificial memory cells, to apply a monitoring erase pulse (R2) after increasing the voltage of the monitoring erase pulse when the test is not passed, and to perform erasing the selected block by applying a normal erase pulse (Q1) to the well based on the voltage of the monitoring erase pulse (R2) when the test is passed.

Description

Technical Field

[0001] This invention relates to a semiconductor device for flash memory, and more particularly to an erasure method for NAND flash memory. Background Technology

[0002] In a typical flash memory, when data is programmed, electrons accumulate in the floating gate, shifting the threshold voltage of the memory cell in the positive direction; when data is erased, electrons are released from the floating gate, shifting the threshold voltage of the memory cell in the negative direction. This programming and erasing must be controlled so that the threshold voltage of the memory cell falls within the distribution width of "0" and "1". Furthermore, when the memory cell stores multiple bits, it must be further controlled so that the threshold voltage of the memory cell falls within the distribution width of "00", "01", "10", and "11".

[0003] To control the threshold distribution of memory cells, incremental step pulse erase (ISPE) is used for erasing memory cells. For example... Figure 1 As shown in (A), ISPE applies an erase pulse Vers0 to the P-well of the selected block. If the erase test fails, an erase pulse Vers1 with a step voltage higher than the erase pulse Vers0 is applied to increase the voltage of the erase pulse until the erase of all memory cells in the block is deemed successful (e.g., Patent Document 1).

[0004] The same applies to programming; to accurately inject electrons into the memory cells, incremental step pulse programming (ISPP) can be used. For example... Figure 1 As shown in (B), the ISPP method applies a programming pulse Vpgm0 to the selected page. If the programming test fails, a programming pulse Vpgm1 with a higher step voltage than the programming pulse Vpgm0 is applied, increasing the voltage of the programming pulse until the programming of all memory cells in the page is deemed successful. Summary of the Invention

[0005] Figure 2 This is a graph representing the programming / erasing cycle characteristics. The vertical axis represents the memory cell threshold (Vth), and the horizontal axis represents the number of programming / erasing cycles. The upper line represents the memory cell threshold in the programming state, and the lower line represents the memory cell threshold in the erasing state. The cycle characteristics of four articles from different generations are shown here. The programming / erasing cycle characteristics are obtained, for example, by repeatedly applying programming pulses with a certain voltage and erasing pulses with a certain voltage.

[0006] As the number of program / erase cycles increases, the degradation of Gm (transconductance) becomes more pronounced, making it difficult for current to flow within the memory cell. As a result, as shown in the figure, the threshold gradually shifts in the positive direction starting from approximately 1K cycles. Since programming a memory cell raises the threshold, increasing the number of cycles makes programming easier, i.e., faster. If the programming test voltage is the same, programming will pass the test at a lower programming pulse voltage, but this applies significant stress to the memory cell during the programming process, accelerating the degradation of Gm.

[0007] On the other hand, since erasing a memory cell reduces the threshold, increasing the number of cycles makes erasing more difficult, for example, slowing down the erasure speed. Ideally, ISPE erasure can control the number of erase pulses applied. However, if the memory erasure speed slows down due to the increased number of cycles, the number of erase pulses applied increases, increasing the stress on the memory cell, accelerating the degradation of the memory cell's Gm, and ultimately reducing durability characteristics (the number of times data can be rewritten) and data retention characteristics. Furthermore, relatively easy-to-erase memory cells are over-erased, while difficult-to-erase cells suffer from insufficient erase voltage and insufficient threshold offset, causing the memory cell's threshold to easily deviate from the threshold distribution. Consequently, in ISPE, if the erase test fails even after applying the maximum number of erase pulses, the block is managed as a bad block, thus limiting the usable storage capacity.

[0008] The purpose of this invention is to solve the existing problems by providing a semiconductor device and erasing method that can control the number of erase pulses applied.

[0009] The erasure method of the NAND flash memory of the present invention includes: a step of programming a plurality of sacrificial memory cells in a block at different write levels; a step of applying a monitoring erase pulse to a well when erasing a selected block in response to an erase command; a step of inspecting the plurality of sacrificial memory cells; a step of applying a monitoring erase pulse after increasing the voltage of the monitoring erase pulse when the inspection fails, until the inspection of the plurality of sacrificial memory cells passes; and a step of erasing the selected block by applying an erase pulse to the well based on the voltage of the monitoring erase pulse when the inspection passes.

[0010] In one embodiment, multiple sacrificial memory cells are each programmed to different write levels using programming pulses used during the programming operation prior to erasure. In one embodiment, the multiple sacrificial memory cells are programmed with a set programming pulse based on the number of programming / erasing cycles. In one embodiment, the multiple sacrificial memory cells include a first sacrificial memory cell programmed with a first write level and a second sacrificial memory cell programmed with a second write level (second write level > first write level), wherein the increase in the voltage of the monitoring erase pulse when the first and second sacrificial memory cells fail is greater than the increase in the voltage when the first sacrificial memory cell passes and the second sacrificial memory cell fails. In one embodiment, the voltage of the erase pulse is set based on the voltage of the monitoring erase pulse when the first and second sacrificial memory cells pass. In one embodiment, the monitoring erase pulse is a voltage waveform tilted compared to the erase pulse. In one embodiment, the multiple sacrificial memory cells are programmed after the erase of a selected block. In one embodiment, the multiple sacrificial memory cells are programmed after the programming of a selected page.

[0011] Furthermore, the NAND flash memory erasure method of the present invention, which uses the programming pulse during the programming operation before erasure, programs multiple sacrificial memory cells at different write levels. When erasing the selected block, a monitoring erasure pulse is applied to the trap, and the offset of the threshold of multiple sacrificial memory cells is monitored. Based on the monitoring results, the erasure pulse used to erase the selected block is determined.

[0012] The semiconductor device of the present invention includes: a NAND-type memory cell array, wherein blocks of the NAND-type memory cell array include a plurality of sacrificial memory cells; and an erasure component that erases selected blocks of the memory cell array, the erasure component programming the plurality of sacrificial memory cells at different write levels, and when erasing the selected blocks in response to an erase command, checking the plurality of sacrificial memory cells after applying a monitoring erase pulse to a well, and if the check fails, increasing the voltage of the monitoring erase pulse and applying the monitoring erase pulse again until the check of the plurality of sacrificial memory cells passes, and when the check passes, applying an erase pulse to the well based on the voltage of the monitoring erase pulse to erase the selected blocks.

[0013] In one embodiment, the erasure unit programs a plurality of sacrificial memory cells using programming pulses set according to the number of programming / erasing cycles. In one embodiment, the plurality of sacrificial memory cells includes a first sacrificial memory cell programmed at a first write level and a second sacrificial memory cell programmed at a second write level (second write level > first write level). The erasure unit increases the voltage of the monitoring erase pulse when the first and second sacrificial memory cells fail by a greater amount than the voltage increase when the first sacrificial memory cell passes and the second sacrificial memory cell fails. In one embodiment, the erasure unit sets the voltage of the erase pulse based on the voltage of the monitoring erase pulse when the first and second sacrificial memory cells pass. In one embodiment, the erasure unit programs the plurality of sacrificial memory cells after erasing a selected block. In one embodiment, the plurality of sacrificial memory cells are located in an area of ​​the memory cell array that is not used by the user. In one embodiment, the semiconductor device further includes a setting information storage unit that stores setting information about ISPE and setting information about ISPP. The erasure unit refers to the setting information storage unit to determine the voltage used for programming the sacrificial memory cells and the voltage used for erasing the block.

[0014] According to the present invention, since multiple sacrificial memory cells are monitored by applying a monitoring erase pulse to optimize the voltage of the erase pulse, erasure can be performed without significantly increasing the number of erase pulses applied, even if the number of programming / erasing cycles increases. This reduces stress on the memory cells, suppresses Gm degradation of the memory cells, and improves the durability and data retention characteristics of the memory cells. Attached Figure Description

[0015] Figure 1 (A) Figure 1 (B) is a diagram illustrating the erasure process of existing flash memory using ISPE;

[0016] Figure 2 It is a graph showing the relationship between the programming / erasing cycle and the threshold change;

[0017] Figure 3 This is a block diagram illustrating the structure of a NAND flash memory according to an embodiment of the present invention;

[0018] Figure 4 This is a diagram illustrating the structure of NAND storage cells and sacrificial storage cells within a block according to an embodiment of the present invention;

[0019] Figure 5 (A) Figure 5 (B) is a diagram illustrating the programming of the sacrificial memory unit according to an embodiment of the present invention;

[0020] Figure 6 This is a flowchart illustrating the erasure action in an embodiment of the present invention;

[0021] Figure 7 This is an example of the waveform of the erase pulse based on ISPE according to an embodiment of the present invention.

[0022] [Explanation of Symbols]

[0023] 100: Flash Memory

[0024] 110: Memory cell array

[0025] 120: Input / output buffer

[0026] 130: Address Register

[0027] 140: Controller

[0028] 150: Setting up an information storage unit

[0029] 160: Word line selection circuit

[0030] 170: Page buffer / read circuit

[0031] 180: Column Selection Circuit

[0032] 190: Internal voltage generation circuit

[0033] Ax: Row address information / Row address

[0034] Ay: Column address information / column address

[0035] BLK(0), BLK(1), ..., BLK(m-1): Blocks

[0036] EV_E: Check for even-numbered bit lines

[0037] EV_O: Check of odd-numbered bit lines

[0038] L0, L1, L2: Write level

[0039] MC0, MC1, MC2, ..., MC31: Storage units

[0040] NA: NAND flash memory cell

[0041] Q1, Q2: Erasure pulse

[0042] R1, R2: Ramp waveform

[0043] S0, S1, S2: Sacrificial storage units

[0044] SBL0, SBL1, SBL2: Bit lines

[0045] S_EV: Verification

[0046] SGD, SGS: Select gate line

[0047] SL: Source Line

[0048] SMC0, SMC1, SMC2: Sacrificial memory units

[0049] TD: Bit-line side selection transistor

[0050] TS: Source-side selection transistor

[0051] t1, t2, t3: Time points

[0052] Vpgm, Vpgm_init+ΔISPP, Vpgm_init+ΔISPP*2: Programming voltage

[0053] Vpgm0, Vpgm1, ..., Vpgm(n): Programming pulses

[0054] Vpgm_init: Programming pulse / programming voltage

[0055] Vpass: Through voltage

[0056] Vread: Readout voltage

[0057] Vers: Erasure voltage

[0058] Vers0, Vers1, ..., Vers(n): Erase pulses

[0059] Vers_init: Erase pulse / initial voltage

[0060] Vers_init+ΔISPE: Erase voltage / peak value

[0061] Vers_init+2*ΔISPE, Vers_init+3*ΔISPE: Peak values

[0062] WL0, WL1, WL2, ..., WL31, WLx: Word lines Detailed Implementation

[0063] Next, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The semiconductor device of the present invention includes, for example, a NAND flash memory, or a microprocessor, microcontroller, logic, application-specific integrated circuit (ASIC), processor for processing images and sound, processor for processing wireless signals, etc., in which such flash memory is embedded. In the following description, a NAND flash memory is illustrated. In one embodiment, the NAND flash memory may be equipped with a Serial Peripheral Interface (SPI) to achieve compatibility with NOR flash memory.

[0064] [Example]

[0065] Figure 3 This is a block diagram illustrating the structure of a NAND flash memory according to an embodiment of the present invention. The flash memory 100 of this embodiment is configured to include: a memory cell array 110, which arranges multiple memory cells in a matrix; an input / output buffer 120, which outputs read data to the outside or imports data input from the outside; an address register 130, which receives address data via the input / output buffer 120; a controller 140, which controls each part based on command data received via the input / output buffer 120 or control signals applied to external terminals; a setting information storage unit 150, which stores setting information regarding ISPE and ISPP; and a word line selection circuit 160, which selects the word line based on the row data from the address register 130. Address information Ax is used for block selection and word line selection, etc.; page buffer / read circuit 170 holds data read from the selected page of the memory cell array 110, or holds data used for programming in the selected page; column selection circuit 180 selects columns within the page buffer / read circuit 170 based on column address information Ay from address register 130, etc.; and internal voltage generation circuit 190 generates various voltages required for reading, programming and erasing (programming voltage Vpgm, pass voltage Vpass, read voltage Vread, erase voltage Vers, etc.).

[0066] Storage cell array 110, for example, has m blocks BLK arranged along the column direction, such as Figure 4As shown, multiple NAND memory cells NA are formed in each block. Each NAND memory cell includes multiple memory cells (MC0, MC1, ..., MC31) connected in series, a bit line select transistor TD, and a source line select transistor TS. The drain of the bit line select transistor TD is connected to a corresponding bit line, and the source of the source line select transistor TS is connected to a common source line SL. The gate of each memory cell is connected to a word line. The gates of the bit line select transistor TD and the source line select transistor TS are connected to the select gate line SGD and the select gate line SGS, respectively. The word line WL, the select gate line SGD, and the select gate line SGS are driven by the word line select circuit 160. In addition, each bit line BL0, BL1, and BLn are connected to the page buffer / read circuit 170 via a bit line select circuit for selecting even or odd bit lines.

[0067] The block in this embodiment is further provided with multiple sacrificial memory cells S0, S1, and S2 for monitoring the offset of a threshold of the memory cell during an erase operation. The sacrificial memory cells S0, S1, and S2 are configured similarly to the NAND memory cells NA, but these sacrificial memory cells are formed in areas that are not used by the user or in areas that the user cannot access. The sacrificial memory cells S0, S1, and S2 are connected to the page buffer / read circuit 170 via corresponding bit lines SBL0, SBL1, and SBL2, in the same way as the other NAND memory cells NA. Furthermore, three sacrificial memory cells S0, S1, and S2 are illustrated here, but the number of sacrificial memory cells is not limited to this.

[0068] The setting information storage unit 150 stores the initial value of the erase pulse Vers_init, the step voltage, and the maximum number of times the erase pulse is applied as setting information for ISPE. Additionally, the setting information storage unit 150 stores the initial value of the programming pulse Vpgm_init, the step voltage, and the maximum number of times the programming pulse is applied as setting information for ISPP. In one embodiment, this setting information can be loaded from the fuse memory that stores setting information for the operation of the flash memory during power-on. When performing erase and programming operations, the controller 140 determines the initial voltage and step voltage of the erase pulse and programming pulse by referring to the setting information stored in the setting information storage unit 150. Furthermore, when the controller 140 dynamically changes the initial voltage and step voltage of the erase pulse and programming pulse according to the number of programming / erasing cycles, it updates the setting information storage unit 150 with the changed setting information.

[0069] The word line selection circuit 160 drives the memory cell via the word line WL based on the row address Ax. Additionally, it drives the bit line-side selection transistor and the source line-side selection transistor via the select gate line SGD and select gate line SGS to select the block and page. The column selection circuit 180 selects the bit line according to the column address Ay, for example, to select the start position for reading data within the page.

[0070] The controller 140 uses a microcontroller or state machine to construct a read-only memory (ROM) / random access memory (RAM) to control the operation of the flash memory 100. During the read operation, a positive voltage is applied to the bit lines, a voltage (e.g., 0V) is applied to the select word lines, and a pass voltage (e.g., 4.5V) is applied to the non-select word lines. This turns on the bit line-side select transistor and the source line-side select transistor, while applying 0V to the common source line. During the programming operation, a high programming voltage Vpgm (15V–20V) is applied to the select word lines, and an intermediate potential (e.g., 10V) is applied to the non-select word lines. This turns on the bit line-side select transistor and turns off the source line-side select transistor, supplying the potential corresponding to the data "0" or "1" to the bit lines. During the erase operation, 0V is applied to the select word line within the block, and a high voltage Vers (e.g., 20V) is applied to the P-well to extract electrons from the floating gate to the substrate, thereby erasing data in blocks.

[0071] Next, the erasure operation of this embodiment will be described. In this embodiment, before performing a substantial erasure of the selected block, a monitoring erasure pulse is applied to monitor the offset of the threshold of the sacrificial memory cells S0, S1, and S2 at this time. Based on this monitoring result, the voltage of the erasure pulse used for the substantial erasure is determined, and the selected block is erased by applying the erasure pulse according to ISPE.

[0072] Sacrificial memory cells S0, S1, and S2 are programmed at different write levels before erasure. The number (bits) of sacrificial memory cells is not particularly limited and is determined, for example, by the type of write level and the number of pages within the block. For example, when programming with three write levels, at least three (bits) of sacrificial memory cells are required. If monitoring for manufacturing variations is desired, multiple sacrificial memory cells can be prepared relative to a single write level. Furthermore, a block can be programmed a number of times corresponding to the number of pages, and the sacrificial memory cells can be set to a size corresponding to the number of programming cycles within the block.

[0073] Here, for example Figure 5(A) illustrates an example of programming three sacrificial memory cells S0, S1, and S2 using three write levels L0, L1, and L2. During programming, the sacrificial memory cells S0, S1, and S2 are in an erase state. Controller 140 selects word line Wx and programs the sacrificial memory cells SMC0, SMC1, and SMC2 on the same page of the sacrificial memory cells S0, S1, and S2 using write levels L0, L1, and L2.

[0074] Figure 5 (B) is a schematic diagram illustrating the application of programming voltages to sacrificial memory cells SMC0, SMC1, and SMC2. At time t1, a programming voltage Vpgm_init is applied to the word line WLx. At this time, a data "0" voltage is applied to the bit lines SBL0, SBL1, and SBL2 of the sacrificial memory cells S0, S1, and S2. Thus, the sacrificial memory cells SMC0, SMC1, and SMC2 are programmed. Next, at time t2, a programming voltage Vpgm_init + ΔISPP (ΔISPP is a step voltage) is applied to the word line WLx. At this time, a programming disable voltage is applied to the bit line SBL0, and a data "0" voltage is applied to the bit lines SBL1 and SBL2. Thus, the sacrificial memory cells SMC1 and SMC2 are programmed. At time t3, Vpgm_init + ΔISPP*2 is applied to the word line WLx. At this time, a programming disable voltage is applied to the sacrificial memory cells SMC0 and SMC1, and a data "0" voltage is applied to the bit line SBL2. As a result, the sacrificial memory cell SMC2 is programmed. Thus, the sacrificial memory cells SMC0, SMC1, and SMC2 are programmed with write levels L0, L1, and L2 (L0 < L1 < L2), and the threshold of each sacrificial memory cell is shifted in the positive direction corresponding to the write level.

[0075] The programming voltage for programming the sacrificial memory cell is determined based on the ISPP setting information stored in the setting information storage unit 150. When performing page programming in this block, the controller 140 refers to the ISPP programming voltage (including the initial voltage and step voltage) stored in the setting information storage unit 150. Furthermore, the controller 140 can dynamically change the programming voltage during page programming. For example, sometimes the programming speed of the selected memory cell is monitored before programming, and the programming voltage is reduced or the step voltage is made variable based on this monitoring result. This monitoring takes into account the increase in the threshold caused by the increase in the number of programming / erase cycles. In the case of such dynamic changes in the programming voltage, the controller 140 changes or updates the ISPP setting information in the setting information storage unit 150.

[0076] Furthermore, when the controller 140 performs page programming in this block at a different timing, it selects a new word line WLx and programs the sacrificial memory cell using the programming pulse applied during the latest page programming. The controller 140 saves the information of the latest word line WLx when programming the sacrificial memory cell in association with the setting information storage unit 150.

[0077] Figure 6 This is a flowchart illustrating the erasure action in this embodiment. Figure 7 This is an example of the waveform of the erase pulse applied to the P-well during the erase operation. Controller 140, in response to an erase command, begins the block erase sequence (S100). Controller 140 may begin the erase sequence, for example, in response to receiving an erase command and address from an external source, or in response to an internal erase command such as internal garbage collection.

[0078] Controller 140 first sets the word line of the selected block to GND level and applies a voltage such as GND to the P-well. Figure 7 The ramp waveform R1 shown is used as a monitoring erase pulse. The ramp waveform R1 is not intended for erasing, but rather for monitoring the threshold deviation of the sacrificial memory cell. Therefore, it is adjusted to a voltage waveform with less energy than a typical erase pulse to prevent the threshold of the sacrificial memory cell from rapidly becoming negative. In the example shown, after the ramp waveform R1 increases from GND to a certain voltage (e.g., 8V), the voltage increase is sloping from that certain voltage to the initial voltage Vers_init. Furthermore, the initial voltage Vers_init is determined with reference to the ISPE setting information stored in the setting information storage unit 150.

[0079] After applying the ramp waveform R1, the controller 140 performs a check on the sacrificial memory cells S1, S2, and S3 (S110). It should be noted that only the sacrificial memory cells are checked. By applying a monitoring erase pulse, the threshold values ​​of the sacrificial memory cells SMC0, SMC1, and SMC2 shift negatively. The check verifies whether the threshold values ​​of the sacrificial memory cells SMC0, SMC1, and SMC2 have reached a predetermined value (e.g., 0V). If they have, the check is successful. During the readout check, a voltage is applied to the select word line of the selected block, and a readout pass voltage is applied to the other non-select word lines. Figure 7 S_EV illustrates the timing of the verification of the sacrifice memory cell.

[0080] If all sacrificial memory cells S1, S2, and S3 pass the inspection (S130), the controller 140 applies a standard ISPE-based erase pulse to the P-well to begin erasing the selected block (S150). If all sacrificial memory cells S1, S2, and S3 pass the inspection by applying a single ramp waveform R1, the peak value of the erase pulse is Vers_init + ΔISPE, and the erase pulse rises rapidly from GND to its peak value.

[0081] When the test fails, the controller 140 increases the voltage of the monitoring erase pulse and applies it to the P-well (S140). The magnitude of the increased step voltage depends on whether the sacrificial memory cells SMC0, SMC1, and SMC2 pass. If sacrificial memory cell SMC0 passes while both sacrificial memory cells SMC1 and SMC2 fail, the voltage of the next monitoring erase pulse is set to Vers_init + 2 * ΔISPE (the step voltage is doubled). If only sacrificial memory cell SMC2 fails, the voltage of the next monitoring erase pulse is set to Vers_init + ΔISPE. Figure 7 The ramp waveform R2 represents the erase voltage Vers_init+ΔISPE when only the memory cell SMC2 fails.

[0082] After applying the ramp waveform R2, the sacrificial memory cells are checked again (S120). This routine continues until all sacrificial memory cells pass the test. Figure 7 The erase pulse Q1 in the figure represents the waveform when the test is passed after applying the ramp waveform R2. The peak value of the erase pulse Q1 is Vers_init+2*ΔISPE.

[0083] After the erase pulse Q1 is applied, an erase test is performed (S160). Figure 7 EV_E indicates the inspection of even-numbered bit lines, and EV_O indicates the inspection of odd-numbered bit lines. If the erase inspection fails, controller 140 applies an erase pulse Q2, which is a step voltage increase on the erase pulse, to the P-well to erase the selected block (S150). The peak value of erase pulse Q2 is Vers_init + 3 * ΔISPE. This routine continues until all bit lines within the selected block pass the inspection.

[0084] If the erase test passes, the controller 140 refers to the ISPP setting information in the setting information storage unit 150 and programs the sacrificial memory cell at different write levels. In addition, the controller 140 saves or updates the initial voltage of the erase pulse to the ISPE setting information in the setting information storage unit 150 (S170).

[0085] As described above, according to this embodiment, the offset of the threshold of the sacrificial memory cell within the selected block is monitored during the erase operation, and an erase pulse is applied based on this monitoring result. Therefore, the increase in the number of erase pulses applied due to the increase in the number of programming / erasing cycles can be suppressed, thereby reducing the stress on the memory cell and reducing Gm degradation. At the same time, stable programming can be achieved, and it also helps to control the number of programming pulses applied.

[0086] In the embodiment described, programming with three different write levels is performed in the sacrificial memory cell, but this is just one example; programming with two or more write levels is also possible.

[0087] Although preferred embodiments of the present invention have been described in detail, the present invention is not limited to specific embodiments, and various modifications and alterations can be made within the scope of the spirit of the invention as set forth in the claims.

Claims

1. An erasing method, which is an erasing method for a NAND flash memory, the erasing method comprising: The steps of programming multiple sacrificial memory cells within a block with different write levels; When erasing a selected block in response to an erase command, the step of applying an erase pulse to the trap will be monitored. The steps for inspecting the plurality of sacrificial memory cells; When the inspection fails, the voltage of the monitoring erase pulse is increased and then the monitoring erase pulse is applied until the inspection of the plurality of sacrificial memory cells passes. as well as When the inspection is passed, the step of applying an erase pulse to the trap to erase the selected block based on the voltage of the monitoring erase pulse is as follows: The plurality of sacrificial memory cells include a first sacrificial memory cell programmed with a first write level and a second sacrificial memory cell programmed with a second write level, wherein the second write level is greater than the first write level. When both the first and second sacrificial storage units fail, the increase in the voltage of the monitoring erase pulse is greater than the increase in voltage when the first sacrificial storage unit is qualified and the second sacrificial storage unit fails.

2. The erasure method according to claim 1, wherein, The plurality of sacrificial memory cells are each programmed to a different write level using the programming pulses used during the programming action prior to erasure.

3. The erasure method according to claim 1, wherein, The plurality of sacrificial memory cells are programmed according to a set programming pulse based on the number of programming / erasing cycles.

4. The erasure method according to claim 1, wherein, The voltage of the erase pulse is set based on the voltage of the monitoring erase pulse when the first and second sacrificial memory cells are qualified.

5. The erasure method according to claim 1, wherein, The monitoring erase pulse is a voltage waveform that is tilted compared to the erase pulse.

6. The erasure method according to claim 1, wherein, The plurality of sacrificial storage units are programmed after the selected block is erased.

7. The erasure method according to claim 1, wherein, The plurality of sacrificial storage units are programmed after the page selection is programmed.

8. An erasing method for a NAND flash memory, wherein, Using the programming pulses from the pre-erase programming action, multiple sacrificial memory cells are programmed at different write levels. During the erasure of the selected block, a monitoring erase pulse is applied to the trap, and the offset of the threshold of the plurality of sacrifice memory cells is monitored. The erasure pulse used to erase the selected block is determined based on the monitoring results. The plurality of sacrificial memory cells include a first sacrificial memory cell programmed with a first write level and a second sacrificial memory cell programmed with a second write level, wherein the second write level is greater than the first write level. When both the first and second sacrificial storage units fail, the increase in the voltage of the monitoring erase pulse is greater than the increase in voltage when the first sacrificial storage unit is qualified and the second sacrificial storage unit fails.

9. A semiconductor device comprising: a NAND flash memory cell array, wherein blocks of the NAND flash memory cell array include a plurality of sacrificial memory cells; and The eraser component erases selected blocks of the NAND flash memory array. The erasure unit programs the plurality of sacrificial memory cells at different write levels. When erasing a selected block in response to an erase command, it checks the plurality of sacrificial memory cells after applying a monitoring erase pulse to the sink. If the check fails, the voltage of the monitoring erase pulse is increased and then applied again until the check of the plurality of sacrificial memory cells passes. When the check passes, an erase pulse is applied to the sink based on the voltage of the monitoring erase pulse to erase the selected block. in, The plurality of sacrificial memory cells include a first sacrificial memory cell programmed with a first write level and a second sacrificial memory cell programmed with a second write level, wherein the second write level is greater than the first write level, and the increase in voltage of the monitoring erase pulse when the first sacrificial memory cell and the second sacrificial memory cell fail is greater than the increase in voltage when the first sacrificial memory cell is qualified and the second sacrificial memory cell fails.

10. The semiconductor device according to claim 9, wherein, The erasure component programs the plurality of sacrificial memory cells using programming pulses set according to the number of programming / erasing cycles.

11. The semiconductor device according to claim 9, wherein, The erasure component sets the voltage of the erasure pulse based on the voltage of the monitoring erasure pulse when the first and second sacrificial memory cells are qualified.

12. The semiconductor device according to claim 10, wherein, The erasure component programs the plurality of sacrificial storage units after erasing the selected block.

13. The semiconductor device according to claim 9, wherein, The plurality of sacrificial storage cells are located in areas of the NAND-type storage cell array that are not used by users.

14. The semiconductor device according to claim 9, wherein, The semiconductor device further includes a setting information storage unit that stores setting information for incremental step pulse erasure and setting information for incremental step pulse programming. The erasure component refers to the setting information storage unit to determine the voltage for programming the plurality of sacrificial memory cells and the voltage for erasing blocks.

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