A semiconductor structure and a method of manufacturing the same

Abstract

The embodiments of the present disclosure disclose a semiconductor and a manufacturing method thereof, the manufacturing method comprising: providing a substrate; depositing a dielectric layer on the substrate; wherein during the deposition of the dielectric layer, a reaction temperature gradually increases from a first reaction temperature to a second reaction temperature, so that the density of the dielectric layer gradually increases in a direction perpendicular to the upper surface of the substrate and from the bottom of the dielectric layer to the top of the dielectric layer.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for manufacturing the same. Background Technology

[0002] In the fabrication of semiconductor structures, a dielectric layer is typically prepared, and then the dielectric layer is etched to form an opening within it. The dielectric layer including the opening can be used as an inter-metal dielectric layer or a hard mask layer. For example, a metal layer can be subsequently formed within the opening, or the target material layer located below it can be etched using the dielectric layer as a hard mask layer.

[0003] However, due to the characteristics of the etching process, the top of the opening is wider and the bottom is narrower, resulting in an undesirable opening profile and causing a series of problems. Summary of the Invention

[0004] This disclosure provides a method for manufacturing a semiconductor structure, including:

[0005] Provide substrate;

[0006] A dielectric layer is deposited on the substrate; wherein, during the deposition of the dielectric layer, the reaction temperature is gradually increased from a first reaction temperature to a second reaction temperature, such that the density of the dielectric layer gradually increases in a direction perpendicular to the upper surface of the substrate and from the bottom of the dielectric layer to the top of the dielectric layer.

[0007] In some embodiments, the difference between the second reaction temperature and the first reaction temperature ranges from 30°C to 150°C.

[0008] In some embodiments, the process of gradually increasing the reaction temperature from the first reaction temperature to the second reaction temperature is linearly gradual, and the rate of change of the reaction temperature ranges from 1°C / s to 5°C / s.

[0009] In some embodiments, depositing a dielectric layer on the substrate includes: depositing the dielectric layer on the substrate using a plasma-enhanced chemical vapor deposition process.

[0010] In some embodiments, the dielectric layer is deposited on the substrate using a plasma-enhanced chemical vapor deposition process, including:

[0011] A plasma processing system is provided, the plasma processing system including a reaction chamber;

[0012] The substrate is placed inside the reaction chamber, and the reaction temperature is set to the first reaction temperature;

[0013] Process gas is introduced into the reaction chamber to deposit a dielectric layer on the substrate, while the reaction temperature is gradually increased from the first reaction temperature to the second reaction temperature.

[0014] In some embodiments, the dielectric layer is an amorphous carbon layer, and the first reaction temperature and the second reaction temperature are in the range of 400°C to 700°C.

[0015] In some embodiments, the dielectric layer is a silicon oxide layer or a silicon oxynitride layer, and the first reaction temperature and the second reaction temperature are in the range of 250°C to 550°C.

[0016] In some embodiments, the dielectric layer is an amorphous silicon layer, and the first reaction temperature and the second reaction temperature are in the range of 350°C to 600°C.

[0017] In some embodiments, after depositing a dielectric layer on the substrate, the method further includes:

[0018] A patterned mask layer is formed on the dielectric layer;

[0019] The dielectric layer is etched using the patterned mask layer as a mask to form a first opening within the dielectric layer; wherein the etching rate of the dielectric layer gradually increases in a direction perpendicular to the upper surface of the substrate and from the top of the dielectric layer to the bottom of the dielectric layer, and the first opening has a uniform width.

[0020] In some embodiments, after etching the dielectric layer using the patterned mask layer as a mask, the method further includes: filling the first opening with a conductive material to form a conductive line, the conductive line having a uniform width in a direction perpendicular to the upper surface of the substrate.

[0021] In some embodiments, prior to depositing a dielectric layer on the substrate, the method further includes: forming a target material layer on the substrate, the target material layer being located below the dielectric layer, the first opening exposing the target material layer;

[0022] After etching the dielectric layer using the patterned mask layer as a mask, the method further includes: etching the target material layer using the dielectric layer as a mask to form a second opening in the target material layer, the second opening being located below the first opening.

[0023] This disclosure also provides a semiconductor structure, including:

[0024] Substrate;

[0025] A dielectric layer is located on the substrate; wherein the density of the dielectric layer gradually increases in a direction perpendicular to the upper surface of the substrate and from the bottom of the dielectric layer to the top of the dielectric layer.

[0026] In some embodiments, the semiconductor structure further includes: a first opening located within the dielectric layer, the first opening being formed by etching the dielectric layer from top to bottom; wherein the first opening has a uniform width in a direction perpendicular to the substrate.

[0027] In some embodiments, the semiconductor structure further includes: a conductive line located within the first opening; wherein the conductive line has a uniform width in a direction perpendicular to the substrate.

[0028] In some embodiments, the semiconductor structure further includes: a target material layer located below the dielectric layer; and a second opening located within the target material layer and below the first opening, wherein the second opening is formed by etching the target material layer from top to bottom using the dielectric layer as a mask.

[0029] The semiconductor structure and its manufacturing method provided in this disclosure include: providing a substrate; depositing a dielectric layer on the substrate; wherein, during the deposition of the dielectric layer, the reaction temperature is gradually increased from a first reaction temperature to a second reaction temperature, such that the density of the dielectric layer gradually increases in the direction perpendicular to the upper surface of the substrate and from the bottom to the top of the dielectric layer. Consequently, the hardness of the dielectric layer also gradually increases in the direction perpendicular to the upper surface of the substrate and from the bottom to the top of the dielectric layer. Subsequently, when etching the dielectric layer to form openings within it, the etching rate gradually increases from top to bottom, resulting in openings with uniform width in the direction perpendicular to the upper surface of the substrate. This improves the uniformity of the width of conductive lines subsequently formed within the openings or the accuracy of pattern transfer using the dielectric layer as a hard mask layer, thereby improving the reliability of the semiconductor structure.

[0030] Details of one or more embodiments of this disclosure are set forth in the following drawings and description. Other features and advantages of this disclosure will become apparent from the accompanying drawings and claims. Attached Figure Description

[0031] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0032] Figure 1 A flowchart illustrating a semiconductor structure manufacturing method provided in an embodiment of this disclosure;

[0033] Figures 2 to 6 A process flow diagram of a method for manufacturing a semiconductor structure provided in this disclosure embodiment;

[0034] Figures 7 to 10 A process flow diagram of a method for manufacturing a semiconductor structure according to another embodiment of this disclosure. Detailed Implementation

[0035] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0036] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0037] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0038] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0039] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0040] In the fabrication of semiconductor structures, a dielectric layer is typically prepared, and then the dielectric layer is etched to form openings within it. The dielectric layer including the openings can be used as an inter-metal dielectric layer or a hard mask layer. For example, a metal layer can be subsequently formed within the openings, or the target material layer located below it can be etched using the dielectric layer as a hard mask layer to transfer the pattern of the dielectric layer onto the target material layer.

[0041] However, due to the characteristics of the etching process, the top of the opening is wider and the bottom is narrower, resulting in an undesirable opening profile. This leads to a series of problems, such as uneven width of the metal layer formed within the opening or poor accuracy of the dielectric layer pattern transfer, ultimately reducing the reliability of the semiconductor structure.

[0042] Based on this, the following technical solutions are proposed for embodiments of this disclosure:

[0043] This disclosure provides a method for manufacturing a semiconductor device; please refer to the following for details. Figure 1 As shown in the figure, the method includes the following steps:

[0044] Step 101: Provide a substrate;

[0045] Step 102: Deposit a dielectric layer on the substrate; wherein, during the deposition of the dielectric layer, the reaction temperature is set to gradually increase from a first reaction temperature to a second reaction temperature, so that the density of the dielectric layer gradually increases in the direction perpendicular to the upper surface of the substrate and from the bottom of the dielectric layer to the top of the dielectric layer.

[0046] Thus, the hardness of the dielectric layer gradually increases in the direction perpendicular to the upper surface of the substrate and from the bottom to the top of the dielectric layer. When etching the dielectric layer to form an opening in the dielectric layer, the etching rate gradually increases from top to bottom, so that the final opening has a uniform width in the direction perpendicular to the upper surface of the substrate. This improves the uniformity of the width of the conductive lines formed in the opening or the accuracy of pattern transfer using the dielectric layer as a hard mask, thereby improving the reliability of the semiconductor structure.

[0047] The specific embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. In describing the embodiments of this disclosure in detail, the schematic diagrams may be partially enlarged without adhering to the usual proportions for ease of explanation, and the schematic diagrams are merely examples and should not be construed as limiting the scope of protection of this disclosure.

[0048] Figures 2 to 6 This is a process flow diagram of a semiconductor structure manufacturing method provided in the embodiments of this disclosure. Figures 7 to 10 A process flow diagram of a method for manufacturing a semiconductor structure according to another embodiment of this disclosure. The following is in conjunction with... Figures 2 to 10 The method for manufacturing the semiconductor structure provided in the embodiments of this disclosure will be described in further detail.

[0049] First, perform step 101, as follows: Figure 2 As shown, a substrate 20 is provided.

[0050] The substrate 20 may be a semiconductor substrate and may include at least one elemental semiconductor material (e.g., a silicon (Si) substrate, a germanium (Ge) substrate), at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In one specific embodiment, the substrate 20 is a silicon substrate, which may be doped or undoped. However, it is not limited to this, and the substrate 20 may also be a substrate comprising any material.

[0051] Next, proceed to step 102, as follows: Figure 3 As shown, a dielectric layer 21 is deposited on a substrate 20; wherein, during the deposition of the dielectric layer 21, the reaction temperature is set to gradually increase from a first reaction temperature to a second reaction temperature, so that the density of the dielectric layer 21 gradually increases in the direction perpendicular to the upper surface of the substrate 20 and from the bottom of the dielectric layer 21 to the top of the dielectric layer 21.

[0052] Specifically, depositing a dielectric layer 21 on the substrate 20 includes: depositing the dielectric layer 21 on the substrate 20 using a plasma-enhanced chemical vapor deposition (PECVD) process.

[0053] More specifically, a dielectric layer 21 is deposited on the substrate 20 using a plasma-enhanced chemical vapor deposition process, including:

[0054] A plasma processing system (not shown) is provided, which includes a reaction chamber (not shown);

[0055] The substrate 20 is placed inside the reaction chamber (not shown), and the reaction temperature is set to the first reaction temperature;

[0056] Process gas is introduced into the reaction chamber (not shown) to deposit a dielectric layer 21 on the substrate 20, while the reaction temperature is gradually increased from a first reaction temperature to a second reaction temperature.

[0057] In one embodiment, the plasma processing system further includes a radio frequency (RF) power supply. During the deposition of the dielectric layer, the RF power supply is used to generate an RF electric field in the reaction chamber. The gas introduced into the reaction chamber forms plasma under the excitation of the RF electric field at a certain temperature. The plasma is highly reactive and reacts easily, thereby depositing a dielectric layer on the substrate surface.

[0058] Next, as Figure 5 As shown, after depositing the dielectric layer 21 on the substrate 20, the method further includes:

[0059] A patterned mask layer 22 is formed on the dielectric layer 21;

[0060] The patterned mask layer 22 is used as a mask to etch the dielectric layer 21 to form a first opening T1 in the dielectric layer 21; wherein, in a direction perpendicular to the upper surface of the substrate 20 and from the top of the dielectric layer 21 to the bottom of the dielectric layer 21, the etching rate of the dielectric layer 21 gradually increases, and the first opening T1 has a uniform width.

[0061] Here, the material of the patterned mask layer 22 can be photoresist, and the method of forming the patterned mask layer 22 can be as follows: first, a photoresist layer (not shown) is formed on the dielectric layer 21; then, exposure and etching processes are performed on the photoresist layer (not shown) to form the patterned mask layer 22.

[0062] The applicant has discovered through research that in related technologies, when etching the dielectric layer from top to bottom, the etching rate gradually decreases, resulting in a gradually decreasing width of the final opening and an unsatisfactory opening profile. In the embodiments of this disclosure, during the deposition of the dielectric layer 21, the reaction temperature is gradually increased from a first reaction temperature to a second reaction temperature. This causes the density of the dielectric layer 21 to gradually increase in the direction perpendicular to the upper surface of the substrate 20 and from the bottom to the top of the dielectric layer 21. Consequently, the hardness of the dielectric layer 20 also gradually increases in this direction. When etching the dielectric layer 21 to form the first opening T1 within it, the etching rate gradually increases from top to bottom, resulting in a uniform width of the final first opening T1 in the direction perpendicular to the upper surface of the substrate 20. This improves the uniformity of the width of the conductive lines subsequently formed within the first opening T1 or the accuracy of pattern transfer using the dielectric layer 21 as a hard mask, thereby improving the reliability of the semiconductor structure.

[0063] In one embodiment, the process of gradually increasing the reaction temperature from a first reaction temperature to a second reaction temperature is linearly gradual, with the rate of change ranging from 1°C / s to 5°C / s, for example, from 2°C / s to 4°C / s. In this embodiment, the reaction temperature is set to change linearly, so that the density and hardness of the dielectric layer 21 also increase linearly in the direction perpendicular to the upper surface of the substrate 20 and from the bottom to the top of the dielectric layer 21. When etching the dielectric layer 21 from top to bottom, the etching rate also changes linearly gradually, which helps to form a first opening T1 with a uniform width.

[0064] It is important to emphasize that the process of gradually increasing the reaction temperature from the first reaction temperature to the second reaction temperature must be a linear change. Compared to nonlinear temperature changes (e.g., gradient temperature changes), linear temperature changes result in a more uniform density change in the dielectric layer, while nonlinear temperature changes result in abrupt density changes. In subsequent etching processes, the structure formed after etching from a dielectric layer with a linear temperature change exhibits a more uniform width, while the structure formed after etching from a dielectric layer with a nonlinear temperature change has uneven widths in the density jump regions. Furthermore, the rate of reaction temperature change is best controlled within the range of 1℃ / s to 5℃ / s. If the rate of reaction temperature change is too small, the density change in the dielectric layer will be insignificant; if the rate of reaction temperature change is too large, the density change in the dielectric layer will be abrupt, both of which will lead to unsatisfactory results in subsequent etching.

[0065] Furthermore, the difference between the second reaction temperature and the first reaction temperature should not be too large or too small. If the difference is too large, the first reaction temperature will be too small or the second reaction temperature will be too large, which will affect the quality and rate of deposition of the dielectric layer 21. If the difference is too small, the density change between the top and bottom of the dielectric layer 21 will be small, resulting in a small difference in the etching rate between the top and bottom of the dielectric layer, which will not effectively improve the profile of the first opening T1. In one embodiment, the difference between the second reaction temperature and the first reaction temperature is in the range of 30°C to 150°C, for example, between 50°C and 100°C.

[0066] The material of dielectric layer 21 includes oxides (e.g., silicon oxide), nitrides (e.g., silicon nitride), carbon oxides (e.g., silicon carbide), nitrides (e.g., silicon nitride), carbon, amorphous silicon, etc. Understandably, the set values ​​of the first reaction temperature and the second reaction temperature are related to the material of dielectric layer 21.

[0067] In one embodiment, the dielectric layer 21 is an amorphous carbon layer, and the first reaction temperature and the second reaction temperature are in the range of 400°C to 700°C. For example, if the first reaction temperature is 500°C, the second reaction temperature can be selected as 600°C. In a specific embodiment, during the deposition of the amorphous carbon layer, the radio frequency power is set to 1250W, and C3H6 gas with a flow rate of 550 sccm is introduced into the reaction chamber.

[0068] In one embodiment, the dielectric layer is a silicon oxide layer or a silicon oxynitride layer, and the first reaction temperature and the second reaction temperature are in the range of 250°C to 550°C. For example, if the first reaction temperature is 350°C, the second reaction temperature can be selected as 450°C. During the deposition of the silicon oxide layer, the radio frequency power is set to 760W, and TEOS (tetraethyl orthosilicate) gas and O2 are introduced into the reaction chamber. During the deposition of the silicon oxynitride layer, the radio frequency power is set to 600W, and SiH4 gas at a flow rate of 150 sccm and N2O gas at a flow rate of 200 sccm are introduced into the reaction chamber.

[0069] In one embodiment, the dielectric layer 21 is an amorphous silicon layer, and the first reaction temperature and the second reaction temperature are in the range of 350°C to 600°C. For example, if the first reaction temperature is 450°C, the second reaction temperature can be selected as 500°C. In a specific embodiment, during the deposition of the amorphous silicon layer, the radio frequency power is set to 600W, and SiH4 gas with a flow rate of 400 sccm is introduced into the reaction chamber.

[0070] In one embodiment, the dielectric layer 21 may include a plurality of sublayers stacked in a direction perpendicular to the upper surface of the substrate 20, and the plurality of sublayers include at least two materials. When forming the plurality of sublayers, different first and second reaction temperatures can be set for different sublayers, such that the density of each sublayer gradually increases in a direction perpendicular to the upper surface of the substrate 20 and from the bottom to the top of the dielectric layer 21, and in two adjacent sublayers, the density at the bottom of the upper sublayer is greater than or equal to the density at the top of the lower sublayer. Thus, the density of the dielectric layer 21 gradually increases in a direction perpendicular to the upper surface of the substrate 20 and from the bottom to the top of the dielectric layer 21.

[0071] Next, as Figure 6 As shown, after etching the dielectric layer 21 using the patterned mask layer 22 as a mask, the method further includes: filling the first opening T1 with conductive material to form a conductive line 23, wherein the conductive line 23 has a uniform width in a direction perpendicular to the upper surface of the substrate 20. Since the first opening T1 has a uniform width in a direction perpendicular to the upper surface of the substrate 20, the conductive line 23 formed within the first opening T1 also has a uniform width, improving the reliability of the semiconductor structure.

[0072] Here, the conductive wire 23 can be formed within the first opening T1 using processes such as chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), electroplating, electroless plating, sputtering, etc. The materials for the conductive wire 23 include tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), metal silicides, metal alloys, or any combination thereof.

[0073] Figures 3 to 6 The dielectric layer 21 shown is used as the interlayer dielectric layer for the conductive line 23. However, it is not limited to this, such as... Figures 7 to 10 As shown, the dielectric layer 21 can also be used as a hard mask layer.

[0074] Specifically, firstly, such as Figure 7 As shown, before depositing the dielectric layer 21 on the substrate 20, the method further includes forming a target material layer 24 on the substrate 20, the target material layer 24 being located below the dielectric layer 21.

[0075] Next, as Figures 8 to 9 As shown, after depositing the dielectric layer 21 on the substrate 20, the method further includes: forming a patterned mask layer 22 on the dielectric layer 21; etching the dielectric layer 21 using the patterned mask layer 22 as a mask to form a first opening T1 in the dielectric layer 21, the first opening T1 exposing the target material layer 24; wherein, in a direction perpendicular to the upper surface of the substrate 20 and from the top of the dielectric layer 21 to the bottom of the dielectric layer 21, the etching rate of the dielectric layer 21 gradually increases, and the first opening T1 has a uniform width.

[0076] Next, as Figure 10 As shown, after etching the dielectric layer 21 using the patterned mask layer 22 as a mask, the method further includes etching the target material layer 24 using the dielectric layer 21 as a mask to form a second opening T2 within the target material layer 24, the second opening T2 being located below the first opening T1. Thus, the pattern of the patterned mask layer 22 can be transferred to the target material layer 24 through the dielectric layer 21. In this embodiment, the first opening T1 has a uniform width in the direction perpendicular to the upper surface of the substrate 20, thereby improving the accuracy of pattern transfer using the dielectric layer 21 as a hard mask, and thus improving the reliability of the semiconductor structure.

[0077] It should be noted that those skilled in the art can change the order of the above steps without departing from the scope of protection of this disclosure.

[0078] This disclosure also provides a semiconductor structure, such as... Figure 6 or Figure 10As shown, it includes: a substrate 20; a dielectric layer 21 located on the substrate 20; wherein, in a direction perpendicular to the upper surface of the substrate 20 and from the bottom to the top of the dielectric layer 21, the density of the dielectric layer 21 gradually increases.

[0079] The substrate 20 may be a semiconductor substrate and may include at least one elemental semiconductor material (e.g., a silicon (Si) substrate, a germanium (Ge) substrate), at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In one specific embodiment, the substrate 20 is a silicon substrate, which may be doped or undoped. However, it is not limited to this, and the substrate 20 may also be a substrate comprising any material.

[0080] In one embodiment, the dielectric layer 21 can be deposited on the substrate 20 using a plasma-enhanced chemical vapor deposition process. For example: first, a plasma processing system is provided, which includes a reaction chamber; then, the substrate 20 is placed in the reaction chamber, and the reaction temperature is set to a first reaction temperature; then, a process gas is introduced into the reaction chamber to deposit the dielectric layer 21 on the substrate 20, while the reaction temperature is gradually increased from the first reaction temperature to a second reaction temperature. Thus, as the reaction temperature increases, the density of the dielectric layer 21 deposited on the substrate 20 gradually increases in the direction perpendicular to the upper surface of the substrate 20 and from the bottom to the top of the dielectric layer 21, and the hardness of the dielectric layer 21 also gradually increases.

[0081] In one embodiment, the plasma processing system further includes a radio frequency power supply. During the deposition of the dielectric layer 21, the radio frequency power supply is used to generate a radio frequency electric field in the reaction chamber. The gas introduced into the reaction chamber forms plasma under the excitation of the radio frequency electric field at a certain temperature. The plasma has strong activity and reacts easily, thereby depositing the dielectric layer 21 on the surface of the substrate 20.

[0082] In one embodiment, the semiconductor structure further includes a first opening T1 located within the dielectric layer 21, the first opening T1 being formed by etching the dielectric layer 21 from top to bottom; wherein, in a direction perpendicular to the substrate 20, the first opening T1 has a uniform width. Here, the method for forming the first opening T1 may be: first, forming a patterned mask layer on the dielectric layer 21; then, using the patterned mask layer as a mask, etching the dielectric layer 21 to form the first opening T1 within the dielectric layer 21. The patterned mask layer may be a photoresist layer. The dielectric layer 21 provided in this embodiment has a gradually increasing density in a direction perpendicular to the upper surface of the substrate 20 and pointing from the bottom to the top of the dielectric layer 21, and the hardness of the dielectric layer 21 also gradually increases. Thus, when etching the dielectric layer 21 to form the first opening T1 within the dielectric layer 21, the etching rate gradually increases from top to bottom, resulting in the final first opening T1 having a uniform width in a direction perpendicular to the upper surface of the substrate 20.

[0083] In one embodiment, during the formation of the dielectric layer 21, the reaction temperature gradually increases from a first reaction temperature to a second reaction temperature in a linearly gradual manner, with the rate of change ranging from 1°C / s to 5°C / s, for example, from 2°C / s to 4°C / s. In this embodiment, the reaction temperature is set to change linearly, so that the density and hardness of the dielectric layer 21 also increase linearly in the direction perpendicular to the upper surface of the substrate 20 and from the bottom to the top of the dielectric layer 21. When etching the dielectric layer 21 from top to bottom to form the first opening T1, the etching rate also changes linearly, thus facilitating the formation of a first opening T1 with a uniform width.

[0084] It is important to emphasize that the process of gradually increasing the reaction temperature from the first reaction temperature to the second reaction temperature must be a linear change. Compared to nonlinear temperature changes (e.g., gradient temperature changes), linear temperature changes result in a more uniform density change in the dielectric layer, while nonlinear temperature changes result in abrupt density changes. In subsequent etching processes, the structure formed after etching from a dielectric layer with a linear temperature change exhibits a more uniform width, while the structure formed after etching from a dielectric layer with a nonlinear temperature change has uneven widths in the density jump regions. Furthermore, the rate of reaction temperature change is best controlled within the range of 1℃ / s to 5℃ / s. If the rate of reaction temperature change is too small, the density change in the dielectric layer will be insignificant; if the rate of reaction temperature change is too large, the density change in the dielectric layer will be abrupt, both of which will lead to unsatisfactory results in subsequent etching.

[0085] The difference between the second reaction temperature and the first reaction temperature should not be too large or too small. If the difference is too large, the first reaction temperature will be too small or the second reaction temperature will be too large, which will affect the quality and rate of deposition of the dielectric layer 21. If the difference is too small, the density change between the top and bottom of the dielectric layer 21 will be small, resulting in a small difference in the etching rate between the top and bottom of the dielectric layer, which will not effectively improve the profile of the first opening T1. In one embodiment, the difference between the second reaction temperature and the first reaction temperature is between 30°C and 150°C, for example, between 50°C and 100°C.

[0086] The dielectric layer 21 is made of materials including oxides (e.g., silicon oxide), nitrides (e.g., silicon nitride), carbon oxides (e.g., silicon carbide), nitrides (e.g., silicon carbide), carbon, amorphous silicon, etc. It is understood that the set values ​​of the first reaction temperature and the second reaction temperature are related to the material of the dielectric layer 21. In one embodiment, the dielectric layer 21 is an amorphous carbon layer, and the range of the first reaction temperature and the second reaction temperature is between 400°C and 700°C. In another embodiment, the dielectric layer 21 is a silicon oxide layer or a silicon oxynitride layer, and the range of the first reaction temperature and the second reaction temperature is between 250°C and 550°C. In yet another embodiment, the dielectric layer 21 is an amorphous silicon layer, and the range of the first reaction temperature and the second reaction temperature is between 350°C and 600°C.

[0087] In one embodiment, the dielectric layer 21 may include a plurality of sublayers stacked in a direction perpendicular to the upper surface of the substrate 20, and the plurality of sublayers include at least two materials. When forming the plurality of sublayers, different first and second reaction temperatures can be set for different sublayers, such that the density of each sublayer gradually increases in a direction perpendicular to the upper surface of the substrate 20 and from the bottom to the top of the dielectric layer 21, and in two adjacent sublayers, the density at the bottom of the upper sublayer is greater than or equal to the density at the top of the lower sublayer. Thus, the density of the dielectric layer 21 gradually increases in a direction perpendicular to the upper surface of the substrate 20 and from the bottom to the top of the dielectric layer 21.

[0088] like Figure 6As shown, in one embodiment, the semiconductor structure further includes a conductive line 23 located within a first opening T1; wherein the conductive line 23 has a uniform width in a direction perpendicular to the substrate 20. The conductive line 23 can be formed within the first opening T1 using processes such as chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), electroplating, electroless plating, and sputtering. The material of the conductive line 23 includes tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), metal silicides, metal alloys, or any combination thereof. Because the first opening T1 has a uniform width in a direction perpendicular to the upper surface of the substrate 20, the conductive line 23 formed within the first opening T1 also has a uniform width, improving the reliability of the semiconductor structure.

[0089] Figure 6 The dielectric layer 21 shown is used as the interlayer dielectric layer for the conductive line 23. However, it is not limited to this, such as... Figure 10 As shown, the dielectric layer 21 can also be used as a hard mask layer. In this embodiment, the semiconductor structure further includes: a target material layer 24, located below the dielectric layer 21; and a second opening T2, located within the target material layer 24 and below the first opening T1. The second opening T2 is formed by etching the target material layer 24 from top to bottom using the dielectric layer 21 as a mask. Specifically, before forming the dielectric layer 21, the target material layer 24 is formed on the substrate 20; after forming the first opening T1 within the first dielectric layer 21, the target material layer 24 is etched using the dielectric layer 21 as a mask to form the second opening T2 within the target material layer 24, thereby transferring the pattern of the dielectric layer 21 to the target material layer 24. In this embodiment, the first opening T1 has a uniform width in the direction perpendicular to the upper surface of the substrate 20, thus improving the accuracy of pattern transfer using the dielectric layer 21 as a hard mask, thereby improving the reliability of the semiconductor structure.

[0090] It should be noted that those skilled in the art can change the order of the above steps without departing from the scope of protection of this disclosure. The above description is only an optional embodiment of this disclosure and is not intended to limit the scope of protection of this disclosure. Any modifications, equivalent substitutions and improvements made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that, include: Provide substrate; A dielectric layer is deposited on the substrate; wherein, during the deposition of the dielectric layer, the reaction temperature is gradually increased from a first reaction temperature to a second reaction temperature, such that the density of the dielectric layer gradually increases in a direction perpendicular to the upper surface of the substrate and from the bottom of the dielectric layer to the top of the dielectric layer; A patterned mask layer is formed on the dielectric layer; The dielectric layer is etched using the patterned mask layer as a mask to form a first opening in the dielectric layer; wherein, in a direction perpendicular to the upper surface of the substrate and from the top of the dielectric layer to the bottom of the dielectric layer, the etching rate of the dielectric layer gradually increases, and the first opening has a uniform width. The process of gradually increasing the reaction temperature from the first reaction temperature to the second reaction temperature is linear and gradual, and the rate of change of the reaction temperature is between 1℃ / s and 5℃ / s.

2. The manufacturing method according to claim 1, characterized in that, The difference between the second reaction temperature and the first reaction temperature ranges from 30°C to 150°C.

3. The manufacturing method according to claim 1, characterized in that, Depositing a dielectric layer on the substrate includes: depositing the dielectric layer on the substrate using a plasma-enhanced chemical vapor deposition process.

4. The manufacturing method according to claim 3, characterized in that, The dielectric layer is deposited on the substrate using a plasma-enhanced chemical vapor deposition process, including: A plasma processing system is provided, the plasma processing system including a reaction chamber; The substrate is placed inside the reaction chamber, and the reaction temperature is set to the first reaction temperature; Process gas is introduced into the reaction chamber to deposit a dielectric layer on the substrate, while the reaction temperature is gradually increased from the first reaction temperature to the second reaction temperature.

5. The manufacturing method according to claim 1, characterized in that, The dielectric layer is an amorphous carbon layer, and the first reaction temperature and the second reaction temperature are in the range of 400°C to 700°C.

6. The manufacturing method according to claim 1, characterized in that, The dielectric layer is a silicon oxide layer or a silicon oxynitride layer, and the first reaction temperature and the second reaction temperature are in the range of 250°C to 550°C.

7. The manufacturing method according to claim 1, characterized in that, The dielectric layer is an amorphous silicon layer, and the first reaction temperature and the second reaction temperature are in the range of 350°C to 600°C.

8. The manufacturing method according to claim 1, characterized in that, After etching the dielectric layer using the patterned mask layer as a mask, the method further includes: filling the first opening with a conductive material to form a conductive line, the conductive line having a uniform width in a direction perpendicular to the upper surface of the substrate.

9. The manufacturing method according to claim 1, characterized in that, Before depositing a dielectric layer on the substrate, the method further includes: forming a target material layer on the substrate, the target material layer being located below the dielectric layer, the first opening exposing the target material layer; After etching the dielectric layer using the patterned mask layer as a mask, the method further includes: etching the target material layer using the dielectric layer as a mask to form a second opening in the target material layer, the second opening being located below the first opening.

10. A semiconductor structure prepared by the manufacturing method according to any one of claims 1-9, characterized in that, include: Substrate; A dielectric layer is located on the substrate; wherein the density of the dielectric layer gradually increases in a direction perpendicular to the upper surface of the substrate and from the bottom of the dielectric layer to the top of the dielectric layer.

11. The semiconductor structure according to claim 10, characterized in that, The semiconductor structure further includes: a first opening located within the dielectric layer, the first opening being formed by etching the dielectric layer from top to bottom; wherein, in a direction perpendicular to the substrate, the first opening has a uniform width.

12. The semiconductor structure according to claim 11, characterized in that, The semiconductor structure further includes: a conductive line located within the first opening; wherein the conductive line has a uniform width in a direction perpendicular to the substrate.

13. The semiconductor structure according to claim 11, characterized in that, The semiconductor structure further includes: a target material layer located below the dielectric layer; and a second opening located within the target material layer and below the first opening, wherein the second opening is formed by etching the target material layer from top to bottom using the dielectric layer as a mask.

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