Semiconductor structure and its formation method

Abstract

This invention discloses a semiconductor structure and a method for forming the same. The method includes: providing a substrate having a plurality of bit line isolation trenches extending along a first direction and isolation structures located within the bit line isolation trenches; patterning and etching the substrate to form a plurality of word line isolation trenches extending along a second direction, wherein a plurality of semiconductor pillars are formed within the plurality of bit line trenches and the plurality of word line trenches; and forming a bit line metal layer on the surface of the semiconductor pillars located below the word line isolation trenches, the bit line metal layer surrounding the sidewalls of the semiconductor pillars. According to the semiconductor structure formation method of this invention, a bit line metal layer can be formed surrounding the sidewalls of the semiconductor pillars, thereby improving channel control, reducing leakage, increasing carrier mobility, and improving the performance of the semiconductor structure.

Description

Technical Field

[0001] This invention relates to the field of pressure sensor technology, and more specifically to a semiconductor structure and its formation method. Background Technology

[0002] The fabrication of semiconductor structures in related technologies typically employs SADP (Self-aligned Double Imaging Patterning) and SAQP (Self-aligned Quadruple Imaging Patterning) processes to form word lines. This requires the use of new photomasks to form the self-aligned word line metal layer and word line isolation layer, which is complex and costly. Furthermore, using new photomasks can easily affect the overlay accuracy. Summary of the Invention

[0003] The purpose of this invention is to provide a method for forming a semiconductor structure, which can form a bit line metal layer around the sidewall of a semiconductor pillar, thereby improving channel control, reducing leakage, increasing carrier mobility, and improving the performance of the semiconductor structure.

[0004] A method for forming a semiconductor structure according to an embodiment of the present invention includes: providing a substrate having a plurality of bit line isolation trenches extending along a first direction and an isolation structure located within the bit line isolation trenches; patterning and etching the substrate to form a plurality of word line isolation trenches extending along a second direction, wherein a plurality of semiconductor pillars are formed in the plurality of bit line isolation trenches and the plurality of word line isolation trenches within the substrate; and forming a bit line metal layer on the surface of the semiconductor pillars located below the word line isolation trenches, the bit line metal layer surrounding the sidewalls of the semiconductor pillars.

[0005] According to some embodiments of the present invention, the method of forming the semiconductor structure further includes: forming a first sacrificial layer in the word line isolation trench and on the bit line metal layer; removing a portion of the first sacrificial layer to expose the semiconductor pillar; and forming a word line gate structure on the surface of the exposed semiconductor pillar, the word line gate structure surrounding the sidewall of the semiconductor pillar.

[0006] According to some embodiments of the present invention, in the step of patterning and etching the substrate to form a plurality of word line isolation trenches extending along a second direction, a mask layer structure is formed on the substrate, and after forming the word line isolation trenches, a portion of the mask layer structure is retained to form a supporting mask layer, the supporting mask layer exposing the word line isolation trenches; the step of removing a portion of the first sacrificial layer to expose the semiconductor pillars includes:

[0007] The steps of forming the word line gate structure include: forming a word line gate dielectric layer on the surface of the exposed semiconductor pillar; forming a word line initial gate layer on the surface of the word line gate dielectric layer; etching the word line initial gate layer using the support mask layer and the sidewalls as masks to form a word line gate layer, forming a word line isolation opening between the word line gate layers, and the word line gate layer and the word line gate dielectric layer together constituting the word line gate structure; and removing the support mask layer and the sidewalls.

[0008] According to some embodiments of the present invention, the step of forming the bit line metal layer includes: forming a protective layer on the sidewall of the word line isolation trench and the sidewall of the supporting mask layer; etching a portion of the substrate downward along the word line isolation trench to expose a portion of the second sacrificial layer located below the word line isolation trench; etching away a portion of the second sacrificial layer to expose a portion of the sidewall of the semiconductor pillar located below the word line isolation trench; and forming the bit line metal layer on the sidewall of the semiconductor pillar.

[0009] According to some embodiments of the present invention, after the step of forming a word line gate structure on the surface of the exposed semiconductor pillar, the method further includes forming a word line isolation layer within the word line isolation opening.

[0010] According to some embodiments of the present invention, the step of forming a substrate includes: providing a substrate; forming a plurality of bit line isolation trenches extending along the first direction in the substrate; forming a second sacrificial layer on the inner wall surface of the bit line isolation trenches; forming a third sacrificial layer on the surface of the second sacrificial layer, wherein the second sacrificial layer and the third sacrificial layer together constitute the isolation structure, and the etching selectivity ratios of the second sacrificial layer and the third sacrificial layer are different.

[0011] According to some embodiments of the present invention, forming a bit line metal layer on the surface of the semiconductor pillar located below the word line isolation trench, the bit line metal layer surrounding the sidewall of the semiconductor pillar includes: etching a portion of the substrate downward along the word line isolation trench to expose a portion of the second sacrificial layer located below the word line isolation trench; etching away a portion of the second sacrificial layer to expose a portion of the sidewall of the semiconductor pillar located below the word line isolation trench; and forming the bit line metal layer on the sidewall of the semiconductor pillar.

[0012] According to some embodiments of the present invention, before etching a portion of the substrate downward along the word line isolation trench, a protective layer is further formed on the sidewall of the word line isolation trench.

[0013] According to some embodiments of the present invention, before forming a bit line metal layer on the surface of the semiconductor pillar, the method further includes: forming a metal silicide layer on the surface of the semiconductor pillar, wherein the bit line metal layer is formed on the surface of the metal silicide layer.

[0014] According to some embodiments of the present invention, the step of forming a bit line metal layer on the surface of the semiconductor pillar includes: forming an initial bit line metal layer on the exposed surface of the semiconductor pillar and within the word line isolation trench; etching away a portion of the initial bit line metal layer located within the word line isolation trench, such that the upper surface of the initial bit line metal layer located within the word line isolation trench is not higher than the upper surface of the third sacrificial layer, thereby forming the bit line metal layer.

[0015] According to some embodiments of the present invention, the upper surface of the bit line metal layer is lower than the upper surface of the third sacrificial layer at the bottom of the word line isolation trench.

[0016] According to some embodiments of the present invention, the step of forming a first sacrificial layer in the word line isolation trench and on the bit line metal layer includes: forming a first initial sacrificial layer on the surface of the word line isolation trench and the support mask layer; removing a portion of the first initial sacrificial layer located on the surface of the support mask layer, and retaining the first initial sacrificial layer located in the word line isolation trench to form the first sacrificial layer.

[0017] According to some embodiments of the present invention, the first sacrificial layer is made of the same material as the protective layer. In the step of removing a portion of the first initial sacrificial layer located on the surface of the support mask layer, a portion of the protective layer located on the sidewall of the support mask layer is also removed. In the step of removing a portion of the first sacrificial layer along the opening between the sidewalls, a protective layer located on the sidewall of the semiconductor pillar is also removed to expose the semiconductor pillar.

[0018] According to some embodiments of the present invention, after removing a portion of the first sacrificial layer along the opening between the sidewalls, the forming method further includes oxidizing the semiconductor pillars such that the cross-sectional area of ​​the exposed portion of the semiconductor pillars is smaller than the cross-sectional area of ​​the unexposed semiconductor pillars.

[0019] According to some embodiments of the present invention, after the step of forming a word line isolation layer in the word line isolation opening, the method further includes: etching back the word line gate dielectric layer, the word line gate layer and the word line isolation layer to form a support groove; and forming a support layer in the support groove.

[0020] The present invention also proposes a semiconductor structure, which is formed by the semiconductor structure formation method of any of the above embodiments.

[0021] The semiconductor structure according to an embodiment of the present invention includes a substrate, the substrate having a plurality of bit line isolation trenches extending along a first direction and an isolation structure located within the bit line isolation trenches, and a plurality of word line isolation trenches extending along a second direction, wherein a plurality of semiconductor pillars are formed in the plurality of bit line isolation trenches and the plurality of word line isolation trenches; and a bit line metal layer located on the surface of the semiconductor pillars below the word line isolation trenches and surrounding the sidewalls of the semiconductor pillars.

[0022] According to the semiconductor structure and its formation method of embodiments of the present invention, by forming a bit line metal layer on the surface of the semiconductor pillar below the word line isolation trench, the bit line metal layer surrounds the sidewall of the semiconductor pillar, thereby improving channel control, reducing leakage, increasing carrier mobility, and improving the performance of the semiconductor structure. Furthermore, by selectively etching a second sacrificial layer and a third sacrificial layer with different etching selectivity ratios to form the bit line metal layer, a new photomask is not required, simplifying the semiconductor structure process and reducing costs, and eliminating the need to consider overlay accuracy issues. Attached Figure Description

[0023] Figure 1 This is a schematic diagram of a semiconductor structure according to an embodiment of the present invention;

[0024] Figures 2-18 This is a cross-sectional view of each step in the method for forming a semiconductor structure according to an embodiment of the present invention, where aa represents the cross-sectional view along the semiconductor structure. Figure 1 The cross-sectional view of line aa, bb is along the Figure 1 A sectional view along line bb, where cc is the sectional view along line bb. Figure 1 A cross-sectional view of the cc line, where dd is along the cc line. Figure 1 A cross-sectional view of the middle dd line;

[0025] Figure 19 This is a flowchart of a method for forming a semiconductor structure according to an embodiment of the present invention.

[0026] Figure label:

[0027] 100: Semiconductor structure;

[0028] 1: Substrate; 11: Substrate; 12: Bit line isolation trench; 13: Isolation structure; 14: Second sacrificial layer; 15: Third sacrificial layer

[0029] 2: Mask layer structure, 21: Support mask layer, 22: Hard carbon layer, 23: First oxynitride layer, 24: Spin-coated hard mask layer, 25: Second oxynitride layer;

[0030] 31: Metal silicide layer; 32: Bit line metal layer; 33: Semiconductor pillar;

[0031] 41: Word line isolation trench; 42: First initial sacrificial layer; 43: First sacrificial layer.

[0032] 51: Sidewall; 52: Word line gate dielectric layer; 53: Word line isolation opening; 54: Word line gate layer; 55: Word line isolation layer; 56: Protective layer

[0033] 6: Support layer. Detailed Implementation

[0034] The following describes in further detail a method for forming a semiconductor structure 100 according to the present invention, with reference to the accompanying drawings and specific embodiments.

[0035] A method for forming a semiconductor structure 100 according to an embodiment of the present invention will now be described with reference to the accompanying drawings.

[0036] like Figure 19 As shown, a method for forming a semiconductor structure 100 according to an embodiment of the present invention may include: S1: providing a substrate 1, the substrate 1 having a plurality of bit line isolation trenches 12 extending along a first direction and an isolation structure 13 located within the bit line isolation trenches 12; S2: patterning and etching the substrate 1 to form a plurality of word line isolation trenches 41 extending along a second direction, the plurality of bit line isolation trenches 41 and the plurality of word line isolation trenches 41 forming a plurality of semiconductor pillars 33 within the substrate 1; S3: forming a bit line metal layer 32 on the surface of the semiconductor pillars 33 located below the word line isolation trenches 41, the bit line metal layer 32 surrounding the sidewalls of the semiconductor pillars 33.

[0037] Figure 1 The diagram shown is a top view of a semiconductor structure 100 according to an embodiment of the present invention. Figures 2-18 The following are cross-sectional views along lines aa, bb, cc, and dd corresponding to the steps of the method for forming a semiconductor structure 100 according to an embodiment of the present invention; combined with... Figures 1-19 A method for forming a semiconductor structure 100 according to an embodiment of the present invention is described, the method comprising the following steps:

[0038] Combination Figures 1-4 As shown, step S1: Provide a substrate 1, which has a plurality of bit line isolation trenches 12 extending along a first direction and an isolation structure 13 located within the bit line isolation trenches 12.

[0039] Specifically, in some embodiments, the step of forming substrate 1 may include: providing substrate 11;

[0040] The substrate 11 may be, but is not limited to, a silicon substrate. This specific embodiment uses a silicon substrate as an example for illustration. In other embodiments, the substrate 11 may also be a semiconductor substrate 11 such as gallium nitride, gallium arsenide, gallium carbide, silicon carbide, or SOI. The substrate 11 is used to support the device structure thereon.

[0041] like Figure 2 As shown, a plurality of bit line isolation trenches 12 extending along a first direction are formed within the substrate 11. Specifically, the plurality of bit line isolation trenches 12 can be formed by etching within the substrate 11 using wet etching or dry etching processes. The bit line isolation trenches 12 extend along the first direction and are spaced apart. Then, as... Figure 3 As shown, a second sacrificial layer 14 can be formed on the inner wall surface of the bit line isolation trench 12 using chemical vapor deposition, physical vapor deposition, or atomic layer deposition. The inner wall surface of the bit line isolation trench 12 refers to the sidewalls and bottom wall of the bit line isolation trench 12; that is, the second sacrificial layer 14 covers the bottom and sidewalls of the bit line isolation trench 12. Then, as... Figure 4 As shown, a third sacrificial layer 15 is formed on the surface of the second sacrificial layer 14. The second and third sacrificial layers 14 together constitute the isolation structure 13. The third and second sacrificial layers 14 fill the bit line isolation trench 12. The second and third sacrificial layers 14 have different etching selectivity ratios, meaning they are made of different materials and have different etching rates. For example, the second and third sacrificial layers 14 and 15 may have a high etching selectivity ratio, which facilitates subsequent selective etching without the need for a new photomask or consideration of overlay accuracy. This improves etching accuracy and simplifies the process. Optionally, the second sacrificial layer 14 can be an oxide layer, such as a silicon oxide layer, and the third sacrificial layer 15 can be a spin-coated hard mask layer. In other embodiments of the present invention, the second and third sacrificial layers 14 and 15 may also be made of other materials, as long as they have high etching selectivity to facilitate subsequent selective etching.

[0042] Step S2: Pattern etching the substrate 1 to form a plurality of word line isolation trenches 41 extending along a second direction, wherein a plurality of semiconductor pillars 33 are formed in the substrate 1 in the plurality of bit line trenches 41 and the plurality of word line isolation trenches 41.

[0043] Specifically, such as Figure 5As shown, a mask layer structure 2 is formed on the surface of a substrate 1. The mask layer structure 2 includes a support mask layer 21 located on the surface of the substrate 1. Specifically, the mask layer structure 2 can be deposited and formed on the surface of the substrate 1. The mask layer structure 2 can be a composite mask layer to facilitate subsequent etching to form a semiconductor structure 100 with a better morphology. The mask layer structure 2 at least includes the support mask layer 21 located on the surface of the substrate 1. In some embodiments, the mask layer structure 2 may further include one or more of the following: a hard carbon layer 22, a silicon oxynitride layer, and a spin-coated hard mask layer located on the support mask layer 21. For example, in... Figure 5 In the example shown, the mask layer structure 2 includes, from bottom to top, a supporting mask layer 21, a hard carbon layer 22, a first oxide nitride layer 23, a spin-coated hard mask layer 24, and a second oxide nitride layer 25. The supporting mask layer 21 can be a silicon nitride layer, and the first oxide nitride layer 23 and the second oxide nitride layer 25 can be silicon oxynitride layers.

[0044] like Figure 6 As shown, a patterned mask layer structure 2 is used, and a substrate 1 is etched to form a plurality of word line isolation trenches 41 extending along a second direction. A plurality of semiconductor pillars 33 are formed within the substrate 1. Specifically, a photoresist layer can be formed on the mask layer structure 2 to define the pattern of the word line isolation trenches 41. Then, the substrate 1 is etched using a photolithography process to form a plurality of word line isolation trenches 41 within the substrate 1. The word line isolation trenches 41 extend along a second direction, wherein the first direction is perpendicular to the second direction. The word line isolation trenches 41 and bit line isolation trenches 12 are perpendicularly arranged, thereby forming a plurality of semiconductor pillars 33 within the substrate 1 through the word line isolation trenches 41 and bit line isolation trenches 12, thus forming a plurality of active regions, such as... Figure 6 As shown, the depth of the word line isolation trench 41 is less than the depth of the bit line isolation trench 12, so as to facilitate the subsequent formation of the bit line metal layer 32 below the word line isolation trench 41.

[0045] like Figure 6 As shown, part of the mask layer structure 2 is removed, and the support mask layer 21 located on the surface of the substrate 1 is retained. That is, after forming the word line isolation trench 41, the support mask layer 21 is retained when the mask layer structure 2 is removed so as to be used for forming the word line gate layer 54 in the subsequent process. The support mask layer 21 can be used as a mask for forming the word line gate layer 54 in the subsequent process. In this way, it is not necessary to set up a new photomask and mask layer when forming the word line gate layer 54, and it is not necessary to consider the overlay accuracy problem.

[0046] like Figures 7-10 As shown, in step S3: a bit line metal layer 32 is formed on the surface of the semiconductor pillar 33 located below the word line isolation trench 41, and the bit line metal layer 32 surrounds the sidewall of the semiconductor pillar 33.

[0047] In some embodiments of the present invention, the step of forming the bit line metal layer 32 may include:

[0048] A portion of the substrate 1 is etched downward along the word line isolation trench 41 to expose a portion of the second sacrificial layer 14 located below the word line isolation trench 41;

[0049] Etching removes a portion of the second sacrificial layer 14 to expose a portion of the sidewall of the semiconductor pillar 33 located below the word line isolation trench 41;

[0050] The bit line metal layer 32 is formed on the sidewall of the semiconductor pillar 33.

[0051] Specifically, before etching the substrate 1 along the word line isolation trench 41, a protective layer 56 can be formed on the sidewall of the word line isolation trench 41, such as... Figure 7 As shown, a protective layer 56 can be formed on the sidewalls of the word line isolation groove 41 and the sidewalls of the supporting mask layer 21; specifically, as Figure 7 As shown, atomic layer deposition (ALD) can be used to deposit material on the inner wall of the word line isolation trench 41 and the surface of the support mask layer 21. Then, an etch-back process is used to remove the material located on the bottom wall of the word line isolation trench 41 and the upper surface of the support mask layer 21, leaving only the deposited material on the sidewalls of the word line isolation trench 41 and the support mask layer 21 to form a protective layer 56. Figure 7 As shown in Figure aa, the protective layer 56 can be used in subsequent processes to protect the sidewalls of the semiconductor pillar 33 and the supporting mask layer 21, so as to prevent the sidewalls of the semiconductor pillar 33 and the supporting mask layer 21 from being etched and affecting the morphology of the semiconductor structure 100, as shown in Figure aa. Figure 7 As shown in Figures aa and dd, the bottom wall of the word line isolation trench 41 is exposed to the substrate 11 without the deposition of the protective layer 56, and a portion of the second sacrificial layer 14 and the third sacrificial layer 15 at the bottom of the word line isolation trench 41 are also exposed.

[0052] like Figure 8 As shown, a portion of the substrate 1 can be etched downwards along the word line isolation trench 41. Specifically, an etchant can be introduced along the word line isolation trench 41 to etch and remove a portion of the substrate 11, thereby exposing a portion of the second sacrificial layer 14 located below the word line isolation trench 41. Optionally, in this step, combined with Figure 8 As shown in Figures aa and dd, a groove can be formed in the substrate 11 below the word line isolation trench 41 to expose the second sacrificial layer 14, as in... Figure 8In the example shown, the groove can be formed into a generally bowl-shaped structure or an elliptical structure, thereby increasing the exposed area of ​​the second sacrificial layer 14 to facilitate subsequent etching of the second sacrificial layer 14. In this step, the protective layer 56 protects the sidewalls of the semiconductor pillar 33 forming the word line isolation trench 41 and the sidewalls of the supporting mask layer 21 from etching, allowing the etchant to etch the substrate 11 located below the word line isolation trench 41 downwards along the word line isolation trench 41.

[0053] like Figure 9 As shown, an etchant can then be introduced along the word line isolation trench 41 to etch away part of the second sacrificial layer 14, thereby exposing the sidewalls of the semiconductor pillar 33 located below the word line isolation trench 41, thus... Figure 9 As shown in Figures aa, cc, and dd, the semiconductor pillars 33 located below the word line isolation trench 41 form the sidewalls of the bit line isolation trench 12, which are exposed. Furthermore, by etching the substrate 1 along the word line isolation trench 41, the sidewalls of the semiconductor pillars 33 located below the word line isolation trench 41 are exposed. This exposes the circumferential sidewalls of the semiconductor pillars 33 located below the word line isolation trench 41. In this step, the protective layer 56 and the second sacrificial layer 14 can have a high selective etching ratio. Optionally, the protective layer 56 can be made of the same material as the third sacrificial layer 15, thereby better protecting the sidewalls of the semiconductor pillars 33. The protective layer 56 can also be etched when the third sacrificial layer 15 is subsequently etched, simplifying the process steps.

[0054] like Figure 10 As shown, metal material can be deposited along word line isolation trench 41 to form bit line metal layer 32 on the surface of exposed semiconductor pillar 33, thereby forming bit line metal layer 32 around semiconductor pillar 33.

[0055] In some embodiments, a metal material can be directly deposited to form a bit line metal layer 32 on the circumferential sidewall of the semiconductor pillar 33. In other embodiments of the invention, a metal silicide layer 31 can be formed on the surface of the semiconductor pillar 33 before depositing the bit line metal layer 32, and then the bit line metal layer 32 can be deposited on the surface of the metal silicide layer 31. Forming the metal silicide layer 31 can reduce contact resistance and improve the performance of the semiconductor structure 100. The metal silicide layer 31 can be cobalt silicide, titanium silicide, tungsten silicide, etc., and the bit line metal layer 32 can be tungsten, nickel, titanium, titanium nitride, and molybdenum, etc. In some examples, the metal silicide layer 31 can be formed by depositing a metal material on the surface of the semiconductor pillar 33 and using a rapid thermal processing process. For example, materials that can react with the silicon substrate 11, such as cobalt, tungsten, nickel, titanium, and molybdenum, can be deposited on the surface of the semiconductor pillar 33, and then a rapid thermal processing process can be used to form tungsten silicide. Alternatively, the metal silicide layer 31 can be formed by directly depositing the metal silicide material on the surface of the semiconductor pillar 33 using a chemical vapor deposition process.

[0056] In some embodiments of the present invention, the step of forming a bit line metal layer 32 on the surface of the semiconductor pillar 33 may include: forming an initial bit line metal layer on the surface of the exposed semiconductor pillar 33 and in the word line isolation trench 41; etching a portion of the initial bit line metal layer located in the word line isolation trench 41 so that the upper surface of the initial bit line metal layer located in the word line isolation trench 41 is not higher than the upper surface of the third sacrificial layer 15, thereby forming the bit line metal layer 32.

[0057] Specifically, metal material can be deposited along the word line isolation trench 41. The metal material is deposited on the sidewalls of the semiconductor pillar 33 (after removing part of the second sacrificial layer 14) and the inner wall of the word line isolation trench 41 to form an initial bit line metal layer. The initial bit line metal layer at least covers part of the sidewalls and bottom wall of the word line isolation trench 41. The initial bit line metal layer located within the word line isolation trench 41 is then etched back, such as... Figure 10 As shown in the dd diagram, the upper surface of the initial bit line metal layer is not higher than the upper surface of the third sacrificial layer 15 located at the bottom of the word line isolation trench 41 to form the bit line metal layer 32, thereby preventing contact connections between the bit line metal layers 32. Further, in... Figure 10 In the example shown in the dd diagram, the upper surface of the bit line metal layer 32 is lower than the upper surface of the third sacrificial layer 15 at the bottom of the word line isolation trench 41, thereby further preventing the connection between the bit line metal layers 32 through the etch-back process.

[0058] like Figure 11As shown, the method for forming the semiconductor structure 100 further includes forming a first sacrificial layer 43 within the word line isolation trench 41 and on the bit line metal layer 32. Specifically, the first sacrificial layer 43 can be formed using one or more of chemical vapor deposition, physical vapor deposition, and atomic layer deposition processes. The first sacrificial layer 43 fills the word line isolation trench 41 and is formed on the bit line metal layer 32, thereby isolating the subsequently formed word line gate layer 54 from the bit line metal layer 32. Optionally, the material of the first sacrificial layer 43 can be the same as that of the third sacrificial layer 15 and the protective layer 56. For example, the materials of the first sacrificial layer 43, the third sacrificial layer 15, and the protective layer 56 can all be spin-coated hard mask materials to facilitate subsequent etching of the sacrificial layer to expose the semiconductor pillar 33.

[0059] In some embodiments, the step of forming the first sacrificial layer 43 may include: such as Figure 11 As shown, a first initial sacrificial layer 42 is formed on the surface of the word line isolation trench 41 and the support mask layer 21. The first initial sacrificial layer 42 can fill the openings of the word line isolation trench 41 corresponding to the word line isolation trench 41 in the support mask layer 21, and then as shown... Figure 12 As shown, a portion of the first initial sacrificial layer 42 located on the surface of the support mask layer 21 is removed, specifically by etching back to remove the portion of the first initial sacrificial layer 42 located within the opening of the support mask layer 21, leaving only the first initial sacrificial layer 42 located within the word line isolation trench 41 to form the first sacrificial layer 43. The first sacrificial layer 43 fills the word line isolation trench 41. In this step, the material of the protective layer 56 can be the same as the material of the first sacrificial layer 43. Thus, when removing the first sacrificial layer 43 located on the surface of the support mask layer 21, the protective layer 56 formed on the surface of the support mask layer 21 can be removed simultaneously to expose the sidewalls of the support mask layer 21.

[0060] like Figure 13 As shown, sidewalls 51 are formed on the sidewalls of the supporting mask layer 21, and openings are formed between the sidewalls 51 to expose the first sacrificial layer 43. Specifically, an atomic layer deposition process can be used to deposit nitride material on the surface of the first sacrificial layer 43 and the surface of the supporting mask layer 21, and then the nitride material is etched back. Due to the geometric effect of the sidewalls, the nitride material deposited on the sidewalls of the supporting mask layer 21 will be retained, thereby forming the sidewalls 51. The sidewalls 51 and the supporting mask layer 21 can be used as mask layers in the subsequent word line gate layer 54 formation process, thus eliminating the need for a new photomask.

[0061] like Figure 14As shown, a portion of the first sacrificial layer 43 can be removed along the opening between the sidewalls 51 to expose the semiconductor pillar 33. Specifically, a wet etching process can be used to etch the first sacrificial layer 43 by introducing an etchant through the opening between the sidewalls 51, thereby removing a portion of the first sacrificial layer 43 to expose the semiconductor pillar 33. The first sacrificial layer 43 can be removed down to a position where the bit line metal layer 32 is not exposed, i.e., a portion of the first sacrificial layer 43 above the bit line metal layer 32 is retained to isolate the subsequently formed word line gate layer 54 from the bit line metal layer 32. In this step, a portion of the protective layer 56 located on the sidewall of the semiconductor pillar 33 can also be removed to expose the sidewall of the semiconductor pillar 33.

[0062] In some examples, such as Figure 14 As shown in the CC diagram, a portion of the isolation structure 13 located in the bit line isolation trench 12 can be removed simultaneously, thereby exposing both the sidewalls of the semiconductor pillar 33 forming the bit line isolation trench 12 and the sidewalls of the semiconductor pillar 33 forming the word line isolation trench 41. This exposes the circumferential sidewalls of the semiconductor pillar 33, facilitating the subsequent formation of the word line gate layer 54 surrounding the semiconductor pillar 33. Specifically, the material of the first sacrificial layer 43 can be the same as the material of the third sacrificial layer 15. When etching back to remove a portion of the first sacrificial layer 43, a portion of the third sacrificial layer 15 can be removed simultaneously, and then a portion of the second sacrificial layer 14 can be etched away to expose the sidewalls of the semiconductor pillar 33.

[0063] In some embodiments, after removing a portion of the first sacrificial layer 43, the semiconductor pillar 33 may be oxidized so that the cross-sectional area of ​​the exposed portion of the semiconductor pillar 33 is smaller than the cross-sectional area of ​​the unexposed semiconductor pillar 33, that is, by oxidizing the semiconductor pillar 33, the semiconductor pillar 33 may be made thinner.

[0064] like Figure 15 As shown, a word line gate dielectric layer 52 is formed on the exposed surface of the semiconductor pillar 33. The word line gate dielectric layer 52 can be an oxide layer; specifically, a silicon oxide layer can be grown on the surface of the semiconductor pillar 33 to form the word line gate dielectric layer 52. The word line gate dielectric layer 52 covers the surface of the exposed semiconductor pillar 33, such as... Figure 15 As shown in Figures aa and c, the word line gate dielectric layer 52 is connected to the second sacrificial layer 14 and formed on the surface of the semiconductor pillar 33, and the support mask layer 21 and sidewall 51 are supported on the semiconductor pillar 33.

[0065] After forming the word line gate dielectric layer 52, the following steps may be performed: forming a word line initial gate layer on the surface of the word line gate dielectric layer 52, wherein the word line initial gate layer is located on the surface of the word line gate dielectric layer and fills the word line isolation trench 41, and then as follows Figure 16As shown, the word line initial gate layer is etched using the support mask layer 21 and the sidewall 51 as a mask to form a word line gate layer 54, and word line isolation openings 53 are formed between the word line gate layers 54.

[0066] Specifically, metal material can be deposited on the surface of the word line gate dielectric layer 52, the support mask layer 21, and the sidewall 51. The thickness of the deposited metal material on the support mask layer 21 can be 10-40 nm or more. Then, the metal material is wet-etched to the surface of the support mask layer 21. The metal material on the upper surface of the support mask layer 21 is removed by wet etching to form the initial word line gate layer. Then, the initial word line gate layer is etched using the support mask layer 21 and the sidewall 51 as masks. In this step, the initial word line gate layer can be etched by dry etching to form the word line gate layer 54 covering the surface of the word line gate dielectric layer 52, and word line isolation openings 53 are formed between the word line gate layers 54. Then, step S12 is performed: the support mask layer 21 and the sidewall 51 are removed.

[0067] like Figure 17 As shown, a word line isolation layer 55 is formed within the word line isolation opening 53. The word line isolation layer 55 fills the word line isolation opening 53 between the word line gate layers 54. Specifically, one or more of chemical vapor deposition, physical vapor deposition, and atomic layer deposition processes can be used to form an initial word line isolation layer on the surface of the semiconductor pillar 33, the surface of the word line gate dielectric layer 52, and the surface of the word line gate layer 54. Then, a portion of the initial word line isolation layer located on the upper surface of the semiconductor pillar 33, the upper surface of the word line gate dielectric layer 52, and the upper surface of the word line gate layer 54 is removed, leaving only the initial word line isolation layer located on the sidewall of the word line gate layer 54 to form the word line isolation layer 55. In this step, planarization processes such as mechanical chemical polishing and etching processes can be used to remove a portion of the initial word line isolation layer.

[0068] In some embodiments of the present invention, such as Figure 18As shown, the method for forming the semiconductor structure 100 may further include etching back the word line gate dielectric layer 52, the word line gate layer 54, and the word line isolation layer 55 to form a support groove, and forming a support layer 6 within the support groove. Specifically, the word line gate layer 54, the word line gate dielectric layer 52, and the word line isolation layer 55 between the semiconductor pillars 33 may be etched back to form a support groove between the semiconductor pillars 33. The depth of the support groove can be set according to actual needs. Then, support material is deposited in the support groove and on the surface of the semiconductor pillars 33, and the support material above the semiconductor pillars 33 is removed, leaving only the support material between the semiconductor pillars 33 to form the support layer 6. The support layer 6 may be connected to multiple semiconductor pillars 33 to support the semiconductor pillars 33. In this step, chemical mechanical polishing and etching processes may be used to remove the support material above the semiconductor pillars 33. Optionally, the support layer 6 may be a nitride layer or an oxide nitride layer, for example, a silicon nitride layer and a silicon oxynitride layer. This invention does not specifically limit the specific application of this method.

[0069] In some embodiments of the present invention, the method for forming the semiconductor structure 100 further includes ion implantation of the substrate 1 to form a source and a drain. The implantation depth of the drain is 160 nm-170 nm, thereby enabling the location of the drain to correspond to the location of the bit line metal layer 32, facilitating the connection between the bit line metal layer 32 and the drain. Specifically, the substrate 11 can be ion implanted for P-well and N-well regions, as well as the source and drain. Phosphorus or arsenic ions can be implanted into the substrate 11 at a depth of 160 nm-170 nm to form the drain, thereby facilitating the connection between the drain and the bit line metal layer 32 and reducing the resistance of the bit line metal layer 32.

[0070] The present invention also proposes a semiconductor structure 100, which is prepared by the semiconductor structure 100 formation method of the above embodiment.

[0071] The semiconductor structure 100 according to an embodiment of the present invention may include: a substrate 1 and a bit line metal layer, wherein the substrate 1 is provided with a plurality of bit line isolation trenches 12 extending along a first direction and an isolation structure 13 located within the bit line isolation trenches 12, and a plurality of word line isolation trenches 41 extending along a second direction, wherein a plurality of semiconductor pillars 33 are formed in the plurality of bit line isolation trenches 12 and the plurality of word line isolation trenches 41 in the substrate 1; the bit line metal layer 32 is located on the surface of the semiconductor pillars 33 below the word line isolation trenches 41 and surrounds the sidewalls of the semiconductor pillars 33.

[0072] Therefore, according to the semiconductor structure 100 and its formation method according to embodiments of the present invention, by forming a bit line metal layer 32 on the surface of the semiconductor pillar 33 below the word line isolation trench 41, and the bit line metal layer 32 surrounding the sidewall of the semiconductor pillar 33, it is possible to improve channel control, reduce leakage, improve carrier mobility, and improve the performance of the semiconductor structure 100. Furthermore, by selectively etching the second sacrificial layer 14 and the third sacrificial layer 15 with different etching selectivity ratios to form the bit line metal layer 32, it is not necessary to set up a new photomask, which simplifies the semiconductor structure process and reduces costs, and eliminates the need to consider overlay accuracy issues.

[0073] Furthermore, by using the retained support mask layer 21 and the subsequently formed sidewall 51 as masks for the subsequent formation of the word line gate layer 54, the word line gate layer 54 can be formed without setting a new photomask, thereby simplifying the process and cost of the semiconductor structure 100, and eliminating the need to consider the issue of overlay accuracy.

[0074] Furthermore, in the process of forming the bit line metal layer 32, by filling the bit line isolation trench 12 with the second sacrificial layer 14 and the third sacrificial layer 15 and forming a bowl-shaped groove, the second sacrificial layer 14 and the third sacrificial layer 15 have a high etching selectivity, thereby removing part of the second sacrificial layer 14 to form the bit line metal layer 32 surrounding the sidewall of the semiconductor pillar 33, which can also reduce the resistance between the bit line metal layers 32.

[0075] The above description is only a preferred embodiment of the present invention. It should be noted that those skilled in the art can make several improvements and modifications without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, the substrate having a plurality of bit line isolation trenches extending along a first direction and an isolation structure located within the bit line isolation trenches; The substrate is patterned to form a plurality of word line isolation trenches extending along a second direction, wherein a plurality of semiconductor pillars are formed in the plurality of bit line isolation trenches and the plurality of word line isolation trenches; A bit line metal layer is formed on the surface of the semiconductor pillar located below the word line isolation trench, the bit line metal layer surrounding the sidewall of the semiconductor pillar; A first sacrificial layer is formed within the word line isolation trench and on the bit line metal layer; Remove a portion of the first sacrificial layer to expose the semiconductor pillar; A word line gate structure is formed on the exposed surface of the semiconductor pillar, the word line gate structure surrounding the sidewall of the semiconductor pillar; In the step of patterning the substrate to form a plurality of word line isolation trenches extending along a second direction, a mask layer structure is formed on the substrate, and after the word line isolation trenches are formed, a portion of the mask layer structure is retained to form a support mask layer, the support mask layer exposing the word line isolation trenches. The step of removing a portion of the first sacrificial layer to expose the semiconductor pillar includes: Sidewalls are formed on the sidewalls of the supporting mask layer, and openings are formed between the sidewalls to expose the first sacrificial layer. A portion of the first sacrificial layer is removed along the opening between the sidewalls; The steps for forming the word line gate structure include: A word line gate dielectric layer is formed on the surface of the exposed semiconductor pillar; An initial gate layer for word lines is formed on the surface of the word line gate dielectric layer; The word line initial gate layer is etched using the support mask layer and the sidewall as masks to form the word line gate layer. A word line isolation opening is formed between the word line gate layers. The word line gate layer and the word line gate dielectric layer together constitute the word line gate structure. Remove the supporting mask layer and the sidewall.

2. The method of forming a semiconductor structure of claim 1, wherein, In The step of forming a word line gate structure on the exposed surface of the semiconductor pillar further includes: A word line isolation layer is formed within the word line isolation opening.

3. The method for forming a semiconductor structure according to claim 1, characterized in that, The steps involved in forming the substrate include: Provide substrate; A plurality of bit line isolation trenches extending along the first direction are formed in the substrate; A second sacrificial layer is formed on the inner wall surface of the bit line isolation trench; A third sacrificial layer is formed on the surface of the second sacrificial layer. The second sacrificial layer and the third sacrificial layer together constitute the isolation structure. The etching selectivity of the second sacrificial layer and the third sacrificial layer is different.

4. The method for forming a semiconductor structure according to claim 3, characterized in that, The step of forming a bit line metal layer on the surface of the semiconductor pillar located below the word line isolation trench, the bit line metal layer surrounding the sidewall of the semiconductor pillar, includes: A portion of the substrate is etched downwards along the word line isolation trench to expose a portion of the second sacrificial layer located below the word line isolation trench; Etching removes a portion of the second sacrificial layer to expose a portion of the sidewall of the semiconductor pillar located beneath the word line isolation trench; The bit line metal layer is formed on the sidewall of the semiconductor pillar.

5. The method for forming a semiconductor structure according to claim 4, characterized in that, Before etching a portion of the substrate downwards along the word line isolation trench, the method further includes forming a protective layer on the sidewall of the word line isolation trench.

6. The method of forming a semiconductor structure of claim 4, wherein, In Before forming the bit line metal layer on the surface of the semiconductor pillar, the method further includes: forming a metal silicide layer on the surface of the semiconductor pillar, wherein the bit line metal layer is formed on the surface of the metal silicide layer.

7. The method for forming a semiconductor structure according to claim 4, characterized in that, The step of forming a bit line metal layer on the surface of the semiconductor pillar includes: An initial bit line metal layer is formed on the surface of the exposed semiconductor pillar and within the word line isolation trench; Etching removes a portion of the bit line initial metal layer located within the word line isolation trench, so that the upper surface of the bit line initial metal layer located within the word line isolation trench is not higher than the upper surface of the third sacrificial layer, thereby forming the bit line metal layer.

8. The method for forming a semiconductor structure according to claim 7, characterized in that, The upper surface of the bit line metal layer is lower than the upper surface of the third sacrificial layer at the bottom of the word line isolation trench.

9. The method for forming a semiconductor structure according to claim 5, characterized in that, The step of forming a first sacrificial layer within the word line isolation trench and on the bit line metal layer includes: A first initial sacrificial layer is formed on the surface of the word line isolation trench and the support mask layer; Remove a portion of the first initial sacrificial layer located on the surface of the support mask layer, and retain the first initial sacrificial layer located within the word line isolation trench to form the first sacrificial layer.

10. The method for forming a semiconductor structure according to claim 9, characterized in that, The first sacrificial layer is made of the same material as the protective layer. In the step of removing a portion of the first initial sacrificial layer located on the surface of the support mask layer, a portion of the protective layer located on the sidewall of the support mask layer is also removed. In the step of removing a portion of the first sacrificial layer along the opening between the sidewalls, a protective layer located on the sidewall of the semiconductor pillar is also removed to expose the semiconductor pillar.

11. The method for forming a semiconductor structure according to claim 1, characterized in that, After removing a portion of the first sacrificial layer through the opening between the sidewalls, the forming method further includes oxidizing the semiconductor pillars such that the cross-sectional area of ​​the exposed portion of the semiconductor pillars is smaller than the cross-sectional area of ​​the unexposed semiconductor pillars.

12. The method for forming a semiconductor structure according to claim 2, characterized in that, After the step of forming a word line isolation layer within the word line isolation opening, the method further includes: The word line gate dielectric layer, the word line gate layer, and the word line isolation layer are etched back to form a support groove; A support layer is formed within the support groove.

13. A semiconductor structure, said semiconductor structure being prepared by the formation method according to any one of claims 1-12, characterized in that, include: The substrate has a plurality of bit line isolation trenches extending along a first direction and an isolation structure located within the bit line isolation trenches, and a plurality of word line isolation trenches extending along a second direction, wherein a plurality of semiconductor pillars are formed in the plurality of bit line isolation trenches and the plurality of word line isolation trenches in the substrate; Bit line metal layer, the bit line metal layer being located on the surface of the semiconductor pillar below the word line isolation trench and surrounding the sidewall of the semiconductor pillar.

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