Method for manufacturing a semiconductor structure and semiconductor structure

Abstract

The present disclosure provides a semiconductor structure manufacturing method and a semiconductor structure. The manufacturing method comprises: providing a substrate provided with a first trench at the top; forming a plurality of L-shaped stacked active regions on the first trench, the active region comprising first conductive layers and first dielectric layers stacked alternately; removing part of the first conductive layers to form an L-shaped second trench in the active region; and forming a capacitor structure, part of the capacitor structure being located in the second trench, and a first end of the capacitor structure being connected with the first conductive layer. The L-shaped active region is formed, and the L-shaped second trench is formed in the active region, and then the L-shaped capacitor structure is formed in the second trench. The lower electrode and the upper electrode of the L-shaped capacitor structure have a larger relative area, a larger capacitance capacity, and are beneficial to improving the storage density.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a method for fabricating a semiconductor structure and the semiconductor structure itself. Background Technology

[0002] As semiconductor chips continue to develop, the critical dimension (CD) of chips continues to shrink. However, lithography technology has limitations, which limit the shrinkage of the critical dimension, resulting in low chip storage density. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail in this disclosure. This overview is not intended to limit the scope of the claims.

[0004] A first aspect of this disclosure provides a method for fabricating a semiconductor structure, comprising:

[0005] A base is provided, with a first groove provided on top;

[0006] Multiple L-shaped stacked active regions are formed on the first trench, the active regions comprising alternating stacked first conductive layers and first dielectric layers;

[0007] A portion of the first conductive layer is removed to form an L-shaped second trench in the active region;

[0008] A capacitor structure is formed, a portion of which is located in the second trench, and a first end of the capacitor structure is connected to the first conductive layer.

[0009] In some embodiments, a plurality of L-shaped stacked active regions are formed on the first trench, including:

[0010] A Z-shaped stacked active layer is formed on the substrate;

[0011] By removing part of the structure of the active layer, the remaining active layer located in the first trench forms multiple L-shaped stacked active regions.

[0012] In some embodiments, the active layer forming the Z-shaped stack includes:

[0013] A first conductive material layer and a first dielectric material layer are alternately formed on the substrate;

[0014] A third trench is formed, exposing the bottom wall of the first trench and the sidewalls of the first conductive material layer and the first dielectric material layer, the third trench separating the first conductive material layer and the first dielectric material layer into at least two Z-shaped stacked active layers.

[0015] In some embodiments, after forming a Z-shaped stacked active layer, the method for fabricating the semiconductor structure further includes:

[0016] A portion of the first conductive layer is removed to form a fourth trench between adjacent first dielectric layers, the fourth trench being connected to the third trench;

[0017] Bit lines are formed in the fourth trench.

[0018] In some embodiments, removing a portion of the structure of the active layer includes:

[0019] Remove the active layer extending beyond the first trench to form an L-shaped stack of active layers; and / or,

[0020] A portion of the structure of the active layer is removed to form a plurality of fifth trenches, which divide the active layer into a plurality of active regions.

[0021] In some embodiments, after removing a portion of the active layer, the method for fabricating the semiconductor structure further includes:

[0022] Fill the first trench;

[0023] The top surface of the first trench after flattening and filling.

[0024] In some embodiments, after planarizing the top surface of the first trench after filling, the method for fabricating the semiconductor structure further includes:

[0025] Multiple word lines are formed, and the word lines are in contact with the active region.

[0026] In some embodiments, removing a portion of the first conductive layer to form an L-shaped second trench in the active region includes:

[0027] A second dielectric layer and a first support layer are formed on the top surface of the filled first trench;

[0028] A first through-hole is formed, which penetrates the second dielectric layer and the first support layer in the thickness direction of the substrate to expose the top surface of the first conductive layer;

[0029] A portion of the first conductive layer is removed along the first through-hole.

[0030] In some embodiments, forming a capacitor structure includes:

[0031] The capacitor structure is formed in the second trench and the first through hole through the first through hole.

[0032] In some embodiments, after forming the capacitor structure, the method for fabricating the semiconductor structure further includes:

[0033] A third dielectric layer and a second support layer are formed on the top surface of the first support layer;

[0034] A second through-hole and a third through-hole are formed. The second through-hole penetrates the third dielectric layer and the second support layer in the thickness direction of the substrate and exposes the second end of the capacitor structure. The third through-hole penetrates the third dielectric layer, the second support layer, the first support layer and the second dielectric layer in the thickness direction of the substrate and exposes at least a portion of the top surface of the word line.

[0035] The capacitor conductive structure is formed in the second through hole, and the word line conductive structure is formed in the third through hole.

[0036] According to a second aspect of the present disclosure, a semiconductor structure is provided, comprising:

[0037] Base;

[0038] An active region is disposed on the substrate, and the active region has an L-shaped stacked structure, including an alternately stacked first conductive layer and a first dielectric layer;

[0039] A capacitor structure, wherein the first end of the capacitor structure is L-shaped and connected to the first conductive layer.

[0040] In some embodiments, the semiconductor structure further includes:

[0041] Bit lines are located between adjacent first dielectric layers and are connected to the first conductive layer.

[0042] In some embodiments, the semiconductor structure further includes:

[0043] The word line covers part of the sidewalls of the first conductive layer and the first dielectric layer.

[0044] In some embodiments, the semiconductor structure further includes:

[0045] A filler layer is located on the substrate;

[0046] A layered structure is located on the filling layer;

[0047] The stacked structure is a stacked structure of a first support layer, a second dielectric layer and a first support layer. The second dielectric layer and the first support layer are provided with a first through hole. The first through hole penetrates the second dielectric layer and the first support layer in the thickness direction of the substrate. The capacitor structure is disposed in the first through hole.

[0048] In some embodiments, the semiconductor structure further includes:

[0049] The third dielectric layer is located on the first support layer;

[0050] The second support layer is located on the third dielectric layer;

[0051] The third dielectric layer and the second support layer are provided with a second through hole, which penetrates the third dielectric layer and the second support layer in the thickness direction of the substrate, exposing the second end of the capacitor structure.

[0052] The semiconductor structure fabrication method and semiconductor structure disclosed herein form an L-shaped active region and an L-shaped second trench in the active region, thereby enabling the formation of an L-shaped capacitor structure in the second trench. The lower electrode and upper electrode of the L-shaped capacitor structure have a larger relative area and a larger capacitance, which is beneficial for improving storage density.

[0053] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0054] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of these embodiments. In these drawings, similar reference numerals are used to denote similar elements. The drawings described below are some embodiments of the present disclosure, but not all embodiments. Other drawings will be readily available to those skilled in the art based on these drawings without inventive effort.

[0055] Figure 1 This is a flowchart illustrating a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0056] Figure 2 This is a schematic diagram illustrating a semiconductor structure forming a substrate according to an exemplary embodiment.

[0057] Figure 3 This is a schematic diagram illustrating a semiconductor structure after the formation of an active layer, according to an exemplary embodiment.

[0058] Figure 4 This is a schematic diagram illustrating a semiconductor structure after the formation of a photoresist layer, according to an exemplary embodiment.

[0059] Figure 5 This is a schematic diagram illustrating a semiconductor structure after the formation of a third trench, according to an exemplary embodiment.

[0060] Figure 6 This is a schematic diagram illustrating a semiconductor structure after the formation of a fourth trench, according to an exemplary embodiment.

[0061] Figure 7This is a schematic diagram illustrating a semiconductor structure after the formation of a first coating, according to an exemplary embodiment.

[0062] Figure 8 This is a schematic diagram illustrating a semiconductor structure after forming a bit line material layer, according to an exemplary embodiment.

[0063] Figure 9 This is a schematic diagram illustrating a semiconductor structure after bit line formation, according to an exemplary embodiment.

[0064] Figure 10 This is a schematic diagram illustrating a semiconductor structure after the formation of a photoresist layer, according to an exemplary embodiment.

[0065] Figure 11 This is a schematic diagram illustrating a semiconductor structure after a patterned photoresist layer has been formed, according to an exemplary embodiment.

[0066] Figure 12 This is a schematic diagram illustrating a semiconductor structure after forming multiple active regions, according to an exemplary embodiment.

[0067] Figure 13 This is a schematic diagram illustrating a semiconductor structure after the formation of a photoresist layer, according to an exemplary embodiment.

[0068] Figure 14 This is a schematic diagram illustrating a semiconductor structure after a patterned photoresist layer has been formed, according to an exemplary embodiment.

[0069] Figure 15 This is a schematic diagram illustrating a semiconductor structure after forming an L-shaped active region, according to an exemplary embodiment.

[0070] Figure 16 This is a schematic diagram illustrating a semiconductor structure after the formation of a fill layer, according to an exemplary embodiment.

[0071] Figure 17 This is a schematic diagram illustrating the semiconductor structure after the formation of the sixth trench, according to an exemplary embodiment.

[0072] Figure 18 This is a schematic diagram illustrating a semiconductor structure after forming a word line material layer, according to an exemplary embodiment.

[0073] Figure 19 This is a schematic diagram illustrating the semiconductor structure after word line formation according to an exemplary embodiment.

[0074] Figure 20 This is a schematic diagram illustrating a semiconductor structure after the formation of a first support layer and a second dielectric layer, according to an exemplary embodiment.

[0075] Figure 21This is a schematic diagram illustrating a semiconductor structure after the formation of a second trench, according to an exemplary embodiment.

[0076] Figure 22 This is a schematic diagram of a semiconductor structure after forming a capacitor structure, according to an exemplary embodiment.

[0077] Figure 23 yes Figure 22 A magnified view of region A in the middle.

[0078] Figure 24 This is a schematic diagram illustrating a semiconductor structure after forming a second and a third via, according to an exemplary embodiment.

[0079] Figure 25 This is a schematic diagram of a semiconductor structure after forming a capacitor conductive structure and a word line conductive structure, according to an exemplary embodiment.

[0080] Figure label:

[0081] 10. Substrate; 11. Substrate; 12. Low dielectric constant material layer; 13. Oxide layer; 131. Base plate; 132. Side plate; 133. First trench;

[0082] 20. Active region; 20'. Active layer; 21. First conductive layer; 21'. First conductive material layer; 22. First dielectric layer; 22'. First dielectric material layer; 23. Second trench;

[0083] 30. Capacitor structure; 31. Lower electrode; 32. Dielectric layer; 33. Upper electrode;

[0084] 40. The third trench;

[0085] 50. Fourth trench; 51. Bit line; 51'. Bit line material layer; 52. First coating;

[0086] 60. Fifth trench;

[0087] 70. Filler layer;

[0088] 80. Sixth groove; 81. Word line; 81'. Word line material layer; 811. Word line conductive structure; 82. Second coating;

[0089] 90. First support layer;

[0090] 100. Second dielectric layer;

[0091] 110. First through hole;

[0092] 120. Second support layer;

[0093] 130. Third dielectric layer;

[0094] 140. Second through hole; 141. Capacitor conductive structure 141;

[0095] 150. Third through hole;

[0096] 160. Photoresist layer. Detailed Implementation

[0097] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions in the disclosed embodiments will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without creative effort are within the scope of protection of this disclosure. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0098] As semiconductor chips continue to develop, the critical dimension (CD) of chips continues to shrink. However, lithography technology has limitations, which limit the shrinkage of the critical dimension, resulting in low chip storage density.

[0099] This disclosure provides a method for fabricating a semiconductor structure in exemplary embodiments. Figure 1 A flowchart illustrating a method for fabricating a semiconductor structure according to an exemplary embodiment of the present disclosure is shown. Figures 2-25 The diagram below illustrates the various stages of semiconductor structure fabrication. Figures 2-25 The methods for fabricating semiconductor structures are introduced.

[0100] This embodiment does not limit the semiconductor structure. The following description will take dynamic random access memory (DRAM) as an example, but this embodiment is not limited to this. The semiconductor structure in this embodiment can also be other structures.

[0101] like Figure 2 As shown, an exemplary embodiment of this disclosure provides a method for fabricating a semiconductor structure, comprising the following steps:

[0102] S100 provides a base with a first groove on top.

[0103] Specifically, such as Figure 2 As shown, the substrate 10 includes a substrate 11. The material of the substrate 11 can be silicon (Si), germanium (Ge), or silicon-germanium (GeSi), silicon carbide (SiC); it can also be silicon-on-insulator (SOI), germanium-on-insulator (GOI); or it can be other materials, such as gallium arsenide or other III-V compounds. The substrate 11 is used to support the components disposed on it.

[0104] Reference Figure 2 A low-k material layer 12 is disposed above the substrate 11. The low-k material layer 12 can be formed by deposition processes such as atomic layer deposition (ALD) and chemical vapor deposition (CVD). The material of the low-k material layer 12 is such as silicon carbon nitride (SiCN). The low-k material layer 12 is used to isolate the substrate 11 from the components above the low-k material layer 12.

[0105] Reference Figure 2 An oxide layer 13 is disposed on the low dielectric constant material layer 12, and the top surface of the oxide layer 13 has a first trench 133. The oxide layer 13 can be formed by the aforementioned deposition process or high density plasma (HDP) process, and the oxide layer 13 can be, for example, a plasma-enhanced tetraethyl orthosilicate (TEOS) layer.

[0106] The process of forming the first trench 133 is as follows: after forming the oxide layer 13, a portion of the oxide layer 13 is removed by photolithography; the area where the oxide layer 13 is removed constitutes the first trench 133. In one example, refer to… Figure 2 After removing part of the structure of oxide layer 13, the remaining oxide layer 13 is U-shaped (along... Figure 2 (Viewed from the x-direction as shown), the U-shaped oxide layer 13 includes a base plate 131 and two side plates 132. The top surface of the base plate 131 forms the bottom wall of the first trench 133, and the side walls of the side plates 132 form the two side walls of the first trench 133. Thus, when the active layer 20' is formed in a subsequent process, the active layer 20' can cover the top surface of the base plate 131, the sides of the two side plates 132, and the top surface of the side plates 132, making the active layer 20' a U-shape with flanges. In another example (not shown in the figures), after removing part of the oxide layer structure, the remaining oxide layer is L-shaped. The L-shaped oxide layer includes a base plate and a side plate. The top surface of the base plate forms the bottom wall of the first trench, and the sides of the side plates form the side walls of the first trench. Thus, when the active layer is formed in a subsequent process, the active layer can cover the top surface of the base plate, the sides of the side plates, and the top surface of the side plates, making the active layer Z-shaped.

[0107] S200, Multiple L-shaped stacked active regions are formed on the first trench, the active regions including alternating stacked first conductive layers and first dielectric layers.

[0108] In this step, such as Figure 15 As shown, an L-shaped stack of active regions 20 can be formed on the substrate 10 through a deposition process.

[0109] Among them, reference Figure 15 The active region 20 includes a first conductive layer 21 and a first dielectric layer 22 stacked alternately in a vertical direction. The material of the first conductive layer 21 may be, for example, polysilicon (Poly), tungsten (W), copper (Cu), etc., and the first dielectric layer 22 may be, for example, silicon nitride (SiN). x ) layer, silicon dioxide (SiO) x ) layer, or silicon nitride (SiN) x ) layer and silicon dioxide (SiO) x (Layer stacking)

[0110] S300: Remove part of the first conductive layer to form an L-shaped second trench in the active region.

[0111] In this step, such as Figure 20 and Figure 21 As shown, part of the first conductive layer 21 can be removed by an etching process.

[0112] In one example, refer to Figure 21 The etching gas can use the first dielectric layer 22 as a mask to penetrate downwards ( Figure 2 The etching process (in the reverse direction of the z-direction shown) removes the first conductive layer 21 between adjacent first dielectric layers 22, and the etching gas can diffuse laterally (as shown in the reverse direction of the z-direction) Figure 2 As shown in the x and y directions, a portion of the first conductive layer 21 is removed, thereby forming an L-shaped second trench 23 between adjacent first dielectric layers 22.

[0113] S400, A capacitor structure is formed, a portion of the capacitor structure is located in the second trench, and the first end of the capacitor structure is connected to the first conductive layer.

[0114] In this step, such as Figure 22 and Figure 23 As shown, the lower electrode 31, dielectric layer 32, and upper electrode 33 of the capacitor structure 30 can be sequentially formed through a deposition process. In one example, refer to... Figure 23 The lower electrode 31 can be connected to the active region 20 (i.e., the first conductive layer 21 and the first dielectric layer 22). When powered on, 33 connects to the capacitor conductive structure 141 (see reference). Figure 25 (Detailed explanation follows) The lower electrode 31 and the upper electrode 33 are connected, which are equivalent to the two plates of a parallel plate capacitor. Under the action of current, the capacitor structure 30 can store and release charge, realizing the functions of logic "1" and logic "0".

[0115] In this embodiment, an L-shaped active region is formed, and an L-shaped second trench is formed in the active region, thereby enabling the formation of an L-shaped capacitor structure in the second trench. The lower and upper electrodes of the L-shaped capacitor structure have a larger relative area and a larger capacitance, which is beneficial for improving storage density.

[0116] In an exemplary embodiment, step S200 in the above embodiment, forming a plurality of L-shaped stacked active regions on the first trench, may specifically include the following steps:

[0117] S210, forming a Z-shaped stacked active region on the substrate.

[0118] In this step, such as Figure 5 As shown, a first conductive layer 21 and a first dielectric layer 22 can be alternately formed on a substrate 10 by a deposition process, and the first conductive layer 21 and the first dielectric layer 22 constitute an active region 20.

[0119] In one example, when forming a Z-type active layer 20' on a U-shaped oxide layer 13, the method for fabricating the semiconductor structure may specifically include the following steps:

[0120] S211. A first conductive material layer and a first dielectric material layer are alternately formed on the substrate.

[0121] In this step, such as Figure 3 As shown, a first conductive material layer 21' and a first dielectric material layer 22' can be alternately formed on the substrate 10 by a deposition process. Both the first conductive material layer 21' and the first dielectric material layer 22' are U-shaped with flanges.

[0122] S212. A third trench is formed, exposing the bottom wall of the first trench and the sidewalls of the first conductive material layer and the first dielectric material layer. The third trench separates the first conductive material layer and the first dielectric material layer into two Z-shaped stacked active layers.

[0123] In this step, such as Figure 4 and Figure 5 As shown, a portion of the structure of the first conductive material layer 21' and the first dielectric material layer 22' can be removed by an etching process, exposing a portion of the bottom wall of the first trench 133. The removed areas of the first conductive material layer 21' and the first dielectric material layer 22' form a third trench 40. The third trench 40 can separate the retained first conductive material layer 21' and the first dielectric material layer 22' into two independent Z-shaped active layers 20'.

[0124] In another example, when an active layer 20' is formed on an L-shaped oxide layer 13, a Z-shaped active layer 20' can be formed directly.

[0125] It should be noted that, compared with forming the active layer 20' on the L-shaped oxide layer 13, the scheme of forming the active layer 20' on the U-shaped oxide layer 13 can produce twice the number of capacitor structures 30 under similar process steps. Therefore, in actual production, the oxide layer 13 is usually etched into a U-shape to produce more capacitor structures 30 and improve the storage density of the semiconductor structure.

[0126] The method for fabricating the semiconductor structure after forming the Z-shaped stacked active layer 20' also includes:

[0127] S213. Remove part of the first conductive layer to form a fourth trench between adjacent first dielectric layers, the fourth trench being connected to the third trench.

[0128] In this step, such as Figure 4 As shown, part of the first conductive layer 21 can be removed by an etching process. Specifically, the etching gas can be applied in the horizontal direction ( Figure 2 The diffusion (in the x and y directions shown) removes part of the first conductive layer 21.

[0129] S214. A bit line is formed in the fourth trench.

[0130] In this step, such as Figures 7 to 9 As shown, a bit line 51 can be formed in the fourth trench 50 by a deposition process.

[0131] Specifically, refer to Figures 7 to 9 A first coating 52 can be formed on the substrate 10. The first coating 52 can cover the surfaces of the first dielectric layer 22 and the first conductive layer 21. Specifically, the first coating 52 can at least cover the surface of the fourth trench 50. The material of the first coating 52 is, for example, titanium nitride (TiN). Titanium nitride has low affinity for metals, high anti-adhesion temperature, and inhibits diffusion at high temperatures, thus exhibiting good resistance to adhesive wear and diffusion wear.

[0132] After the first coating 52 is formed, refer to Figure 8 A bit line material layer 51' can be formed on the substrate 10 by a deposition process, the bit line material layer 51' filling at least the third trench 40 and the fourth trench 50. A portion of the bit line material layer 51' is removed by an etching process, leaving the bit line material layer 51' located in the fourth trench 50. The retained bit line material layer 51' forms a bit line 51, the bit line 51 being along a first direction ( Figure 2 (as shown in the x-direction). The material of bit line 51 can be a conductive material such as copper (Cu) or tungsten (W).

[0133] S220. Remove part of the structure of the active region, and the remaining active layer located in the first trench forms multiple L-shaped stacked active regions.

[0134] Removing a portion of the active layer structure may specifically include the following steps:

[0135] S221. Remove the active layer that extends beyond the first trench to form an L-shaped stack of active layers.

[0136] In this step, such as Figure 10 and Figure 15 As shown, a photoresist layer 160 can be formed on the active layer 20', and the photoresist layer 160 exposes more than ( Figure 2 The top surface of the active layer 20' of the first trench 133 (shown in the z direction) can be exposed by photolithography and etching processes to remove the active layer 20' not covered by the photoresist layer 160 until the top surface of the baffle covered by the active layer 20' is exposed, thereby forming an L-shaped stacked active layer 20'.

[0137] S222. Remove part of the structure of the active layer to form multiple fifth trenches, which divide the active layer into multiple active regions.

[0138] In this step, such as Figure 11 As shown, multiple photoresist layers 160 can be formed on the active layer 20', and the multiple photoresist layers 160 are along the first direction ( Figure 2 The active layer 20', which is not covered by the photoresist layer 160, is arranged in the x direction shown in the figure, so that the active layer 20' can be removed by photolithography and etching processes, thereby dividing the active layer 20' into multiple independent active regions 20.

[0139] It should be noted that step S226 needs to be performed after bit line 51 is formed.

[0140] The method for fabricating the semiconductor structure after removing part of the active layer 20' may further include the following steps:

[0141] S223, Fill the first trench.

[0142] In this step, such as Figure 16 As shown, a filling layer 70 can be formed on the substrate 10 by a deposition process. The filling layer 70 can fill the depression of the first trench 133 to serve as an isolation structure for the bit line 51.

[0143] S224, the top surface of the first trench after flattening and filling.

[0144] In this step, such as Figure 16 As shown, the top surface of the filler layer 70 can be polished using a chemical mechanical polishing (CMP) process.

[0145] S225, forming multiple character lines, with the character lines contacting the active area.

[0146] In this step, such as Figure 19 As shown, a photoresist layer can be formed on the top surface of the filler layer 70. Figure 17 (Not shown), the photoresist layer can expose part of the top surface of the filling layer 70. The exposed part of the filling layer 70 is removed by photolithography and etching processes, and a sixth trench 80 is formed in the filling layer 70. The sixth trench 80 can expose part of the top surface and side surface of the active region 20, and then conductive material can be deposited in the sixth trench 80 to form word lines.

[0147] Among them, reference Figure 18 Before depositing the conductive material, a second coating 82 can be deposited in the sixth trench 80. The second coating 82 has the function of preventing the diffusion of the conductive material. The material of the second coating 82 can be, for example, titanium nitride (TiN).

[0148] In an exemplary embodiment, the removal of a portion of the first conductive layer 21 in step S300 of the above embodiment to form an L-shaped second trench 23 in the active region 20 may specifically include the following steps:

[0149] S310. A second dielectric layer and a first support layer are formed on the top surface of the filled first trench.

[0150] In this step, such as Figure 20 As shown, a second dielectric layer 100 and a first support layer 90 can be formed on the top surface of the filled first trench 133 by a deposition process. Specifically, multiple layers of first support layers 90 and second dielectric layers 100 and first support layers 90 are sequentially and alternately formed on the top surface of the filled layer 70 by a deposition process, with a second dielectric layer 100 between every two first support layers 90. In some possible embodiments, two first support layers 90 and one second dielectric layer 100 can be formed on the filled layer 70.

[0151] By setting multiple first support layers 90, a capacitor structure 30 with a larger aspect ratio can be formed, meeting the requirements of higher integration and continuously decreasing design size.

[0152] The material of the first support layer 90 may be silicon nitride (SiN), and the material of the second dielectric layer 100 may be tetraethyl orthosilicate (TEOS).

[0153] S320. A first through-hole is formed, which penetrates the second dielectric layer and the first support layer in the thickness direction of the substrate to expose the top surface of the first conductive layer.

[0154] In this step, such as Figure 20 and 21As shown, a portion of the structure of the first support layer 90 and the second dielectric layer 100 can be removed by photolithography and etching processes, thereby forming a first via 110 in the first support layer 90 and the second dielectric layer 100. The first via 110 is located in the thickness direction of the substrate 10. Figure 25 The first via 110 extends through the first support layer 90 and the second dielectric layer 100 in the z-direction shown in the diagram, exposing the top surface of the first conductive layer 21. The first channel serves as a channel for etching gas in subsequent processes and for forming the capacitor structure 30.

[0155] S330, Remove part of the structure of the first conductive layer 21 along the first through hole 110.

[0156] In this step, such as Figure 21 As shown, part of the structure of the first conductive layer 21 can be removed by an etching process. Specifically, the etching gas can move downward through the first via 110. After the etching gas contacts the first conductive layer 21, it can remove the first conductive layer 21 between adjacent first dielectric layers 22 by using the adjacent first dielectric layer 22 as a mask.

[0157] In an exemplary embodiment, step S400 in the above embodiment, forming the capacitor structure 30, may specifically include the following steps:

[0158] S410. A capacitor structure is formed in the second trench and the first through hole through the first through hole.

[0159] like Figure 22 and Figure 23 As shown, the capacitor structure 30 includes a bottom electrode 31 (Bottom Electrode, BE) and an upper electrode 33 (Top Electrode, TE), as well as a dielectric layer 32 disposed between the bottom electrode 31 and the upper electrode 33. The steps to form the capacitor structure 30 may be to form the bottom electrode 31, the dielectric layer 32 and the upper electrode 33 in sequence.

[0160] Specifically, refer to Figure 22 and Figure 23 Conductive material can be deposited on the sidewalls of the first via 110, the sidewalls of the second trench 23, and the bottom wall to form the lower electrode 31. Next, a high-k dielectric material can be deposited on the surface of the lower electrode 31 to form a dielectric layer 32. Then, a conductive material can be deposited on the surface of the dielectric layer 32 using a deposition process to form the upper electrode 33. The high-k dielectric material can be, for example, AlO₂. x HfO x ZrO x TaO xAny one or more combinations thereof, the conductive material is limited by the fact that the interface quality between the dielectric material and the polycrystalline silicon electrode may decrease as the dielectric constant increases. Therefore, conductive materials are often metals with high work function, such as TiN. x TaN x WN x Any one or more combinations of refractory metal materials.

[0161] It should be noted that during the deposition process of forming the lower electrode, dielectric layer and upper electrode, some conductive material and high dielectric constant material will be formed on the top surface of the first support layer 90. This part of the material can be removed by chemical mechanical polishing to expose the top surface of the first support layer 90.

[0162] After forming the capacitor structure 30, the method for fabricating the semiconductor structure also includes the following steps:

[0163] S420, A third dielectric layer and a second support layer are formed on the top surface of the first support layer.

[0164] In this step, such as Figure 24 As shown, a third dielectric layer 130 and a second dielectric layer 120 can be formed on the top surface of the first dielectric layer 90 using a deposition process. The material of the second dielectric layer 120 can be the same as that of the first dielectric layer 90, and the material of the third dielectric layer 130 can be the same as that of the second dielectric layer 100.

[0165] S430, a second through-hole 140 and a third through-hole 150 are formed. The second through-hole 140 penetrates the third dielectric layer 130 and the second support layer 120 in the thickness direction of the substrate 10 and exposes the second end of the capacitor structure 30. The third through-hole 150 penetrates the third dielectric layer 130, the second support layer 120, the first support layer 90 and the second dielectric layer 100 in the thickness direction of the substrate 10 and exposes at least a portion of the top surface of the word line.

[0166] In this step, such as Figure 25 As shown, a portion of the structure of the second support layer 120 and the third dielectric layer 130 can be removed by photolithography and etching processes, thereby forming a second via 140 in the second support layer 120 and the third dielectric layer 130. The second via 140 is located in the thickness direction of the substrate 10. Figure 25 The second via 140 extends through the second support layer 120 and the third dielectric layer 130 in the z direction shown in the figure. The second via 140 can expose the upper electrode of the second end of the capacitor structure 30. The channel formed by the second via 140 is used to form the capacitor conductive structure 141 in subsequent processes.

[0167] In this step, such as Figure 25As shown, while forming the second via 140, the second support layer 120, the third dielectric layer 130, the first support layer 90 and the second dielectric layer 100 can also be removed by photolithography and etching processes. The third via 150 can expose at least part of the top surface of the word line. The channel formed by the third via 150 is used to form the word line conductive structure 811 in subsequent processes.

[0168] S440, a capacitor conductive structure 141 is formed in the second through hole 140, and a word line conductive structure 811 is formed in the third through hole 150.

[0169] In this step, such as Figure 25 As shown, a capacitor conductive structure 141 can be formed in the second via 140 using a deposition process. The material of the capacitor conductive structure 141 can be copper (Cu), tungsten (W), TiNx, TaNx, WNx, etc.

[0170] In this step, such as Figure 25 As shown, a word line conductive structure 811 can be formed in the third via 150 using a deposition process. The material of the word line conductive structure 811 can be the same as the material of the capacitor conductive structure 141.

[0171] It should be noted that before forming the capacitor conductive structure 141 and the word line conductive structure 811, a third coating (not shown) can be formed in the second through hole 140 and the third through hole 150. The third coating can prevent the diffusion of metal materials. The material of the third coating can be, for example, titanium nitride (TiN).

[0172] According to an exemplary embodiment of this disclosure, such as Figure 25 As shown, this disclosure also provides a semiconductor structure, which includes a substrate 10, an active region 20, and a capacitor structure 30.

[0173] In this embodiment, as Figure 25 As shown, the substrate 10 includes a substrate 11, which can be made of silicon (Si), germanium (Ge), or silicon-germanium (GeSi), silicon carbide (SiC); it can also be silicon-on-insulator (SOI), germanium-on-insulator (GOI); or it can be other materials, such as gallium arsenide or other III-V compounds. The substrate 11 is used to support components disposed on it. (Refer to...) Figure 25 A low-k material layer, such as silicon carbon nitride (SiCN), is disposed above the substrate 11. The low-k material layer 12 is used to isolate the substrate 11 from the components above the low-k material layer 12. (Refer to...) Figure 25An oxide layer 13 is disposed on the low dielectric constant material layer 12, and the top surface of the oxide layer 13 has a first trench 133. The oxide layer 13 can be formed by the aforementioned deposition process or high density plasma (HDP) process, and the oxide layer 13 can be, for example, a plasma-enhanced tetraethyl orthosilicate (TEOS) layer.

[0174] In this embodiment, as Figure 25 As shown, an L-shaped stacked active region 20 is disposed on the substrate 10. The active region 20 includes alternating stacked first conductive layers 21 and first dielectric layers 22. The material of the first conductive layer 21 may be, for example, polysilicon (Poly), tungsten (W), copper (Cu), etc., and the first dielectric layer 22 may be, for example, a silicon nitride (SiNx) layer, a silicon oxide (SiOx) layer, or a stack of silicon nitride (SiNx) and silicon oxide (SiOx) layers. An L-shaped second trench 23 is formed between adjacent first dielectric layers 22.

[0175] In this embodiment, as Figure 23 and Figure 25 As shown, a portion of the capacitor structure 30 is located in the second trench 23, and the first end of the capacitor structure 30 is connected to the first conductive layer 21. The capacitor structure 30 includes a lower electrode 31 (Bottom Electrode, BE) and an upper electrode 33 (Top Electrode, TE), and a dielectric layer 32 disposed between the lower electrode 31 and the upper electrode 33.

[0176] Among them, reference Figure 25 The semiconductor structure also includes a fill layer 70 and a stacked structure. The fill layer 70 is located on the substrate 10, and the stacked structure is located on the fill layer 70. The stacked structure is a stacked structure of a first support layer 90, a second dielectric layer 100, and the first support layer 90. The stacked structure is provided with a first through-hole 110, which is located in the thickness direction of the substrate 10. Figure 25 The capacitor structure 30 is located in the first via 110, which extends through the stacked structure in the z-direction shown in the diagram. The material of the first support layer 90 may be, for example, silicon nitride (SiN), and the material of the second dielectric layer 100 may be, for example, tetraethyl orthosilicate (TEOS).

[0177] Among them, reference Figure 25 The semiconductor structure also includes a second support layer 120 and a third dielectric layer 130. The third dielectric layer 130 is located on the first support layer 90, and the second support layer 120 is located on the third dielectric layer 130. The third dielectric layer 130 and the second support layer 120 are provided with a second via 140. The second via 140 penetrates the third dielectric layer 130 and the second support layer 120 in the thickness direction of the substrate 10 to expose the upper electrode of the second end of the capacitor structure 30. A conductive structure of the capacitor structure 30 is provided in the second via 140.

[0178] Among them, reference Figure 25 The semiconductor structure also includes bit lines 51 and word lines 81. Bit lines 51 are located between adjacent first dielectric layers 22 and are connected to the first conductive layer 21. Word lines 81 cover part of the sidewalls of the first conductive layer 21 and the first dielectric layer 22, so that word lines 81 can control the connection or disconnection of the channel region of the active region 20 to realize the reading and writing of the control capacitor structure 30.

[0179] In the description of this specification, references to the terms "embodiment," "exemplary embodiment," "some implementation," "illustrated implementation," "example," etc., refer to specific features, structures, materials, or characteristics described in connection with an implementation or example that are included in at least one implementation or example of this disclosure.

[0180] In this specification, the illustrative expressions of the terms used do not necessarily refer to the same implementation or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more implementations or examples.

[0181] In the description of this disclosure, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this disclosure.

[0182] It is understood that the terms "first," "second," etc., as used in this disclosure may be used to describe various structures, but these structures are not limited by these terms. These terms are only used to distinguish one structure from another.

[0183] In one or more accompanying drawings, the same elements are represented by similar reference numerals. For clarity, many parts in the drawings are not drawn to scale. Furthermore, certain well-known parts may not be shown. For simplicity, a structure obtained after several steps may be depicted in a single drawing. Many specific details of this disclosure, such as the structure, materials, dimensions, processing methods, and techniques of the devices, are described below to provide a clearer understanding of the disclosure. However, as those skilled in the art will understand, this disclosure may be implemented without adhering to these specific details.

[0184] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this disclosure, and are not intended to limit them. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this disclosure.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: A base is provided, with a first groove provided on top; Multiple L-shaped stacked active regions are formed on the first trench, the active regions comprising alternating stacked first conductive layers and first dielectric layers; A portion of the first conductive layer is removed to form an L-shaped second trench in the active region; A capacitor structure is formed, a portion of which is located in the second trench, and a first end of the capacitor structure is connected to the first conductive layer. A plurality of L-shaped stacked active regions are formed on the first trench, including: A first conductive material layer and a first dielectric material layer are alternately formed on the substrate, both of which are U-shaped with flanges. A third trench is formed, exposing the bottom wall of the first trench and the sidewalls of the first conductive material layer and the first dielectric material layer. The third trench separates the first conductive material layer and the first dielectric material layer into at least two Z-shaped stacked active layers. By removing part of the structure of the active layer, the remaining active layer located in the first trench forms multiple L-shaped stacked active regions.

2. The method for fabricating a semiconductor structure according to claim 1, characterized in that, After forming the Z-shaped stacked active layers, the method for fabricating the semiconductor structure further includes: A portion of the first conductive layer is removed to form a fourth trench between adjacent first dielectric layers, the fourth trench being connected to the third trench; Bit lines are formed in the fourth trench.

3. The method for fabricating a semiconductor structure according to claim 1, characterized in that, Removing a portion of the structure of the active layer includes: Remove the active layer extending beyond the first trench to form an L-shaped stack of active layers; and / or, A portion of the structure of the active layer is removed to form a plurality of fifth trenches, which divide the active layer into a plurality of active regions.

4. The method for fabricating a semiconductor structure according to claim 1, characterized in that, After removing a portion of the active layer, the method for fabricating the semiconductor structure further includes: Fill the first trench; The top surface of the first trench after flattening and filling.

5. The method for fabricating a semiconductor structure according to claim 4, characterized in that, After planarizing and filling the top surface of the first trench, the method for fabricating the semiconductor structure further includes: Multiple word lines are formed, and the word lines are in contact with the active region.

6. The method for fabricating a semiconductor structure according to claim 5, characterized in that, Removing a portion of the first conductive layer to form an L-shaped second trench in the active region includes: A second dielectric layer and a first support layer are formed on the top surface of the filled first trench; A first through-hole is formed, which penetrates the second dielectric layer and the first support layer in the thickness direction of the substrate to expose the top surface of the first conductive layer; A portion of the first conductive layer is removed along the first through-hole.

7. The method for fabricating a semiconductor structure according to claim 6, characterized in that, Forming a capacitor structure includes: The capacitor structure is formed in the second trench and the first through hole through the first through hole.

8. The method for fabricating a semiconductor structure according to claim 7, characterized in that, After forming the capacitor structure, the methods for fabricating semiconductor structures also include: A third dielectric layer and a second support layer are formed on the top surface of the first support layer; A second through-hole and a third through-hole are formed. The second through-hole penetrates the third dielectric layer and the second support layer in the thickness direction of the substrate and exposes the second end of the capacitor structure. The third through-hole penetrates the third dielectric layer, the second support layer, the first support layer and the second dielectric layer in the thickness direction of the substrate and exposes at least a portion of the top surface of the word line. A capacitive conductive structure is formed in the second through hole, and a word line conductive structure is formed in the third through hole.

9. A semiconductor structure, characterized in that, include: Base; An active region is disposed on the substrate, and the active region is a stacked structure comprising an alternately stacked first conductive layer and a first dielectric layer; A filling layer is located on the active region; A layered structure is located on the filler layer; The stacked structure is a stacked structure of a first support layer, a second dielectric layer and a first support layer. A first through hole is provided in the second dielectric layer and the first support layer. The first through hole penetrates the second dielectric layer, the first support layer and the filler layer in the thickness direction of the substrate. The second trench is formed by removing a portion of the first conductive layer in the active region along the first through-hole, and the second trench is L-shaped. A capacitor structure is disposed in the first through hole and the second trench. The capacitor structure is L-shaped and its first end is connected to the first conductive layer.

10. The semiconductor structure according to claim 9, characterized in that, The semiconductor structure also includes: Bit lines are located between adjacent first dielectric layers and are connected to the first conductive layer.

11. The semiconductor structure according to claim 9, characterized in that, The semiconductor structure also includes: The word line covers part of the sidewalls of the first conductive layer and the first dielectric layer.

12. The semiconductor structure according to claim 9, characterized in that, The semiconductor structure also includes: The third dielectric layer is located on the first support layer; The second support layer is located on the third dielectric layer; The third dielectric layer and the second support layer are provided with a second through hole, which penetrates the third dielectric layer and the second support layer in the thickness direction of the substrate, exposing the second end of the capacitor structure.

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